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1/*2 * Copyright (c) 2004-2011 Atheros Communications Inc.3 * Copyright (c) 2011 Qualcomm Atheros, Inc.4 *5 * Permission to use, copy, modify, and/or distribute this software for any6 * purpose with or without fee is hereby granted, provided that the above7 * copyright notice and this permission notice appear in all copies.8 *9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.16 */17 18#ifndef HIF_H19#define HIF_H20 21#include "common.h"22#include "core.h"23 24#include <linux/scatterlist.h>25 26#define BUS_REQUEST_MAX_NUM 6427#define HIF_MBOX_BLOCK_SIZE 12828#define HIF_MBOX0_BLOCK_SIZE 129 30#define HIF_DMA_BUFFER_SIZE (32 * 1024)31#define CMD53_FIXED_ADDRESS 132#define CMD53_INCR_ADDRESS 233 34#define MAX_SCATTER_REQUESTS 435#define MAX_SCATTER_ENTRIES_PER_REQ 1636#define MAX_SCATTER_REQ_TRANSFER_SIZE (32 * 1024)37 38/* Mailbox address in SDIO address space */39#define HIF_MBOX_BASE_ADDR 0x80040#define HIF_MBOX_WIDTH 0x80041 42#define HIF_MBOX_END_ADDR (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)43 44/* version 1 of the chip has only a 12K extended mbox range */45#define HIF_MBOX0_EXT_BASE_ADDR 0x400046#define HIF_MBOX0_EXT_WIDTH (12*1024)47 48/* GMBOX addresses */49#define HIF_GMBOX_BASE_ADDR 0x700050#define HIF_GMBOX_WIDTH 0x400051 52/* interrupt mode register */53#define CCCR_SDIO_IRQ_MODE_REG 0xF054 55/* mode to enable special 4-bit interrupt assertion without clock */56#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0)57 58/* HTC runs over mailbox 0 */59#define HTC_MAILBOX 060 61#define ATH6KL_TARGET_DEBUG_INTR_MASK 0x0162 63/* FIXME: are these duplicates with MAX_SCATTER_ values in hif.h? */64#define ATH6KL_SCATTER_ENTRIES_PER_REQ 1665#define ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER (16 * 1024)66#define ATH6KL_SCATTER_REQS 467 68#define ATH6KL_HIF_COMMUNICATION_TIMEOUT 100069 70struct bus_request {71 struct list_head list;72 73 /* request data */74 u32 address;75 76 u8 *buffer;77 u32 length;78 u32 request;79 struct htc_packet *packet;80 int status;81 82 /* this is a scatter request */83 struct hif_scatter_req *scat_req;84};85 86/* direction of transfer (read/write) */87#define HIF_READ 0x0000000188#define HIF_WRITE 0x0000000289#define HIF_DIR_MASK (HIF_READ | HIF_WRITE)90 91/*92 * emode - This indicates the whether the command is to be executed in a93 * blocking or non-blocking fashion (HIF_SYNCHRONOUS/94 * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been95 * implemented using the asynchronous mode allowing the bus96 * driver to indicate the completion of operation through the97 * registered callback routine. The requirement primarily comes98 * from the contexts these operations get called from (a driver's99 * transmit context or the ISR context in case of receive).100 * Support for both of these modes is essential.101 */102#define HIF_SYNCHRONOUS 0x00000010103#define HIF_ASYNCHRONOUS 0x00000020104#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)105 106/*107 * dmode - An interface may support different kinds of commands based on108 * the tradeoff between the amount of data it can carry and the109 * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/110 * HIF_BLOCK_BASIS). In case of latter, the data is rounded off111 * to the nearest block size by padding. The size of the block is112 * configurable at compile time using the HIF_BLOCK_SIZE and is113 * negotiated with the target during initialization after the114 * ATH6KL interrupts are enabled.115 */116#define HIF_BYTE_BASIS 0x00000040117#define HIF_BLOCK_BASIS 0x00000080118#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)119 120/*121 * amode - This indicates if the address has to be incremented on ATH6KL122 * after every read/write operation (HIF?FIXED_ADDRESS/123 * HIF_INCREMENTAL_ADDRESS).124 */125#define HIF_FIXED_ADDRESS 0x00000100126#define HIF_INCREMENTAL_ADDRESS 0x00000200127#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)128 129#define HIF_WR_ASYNC_BYTE_INC \130 (HIF_WRITE | HIF_ASYNCHRONOUS | \131 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)132 133#define HIF_WR_ASYNC_BLOCK_INC \134 (HIF_WRITE | HIF_ASYNCHRONOUS | \135 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)136 137#define HIF_WR_SYNC_BYTE_FIX \138 (HIF_WRITE | HIF_SYNCHRONOUS | \139 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)140 141#define HIF_WR_SYNC_BYTE_INC \142 (HIF_WRITE | HIF_SYNCHRONOUS | \143 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)144 145#define HIF_WR_SYNC_BLOCK_INC \146 (HIF_WRITE | HIF_SYNCHRONOUS | \147 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)148 149#define HIF_RD_SYNC_BYTE_INC \150 (HIF_READ | HIF_SYNCHRONOUS | \151 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)152 153#define HIF_RD_SYNC_BYTE_FIX \154 (HIF_READ | HIF_SYNCHRONOUS | \155 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)156 157#define HIF_RD_ASYNC_BLOCK_FIX \158 (HIF_READ | HIF_ASYNCHRONOUS | \159 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)160 161#define HIF_RD_SYNC_BLOCK_FIX \162 (HIF_READ | HIF_SYNCHRONOUS | \163 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)164 165struct hif_scatter_item {166 u8 *buf;167 int len;168 struct htc_packet *packet;169};170 171struct hif_scatter_req {172 struct list_head list;173 /* address for the read/write operation */174 u32 addr;175 176 /* request flags */177 u32 req;178 179 /* total length of entire transfer */180 u32 len;181 182 bool virt_scat;183 184 void (*complete) (struct htc_target *, struct hif_scatter_req *);185 int status;186 int scat_entries;187 188 struct bus_request *busrequest;189 struct scatterlist *sgentries;190 191 /* bounce buffer for upper layers to copy to/from */192 u8 *virt_dma_buf;193 194 u32 scat_q_depth;195 196 struct hif_scatter_item scat_list[];197};198 199struct ath6kl_irq_proc_registers {200 u8 host_int_status;201 u8 cpu_int_status;202 u8 error_int_status;203 u8 counter_int_status;204 u8 mbox_frame;205 u8 rx_lkahd_valid;206 u8 host_int_status2;207 u8 gmbox_rx_avail;208 __le32 rx_lkahd[2];209 __le32 rx_gmbox_lkahd_alias[2];210} __packed;211 212struct ath6kl_irq_enable_reg {213 u8 int_status_en;214 u8 cpu_int_status_en;215 u8 err_int_status_en;216 u8 cntr_int_status_en;217} __packed;218 219struct ath6kl_device {220 /* protects irq_proc_reg and irq_en_reg below */221 spinlock_t lock;222 struct ath6kl_irq_proc_registers irq_proc_reg;223 struct ath6kl_irq_enable_reg irq_en_reg;224 struct htc_target *htc_cnxt;225 struct ath6kl *ar;226};227 228struct ath6kl_hif_ops {229 int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf,230 u32 len, u32 request);231 int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer,232 u32 length, u32 request, struct htc_packet *packet);233 234 void (*irq_enable)(struct ath6kl *ar);235 void (*irq_disable)(struct ath6kl *ar);236 237 struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar);238 void (*scatter_req_add)(struct ath6kl *ar,239 struct hif_scatter_req *s_req);240 int (*enable_scatter)(struct ath6kl *ar);241 int (*scat_req_rw) (struct ath6kl *ar,242 struct hif_scatter_req *scat_req);243 void (*cleanup_scatter)(struct ath6kl *ar);244 int (*suspend)(struct ath6kl *ar, struct cfg80211_wowlan *wow);245 int (*resume)(struct ath6kl *ar);246 int (*diag_read32)(struct ath6kl *ar, u32 address, u32 *value);247 int (*diag_write32)(struct ath6kl *ar, u32 address, __le32 value);248 int (*bmi_read)(struct ath6kl *ar, u8 *buf, u32 len);249 int (*bmi_write)(struct ath6kl *ar, u8 *buf, u32 len);250 int (*power_on)(struct ath6kl *ar);251 int (*power_off)(struct ath6kl *ar);252 void (*stop)(struct ath6kl *ar);253 int (*pipe_send)(struct ath6kl *ar, u8 pipe, struct sk_buff *hdr_buf,254 struct sk_buff *buf);255 void (*pipe_get_default)(struct ath6kl *ar, u8 *pipe_ul, u8 *pipe_dl);256 int (*pipe_map_service)(struct ath6kl *ar, u16 service_id, u8 *pipe_ul,257 u8 *pipe_dl);258 u16 (*pipe_get_free_queue_number)(struct ath6kl *ar, u8 pipe);259};260 261int ath6kl_hif_setup(struct ath6kl_device *dev);262int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev);263int ath6kl_hif_mask_intrs(struct ath6kl_device *dev);264int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev,265 u32 *lk_ahd, int timeout);266int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx);267int ath6kl_hif_disable_intrs(struct ath6kl_device *dev);268 269int ath6kl_hif_rw_comp_handler(void *context, int status);270int ath6kl_hif_intr_bh_handler(struct ath6kl *ar);271 272/* Scatter Function and Definitions */273int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,274 struct hif_scatter_req *scat_req, bool read);275 276#endif277