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1/*2 * Copyright (c) 2010-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef AR9003_EEPROM_H18#define AR9003_EEPROM_H19 20#include <linux/types.h>21 22#define AR9300_EEP_VER 0xD00023#define AR9300_EEP_VER_MINOR_MASK 0xFFF24#define AR9300_EEP_MINOR_VER_1 0x125#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_126 27/* 16-bit offset location start of calibration struct */28#define AR9300_EEP_START_LOC 25629#define AR9300_NUM_5G_CAL_PIERS 830#define AR9300_NUM_2G_CAL_PIERS 331#define AR9300_NUM_5G_20_TARGET_POWERS 832#define AR9300_NUM_5G_40_TARGET_POWERS 833#define AR9300_NUM_2G_CCK_TARGET_POWERS 234#define AR9300_NUM_2G_20_TARGET_POWERS 335#define AR9300_NUM_2G_40_TARGET_POWERS 336/* #define AR9300_NUM_CTLS 21 */37#define AR9300_NUM_CTLS_5G 938#define AR9300_NUM_CTLS_2G 1239#define AR9300_NUM_BAND_EDGES_5G 840#define AR9300_NUM_BAND_EDGES_2G 441#define AR9300_EEPMISC_WOW 0x0242#define AR9300_CUSTOMER_DATA_SIZE 2043 44#define AR9300_MAX_CHAINS 345#define AR9300_ANT_16S 2546#define AR9300_FUTURE_MODAL_SZ 647 48#define AR9300_PAPRD_RATE_MASK 0x01ffffff49#define AR9300_PAPRD_SCALE_1 0x0e00000050#define AR9300_PAPRD_SCALE_1_S 2551#define AR9300_PAPRD_SCALE_2 0x7000000052#define AR9300_PAPRD_SCALE_2_S 2853 54#define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc955 56/* Delta from which to start power to pdadc table */57/* This offset is used in both open loop and closed loop power control58 * schemes. In open loop power control, it is not really needed, but for59 * the "sake of consistency" it was kept. For certain AP designs, this60 * value is overwritten by the value in the flag "pwrTableOffset" just61 * before writing the pdadc vs pwr into the chip registers.62 */63#define AR9300_PWR_TABLE_OFFSET 064 65/* Noise power data definitions66 * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET67 * (e.g. -25 = (-25/4 - 90) = -96.25 dBm)68 * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm69 * resolution (2 bits) is 0.25dBm70 */71#define NOISE_PWR_DATA_OFFSET -9072#define NOISE_PWR_DBM_2_INT(_p) ((((_p) + 3) >> 2) + NOISE_PWR_DATA_OFFSET)73#define N2DBM(_p) NOISE_PWR_DBM_2_INT(_p)74 75/* byte addressable */76#define AR9300_EEPROM_SIZE (16*1024)77 78#define AR9300_BASE_ADDR_4K 0xfff79#define AR9300_BASE_ADDR 0x3ff80#define AR9300_BASE_ADDR_512 0x1ff81 82/* AR5416_EEPMISC_BIG_ENDIAN not set indicates little endian */83#define AR9300_EEPMISC_LITTLE_ENDIAN 084 85#define AR9300_OTP_BASE(_ah) \86 ((AR_SREV_9340(_ah) || AR_SREV_9550(_ah)) ? 0x30000 : 0x14000)87#define AR9300_OTP_STATUS(_ah) \88 ((AR_SREV_9340(_ah) || AR_SREV_9550(_ah)) ? 0x31018 : 0x15f18)89#define AR9300_OTP_STATUS_TYPE 0x790#define AR9300_OTP_STATUS_VALID 0x491#define AR9300_OTP_STATUS_ACCESS_BUSY 0x292#define AR9300_OTP_STATUS_SM_BUSY 0x193#define AR9300_OTP_READ_DATA(_ah) \94 ((AR_SREV_9340(_ah) || AR_SREV_9550(_ah)) ? 0x3101c : 0x15f1c)95 96enum targetPowerHTRates {97 HT_TARGET_RATE_0_8_16,98 HT_TARGET_RATE_1_3_9_11_17_19,99 HT_TARGET_RATE_4,100 HT_TARGET_RATE_5,101 HT_TARGET_RATE_6,102 HT_TARGET_RATE_7,103 HT_TARGET_RATE_12,104 HT_TARGET_RATE_13,105 HT_TARGET_RATE_14,106 HT_TARGET_RATE_15,107 HT_TARGET_RATE_20,108 HT_TARGET_RATE_21,109 HT_TARGET_RATE_22,110 HT_TARGET_RATE_23111};112 113enum targetPowerLegacyRates {114 LEGACY_TARGET_RATE_6_24,115 LEGACY_TARGET_RATE_36,116 LEGACY_TARGET_RATE_48,117 LEGACY_TARGET_RATE_54118};119 120enum targetPowerCckRates {121 LEGACY_TARGET_RATE_1L_5L,122 LEGACY_TARGET_RATE_5S,123 LEGACY_TARGET_RATE_11L,124 LEGACY_TARGET_RATE_11S125};126 127enum ar9300_Rates {128 ALL_TARGET_LEGACY_6_24,129 ALL_TARGET_LEGACY_36,130 ALL_TARGET_LEGACY_48,131 ALL_TARGET_LEGACY_54,132 ALL_TARGET_LEGACY_1L_5L,133 ALL_TARGET_LEGACY_5S,134 ALL_TARGET_LEGACY_11L,135 ALL_TARGET_LEGACY_11S,136 ALL_TARGET_HT20_0_8_16,137 ALL_TARGET_HT20_1_3_9_11_17_19,138 ALL_TARGET_HT20_4,139 ALL_TARGET_HT20_5,140 ALL_TARGET_HT20_6,141 ALL_TARGET_HT20_7,142 ALL_TARGET_HT20_12,143 ALL_TARGET_HT20_13,144 ALL_TARGET_HT20_14,145 ALL_TARGET_HT20_15,146 ALL_TARGET_HT20_20,147 ALL_TARGET_HT20_21,148 ALL_TARGET_HT20_22,149 ALL_TARGET_HT20_23,150 ALL_TARGET_HT40_0_8_16,151 ALL_TARGET_HT40_1_3_9_11_17_19,152 ALL_TARGET_HT40_4,153 ALL_TARGET_HT40_5,154 ALL_TARGET_HT40_6,155 ALL_TARGET_HT40_7,156 ALL_TARGET_HT40_12,157 ALL_TARGET_HT40_13,158 ALL_TARGET_HT40_14,159 ALL_TARGET_HT40_15,160 ALL_TARGET_HT40_20,161 ALL_TARGET_HT40_21,162 ALL_TARGET_HT40_22,163 ALL_TARGET_HT40_23,164 ar9300RateSize,165};166 167 168struct eepFlags {169 u8 opFlags;170 u8 eepMisc;171} __packed;172 173enum CompressAlgorithm {174 _CompressNone = 0,175 _CompressLzma,176 _CompressPairs,177 _CompressBlock,178 _Compress4,179 _Compress5,180 _Compress6,181 _Compress7,182};183 184struct ar9300_base_eep_hdr {185 __le16 regDmn[2];186 /* 4 bits tx and 4 bits rx */187 u8 txrxMask;188 struct eepFlags opCapFlags;189 u8 rfSilent;190 u8 blueToothOptions;191 u8 deviceCap;192 /* takes lower byte in eeprom location */193 u8 deviceType;194 /* offset in dB to be added to beginning195 * of pdadc table in calibration196 */197 int8_t pwrTableOffset;198 u8 params_for_tuning_caps[2];199 /*200 * bit0 - enable tx temp comp201 * bit1 - enable tx volt comp202 * bit2 - enable fastClock - default to 1203 * bit3 - enable doubling - default to 1204 * bit4 - enable internal regulator - default to 1205 */206 u8 featureEnable;207 /* misc flags: bit0 - turn down drivestrength */208 u8 miscConfiguration;209 u8 eepromWriteEnableGpio;210 u8 wlanDisableGpio;211 u8 wlanLedGpio;212 u8 rxBandSelectGpio;213 u8 txrxgain;214 /* SW controlled internal regulator fields */215 __le32 swreg;216} __packed;217 218struct ar9300_modal_eep_header {219 /* 4 idle, t1, t2, b (4 bits per setting) */220 __le32 antCtrlCommon;221 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */222 __le32 antCtrlCommon2;223 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */224 __le16 antCtrlChain[AR9300_MAX_CHAINS];225 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */226 u8 xatten1DB[AR9300_MAX_CHAINS];227 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */228 u8 xatten1Margin[AR9300_MAX_CHAINS];229 int8_t tempSlope;230 int8_t voltSlope;231 /* spur channels in usual fbin coding format */232 u8 spurChans[AR_EEPROM_MODAL_SPURS];233 /* 3 Check if the register is per chain */234 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];235 u8 reserved[11];236 int8_t quick_drop;237 u8 xpaBiasLvl;238 u8 txFrameToDataStart;239 u8 txFrameToPaOn;240 u8 txClip;241 int8_t antennaGain;242 u8 switchSettling;243 int8_t adcDesiredSize;244 u8 txEndToXpaOff;245 u8 txEndToRxOn;246 u8 txFrameToXpaOn;247 u8 thresh62;248 __le32 papdRateMaskHt20;249 __le32 papdRateMaskHt40;250 __le16 switchcomspdt;251 u8 xlna_bias_strength;252 u8 futureModal[7];253} __packed;254 255struct ar9300_cal_data_per_freq_op_loop {256 int8_t refPower;257 /* pdadc voltage at power measurement */258 u8 voltMeas;259 /* pcdac used for power measurement */260 u8 tempMeas;261 /* range is -60 to -127 create a mapping equation 1db resolution */262 int8_t rxNoisefloorCal;263 /*range is same as noisefloor */264 int8_t rxNoisefloorPower;265 /* temp measured when noisefloor cal was performed */266 u8 rxTempMeas;267} __packed;268 269struct cal_tgt_pow_legacy {270 u8 tPow2x[4];271} __packed;272 273struct cal_tgt_pow_ht {274 u8 tPow2x[14];275} __packed;276 277struct cal_ctl_data_2g {278 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];279} __packed;280 281struct cal_ctl_data_5g {282 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];283} __packed;284 285#define MAX_BASE_EXTENSION_FUTURE 2286 287struct ar9300_BaseExtension_1 {288 u8 ant_div_control;289 u8 future[MAX_BASE_EXTENSION_FUTURE];290 /*291 * misc_enable:292 *293 * BIT 0 - TX Gain Cap enable.294 * BIT 1 - Uncompressed Checksum enable.295 * BIT 2/3 - MinCCApwr enable 2g/5g.296 */297 u8 misc_enable;298 int8_t tempslopextension[8];299 int8_t quick_drop_low;300 int8_t quick_drop_high;301} __packed;302 303struct ar9300_BaseExtension_2 {304 int8_t tempSlopeLow;305 int8_t tempSlopeHigh;306 u8 xatten1DBLow[AR9300_MAX_CHAINS];307 u8 xatten1MarginLow[AR9300_MAX_CHAINS];308 u8 xatten1DBHigh[AR9300_MAX_CHAINS];309 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];310} __packed;311 312struct ar9300_eeprom {313 u8 eepromVersion;314 u8 templateVersion;315 u8 macAddr[6];316 u8 custData[AR9300_CUSTOMER_DATA_SIZE];317 318 struct ar9300_base_eep_hdr baseEepHeader;319 320 struct ar9300_modal_eep_header modalHeader2G;321 struct ar9300_BaseExtension_1 base_ext1;322 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];323 struct ar9300_cal_data_per_freq_op_loop324 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];325 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];326 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];327 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];328 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];329 struct cal_tgt_pow_legacy330 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];331 struct cal_tgt_pow_legacy332 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];333 struct cal_tgt_pow_ht334 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];335 struct cal_tgt_pow_ht336 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];337 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];338 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];339 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];340 struct ar9300_modal_eep_header modalHeader5G;341 struct ar9300_BaseExtension_2 base_ext2;342 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];343 struct ar9300_cal_data_per_freq_op_loop344 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];345 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];346 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];347 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];348 struct cal_tgt_pow_legacy349 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];350 struct cal_tgt_pow_ht351 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];352 struct cal_tgt_pow_ht353 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];354 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];355 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];356 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];357} __packed;358 359s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);360s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);361u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz);362u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz);363 364u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);365 366u32 ar9003_get_paprd_rate_mask_ht20(struct ath_hw *ah, bool is2ghz);367u32 ar9003_get_paprd_rate_mask_ht40(struct ath_hw *ah, bool is2ghz);368unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,369 struct ath9k_channel *chan);370 371void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);372int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray);373 374#endif375