1197 lines · c
1/*2 * Copyright (c) 2008-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#include "hw.h"18#include "ar9003_mac.h"19#include "ar9003_2p2_initvals.h"20#include "ar9003_buffalo_initvals.h"21#include "ar9485_initvals.h"22#include "ar9340_initvals.h"23#include "ar9330_1p1_initvals.h"24#include "ar9330_1p2_initvals.h"25#include "ar955x_1p0_initvals.h"26#include "ar9580_1p0_initvals.h"27#include "ar9462_2p0_initvals.h"28#include "ar9462_2p1_initvals.h"29#include "ar9565_1p0_initvals.h"30#include "ar9565_1p1_initvals.h"31#include "ar953x_initvals.h"32#include "ar956x_initvals.h"33 34/* General hardware code for the AR9003 hadware family */35 36/*37 * The AR9003 family uses a new INI format (pre, core, post38 * arrays per subsystem). This provides support for the39 * AR9003 2.2 chipsets.40 */41static void ar9003_hw_init_mode_regs(struct ath_hw *ah)42{43 if (AR_SREV_9330_11(ah)) {44 /* mac */45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],46 ar9331_1p1_mac_core);47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],48 ar9331_1p1_mac_postamble);49 50 /* bb */51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],52 ar9331_1p1_baseband_core);53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],54 ar9331_1p1_baseband_postamble);55 56 /* radio */57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],58 ar9331_1p1_radio_core);59 60 /* soc */61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],62 ar9331_1p1_soc_preamble);63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],64 ar9331_1p1_soc_postamble);65 66 /* rx/tx gain */67 INIT_INI_ARRAY(&ah->iniModesRxGain,68 ar9331_common_rx_gain_1p1);69 INIT_INI_ARRAY(&ah->iniModesTxGain,70 ar9331_modes_lowest_ob_db_tx_gain_1p1);71 72 /* Japan 2484 Mhz CCK */73 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,74 ar9331_1p1_baseband_core_txfir_coeff_japan_2484);75 76 /* additional clock settings */77 if (ah->is_clk_25mhz)78 INIT_INI_ARRAY(&ah->iniAdditional,79 ar9331_1p1_xtal_25M);80 else81 INIT_INI_ARRAY(&ah->iniAdditional,82 ar9331_1p1_xtal_40M);83 } else if (AR_SREV_9330_12(ah)) {84 /* mac */85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],86 ar9331_1p2_mac_core);87 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],88 ar9331_1p2_mac_postamble);89 90 /* bb */91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],92 ar9331_1p2_baseband_core);93 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],94 ar9331_1p2_baseband_postamble);95 96 /* radio */97 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],98 ar9331_1p2_radio_core);99 100 /* soc */101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],102 ar9331_1p2_soc_preamble);103 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],104 ar9331_1p2_soc_postamble);105 106 /* rx/tx gain */107 INIT_INI_ARRAY(&ah->iniModesRxGain,108 ar9331_common_rx_gain_1p2);109 INIT_INI_ARRAY(&ah->iniModesTxGain,110 ar9331_modes_lowest_ob_db_tx_gain_1p2);111 112 /* Japan 2484 Mhz CCK */113 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,114 ar9331_1p2_baseband_core_txfir_coeff_japan_2484);115 116 /* additional clock settings */117 if (ah->is_clk_25mhz)118 INIT_INI_ARRAY(&ah->iniAdditional,119 ar9331_1p2_xtal_25M);120 else121 INIT_INI_ARRAY(&ah->iniAdditional,122 ar9331_1p2_xtal_40M);123 } else if (AR_SREV_9340(ah)) {124 /* mac */125 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],126 ar9340_1p0_mac_core);127 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],128 ar9340_1p0_mac_postamble);129 130 /* bb */131 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],132 ar9340_1p0_baseband_core);133 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],134 ar9340_1p0_baseband_postamble);135 136 /* radio */137 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],138 ar9340_1p0_radio_core);139 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],140 ar9340_1p0_radio_postamble);141 142 /* soc */143 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],144 ar9340_1p0_soc_preamble);145 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],146 ar9340_1p0_soc_postamble);147 148 /* rx/tx gain */149 INIT_INI_ARRAY(&ah->iniModesRxGain,150 ar9340Common_wo_xlna_rx_gain_table_1p0);151 INIT_INI_ARRAY(&ah->iniModesTxGain,152 ar9340Modes_high_ob_db_tx_gain_table_1p0);153 154 INIT_INI_ARRAY(&ah->iniModesFastClock,155 ar9340Modes_fast_clock_1p0);156 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,157 ar9340_1p0_baseband_core_txfir_coeff_japan_2484);158 INIT_INI_ARRAY(&ah->ini_dfs,159 ar9340_1p0_baseband_postamble_dfs_channel);160 161 if (!ah->is_clk_25mhz)162 INIT_INI_ARRAY(&ah->iniAdditional,163 ar9340_1p0_radio_core_40M);164 } else if (AR_SREV_9485_11_OR_LATER(ah)) {165 /* mac */166 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],167 ar9485_1_1_mac_core);168 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],169 ar9485_1_1_mac_postamble);170 171 /* bb */172 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);173 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],174 ar9485_1_1_baseband_core);175 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],176 ar9485_1_1_baseband_postamble);177 178 /* radio */179 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],180 ar9485_1_1_radio_core);181 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],182 ar9485_1_1_radio_postamble);183 184 /* soc */185 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],186 ar9485_1_1_soc_preamble);187 188 /* rx/tx gain */189 INIT_INI_ARRAY(&ah->iniModesRxGain,190 ar9485Common_wo_xlna_rx_gain_1_1);191 INIT_INI_ARRAY(&ah->iniModesTxGain,192 ar9485_modes_lowest_ob_db_tx_gain_1_1);193 194 /* Japan 2484 Mhz CCK */195 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,196 ar9485_1_1_baseband_core_txfir_coeff_japan_2484);197 198 if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {199 INIT_INI_ARRAY(&ah->iniPcieSerdes,200 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);201 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,202 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);203 } else {204 INIT_INI_ARRAY(&ah->iniPcieSerdes,205 ar9485_1_1_pcie_phy_clkreq_disable_L1);206 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,207 ar9485_1_1_pcie_phy_clkreq_disable_L1);208 }209 } else if (AR_SREV_9462_21(ah)) {210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],211 ar9462_2p1_mac_core);212 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],213 ar9462_2p1_mac_postamble);214 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],215 ar9462_2p1_baseband_core);216 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],217 ar9462_2p1_baseband_postamble);218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],219 ar9462_2p1_radio_core);220 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],221 ar9462_2p1_radio_postamble);222 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,223 ar9462_2p1_radio_postamble_sys2ant);224 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],225 ar9462_2p1_soc_preamble);226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],227 ar9462_2p1_soc_postamble);228 INIT_INI_ARRAY(&ah->iniModesRxGain,229 ar9462_2p1_common_rx_gain);230 INIT_INI_ARRAY(&ah->iniModesFastClock,231 ar9462_2p1_modes_fast_clock);232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,233 ar9462_2p1_baseband_core_txfir_coeff_japan_2484);234 235 /* Awake -> Sleep Setting */236 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&237 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {238 INIT_INI_ARRAY(&ah->iniPcieSerdes,239 ar9462_2p1_pciephy_clkreq_disable_L1);240 }241 242 /* Sleep -> Awake Setting */243 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&244 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {245 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,246 ar9462_2p1_pciephy_clkreq_disable_L1);247 }248 } else if (AR_SREV_9462_20(ah)) {249 250 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);251 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],252 ar9462_2p0_mac_postamble);253 254 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],255 ar9462_2p0_baseband_core);256 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],257 ar9462_2p0_baseband_postamble);258 259 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],260 ar9462_2p0_radio_core);261 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],262 ar9462_2p0_radio_postamble);263 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,264 ar9462_2p0_radio_postamble_sys2ant);265 266 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],267 ar9462_2p0_soc_preamble);268 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],269 ar9462_2p0_soc_postamble);270 271 INIT_INI_ARRAY(&ah->iniModesRxGain,272 ar9462_2p0_common_rx_gain);273 274 /* Awake -> Sleep Setting */275 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&276 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {277 INIT_INI_ARRAY(&ah->iniPcieSerdes,278 ar9462_2p0_pciephy_clkreq_disable_L1);279 }280 281 /* Sleep -> Awake Setting */282 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&283 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {284 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,285 ar9462_2p0_pciephy_clkreq_disable_L1);286 }287 288 /* Fast clock modal settings */289 INIT_INI_ARRAY(&ah->iniModesFastClock,290 ar9462_2p0_modes_fast_clock);291 292 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,293 ar9462_2p0_baseband_core_txfir_coeff_japan_2484);294 } else if (AR_SREV_9550(ah)) {295 /* mac */296 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],297 ar955x_1p0_mac_core);298 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],299 ar955x_1p0_mac_postamble);300 301 /* bb */302 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],303 ar955x_1p0_baseband_core);304 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],305 ar955x_1p0_baseband_postamble);306 307 /* radio */308 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],309 ar955x_1p0_radio_core);310 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],311 ar955x_1p0_radio_postamble);312 313 /* soc */314 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],315 ar955x_1p0_soc_preamble);316 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],317 ar955x_1p0_soc_postamble);318 319 /* rx/tx gain */320 INIT_INI_ARRAY(&ah->iniModesRxGain,321 ar955x_1p0_common_wo_xlna_rx_gain_table);322 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,323 ar955x_1p0_common_wo_xlna_rx_gain_bounds);324 INIT_INI_ARRAY(&ah->iniModesTxGain,325 ar955x_1p0_modes_xpa_tx_gain_table);326 327 /* Fast clock modal settings */328 INIT_INI_ARRAY(&ah->iniModesFastClock,329 ar955x_1p0_modes_fast_clock);330 } else if (AR_SREV_9531(ah)) {331 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],332 qca953x_1p0_mac_core);333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],334 qca953x_1p0_mac_postamble);335 if (AR_SREV_9531_20(ah)) {336 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],337 qca953x_2p0_baseband_core);338 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],339 qca953x_2p0_baseband_postamble);340 } else {341 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],342 qca953x_1p0_baseband_core);343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],344 qca953x_1p0_baseband_postamble);345 }346 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],347 qca953x_1p0_radio_core);348 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],349 qca953x_1p0_radio_postamble);350 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],351 qca953x_1p0_soc_preamble);352 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],353 qca953x_1p0_soc_postamble);354 355 if (AR_SREV_9531_20(ah)) {356 INIT_INI_ARRAY(&ah->iniModesRxGain,357 qca953x_2p0_common_wo_xlna_rx_gain_table);358 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,359 qca953x_2p0_common_wo_xlna_rx_gain_bounds);360 } else {361 INIT_INI_ARRAY(&ah->iniModesRxGain,362 qca953x_1p0_common_wo_xlna_rx_gain_table);363 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,364 qca953x_1p0_common_wo_xlna_rx_gain_bounds);365 }366 367 if (AR_SREV_9531_20(ah))368 INIT_INI_ARRAY(&ah->iniModesTxGain,369 qca953x_2p0_modes_no_xpa_tx_gain_table);370 else if (AR_SREV_9531_11(ah))371 INIT_INI_ARRAY(&ah->iniModesTxGain,372 qca953x_1p1_modes_no_xpa_tx_gain_table);373 else374 INIT_INI_ARRAY(&ah->iniModesTxGain,375 qca953x_1p0_modes_no_xpa_tx_gain_table);376 377 INIT_INI_ARRAY(&ah->iniModesFastClock,378 qca953x_1p0_modes_fast_clock);379 } else if (AR_SREV_9561(ah)) {380 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],381 qca956x_1p0_mac_core);382 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],383 qca956x_1p0_mac_postamble);384 385 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],386 qca956x_1p0_baseband_core);387 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],388 qca956x_1p0_baseband_postamble);389 390 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],391 qca956x_1p0_radio_core);392 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],393 qca956x_1p0_radio_postamble);394 395 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],396 qca956x_1p0_soc_preamble);397 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],398 qca956x_1p0_soc_postamble);399 400 INIT_INI_ARRAY(&ah->iniModesRxGain,401 qca956x_1p0_common_wo_xlna_rx_gain_table);402 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,403 qca956x_1p0_common_wo_xlna_rx_gain_bounds);404 INIT_INI_ARRAY(&ah->iniModesTxGain,405 qca956x_1p0_modes_no_xpa_tx_gain_table);406 407 INIT_INI_ARRAY(&ah->ini_dfs,408 qca956x_1p0_baseband_postamble_dfs_channel);409 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,410 qca956x_1p0_baseband_core_txfir_coeff_japan_2484);411 INIT_INI_ARRAY(&ah->iniModesFastClock,412 qca956x_1p0_modes_fast_clock);413 } else if (AR_SREV_9580(ah)) {414 /* mac */415 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],416 ar9580_1p0_mac_core);417 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],418 ar9580_1p0_mac_postamble);419 420 /* bb */421 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],422 ar9580_1p0_baseband_core);423 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],424 ar9580_1p0_baseband_postamble);425 426 /* radio */427 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],428 ar9580_1p0_radio_core);429 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],430 ar9580_1p0_radio_postamble);431 432 /* soc */433 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],434 ar9580_1p0_soc_preamble);435 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],436 ar9580_1p0_soc_postamble);437 438 /* rx/tx gain */439 INIT_INI_ARRAY(&ah->iniModesRxGain,440 ar9580_1p0_rx_gain_table);441 INIT_INI_ARRAY(&ah->iniModesTxGain,442 ar9580_1p0_low_ob_db_tx_gain_table);443 444 INIT_INI_ARRAY(&ah->iniModesFastClock,445 ar9580_1p0_modes_fast_clock);446 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,447 ar9580_1p0_baseband_core_txfir_coeff_japan_2484);448 INIT_INI_ARRAY(&ah->ini_dfs,449 ar9580_1p0_baseband_postamble_dfs_channel);450 } else if (AR_SREV_9565_11_OR_LATER(ah)) {451 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],452 ar9565_1p1_mac_core);453 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],454 ar9565_1p1_mac_postamble);455 456 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],457 ar9565_1p1_baseband_core);458 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],459 ar9565_1p1_baseband_postamble);460 461 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],462 ar9565_1p1_radio_core);463 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],464 ar9565_1p1_radio_postamble);465 466 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],467 ar9565_1p1_soc_preamble);468 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],469 ar9565_1p1_soc_postamble);470 471 INIT_INI_ARRAY(&ah->iniModesRxGain,472 ar9565_1p1_Common_rx_gain_table);473 INIT_INI_ARRAY(&ah->iniModesTxGain,474 ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);475 476 /* Awake -> Sleep Setting */477 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&478 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {479 INIT_INI_ARRAY(&ah->iniPcieSerdes,480 ar9565_1p1_pciephy_clkreq_disable_L1);481 }482 483 /* Sleep -> Awake Setting */484 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&485 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {486 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,487 ar9565_1p1_pciephy_clkreq_disable_L1);488 }489 490 INIT_INI_ARRAY(&ah->iniModesFastClock,491 ar9565_1p1_modes_fast_clock);492 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,493 ar9565_1p1_baseband_core_txfir_coeff_japan_2484);494 } else if (AR_SREV_9565(ah)) {495 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],496 ar9565_1p0_mac_core);497 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],498 ar9565_1p0_mac_postamble);499 500 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],501 ar9565_1p0_baseband_core);502 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],503 ar9565_1p0_baseband_postamble);504 505 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],506 ar9565_1p0_radio_core);507 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],508 ar9565_1p0_radio_postamble);509 510 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],511 ar9565_1p0_soc_preamble);512 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],513 ar9565_1p0_soc_postamble);514 515 INIT_INI_ARRAY(&ah->iniModesRxGain,516 ar9565_1p0_Common_rx_gain_table);517 INIT_INI_ARRAY(&ah->iniModesTxGain,518 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);519 520 /* Awake -> Sleep Setting */521 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&522 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) {523 INIT_INI_ARRAY(&ah->iniPcieSerdes,524 ar9565_1p0_pciephy_clkreq_disable_L1);525 }526 527 /* Sleep -> Awake Setting */528 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) &&529 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) {530 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,531 ar9565_1p0_pciephy_clkreq_disable_L1);532 }533 534 INIT_INI_ARRAY(&ah->iniModesFastClock,535 ar9565_1p0_modes_fast_clock);536 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,537 ar9565_1p0_baseband_core_txfir_coeff_japan_2484);538 } else {539 /* mac */540 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],541 ar9300_2p2_mac_core);542 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],543 ar9300_2p2_mac_postamble);544 545 /* bb */546 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],547 ar9300_2p2_baseband_core);548 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],549 ar9300_2p2_baseband_postamble);550 551 /* radio */552 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],553 ar9300_2p2_radio_core);554 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],555 ar9300_2p2_radio_postamble);556 557 /* soc */558 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],559 ar9300_2p2_soc_preamble);560 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],561 ar9300_2p2_soc_postamble);562 563 /* rx/tx gain */564 INIT_INI_ARRAY(&ah->iniModesRxGain,565 ar9300Common_rx_gain_table_2p2);566 INIT_INI_ARRAY(&ah->iniModesTxGain,567 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);568 569 /* Load PCIE SERDES settings from INI */570 571 /* Awake Setting */572 573 INIT_INI_ARRAY(&ah->iniPcieSerdes,574 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);575 576 /* Sleep Setting */577 578 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,579 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);580 581 /* Fast clock modal settings */582 INIT_INI_ARRAY(&ah->iniModesFastClock,583 ar9300Modes_fast_clock_2p2);584 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,585 ar9300_2p2_baseband_core_txfir_coeff_japan_2484);586 INIT_INI_ARRAY(&ah->ini_dfs,587 ar9300_2p2_baseband_postamble_dfs_channel);588 }589}590 591static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)592{593 if (AR_SREV_9330_12(ah))594 INIT_INI_ARRAY(&ah->iniModesTxGain,595 ar9331_modes_lowest_ob_db_tx_gain_1p2);596 else if (AR_SREV_9330_11(ah))597 INIT_INI_ARRAY(&ah->iniModesTxGain,598 ar9331_modes_lowest_ob_db_tx_gain_1p1);599 else if (AR_SREV_9340(ah))600 INIT_INI_ARRAY(&ah->iniModesTxGain,601 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);602 else if (AR_SREV_9485_11_OR_LATER(ah))603 INIT_INI_ARRAY(&ah->iniModesTxGain,604 ar9485_modes_lowest_ob_db_tx_gain_1_1);605 else if (AR_SREV_9550(ah))606 INIT_INI_ARRAY(&ah->iniModesTxGain,607 ar955x_1p0_modes_xpa_tx_gain_table);608 else if (AR_SREV_9531_10(ah))609 INIT_INI_ARRAY(&ah->iniModesTxGain,610 qca953x_1p0_modes_xpa_tx_gain_table);611 else if (AR_SREV_9531_11(ah))612 INIT_INI_ARRAY(&ah->iniModesTxGain,613 qca953x_1p1_modes_xpa_tx_gain_table);614 else if (AR_SREV_9531_20(ah))615 INIT_INI_ARRAY(&ah->iniModesTxGain,616 qca953x_2p0_modes_xpa_tx_gain_table);617 else if (AR_SREV_9561(ah))618 INIT_INI_ARRAY(&ah->iniModesTxGain,619 qca956x_1p0_modes_xpa_tx_gain_table);620 else if (AR_SREV_9580(ah))621 INIT_INI_ARRAY(&ah->iniModesTxGain,622 ar9580_1p0_lowest_ob_db_tx_gain_table);623 else if (AR_SREV_9462_21(ah))624 INIT_INI_ARRAY(&ah->iniModesTxGain,625 ar9462_2p1_modes_low_ob_db_tx_gain);626 else if (AR_SREV_9462_20(ah))627 INIT_INI_ARRAY(&ah->iniModesTxGain,628 ar9462_2p0_modes_low_ob_db_tx_gain);629 else if (AR_SREV_9565_11(ah))630 INIT_INI_ARRAY(&ah->iniModesTxGain,631 ar9565_1p1_modes_low_ob_db_tx_gain_table);632 else if (AR_SREV_9565(ah))633 INIT_INI_ARRAY(&ah->iniModesTxGain,634 ar9565_1p0_modes_low_ob_db_tx_gain_table);635 else636 INIT_INI_ARRAY(&ah->iniModesTxGain,637 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);638}639 640static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)641{642 if (AR_SREV_9330_12(ah))643 INIT_INI_ARRAY(&ah->iniModesTxGain,644 ar9331_modes_high_ob_db_tx_gain_1p2);645 else if (AR_SREV_9330_11(ah))646 INIT_INI_ARRAY(&ah->iniModesTxGain,647 ar9331_modes_high_ob_db_tx_gain_1p1);648 else if (AR_SREV_9340(ah))649 INIT_INI_ARRAY(&ah->iniModesTxGain,650 ar9340Modes_high_ob_db_tx_gain_table_1p0);651 else if (AR_SREV_9485_11_OR_LATER(ah))652 INIT_INI_ARRAY(&ah->iniModesTxGain,653 ar9485Modes_high_ob_db_tx_gain_1_1);654 else if (AR_SREV_9580(ah))655 INIT_INI_ARRAY(&ah->iniModesTxGain,656 ar9580_1p0_high_ob_db_tx_gain_table);657 else if (AR_SREV_9550(ah))658 INIT_INI_ARRAY(&ah->iniModesTxGain,659 ar955x_1p0_modes_no_xpa_tx_gain_table);660 else if (AR_SREV_9531(ah)) {661 if (AR_SREV_9531_20(ah))662 INIT_INI_ARRAY(&ah->iniModesTxGain,663 qca953x_2p0_modes_no_xpa_tx_gain_table);664 else if (AR_SREV_9531_11(ah))665 INIT_INI_ARRAY(&ah->iniModesTxGain,666 qca953x_1p1_modes_no_xpa_tx_gain_table);667 else668 INIT_INI_ARRAY(&ah->iniModesTxGain,669 qca953x_1p0_modes_no_xpa_tx_gain_table);670 } else if (AR_SREV_9561(ah))671 INIT_INI_ARRAY(&ah->iniModesTxGain,672 qca956x_1p0_modes_no_xpa_tx_gain_table);673 else if (AR_SREV_9462_21(ah))674 INIT_INI_ARRAY(&ah->iniModesTxGain,675 ar9462_2p1_modes_high_ob_db_tx_gain);676 else if (AR_SREV_9462_20(ah))677 INIT_INI_ARRAY(&ah->iniModesTxGain,678 ar9462_2p0_modes_high_ob_db_tx_gain);679 else if (AR_SREV_9565_11(ah))680 INIT_INI_ARRAY(&ah->iniModesTxGain,681 ar9565_1p1_modes_high_ob_db_tx_gain_table);682 else if (AR_SREV_9565(ah))683 INIT_INI_ARRAY(&ah->iniModesTxGain,684 ar9565_1p0_modes_high_ob_db_tx_gain_table);685 else686 INIT_INI_ARRAY(&ah->iniModesTxGain,687 ar9300Modes_high_ob_db_tx_gain_table_2p2);688}689 690static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)691{692 if (AR_SREV_9330_12(ah))693 INIT_INI_ARRAY(&ah->iniModesTxGain,694 ar9331_modes_low_ob_db_tx_gain_1p2);695 else if (AR_SREV_9330_11(ah))696 INIT_INI_ARRAY(&ah->iniModesTxGain,697 ar9331_modes_low_ob_db_tx_gain_1p1);698 else if (AR_SREV_9340(ah))699 INIT_INI_ARRAY(&ah->iniModesTxGain,700 ar9340Modes_low_ob_db_tx_gain_table_1p0);701 else if (AR_SREV_9531_11(ah))702 INIT_INI_ARRAY(&ah->iniModesTxGain,703 qca953x_1p1_modes_no_xpa_low_power_tx_gain_table);704 else if (AR_SREV_9485_11_OR_LATER(ah))705 INIT_INI_ARRAY(&ah->iniModesTxGain,706 ar9485Modes_low_ob_db_tx_gain_1_1);707 else if (AR_SREV_9580(ah))708 INIT_INI_ARRAY(&ah->iniModesTxGain,709 ar9580_1p0_low_ob_db_tx_gain_table);710 else if (AR_SREV_9561(ah))711 INIT_INI_ARRAY(&ah->iniModesTxGain,712 qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table);713 else if (AR_SREV_9565_11(ah))714 INIT_INI_ARRAY(&ah->iniModesTxGain,715 ar9565_1p1_modes_low_ob_db_tx_gain_table);716 else if (AR_SREV_9565(ah))717 INIT_INI_ARRAY(&ah->iniModesTxGain,718 ar9565_1p0_modes_low_ob_db_tx_gain_table);719 else720 INIT_INI_ARRAY(&ah->iniModesTxGain,721 ar9300Modes_low_ob_db_tx_gain_table_2p2);722}723 724static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)725{726 if (AR_SREV_9330_12(ah))727 INIT_INI_ARRAY(&ah->iniModesTxGain,728 ar9331_modes_high_power_tx_gain_1p2);729 else if (AR_SREV_9330_11(ah))730 INIT_INI_ARRAY(&ah->iniModesTxGain,731 ar9331_modes_high_power_tx_gain_1p1);732 else if (AR_SREV_9340(ah))733 INIT_INI_ARRAY(&ah->iniModesTxGain,734 ar9340Modes_high_power_tx_gain_table_1p0);735 else if (AR_SREV_9485_11_OR_LATER(ah))736 INIT_INI_ARRAY(&ah->iniModesTxGain,737 ar9485Modes_high_power_tx_gain_1_1);738 else if (AR_SREV_9580(ah))739 INIT_INI_ARRAY(&ah->iniModesTxGain,740 ar9580_1p0_high_power_tx_gain_table);741 else if (AR_SREV_9565_11(ah))742 INIT_INI_ARRAY(&ah->iniModesTxGain,743 ar9565_1p1_modes_high_power_tx_gain_table);744 else if (AR_SREV_9565(ah))745 INIT_INI_ARRAY(&ah->iniModesTxGain,746 ar9565_1p0_modes_high_power_tx_gain_table);747 else {748 if (ah->config.tx_gain_buffalo)749 INIT_INI_ARRAY(&ah->iniModesTxGain,750 ar9300Modes_high_power_tx_gain_table_buffalo);751 else752 INIT_INI_ARRAY(&ah->iniModesTxGain,753 ar9300Modes_high_power_tx_gain_table_2p2);754 }755}756 757static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)758{759 if (AR_SREV_9340(ah))760 INIT_INI_ARRAY(&ah->iniModesTxGain,761 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);762 else if (AR_SREV_9580(ah))763 INIT_INI_ARRAY(&ah->iniModesTxGain,764 ar9580_1p0_mixed_ob_db_tx_gain_table);765 else if (AR_SREV_9462_21(ah))766 INIT_INI_ARRAY(&ah->iniModesTxGain,767 ar9462_2p1_modes_mix_ob_db_tx_gain);768 else if (AR_SREV_9462_20(ah))769 INIT_INI_ARRAY(&ah->iniModesTxGain,770 ar9462_2p0_modes_mix_ob_db_tx_gain);771 else772 INIT_INI_ARRAY(&ah->iniModesTxGain,773 ar9300Modes_mixed_ob_db_tx_gain_table_2p2);774}775 776static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)777{778 if (AR_SREV_9485_11_OR_LATER(ah))779 INIT_INI_ARRAY(&ah->iniModesTxGain,780 ar9485Modes_green_ob_db_tx_gain_1_1);781 else if (AR_SREV_9580(ah))782 INIT_INI_ARRAY(&ah->iniModesTxGain,783 ar9580_1p0_type5_tx_gain_table);784 else if (AR_SREV_9561(ah))785 INIT_INI_ARRAY(&ah->iniModesTxGain,786 qca956x_1p0_modes_no_xpa_green_tx_gain_table);787 else if (AR_SREV_9300_22(ah))788 INIT_INI_ARRAY(&ah->iniModesTxGain,789 ar9300Modes_type5_tx_gain_table_2p2);790}791 792static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)793{794 if (AR_SREV_9340(ah))795 INIT_INI_ARRAY(&ah->iniModesTxGain,796 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);797 else if (AR_SREV_9485_11_OR_LATER(ah))798 INIT_INI_ARRAY(&ah->iniModesTxGain,799 ar9485Modes_green_spur_ob_db_tx_gain_1_1);800 else if (AR_SREV_9580(ah))801 INIT_INI_ARRAY(&ah->iniModesTxGain,802 ar9580_1p0_type6_tx_gain_table);803}804 805static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)806{807 if (AR_SREV_9340(ah))808 INIT_INI_ARRAY(&ah->iniModesTxGain,809 ar9340_cus227_tx_gain_table_1p0);810}811 812typedef void (*ath_txgain_tab)(struct ath_hw *ah);813 814static void ar9003_tx_gain_table_apply(struct ath_hw *ah)815{816 static const ath_txgain_tab modes[] = {817 ar9003_tx_gain_table_mode0,818 ar9003_tx_gain_table_mode1,819 ar9003_tx_gain_table_mode2,820 ar9003_tx_gain_table_mode3,821 ar9003_tx_gain_table_mode4,822 ar9003_tx_gain_table_mode5,823 ar9003_tx_gain_table_mode6,824 ar9003_tx_gain_table_mode7,825 };826 int idx = ar9003_hw_get_tx_gain_idx(ah);827 828 if (idx >= ARRAY_SIZE(modes))829 idx = 0;830 831 modes[idx](ah);832}833 834static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)835{836 if (AR_SREV_9330_12(ah))837 INIT_INI_ARRAY(&ah->iniModesRxGain,838 ar9331_common_rx_gain_1p2);839 else if (AR_SREV_9330_11(ah))840 INIT_INI_ARRAY(&ah->iniModesRxGain,841 ar9331_common_rx_gain_1p1);842 else if (AR_SREV_9340(ah))843 INIT_INI_ARRAY(&ah->iniModesRxGain,844 ar9340Common_rx_gain_table_1p0);845 else if (AR_SREV_9485_11_OR_LATER(ah))846 INIT_INI_ARRAY(&ah->iniModesRxGain,847 ar9485_common_rx_gain_1_1);848 else if (AR_SREV_9550(ah)) {849 INIT_INI_ARRAY(&ah->iniModesRxGain,850 ar955x_1p0_common_rx_gain_table);851 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,852 ar955x_1p0_common_rx_gain_bounds);853 } else if (AR_SREV_9531(ah)) {854 INIT_INI_ARRAY(&ah->iniModesRxGain,855 qca953x_1p0_common_rx_gain_table);856 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,857 qca953x_1p0_common_rx_gain_bounds);858 } else if (AR_SREV_9561(ah)) {859 INIT_INI_ARRAY(&ah->iniModesRxGain,860 qca956x_1p0_common_rx_gain_table);861 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,862 qca956x_1p0_common_rx_gain_bounds);863 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,864 qca956x_1p0_xlna_only);865 } else if (AR_SREV_9580(ah))866 INIT_INI_ARRAY(&ah->iniModesRxGain,867 ar9580_1p0_rx_gain_table);868 else if (AR_SREV_9462_21(ah))869 INIT_INI_ARRAY(&ah->iniModesRxGain,870 ar9462_2p1_common_rx_gain);871 else if (AR_SREV_9462_20(ah))872 INIT_INI_ARRAY(&ah->iniModesRxGain,873 ar9462_2p0_common_rx_gain);874 else if (AR_SREV_9565_11(ah))875 INIT_INI_ARRAY(&ah->iniModesRxGain,876 ar9565_1p1_Common_rx_gain_table);877 else if (AR_SREV_9565(ah))878 INIT_INI_ARRAY(&ah->iniModesRxGain,879 ar9565_1p0_Common_rx_gain_table);880 else881 INIT_INI_ARRAY(&ah->iniModesRxGain,882 ar9300Common_rx_gain_table_2p2);883}884 885static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)886{887 if (AR_SREV_9330_12(ah))888 INIT_INI_ARRAY(&ah->iniModesRxGain,889 ar9331_common_wo_xlna_rx_gain_1p2);890 else if (AR_SREV_9330_11(ah))891 INIT_INI_ARRAY(&ah->iniModesRxGain,892 ar9331_common_wo_xlna_rx_gain_1p1);893 else if (AR_SREV_9340(ah))894 INIT_INI_ARRAY(&ah->iniModesRxGain,895 ar9340Common_wo_xlna_rx_gain_table_1p0);896 else if (AR_SREV_9485_11_OR_LATER(ah))897 INIT_INI_ARRAY(&ah->iniModesRxGain,898 ar9485Common_wo_xlna_rx_gain_1_1);899 else if (AR_SREV_9462_21(ah))900 INIT_INI_ARRAY(&ah->iniModesRxGain,901 ar9462_2p1_common_wo_xlna_rx_gain);902 else if (AR_SREV_9462_20(ah))903 INIT_INI_ARRAY(&ah->iniModesRxGain,904 ar9462_2p0_common_wo_xlna_rx_gain);905 else if (AR_SREV_9550(ah)) {906 INIT_INI_ARRAY(&ah->iniModesRxGain,907 ar955x_1p0_common_wo_xlna_rx_gain_table);908 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,909 ar955x_1p0_common_wo_xlna_rx_gain_bounds);910 } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {911 INIT_INI_ARRAY(&ah->iniModesRxGain,912 qca953x_1p0_common_wo_xlna_rx_gain_table);913 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,914 qca953x_1p0_common_wo_xlna_rx_gain_bounds);915 } else if (AR_SREV_9531_20(ah)) {916 INIT_INI_ARRAY(&ah->iniModesRxGain,917 qca953x_2p0_common_wo_xlna_rx_gain_table);918 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,919 qca953x_2p0_common_wo_xlna_rx_gain_bounds);920 } else if (AR_SREV_9561(ah)) {921 INIT_INI_ARRAY(&ah->iniModesRxGain,922 qca956x_1p0_common_wo_xlna_rx_gain_table);923 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,924 qca956x_1p0_common_wo_xlna_rx_gain_bounds);925 } else if (AR_SREV_9580(ah))926 INIT_INI_ARRAY(&ah->iniModesRxGain,927 ar9580_1p0_wo_xlna_rx_gain_table);928 else if (AR_SREV_9565_11(ah))929 INIT_INI_ARRAY(&ah->iniModesRxGain,930 ar9565_1p1_common_wo_xlna_rx_gain_table);931 else if (AR_SREV_9565(ah))932 INIT_INI_ARRAY(&ah->iniModesRxGain,933 ar9565_1p0_common_wo_xlna_rx_gain_table);934 else935 INIT_INI_ARRAY(&ah->iniModesRxGain,936 ar9300Common_wo_xlna_rx_gain_table_2p2);937}938 939static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)940{941 if (AR_SREV_9462_21(ah)) {942 INIT_INI_ARRAY(&ah->iniModesRxGain,943 ar9462_2p1_common_mixed_rx_gain);944 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,945 ar9462_2p1_baseband_core_mix_rxgain);946 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,947 ar9462_2p1_baseband_postamble_mix_rxgain);948 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,949 ar9462_2p1_baseband_postamble_5g_xlna);950 } else if (AR_SREV_9462_20(ah)) {951 INIT_INI_ARRAY(&ah->iniModesRxGain,952 ar9462_2p0_common_mixed_rx_gain);953 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,954 ar9462_2p0_baseband_core_mix_rxgain);955 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,956 ar9462_2p0_baseband_postamble_mix_rxgain);957 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,958 ar9462_2p0_baseband_postamble_5g_xlna);959 }960}961 962static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)963{964 if (AR_SREV_9462_21(ah)) {965 INIT_INI_ARRAY(&ah->iniModesRxGain,966 ar9462_2p1_common_5g_xlna_only_rxgain);967 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,968 ar9462_2p1_baseband_postamble_5g_xlna);969 } else if (AR_SREV_9462_20(ah)) {970 INIT_INI_ARRAY(&ah->iniModesRxGain,971 ar9462_2p0_common_5g_xlna_only_rxgain);972 INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna,973 ar9462_2p0_baseband_postamble_5g_xlna);974 }975}976 977static void ar9003_rx_gain_table_apply(struct ath_hw *ah)978{979 switch (ar9003_hw_get_rx_gain_idx(ah)) {980 case 0:981 default:982 ar9003_rx_gain_table_mode0(ah);983 break;984 case 1:985 ar9003_rx_gain_table_mode1(ah);986 break;987 case 2:988 ar9003_rx_gain_table_mode2(ah);989 break;990 case 3:991 ar9003_rx_gain_table_mode3(ah);992 break;993 }994}995 996/* set gain table pointers according to values read from the eeprom */997static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)998{999 ar9003_tx_gain_table_apply(ah);1000 ar9003_rx_gain_table_apply(ah);1001}1002 1003/*1004 * Helper for ASPM support.1005 *1006 * Disable PLL when in L0s as well as receiver clock when in L1.1007 * This power saving option must be enabled through the SerDes.1008 *1009 * Programming the SerDes must go through the same 288 bit serial shift1010 * register as the other analog registers. Hence the 9 writes.1011 */1012static void ar9003_hw_configpcipowersave(struct ath_hw *ah,1013 bool power_off)1014{1015 unsigned int i;1016 struct ar5416IniArray *array;1017 1018 /*1019 * Increase L1 Entry Latency. Some WB222 boards don't have1020 * this change in eeprom/OTP.1021 *1022 */1023 if (AR_SREV_9462(ah)) {1024 u32 val = ah->config.aspm_l1_fix;1025 if ((val & 0xff000000) == 0x17000000) {1026 val &= 0x00ffffff;1027 val |= 0x27000000;1028 REG_WRITE(ah, 0x570c, val);1029 }1030 }1031 1032 /* Nothing to do on restore for 11N */1033 if (!power_off /* !restore */) {1034 /* set bit 19 to allow forcing of pcie core into L1 state */1035 REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);1036 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);1037 }1038 1039 /*1040 * Configure PCIE after Ini init. SERDES values now come from ini file1041 * This enables PCIe low power mode.1042 */1043 array = power_off ? &ah->iniPcieSerdes :1044 &ah->iniPcieSerdesLowPower;1045 1046 for (i = 0; i < array->ia_rows; i++) {1047 REG_WRITE(ah,1048 INI_RA(array, i, 0),1049 INI_RA(array, i, 1));1050 }1051}1052 1053static void ar9003_hw_init_hang_checks(struct ath_hw *ah)1054{1055 /*1056 * All chips support detection of BB/MAC hangs.1057 */1058 ah->config.hw_hang_checks |= HW_BB_WATCHDOG;1059 ah->config.hw_hang_checks |= HW_MAC_HANG;1060 1061 /*1062 * This is not required for AR9580 1.01063 */1064 if (AR_SREV_9300_22(ah))1065 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;1066 1067 if (AR_SREV_9330(ah))1068 ah->bb_watchdog_timeout_ms = 85;1069 else1070 ah->bb_watchdog_timeout_ms = 25;1071}1072 1073/*1074 * MAC HW hang check1075 * =================1076 *1077 * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.1078 *1079 * The state of each DCU chain (mapped to TX queues) is available from these1080 * DMA debug registers:1081 *1082 * Chain 0 state : Bits 4:0 of AR_DMADBG_41083 * Chain 1 state : Bits 9:5 of AR_DMADBG_41084 * Chain 2 state : Bits 14:10 of AR_DMADBG_41085 * Chain 3 state : Bits 19:15 of AR_DMADBG_41086 * Chain 4 state : Bits 24:20 of AR_DMADBG_41087 * Chain 5 state : Bits 29:25 of AR_DMADBG_41088 * Chain 6 state : Bits 4:0 of AR_DMADBG_51089 * Chain 7 state : Bits 9:5 of AR_DMADBG_51090 * Chain 8 state : Bits 14:10 of AR_DMADBG_51091 * Chain 9 state : Bits 19:15 of AR_DMADBG_51092 *1093 * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.1094 */1095 1096#define NUM_STATUS_READS 501097 1098static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)1099{1100 u32 dma_dbg_chain, dma_dbg_complete;1101 u8 dcu_chain_state, dcu_complete_state;1102 unsigned int dbg_reg, reg_offset;1103 int i;1104 1105 if (queue < 6) {1106 dbg_reg = AR_DMADBG_4;1107 reg_offset = queue * 5;1108 } else {1109 dbg_reg = AR_DMADBG_5;1110 reg_offset = (queue - 6) * 5;1111 }1112 1113 for (i = 0; i < NUM_STATUS_READS; i++) {1114 dma_dbg_chain = REG_READ(ah, dbg_reg);1115 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);1116 1117 dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;1118 dcu_complete_state = dma_dbg_complete & 0x3;1119 1120 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))1121 return false;1122 }1123 1124 ath_dbg(ath9k_hw_common(ah), RESET,1125 "MAC Hang signature found for queue: %d\n", queue);1126 1127 return true;1128}1129 1130static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)1131{1132 u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;1133 u8 dcu_chain_state, dcu_complete_state;1134 bool dcu_wait_frdone = false;1135 unsigned long chk_dcu = 0;1136 unsigned int reg_offset;1137 unsigned int i = 0;1138 1139 dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);1140 dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);1141 dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);1142 1143 dcu_complete_state = dma_dbg_6 & 0x3;1144 if (dcu_complete_state != 0x1)1145 goto exit;1146 1147 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {1148 if (i < 6) {1149 chk_dbg = dma_dbg_4;1150 reg_offset = i * 5;1151 } else {1152 chk_dbg = dma_dbg_5;1153 reg_offset = (i - 6) * 5;1154 }1155 1156 dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;1157 if (dcu_chain_state == 0x6) {1158 dcu_wait_frdone = true;1159 chk_dcu |= BIT(i);1160 }1161 }1162 1163 if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {1164 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {1165 if (ath9k_hw_verify_hang(ah, i))1166 return true;1167 }1168 }1169exit:1170 return false;1171}1172 1173/* Sets up the AR9003 hardware familiy callbacks */1174void ar9003_hw_attach_ops(struct ath_hw *ah)1175{1176 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);1177 struct ath_hw_ops *ops = ath9k_hw_ops(ah);1178 1179 ar9003_hw_init_mode_regs(ah);1180 1181 if (AR_SREV_9003_PCOEM(ah)) {1182 WARN_ON(!ah->iniPcieSerdes.ia_array);1183 WARN_ON(!ah->iniPcieSerdesLowPower.ia_array);1184 }1185 1186 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;1187 priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;1188 priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;1189 1190 ops->config_pci_powersave = ar9003_hw_configpcipowersave;1191 1192 ar9003_hw_attach_phy_ops(ah);1193 ar9003_hw_attach_calib_ops(ah);1194 ar9003_hw_attach_mac_ops(ah);1195 ar9003_hw_attach_aic_ops(ah);1196}1197