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1/*2 * Copyright (c) 2010-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef AR9003_MAC_H18#define AR9003_MAC_H19 20#define AR_DescId 0xffff000021#define AR_DescId_S 1622#define AR_CtrlStat 0x0000400023#define AR_CtrlStat_S 1424#define AR_TxRxDesc 0x0000800025#define AR_TxRxDesc_S 1526#define AR_TxQcuNum 0x00000f0027#define AR_TxQcuNum_S 828 29#define AR_BufLen 0x0fff000030#define AR_BufLen_S 1631 32#define AR_TxDescId 0xffff000033#define AR_TxDescId_S 1634#define AR_TxPtrChkSum 0x0000ffff35 36#define AR_LowRxChain 0x0000400037 38#define AR_Not_Sounding 0x2000000039 40/* ctl 12 */41#define AR_PAPRDChainMask 0x00000e0042#define AR_PAPRDChainMask_S 943 44#define MAP_ISR_S2_CST 645#define MAP_ISR_S2_GTT 646#define MAP_ISR_S2_TIM 347#define MAP_ISR_S2_CABEND 048#define MAP_ISR_S2_DTIMSYNC 749#define MAP_ISR_S2_DTIM 750#define MAP_ISR_S2_TSFOOR 451#define MAP_ISR_S2_BB_WATCHDOG 652 53#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)54 55struct ar9003_rxs {56 u32 ds_info;57 u32 status1;58 u32 status2;59 u32 status3;60 u32 status4;61 u32 status5;62 u32 status6;63 u32 status7;64 u32 status8;65 u32 status9;66 u32 status10;67 u32 status11;68} __packed __aligned(4);69 70/* Transmit Control Descriptor */71struct ar9003_txc {72 u32 info; /* descriptor information */73 u32 link; /* link pointer */74 u32 data0; /* data pointer to 1st buffer */75 u32 ctl3; /* DMA control 3 */76 u32 data1; /* data pointer to 2nd buffer */77 u32 ctl5; /* DMA control 5 */78 u32 data2; /* data pointer to 3rd buffer */79 u32 ctl7; /* DMA control 7 */80 u32 data3; /* data pointer to 4th buffer */81 u32 ctl9; /* DMA control 9 */82 u32 ctl10; /* DMA control 10 */83 u32 ctl11; /* DMA control 11 */84 u32 ctl12; /* DMA control 12 */85 u32 ctl13; /* DMA control 13 */86 u32 ctl14; /* DMA control 14 */87 u32 ctl15; /* DMA control 15 */88 u32 ctl16; /* DMA control 16 */89 u32 ctl17; /* DMA control 17 */90 u32 ctl18; /* DMA control 18 */91 u32 ctl19; /* DMA control 19 */92 u32 ctl20; /* DMA control 20 */93 u32 ctl21; /* DMA control 21 */94 u32 ctl22; /* DMA control 22 */95 u32 ctl23; /* DMA control 23 */96 u32 pad[8]; /* pad to cache line (128 bytes/32 dwords) */97} __packed __aligned(4);98 99struct ar9003_txs {100 u32 ds_info;101 u32 status1;102 u32 status2;103 u32 status3;104 u32 status4;105 u32 status5;106 u32 status6;107 u32 status7;108 u32 status8;109} __packed __aligned(4);110 111void ar9003_hw_attach_mac_ops(struct ath_hw *hw);112void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);113void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,114 enum ath9k_rx_qtype qtype);115 116int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,117 struct ath_rx_status *rxs,118 void *buf_addr);119void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);120void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,121 u32 ts_paddr_start,122 u16 size);123#endif124