1321 lines · c
1/*2 * Copyright (c) 2010-2011 Atheros Communications, Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef AR9003_PHY_H18#define AR9003_PHY_H19 20/*21 * Channel Register Map22 */23#define AR_CHAN_BASE 0x980024 25#define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)26#define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)27#define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)28#define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)29#define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)30#define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)31#define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)32#define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)33#define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)34#define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0)35#define AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT 1636 37#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF0000038#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 2039 40#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF41#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 042 43#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x4000000044#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 3045 46#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x8000000047#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 3148 49#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x400000050#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 2651 52#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */53#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 1754#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF55#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 056#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x0000010057#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 858#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC000059#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 1860 61#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x2000000062#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 2963 64#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x8000000065#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 3166 67#define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20)68 69#define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24)70#define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28)71#define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c)72 73#define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30)74#define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34)75#define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38)76#define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c)77#define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80)78#define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84)79 80#define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0)81#define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4)82#define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0)83#define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4)84#define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8)85#define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc)86 87/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */88#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)89#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)90#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)91#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)92#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)93#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)94 95#define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0)96#define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4)97#define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8)98#define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300)99 100/*101 * Channel Field Definitions102 */103#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000104#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff105#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000106#define AR_PHY_TIMING3_DSC_MAN_S 17107#define AR_PHY_TIMING3_DSC_EXP 0x0001E000108#define AR_PHY_TIMING3_DSC_EXP_S 13109#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000110#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12111#define AR_PHY_TIMING4_DO_CAL 0x10000112 113#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000114#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28115#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000116#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29117 118#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000119#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30120#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000121#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31122 123#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000124#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000125#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001126#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00127#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8128#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000129#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14130#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000131#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21132#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F133#define AR_PHY_SFCORR_M2COUNT_THR_S 0134#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000135#define AR_PHY_SFCORR_M1_THRESH_S 17136#define AR_PHY_SFCORR_M2_THRESH 0x7F000000137#define AR_PHY_SFCORR_M2_THRESH_S 24138#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F139#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0140#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80141#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7142#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000143#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14144#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000145#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21146#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000147#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28148#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28149#define AR_PHY_EXT_CCA_THRESH62 0x007F0000150#define AR_PHY_EXT_CCA_THRESH62_S 16151#define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX 0x0000FF00152#define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX_S 8153#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000154#define AR_PHY_EXT_MINCCA_PWR_S 16155#define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L156#define AR_PHY_EXT_CYCPWR_THR1_S 9157#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE158#define AR_PHY_TIMING5_CYCPWR_THR1_S 1159#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001160#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0161#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000162#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16163#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)164#define AR_PHY_TIMING5_RSSI_THR1A_S 16165#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)166#define AR_PHY_RADAR_0_ENA 0x00000001167#define AR_PHY_RADAR_0_FFT_ENA 0x80000000168#define AR_PHY_RADAR_0_INBAND 0x0000003e169#define AR_PHY_RADAR_0_INBAND_S 1170#define AR_PHY_RADAR_0_PRSSI 0x00000FC0171#define AR_PHY_RADAR_0_PRSSI_S 6172#define AR_PHY_RADAR_0_HEIGHT 0x0003F000173#define AR_PHY_RADAR_0_HEIGHT_S 12174#define AR_PHY_RADAR_0_RRSSI 0x00FC0000175#define AR_PHY_RADAR_0_RRSSI_S 18176#define AR_PHY_RADAR_0_FIRPWR 0x7F000000177#define AR_PHY_RADAR_0_FIRPWR_S 24178#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000179#define AR_PHY_RADAR_1_USE_FIR128 0x00400000180#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000181#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16182#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000183#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000184#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000185#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00186#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8187#define AR_PHY_RADAR_1_MAXLEN 0x000000FF188#define AR_PHY_RADAR_1_MAXLEN_S 0189#define AR_PHY_RADAR_EXT_ENA 0x00004000190#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000191#define AR_PHY_RADAR_DC_PWR_THRESH_S 15192#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000193#define AR_PHY_RADAR_LB_DC_CAP_S 23194#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)195#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6196#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)197#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12198#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19199#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f200#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0201#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5202#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008203#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3204#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F205#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0206#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80207#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7208#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000209#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000210#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15211#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000212#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22213 214/*215 * MRC Register Map216 */217#define AR_MRC_BASE 0x9c00218 219#define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0)220#define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4)221#define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8)222#define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)223#define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10)224#define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14)225#define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18)226#define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)227#define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)228 229#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0230#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5231#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F232#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0233#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B 0x00FE0000234#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_S 17235#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B 0x0001F000236#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B_S 12237 238#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0239#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5240#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F241#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0242#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B 0x00FE0000243#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_S 17244#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B 0x0001F000245#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B_S 12246 247 248/*249 * MRC Feild Definitions250 */251#define AR_PHY_SGI_DSC_MAN 0x0007FFF0252#define AR_PHY_SGI_DSC_MAN_S 4253#define AR_PHY_SGI_DSC_EXP 0x0000000F254#define AR_PHY_SGI_DSC_EXP_S 0255/*256 * BBB Register Map257 */258#define AR_BBB_BASE 0x9d00259 260/*261 * AGC Register Map262 */263#define AR_AGC_BASE 0x9e00264 265#define AR_PHY_SETTLING (AR_AGC_BASE + 0x0)266#define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)267#define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8)268#define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc)269#define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10)270#define AR_PHY_AGC (AR_AGC_BASE + 0x14)271#define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)272#define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)273#define AR_PHY_CCA_CTRL_0 (AR_AGC_BASE + 0x20)274#define AR_PHY_RESTART (AR_AGC_BASE + 0x24)275 276/*277 * Antenna Diversity settings278 */279#define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)280#define AR_ANT_DIV_CTRL_ALL 0x7e000000281#define AR_ANT_DIV_CTRL_ALL_S 25282#define AR_ANT_DIV_ENABLE 0x1000000283#define AR_ANT_DIV_ENABLE_S 24284 285 286#define AR_PHY_ANT_FAST_DIV_BIAS 0x00007e00287#define AR_PHY_ANT_FAST_DIV_BIAS_S 9288#define AR_PHY_ANT_SW_RX_PROT 0x00800000289#define AR_PHY_ANT_SW_RX_PROT_S 23290#define AR_PHY_ANT_DIV_LNADIV 0x01000000291#define AR_PHY_ANT_DIV_LNADIV_S 24292#define AR_PHY_ANT_DIV_ALT_LNACONF 0x06000000293#define AR_PHY_ANT_DIV_ALT_LNACONF_S 25294#define AR_PHY_ANT_DIV_MAIN_LNACONF 0x18000000295#define AR_PHY_ANT_DIV_MAIN_LNACONF_S 27296#define AR_PHY_ANT_DIV_ALT_GAINTB 0x20000000297#define AR_PHY_ANT_DIV_ALT_GAINTB_S 29298#define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000299#define AR_PHY_ANT_DIV_MAIN_GAINTB_S 30300 301#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)302#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)303#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)304#define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38)305#define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c)306#define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40)307#define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)308#define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)309#define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)310#define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)311 312#define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)313#define AR_FAST_DIV_ENABLE 0x2000314#define AR_FAST_DIV_ENABLE_S 13315 316#define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)317#define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)318 319#define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc)320#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe321#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1322#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000323#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29324#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001325#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0326#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00327#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9328 329#define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0)330#define AR_PHY_MRC_CCK_ENABLE 0x00000001331#define AR_PHY_MRC_CCK_ENABLE_S 0332#define AR_PHY_MRC_CCK_MUX_REG 0x00000002333#define AR_PHY_MRC_CCK_MUX_REG_S 1334 335#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)336 337#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110338#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115339#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125340#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125341#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -60342#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -60343#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95344#define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100345 346#define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127347#define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127348#define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60349#define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127350#define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127351#define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60352 353#define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118354 355#define AR9300_EXT_LNA_CTL_GPIO_AR9485 9356 357/*358 * AGC Field Definitions359 */360#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000361#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18362#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00363#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10364#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F365#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0366#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000367#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17368#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000369#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12370#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0371#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6372#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F373#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0374#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000375#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12376#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000377#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18378#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80379#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7380#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000381#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14382#define AR_PHY_SETTLING_SWITCH 0x00003F80383#define AR_PHY_SETTLING_SWITCH_S 7384#define AR_PHY_DESIRED_SZ_ADC 0x000000FF385#define AR_PHY_DESIRED_SZ_ADC_S 0386#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00387#define AR_PHY_DESIRED_SZ_PGA_S 8388#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000389#define AR_PHY_DESIRED_SZ_TOT_DES_S 20390#define AR_PHY_MINCCA_PWR 0x1FF00000391#define AR_PHY_MINCCA_PWR_S 20392#define AR_PHY_CCA_THRESH62 0x0007F000393#define AR_PHY_CCA_THRESH62_S 12394#define AR9280_PHY_MINCCA_PWR 0x1FF00000395#define AR9280_PHY_MINCCA_PWR_S 20396#define AR9280_PHY_CCA_THRESH62 0x000FF000397#define AR9280_PHY_CCA_THRESH62_S 12398#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF399#define AR_PHY_EXT_CCA0_THRESH62_S 0400#define AR_PHY_EXT_CCA0_THRESH62_1 0x000001FF401#define AR_PHY_EXT_CCA0_THRESH62_1_S 0402#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F403#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0404#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0405#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6406#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000407 408#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200409#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9410#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00411#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10412 413#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000414#define AR_PHY_AGC_QUICK_DROP 0x03c00000415#define AR_PHY_AGC_QUICK_DROP_S 22416#define AR_PHY_AGC_COARSE_LOW 0x00007F80417#define AR_PHY_AGC_COARSE_LOW_S 7418#define AR_PHY_AGC_COARSE_HIGH 0x003F8000419#define AR_PHY_AGC_COARSE_HIGH_S 15420#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F421#define AR_PHY_AGC_COARSE_PWR_CONST_S 0422#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000423#define AR_PHY_FIND_SIG_FIRSTEP_S 12424#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000425#define AR_PHY_FIND_SIG_FIRPWR_S 18426#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25427#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)428#define AR_PHY_FIND_SIG_RELPWR_S 6429#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11430#define AR_PHY_FIND_SIG_RELSTEP 0x1f431#define AR_PHY_FIND_SIG_RELSTEP_S 0432#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5433#define AR_PHY_RESTART_ENABLE_DIV_M2FLAG 0x00200000434#define AR_PHY_RESTART_ENABLE_DIV_M2FLAG_S 21435#define AR_PHY_RESTART_DIV_GC 0x001C0000436#define AR_PHY_RESTART_DIV_GC_S 18437#define AR_PHY_RESTART_ENA 0x01438#define AR_PHY_DC_RESTART_DIS 0x40000000439 440#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000441#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24442#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000443#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16444 445#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000446#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24447 448/*449 * SM Register Map450 */451#define AR_SM_BASE 0xa200452 453#define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)454#define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)455#define AR_PHY_MODE (AR_SM_BASE + 0x8)456#define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)457#define AR_PHY_SPUR_MASK_A(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x18 : 0x20))458#define AR_PHY_SPUR_MASK_B(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x1c : 0x24))459#define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)460#define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)461#define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)462#define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)463#define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)464#define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)465#define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)466#define AR_PHY_RIFS (AR_SM_BASE + 0x44)467#define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)468#define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)469 470#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)471#define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)472#define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)473#define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)474#define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)475#define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)476#define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)477#define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)478#define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)479#define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)480#define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)481#define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)482#define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)483#define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)484#define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)485#define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)486#define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)487#define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)488#define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)489 490#define AR_PHY_FLC_PWR_THRESH 7491#define AR_PHY_FLC_PWR_THRESH_S 0492 493#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3494#define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0495 496#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00497#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10498#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF499#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0500 501#define AR_PHY_TEST(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x15c : 0x160))502 503#define AR_PHY_TEST_BBB_OBS_SEL 0x780000504#define AR_PHY_TEST_BBB_OBS_SEL_S 19505 506#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23507#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)508 509#define AR_PHY_TEST_CHAIN_SEL 0xC0000000510#define AR_PHY_TEST_CHAIN_SEL_S 30511 512#define AR_PHY_TEST_CTL_STATUS(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x160 : 0x164))513#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1514#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0515#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C516#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2517#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60518#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5519#define AR_PHY_TEST_CTL_TSTADC_EN 0x100520#define AR_PHY_TEST_CTL_TSTADC_EN_S 8521#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00522#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10523#define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000524#define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29525 526 527#define AR_PHY_TSTDAC(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x164 : 0x168))528 529#define AR_PHY_CHAN_STATUS(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x168 : 0x16c))530 531#define AR_PHY_CHAN_INFO_MEMORY(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x16c : 0x170))532#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008533#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3534 535#define AR_PHY_CHNINFO_NOISEPWR(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x170 : 0x174))536#define AR_PHY_CHNINFO_GAINDIFF(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x174 : 0x178))537#define AR_PHY_CHNINFO_FINETIM(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x178 : 0x17c))538#define AR_PHY_CHAN_INFO_GAIN_0(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x17c : 0x180))539#define AR_PHY_SCRAMBLER_SEED(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x184 : 0x190))540#define AR_PHY_CCK_TX_CTRL(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x188 : 0x194))541 542#define AR_PHY_HEAVYCLIP_CTL(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x198 : 0x1a4))543#define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)544#define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)545#define AR_PHY_HEAVYCLIP_1 (AR_SM_BASE + 0x19c)546#define AR_PHY_HEAVYCLIP_2 (AR_SM_BASE + 0x1a0)547#define AR_PHY_HEAVYCLIP_3 (AR_SM_BASE + 0x1a4)548#define AR_PHY_HEAVYCLIP_4 (AR_SM_BASE + 0x1a8)549#define AR_PHY_HEAVYCLIP_5 (AR_SM_BASE + 0x1ac)550#define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)551 552#define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))553 554#define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)555#define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)556 557#define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)558#define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e559#define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1560#define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001561#define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0562 563#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)564#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)565#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)566 567#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)568#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)569#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)570#define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000571#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16572 573#define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)574#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000575#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25576 577#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)578#define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff579#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0580#define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00581#define AR_PHY_TPC_18_VOLT_CAL_VALUE_S 8582 583#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)584#define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000585#define AR_PHY_TPC_19_ALPHA_VOLT_S 16586#define AR_PHY_TPC_19_ALPHA_THERM 0xff587#define AR_PHY_TPC_19_ALPHA_THERM_S 0588 589#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)590#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001591#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0592#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e593#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1594#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030595#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4596#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0597#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6598#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00599#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10600#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000601#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14602#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000603#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18604#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000605#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22606#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000607#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24608 609 610#define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)611 612#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)613 614#define AR_PHY_TX_IQCAL_CONTROL_0(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \615 0x3c4 : 0x444))616#define AR_PHY_TX_IQCAL_CONTROL_1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \617 0x3c8 : 0x448))618#define AR_PHY_TX_IQCAL_START(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \619 0x3c4 : 0x440))620#define AR_PHY_TX_IQCAL_STATUS_B0(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? \621 0x3f0 : 0x48c))622#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_ah, _i) (AR_SM_BASE + \623 (AR_SREV_9485(_ah) ? \624 0x3d0 : 0x450) + ((_i) << 2))625#define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)626 627#define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)628#define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)629#define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8)630#define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc)631#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)632#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)633#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)634 635#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)636#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff637#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0638 639#define AR_PHY_BB_THERM_ADC_3 (AR_SM_BASE + 0x250)640#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN 0x0001ff00641#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN_S 8642#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET 0x000000ff643#define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_S 0644 645#define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)646#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff647#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0648#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00649#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8650 651#define AR_PHY_65NM_CH0_TXRF3 0x16048652#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001e653#define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1654 655#define AR_PHY_65NM_CH0_SYNTH4 0x1608c656#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)657#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)658#define AR_PHY_65NM_CH0_SYNTH7 0x16098659#define AR_PHY_65NM_CH0_SYNTH12 0x160ac660#define AR_PHY_65NM_CH0_BIAS1 0x160c0661#define AR_PHY_65NM_CH0_BIAS2 0x160c4662#define AR_PHY_65NM_CH0_BIAS4 0x160cc663#define AR_PHY_65NM_CH0_RXTX2 0x16104664#define AR_PHY_65NM_CH1_RXTX2 0x16504665#define AR_PHY_65NM_CH2_RXTX2 0x16904666#define AR_PHY_65NM_CH0_RXTX4 0x1610c667#define AR_PHY_65NM_CH1_RXTX4 0x1650c668#define AR_PHY_65NM_CH2_RXTX4 0x1690c669 670#define AR_PHY_65NM_CH0_BB1 0x16140671#define AR_PHY_65NM_CH0_BB2 0x16144672#define AR_PHY_65NM_CH0_BB3 0x16148673#define AR_PHY_65NM_CH1_BB1 0x16540674#define AR_PHY_65NM_CH1_BB2 0x16544675#define AR_PHY_65NM_CH1_BB3 0x16548676#define AR_PHY_65NM_CH2_BB1 0x16940677#define AR_PHY_65NM_CH2_BB2 0x16944678#define AR_PHY_65NM_CH2_BB3 0x16948679 680#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000681#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19682#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004683#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2684#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008685#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3686 687#define AR_CH0_TOP(_ah) (AR_SREV_9300(_ah) ? 0x16288 : \688 (((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x1628c : 0x16280)))689#define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)690#define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)691 692#define AR_SWITCH_TABLE_COM_ALL (0xffff)693#define AR_SWITCH_TABLE_COM_ALL_S (0)694#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)695#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)696#define AR_SWITCH_TABLE_COM_AR9550_ALL (0xffffff)697#define AR_SWITCH_TABLE_COM_AR9550_ALL_S (0)698#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)699#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)700#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)701 702#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)703#define AR_SWITCH_TABLE_COM2_ALL_S (0)704 705#define AR_SWITCH_TABLE_ALL (0xfff)706#define AR_SWITCH_TABLE_ALL_S (0)707 708#define AR_CH0_THERM(_ah) (AR_SREV_9300(_ah) ? 0x16290 :\709 ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16294 : 0x1628c))710#define AR_CH0_THERM_XPABIASLVL_MSB 0x3711#define AR_CH0_THERM_XPABIASLVL_MSB_S 0712#define AR_CH0_THERM_XPASHORT2GND 0x4713#define AR_CH0_THERM_XPASHORT2GND_S 2714 715#define AR_CH0_THERM_LOCAL 0x80000000716#define AR_CH0_THERM_START 0x20000000717#define AR_CH0_THERM_SAR_ADC_OUT 0x0000ff00718#define AR_CH0_THERM_SAR_ADC_OUT_S 8719 720#define AR_CH0_TOP2(_ah) (AR_SREV_9300(_ah) ? 0x1628c : \721 (AR_SREV_9462(_ah) ? 0x16290 : 0x16284))722#define AR_CH0_TOP2_XPABIASLVL (AR_SREV_9561(ah) ? 0x1e00 : 0xf000)723#define AR_CH0_TOP2_XPABIASLVL_S (AR_SREV_9561(ah) ? 9 : 12)724 725#define AR_CH0_XTAL(_ah) (AR_SREV_9300(_ah) ? 0x16294 : \726 ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16298 : \727 (AR_SREV_9561(_ah) ? 0x162c0 : 0x16290)))728#define AR_CH0_XTAL_CAPINDAC 0x7f000000729#define AR_CH0_XTAL_CAPINDAC_S 24730#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000731#define AR_CH0_XTAL_CAPOUTDAC_S 17732 733#define AR_PHY_PMU1(_ah) ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16340 : \734 (AR_SREV_9561(_ah) ? 0x16cc0 : 0x16c40))735#define AR_PHY_PMU1_PWD 0x1736#define AR_PHY_PMU1_PWD_S 0737 738#define AR_PHY_PMU2(_ah) ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16344 : \739 (AR_SREV_9561(_ah) ? 0x16cc4 : 0x16c44))740#define AR_PHY_PMU2_PGM 0x00200000741#define AR_PHY_PMU2_PGM_S 21742 743#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000744#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19745#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000746#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22747#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000748#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29749#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000750#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24751#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000752#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26753#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001754#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0755#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002756#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1757 758/*759 * SM Field Definitions760 */761#define AR_PHY_CL_CAL_ENABLE 0x00000002762#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001763#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000764#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22765 766#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000767 768#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000769#define AR_PHY_FCAL20_CAP_STATUS_0_S 20770 771#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */772#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */773#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */774#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */775#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */776#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */777#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/778#define AR_PHY_GC_DYN2040_PRI_CH_S 4779#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */780#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */781#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */782#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */783#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */784#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */785#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */786#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */787 788#define AR_PHY_CALMODE_IQ 0x00000000789#define AR_PHY_CALMODE_ADC_GAIN 0x00000001790#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002791#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003792#define AR_PHY_SWAP_ALT_CHAIN 0x00000040793#define AR_PHY_MODE_OFDM 0x00000000794#define AR_PHY_MODE_CCK 0x00000001795#define AR_PHY_MODE_DYNAMIC 0x00000004796#define AR_PHY_MODE_DYNAMIC_S 2797#define AR_PHY_MODE_HALF 0x00000020798#define AR_PHY_MODE_QUARTER 0x00000040799#define AR_PHY_MAC_CLK_MODE 0x00000080800#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100801#define AR_PHY_MODE_SVD_HALF 0x00000200802#define AR_PHY_ACTIVE_EN 0x00000001803#define AR_PHY_ACTIVE_DIS 0x00000000804#define AR_PHY_FORCE_XPA_CFG 0x000000001805#define AR_PHY_FORCE_XPA_CFG_S 0806#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000807#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24808#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000809#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16810#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00811#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8812#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF813#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0814#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000815#define AR_PHY_TX_END_TO_A2_RX_ON_S 16816#define AR_PHY_TX_END_DATA_START 0x000000FF817#define AR_PHY_TX_END_DATA_START_S 0818#define AR_PHY_TX_END_PA_ON 0x0000FF00819#define AR_PHY_TX_END_PA_ON_S 8820#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F821#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0822#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0823#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4824#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00825#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10826#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000827#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16828#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000829#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22830#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000831#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14832#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000833#define AR_PHY_TPCRG1_PD_GAIN_1_S 16834#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000835#define AR_PHY_TPCRG1_PD_GAIN_2_S 18836#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000837#define AR_PHY_TPCRG1_PD_GAIN_3_S 20838#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e839#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1840#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001841#define AR_PHY_TXGAIN_FORCE 0x00000001842#define AR_PHY_TXGAIN_FORCE_S 0843#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00844#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10845#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000846#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14847#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000848#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22849#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0850#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6851#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e852#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1853 854#define AR_PHY_POWER_TX_RATE_MAX 0x993c855#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040856#define PHY_AGC_CLR 0x10000000857#define RFSILENT_BB 0x00002000858#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF859#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800860#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320861#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001862#define AR_PHY_RX_DELAY_DELAY 0x00003FFF863#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010864 865#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001866#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0867#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002868#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1869#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0870#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4871#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00872#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8873#define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000874#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16875#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000876#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 28877#define AR_PHY_SPECTRAL_SCAN_PRIORITY 0x20000000878#define AR_PHY_SPECTRAL_SCAN_PRIORITY_S 29879#define AR_PHY_SPECTRAL_SCAN_USE_ERR5 0x40000000880#define AR_PHY_SPECTRAL_SCAN_USE_ERR5_S 30881#define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT 0x80000000882#define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT_S 31883 884#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004885#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001886#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0887#define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E888#define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1889#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080890#define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7891#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS 0x00000001892#define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S 0893#define AR_PHY_RTT_SW_RTT_TABLE_WRITE 0x00000002894#define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S 1895#define AR_PHY_RTT_SW_RTT_TABLE_ADDR 0x0000001C896#define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S 2897#define AR_PHY_RTT_SW_RTT_TABLE_DATA 0xFFFFFFF0898#define AR_PHY_RTT_SW_RTT_TABLE_DATA_S 4899#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000900#define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31901#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000902#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18903#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001904#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0905 906#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001907#define AR_PHY_CALIBRATED_GAINS_0 0x3e908#define AR_PHY_CALIBRATED_GAINS_0_S 1909 910#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff911#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0912#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000913#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14914 915#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000916#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28917#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR 0x20000000918#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR_S 29919 920#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000921#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30922 923/*924 * Channel 1 Register Map925 */926#define AR_CHAN1_BASE 0xa800927 928#define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30)929#define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0)930#define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4)931 932#define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8)933#define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300)934#define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc)935 936/*937 * Channel 1 Field Definitions938 */939#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000940#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16941 942/*943 * AGC 1 Register Map944 */945#define AR_AGC1_BASE 0xae00946 947#define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4)948#define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18)949#define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c)950#define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20)951#define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180)952#define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184)953#define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200)954 955/*956 * AGC 1 Field Definitions957 */958#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000959#define AR_PHY_CH1_MINCCA_PWR_S 20960 961/*962 * SM 1 Register Map963 */964#define AR_SM1_BASE 0xb200965 966#define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)967#define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)968#define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)969#define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)970#define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)971#define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)972#define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)973#define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)974#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)975#define AR_PHY_PDADC_TAB_1(_ah) (AR_SM1_BASE + (AR_SREV_9462_20_OR_LATER(_ah) ? \976 0x280 : 0x240))977#define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240)978#define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff979#define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0980#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)981#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2))982 983#define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + ((i) ? \984 AR_SM1_BASE : AR_SM_BASE))985#define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + ((i) ? \986 AR_SM1_BASE : AR_SM_BASE))987/*988 * Channel 2 Register Map989 */990#define AR_CHAN2_BASE 0xb800991 992#define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30)993#define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0)994#define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4)995 996#define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8)997#define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300)998#define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc)999 1000/*1001 * Channel 2 Field Definitions1002 */1003#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF00001004#define AR_PHY_CH2_EXT_MINCCA_PWR_S 161005/*1006 * AGC 2 Register Map1007 */1008#define AR_AGC2_BASE 0xbe001009 1010#define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4)1011#define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18)1012#define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c)1013#define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20)1014#define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180)1015 1016/*1017 * AGC 2 Field Definitions1018 */1019#define AR_PHY_CH2_MINCCA_PWR 0x1FF000001020#define AR_PHY_CH2_MINCCA_PWR_S 201021 1022/*1023 * SM 2 Register Map1024 */1025#define AR_SM2_BASE 0xc2001026 1027#define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84)1028#define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0)1029#define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4)1030#define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100)1031#define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180)1032#define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204)1033#define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)1034#define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)1035#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)1036#define AR_PHY_TPC_19_B2 (AR_SM2_BASE + 0x240)1037#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)1038#define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))1039 1040#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x000000011041 1042/* GLB Registers */1043#define AR_GLB_BASE 0x200001044#define AR_GLB_GPIO_CONTROL (AR_GLB_BASE)1045#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)1046#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \1047 (AR_SREV_9462_20_OR_LATER(_ah) ? 0x4c : 0x50))1048#define AR_GLB_STATUS (AR_GLB_BASE + 0x48)1049 1050/*1051 * Misc helper defines1052 */1053#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)1054 1055#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))1056#define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))1057#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))1058#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))1059 1060#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))1061#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))1062#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))1063 1064#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))1065#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))1066#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))1067#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))1068#define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))1069#define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))1070#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))1071#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))1072 1073#define AR_PHY_WATCHDOG_NON_IDLE_ENABLE 0x000000011074#define AR_PHY_WATCHDOG_IDLE_ENABLE 0x000000021075#define AR_PHY_WATCHDOG_IDLE_MASK 0xFFFF00001076#define AR_PHY_WATCHDOG_NON_IDLE_MASK 0x0000FFFC1077 1078#define AR_PHY_WATCHDOG_RST_ENABLE 0x000000021079#define AR_PHY_WATCHDOG_IRQ_ENABLE 0x000000041080#define AR_PHY_WATCHDOG_CNTL2_MASK 0xFFFFFFF91081 1082#define AR_PHY_WATCHDOG_INFO 0x000000071083#define AR_PHY_WATCHDOG_INFO_S 01084#define AR_PHY_WATCHDOG_DET_HANG 0x000000081085#define AR_PHY_WATCHDOG_DET_HANG_S 31086#define AR_PHY_WATCHDOG_RADAR_SM 0x000000F01087#define AR_PHY_WATCHDOG_RADAR_SM_S 41088#define AR_PHY_WATCHDOG_RX_OFDM_SM 0x00000F001089#define AR_PHY_WATCHDOG_RX_OFDM_SM_S 81090#define AR_PHY_WATCHDOG_RX_CCK_SM 0x0000F0001091#define AR_PHY_WATCHDOG_RX_CCK_SM_S 121092#define AR_PHY_WATCHDOG_TX_OFDM_SM 0x000F00001093#define AR_PHY_WATCHDOG_TX_OFDM_SM_S 161094#define AR_PHY_WATCHDOG_TX_CCK_SM 0x00F000001095#define AR_PHY_WATCHDOG_TX_CCK_SM_S 201096#define AR_PHY_WATCHDOG_AGC_SM 0x0F0000001097#define AR_PHY_WATCHDOG_AGC_SM_S 241098#define AR_PHY_WATCHDOG_SRCH_SM 0xF00000001099#define AR_PHY_WATCHDOG_SRCH_SM_S 281100 1101#define AR_PHY_WATCHDOG_STATUS_CLR 0x000000081102 1103/*1104 * PAPRD registers1105 */1106#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)1107 1108#define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4)1109#define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff1110#define AR_PHY_PAPRD_AM2AM_MASK_S 01111 1112#define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8)1113#define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff1114#define AR_PHY_PAPRD_AM2PM_MASK_S 01115 1116#define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec)1117#define AR_PHY_PAPRD_HT40_MASK 0x01ffffff1118#define AR_PHY_PAPRD_HT40_MASK_S 01119 1120#define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0)1121#define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0)1122#define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0)1123#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x000000011124#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 01125#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x000000021126#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S 11127#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf80000001128#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 271129 1130#define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4)1131#define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4)1132#define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4)1133#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x000000011134#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 01135#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x000000021136#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S 11137#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x000000041138#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S 21139#define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f81140#define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S 31141#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe001142#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S 91143#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe00001144#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 171145 1146#define AR_PHY_PAPRD_TRAINER_CNTL1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x580 : 0x490))1147 1148#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x000000011149#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 01150#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e1151#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 11152#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x000001001153#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 81154#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x000002001155#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 91156#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x000004001157#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 101158#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x000008001159#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 111160#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f0001161#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 121162 1163#define AR_PHY_PAPRD_TRAINER_CNTL2(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x584 : 0x494))1164 1165#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF1166#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 01167 1168#define AR_PHY_PAPRD_TRAINER_CNTL3(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x588 : 0x498))1169 1170#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f1171#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 01172#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc01173#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 61174#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f0001175#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 121176#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e00001177#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 171178#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f000001179#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 201180#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f0000001181#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 241182#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x200000001183#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 291184 1185#define AR_PHY_PAPRD_TRAINER_CNTL4(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x58c : 0x49c))1186 1187#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff00001188#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 161189#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f0001190#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 121191#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff1192#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 01193 1194#define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100)1195#define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104)1196#define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108)1197#define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c)1198#define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110)1199#define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114)1200#define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118)1201#define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c)1202#define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF1203#define AR_PHY_PAPRD_PRE_POST_SCALING_S 01204 1205#define AR_PHY_PAPRD_TRAINER_STAT1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x590 : 0x4a0))1206 1207#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x000000011208#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 01209#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x000000021210#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 11211#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x000000041212#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 21213#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x000000081214#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 31215#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f01216#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 41217#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe001218#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 91219 1220#define AR_PHY_PAPRD_TRAINER_STAT2(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x594 : 0x4a4))1221 1222#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff1223#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 01224#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f00001225#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 161226#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x006000001227#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 211228 1229#define AR_PHY_PAPRD_TRAINER_STAT3(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x598 : 0x4a8))1230 1231#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff1232#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 01233 1234#define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120)1235#define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120)1236#define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120)1237 1238#define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)1239#define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)1240#define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)1241#define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF1242#define AR_PHY_PA_GAIN123_PA_GAIN1_S 01243 1244#define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)1245#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F1246#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 01247 1248#define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)1249#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F001250#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 81251 1252#define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)1253#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F001254#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 81255 1256#define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f1257#define AR_PHY_CL_TAB_CL_GAIN_MOD_S 01258 1259#define AR_BTCOEX_WL_LNADIV 0x1a641260#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD 0x00003FFF1261#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S 01262#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY 0x000040001263#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S 141264#define AR_BTCOEX_WL_LNADIV_FORCE_ON 0x000080001265#define AR_BTCOEX_WL_LNADIV_FORCE_ON_S 151266#define AR_BTCOEX_WL_LNADIV_MODE_OPTION 0x000300001267#define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S 161268#define AR_BTCOEX_WL_LNADIV_MODE 0x007c00001269#define AR_BTCOEX_WL_LNADIV_MODE_S 181270#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ 0x008000001271#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S 231272#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE 0x010000001273#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S 241274#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT 0x020000001275#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S 251276#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD 0xFC0000001277#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S 261278 1279/* Manual Peak detector calibration */1280#define AR_PHY_65NM_BASE 0x160001281#define AR_PHY_65NM_RXRF_GAINSTAGES(i) (AR_PHY_65NM_BASE + \1282 (i * 0x400) + 0x8)1283#define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE 0x800000001284#define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE_S 311285#define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC 0x000000021286#define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC_S 11287#define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR 0x700000001288#define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_S 281289#define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR 0x038000001290#define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_S 231291 1292#define AR_PHY_65NM_RXTX2(i) (AR_PHY_65NM_BASE + \1293 (i * 0x400) + 0x104)1294#define AR_PHY_65NM_RXTX2_RXON_OVR 0x000010001295#define AR_PHY_65NM_RXTX2_RXON_OVR_S 121296#define AR_PHY_65NM_RXTX2_RXON 0x000008001297#define AR_PHY_65NM_RXTX2_RXON_S 111298 1299#define AR_PHY_65NM_RXRF_AGC(i) (AR_PHY_65NM_BASE + \1300 (i * 0x400) + 0xc)1301#define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE 0x800000001302#define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE_S 311303#define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR 0x400000001304#define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR_S 301305#define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR 0x200000001306#define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR_S 291307#define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR 0x1E0000001308#define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR_S 251309#define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR 0x000780001310#define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR_S 151311#define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR 0x01F800001312#define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR_S 191313#define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR 0x00007e001314#define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR_S 91315#define AR_PHY_65NM_RXRF_AGC_AGC_OUT 0x000000041316#define AR_PHY_65NM_RXRF_AGC_AGC_OUT_S 21317 1318#define AR9300_DFS_FIRPWR -281319 1320#endif /* AR9003_PHY_H */1321