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1/*2 * Copyright (c) 2008-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef DEBUG_H18#define DEBUG_H19 20#include "hw.h"21#include "dfs_debug.h"22 23struct ath_txq;24struct ath_buf;25struct fft_sample_tlv;26 27#ifdef CONFIG_ATH9K_DEBUGFS28#define TX_STAT_INC(sc, q, c) do { (sc)->debug.stats.txstats[q].c++; } while (0)29#define RX_STAT_INC(sc, c) do { (sc)->debug.stats.rxstats.c++; } while (0)30#define RESET_STAT_INC(sc, type) do { (sc)->debug.stats.reset[type]++; } while (0)31#define ANT_STAT_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].c++; } while (0)32#define ANT_LNA_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].lna_recv_cnt[c]++; } while (0)33#else34#define TX_STAT_INC(sc, q, c) do { (void)(sc); } while (0)35#define RX_STAT_INC(sc, c) do { (void)(sc); } while (0)36#define RESET_STAT_INC(sc, type) do { (void)(sc); } while (0)37#define ANT_STAT_INC(sc, i, c) do { (void)(sc); } while (0)38#define ANT_LNA_INC(sc, i, c) do { (void)(sc); } while (0)39#endif40 41enum ath_reset_type {42 RESET_TYPE_USER,43 RESET_TYPE_BB_HANG,44 RESET_TYPE_BB_WATCHDOG,45 RESET_TYPE_FATAL_INT,46 RESET_TYPE_TX_ERROR,47 RESET_TYPE_TX_GTT,48 RESET_TYPE_TX_HANG,49 RESET_TYPE_PLL_HANG,50 RESET_TYPE_MAC_HANG,51 RESET_TYPE_BEACON_STUCK,52 RESET_TYPE_MCI,53 RESET_TYPE_CALIBRATION,54 RESET_TX_DMA_ERROR,55 RESET_RX_DMA_ERROR,56 __RESET_TYPE_MAX57};58 59#ifdef CONFIG_ATH9K_DEBUGFS60 61/**62 * struct ath_interrupt_stats - Contains statistics about interrupts63 * @total: Total no. of interrupts generated so far64 * @rxok: RX with no errors65 * @rxlp: RX with low priority RX66 * @rxhp: RX with high priority, uapsd only67 * @rxeol: RX with no more RXDESC available68 * @rxorn: RX FIFO overrun69 * @txok: TX completed at the requested rate70 * @txurn: TX FIFO underrun71 * @mib: MIB regs reaching its threshold72 * @rxphyerr: RX with phy errors73 * @rx_keycache_miss: RX with key cache misses74 * @swba: Software Beacon Alert75 * @bmiss: Beacon Miss76 * @bnr: Beacon Not Ready77 * @cst: Carrier Sense TImeout78 * @gtt: Global TX Timeout79 * @tim: RX beacon TIM occurrence80 * @cabend: RX End of CAB traffic81 * @dtimsync: DTIM sync lossage82 * @dtim: RX Beacon with DTIM83 * @bb_watchdog: Baseband watchdog84 * @tsfoor: TSF out of range, indicates that the corrected TSF received85 * from a beacon differs from the PCU's internal TSF by more than a86 * (programmable) threshold87 * @local_timeout: Internal bus timeout.88 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets89 * @gen_timer: Generic hardware timer interrupt90 */91struct ath_interrupt_stats {92 u32 total;93 u32 rxok;94 u32 rxlp;95 u32 rxhp;96 u32 rxeol;97 u32 rxorn;98 u32 txok;99 u32 txeol;100 u32 txurn;101 u32 mib;102 u32 rxphyerr;103 u32 rx_keycache_miss;104 u32 swba;105 u32 bmiss;106 u32 bnr;107 u32 cst;108 u32 gtt;109 u32 tim;110 u32 cabend;111 u32 dtimsync;112 u32 dtim;113 u32 bb_watchdog;114 u32 tsfoor;115 u32 mci;116 u32 gen_timer;117 118 /* Sync-cause stats */119 u32 sync_cause_all;120 u32 sync_rtc_irq;121 u32 sync_mac_irq;122 u32 eeprom_illegal_access;123 u32 apb_timeout;124 u32 pci_mode_conflict;125 u32 host1_fatal;126 u32 host1_perr;127 u32 trcv_fifo_perr;128 u32 radm_cpl_ep;129 u32 radm_cpl_dllp_abort;130 u32 radm_cpl_tlp_abort;131 u32 radm_cpl_ecrc_err;132 u32 radm_cpl_timeout;133 u32 local_timeout;134 u32 pm_access;135 u32 mac_awake;136 u32 mac_asleep;137 u32 mac_sleep_access;138};139 140 141/**142 * struct ath_tx_stats - Statistics about TX143 * @tx_pkts_all: No. of total frames transmitted, including ones that144 may have had errors.145 * @tx_bytes_all: No. of total bytes transmitted, including ones that146 may have had errors.147 * @queued: Total MPDUs (non-aggr) queued148 * @completed: Total MPDUs (non-aggr) completed149 * @a_aggr: Total no. of aggregates queued150 * @a_queued_hw: Total AMPDUs queued to hardware151 * @a_completed: Total AMPDUs completed152 * @a_retries: No. of AMPDUs retried (SW)153 * @a_xretries: No. of AMPDUs dropped due to xretries154 * @txerr_filtered: No. of frames with TXERR_FILT flag set.155 * @fifo_underrun: FIFO underrun occurrences156 Valid only for:157 - non-aggregate condition.158 - first packet of aggregate.159 * @xtxop: No. of frames filtered because of TXOP limit160 * @timer_exp: Transmit timer expiry161 * @desc_cfg_err: Descriptor configuration errors162 * @data_urn: TX data underrun errors163 * @delim_urn: TX delimiter underrun errors164 * @puttxbuf: Number of times hardware was given txbuf to write.165 * @txstart: Number of times hardware was told to start tx.166 * @txprocdesc: Number of times tx descriptor was processed167 * @txfailed: Out-of-memory or other errors in xmit path.168 */169struct ath_tx_stats {170 u32 tx_pkts_all;171 u32 tx_bytes_all;172 u32 queued;173 u32 completed;174 u32 xretries;175 u32 a_aggr;176 u32 a_queued_hw;177 u32 a_completed;178 u32 a_retries;179 u32 a_xretries;180 u32 txerr_filtered;181 u32 fifo_underrun;182 u32 xtxop;183 u32 timer_exp;184 u32 desc_cfg_err;185 u32 data_underrun;186 u32 delim_underrun;187 u32 puttxbuf;188 u32 txstart;189 u32 txprocdesc;190 u32 txfailed;191};192 193/*194 * Various utility macros to print TX/Queue counters.195 */196#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum197#define TXSTATS sc->debug.stats.txstats198#define PR(str, elem) \199 do { \200 seq_printf(file, "%s%13u%11u%10u%10u\n", str, \201 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\202 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\203 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\204 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \205 } while(0)206 207struct ath_rx_rate_stats {208 struct {209 u32 ht20_cnt;210 u32 ht40_cnt;211 u32 sgi_cnt;212 u32 lgi_cnt;213 } ht_stats[24];214 215 struct {216 u32 ofdm_cnt;217 } ofdm_stats[8];218 219 struct {220 u32 cck_lp_cnt;221 u32 cck_sp_cnt;222 } cck_stats[4];223};224 225struct ath_airtime_stats {226 u32 rx_airtime;227 u32 tx_airtime;228};229 230#define ANT_MAIN 0231#define ANT_ALT 1232 233struct ath_antenna_stats {234 u32 recv_cnt;235 u32 rssi_avg;236 u32 lna_recv_cnt[4];237 u32 lna_attempt_cnt[4];238};239 240struct ath_stats {241 struct ath_interrupt_stats istats;242 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];243 struct ath_rx_stats rxstats;244 struct ath_dfs_stats dfs_stats;245 struct ath_antenna_stats ant_stats[2];246 u32 reset[__RESET_TYPE_MAX];247};248 249struct ath9k_debug {250 struct dentry *debugfs_phy;251 u32 regidx;252 struct ath_stats stats;253};254 255int ath9k_init_debug(struct ath_hw *ah);256void ath9k_deinit_debug(struct ath_softc *sc);257 258void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);259void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,260 struct ath_tx_status *ts, struct ath_txq *txq,261 unsigned int flags);262void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);263int ath9k_get_et_sset_count(struct ieee80211_hw *hw,264 struct ieee80211_vif *vif, int sset);265void ath9k_get_et_stats(struct ieee80211_hw *hw,266 struct ieee80211_vif *vif,267 struct ethtool_stats *stats, u64 *data);268void ath9k_get_et_strings(struct ieee80211_hw *hw,269 struct ieee80211_vif *vif,270 u32 sset, u8 *data);271void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,272 struct ieee80211_vif *vif,273 struct ieee80211_sta *sta,274 struct dentry *dir);275void ath9k_debug_stat_ant(struct ath_softc *sc,276 struct ath_hw_antcomb_conf *div_ant_conf,277 int main_rssi_avg, int alt_rssi_avg);278void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);279 280#else281 282static inline int ath9k_init_debug(struct ath_hw *ah)283{284 return 0;285}286 287static inline void ath9k_deinit_debug(struct ath_softc *sc)288{289}290static inline void ath_debug_stat_interrupt(struct ath_softc *sc,291 enum ath9k_int status)292{293}294static inline void ath_debug_stat_tx(struct ath_softc *sc,295 struct ath_buf *bf,296 struct ath_tx_status *ts,297 struct ath_txq *txq,298 unsigned int flags)299{300}301static inline void ath_debug_stat_rx(struct ath_softc *sc,302 struct ath_rx_status *rs)303{304}305static inline void ath9k_debug_stat_ant(struct ath_softc *sc,306 struct ath_hw_antcomb_conf *div_ant_conf,307 int main_rssi_avg, int alt_rssi_avg)308{309 310}311 312static inline void313ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)314{315}316 317#endif /* CONFIG_ATH9K_DEBUGFS */318 319#ifdef CONFIG_ATH9K_STATION_STATISTICS320void ath_debug_rate_stats(struct ath_softc *sc,321 struct ath_rx_status *rs,322 struct sk_buff *skb);323#else324static inline void ath_debug_rate_stats(struct ath_softc *sc,325 struct ath_rx_status *rs,326 struct sk_buff *skb)327{328}329#endif /* CONFIG_ATH9K_STATION_STATISTICS */330 331#endif /* DEBUG_H */332