3387 lines · c
1/*2 * Copyright (c) 2008-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#include <linux/io.h>18#include <linux/slab.h>19#include <linux/module.h>20#include <linux/time.h>21#include <linux/bitops.h>22#include <linux/etherdevice.h>23#include <linux/gpio.h>24#include <linux/unaligned.h>25 26#include "hw.h"27#include "hw-ops.h"28#include "ar9003_mac.h"29#include "ar9003_mci.h"30#include "ar9003_phy.h"31#include "ath9k.h"32 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);34 35MODULE_AUTHOR("Atheros Communications");36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");37MODULE_LICENSE("Dual BSD/GPL");38 39static void ath9k_hw_set_clockrate(struct ath_hw *ah)40{41 struct ath_common *common = ath9k_hw_common(ah);42 struct ath9k_channel *chan = ah->curchan;43 unsigned int clockrate;44 45 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))47 clockrate = 117;48 else if (!chan) /* should really check for CCK instead */49 clockrate = ATH9K_CLOCK_RATE_CCK;50 else if (IS_CHAN_2GHZ(chan))51 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;54 else55 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;56 57 if (chan) {58 if (IS_CHAN_HT40(chan))59 clockrate *= 2;60 if (IS_CHAN_HALF_RATE(chan))61 clockrate /= 2;62 if (IS_CHAN_QUARTER_RATE(chan))63 clockrate /= 4;64 }65 66 common->clockrate = clockrate;67}68 69static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)70{71 struct ath_common *common = ath9k_hw_common(ah);72 73 return usecs * common->clockrate;74}75 76bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)77{78 int i;79 80 BUG_ON(timeout < AH_TIME_QUANTUM);81 82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {83 if ((REG_READ(ah, reg) & mask) == val)84 return true;85 86 udelay(AH_TIME_QUANTUM);87 }88 89 ath_dbg(ath9k_hw_common(ah), ANY,90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",91 timeout, reg, REG_READ(ah, reg), mask, val);92 93 return false;94}95EXPORT_SYMBOL(ath9k_hw_wait);96 97void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,98 int hw_delay)99{100 hw_delay /= 10;101 102 if (IS_CHAN_HALF_RATE(chan))103 hw_delay *= 2;104 else if (IS_CHAN_QUARTER_RATE(chan))105 hw_delay *= 4;106 107 udelay(hw_delay + BASE_ACTIVATE_DELAY);108}109 110void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,111 int column, unsigned int *writecnt)112{113 int r;114 115 ENABLE_REGWRITE_BUFFER(ah);116 for (r = 0; r < array->ia_rows; r++) {117 REG_WRITE(ah, INI_RA(array, r, 0),118 INI_RA(array, r, column));119 DO_DELAY(*writecnt);120 }121 REGWRITE_BUFFER_FLUSH(ah);122}123 124void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)125{126 u32 *tmp_reg_list, *tmp_data;127 int i;128 129 tmp_reg_list = kmalloc_array(size, sizeof(u32), GFP_KERNEL);130 if (!tmp_reg_list) {131 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);132 return;133 }134 135 tmp_data = kmalloc_array(size, sizeof(u32), GFP_KERNEL);136 if (!tmp_data) {137 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);138 goto error_tmp_data;139 }140 141 for (i = 0; i < size; i++)142 tmp_reg_list[i] = array[i][0];143 144 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);145 146 for (i = 0; i < size; i++)147 array[i][1] = tmp_data[i];148 149 kfree(tmp_data);150error_tmp_data:151 kfree(tmp_reg_list);152}153 154u32 ath9k_hw_reverse_bits(u32 val, u32 n)155{156 u32 retval;157 int i;158 159 for (i = 0, retval = 0; i < n; i++) {160 retval = (retval << 1) | (val & 1);161 val >>= 1;162 }163 return retval;164}165 166u16 ath9k_hw_computetxtime(struct ath_hw *ah,167 u8 phy, int kbps,168 u32 frameLen, u16 rateix,169 bool shortPreamble)170{171 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;172 173 if (kbps == 0)174 return 0;175 176 switch (phy) {177 case WLAN_RC_PHY_CCK:178 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;179 if (shortPreamble)180 phyTime >>= 1;181 numBits = frameLen << 3;182 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);183 break;184 case WLAN_RC_PHY_OFDM:185 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {186 bitsPerSymbol =187 ((kbps >> 2) * OFDM_SYMBOL_TIME_QUARTER) / 1000;188 numBits = OFDM_PLCP_BITS + (frameLen << 3);189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);190 txTime = OFDM_SIFS_TIME_QUARTER191 + OFDM_PREAMBLE_TIME_QUARTER192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);193 } else if (ah->curchan &&194 IS_CHAN_HALF_RATE(ah->curchan)) {195 bitsPerSymbol =196 ((kbps >> 1) * OFDM_SYMBOL_TIME_HALF) / 1000;197 numBits = OFDM_PLCP_BITS + (frameLen << 3);198 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);199 txTime = OFDM_SIFS_TIME_HALF +200 OFDM_PREAMBLE_TIME_HALF201 + (numSymbols * OFDM_SYMBOL_TIME_HALF);202 } else {203 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;204 numBits = OFDM_PLCP_BITS + (frameLen << 3);205 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);206 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME207 + (numSymbols * OFDM_SYMBOL_TIME);208 }209 break;210 default:211 ath_err(ath9k_hw_common(ah),212 "Unknown phy %u (rate ix %u)\n", phy, rateix);213 txTime = 0;214 break;215 }216 217 return txTime;218}219EXPORT_SYMBOL(ath9k_hw_computetxtime);220 221void ath9k_hw_get_channel_centers(struct ath_hw *ah,222 struct ath9k_channel *chan,223 struct chan_centers *centers)224{225 int8_t extoff;226 227 if (!IS_CHAN_HT40(chan)) {228 centers->ctl_center = centers->ext_center =229 centers->synth_center = chan->channel;230 return;231 }232 233 if (IS_CHAN_HT40PLUS(chan)) {234 centers->synth_center =235 chan->channel + HT40_CHANNEL_CENTER_SHIFT;236 extoff = 1;237 } else {238 centers->synth_center =239 chan->channel - HT40_CHANNEL_CENTER_SHIFT;240 extoff = -1;241 }242 243 centers->ctl_center =244 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);245 /* 25 MHz spacing is supported by hw but not on upper layers */246 centers->ext_center =247 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);248}249 250/******************/251/* Chip Revisions */252/******************/253 254static bool ath9k_hw_read_revisions(struct ath_hw *ah)255{256 u32 srev;257 u32 val;258 259 if (ah->get_mac_revision)260 ah->hw_version.macRev = ah->get_mac_revision();261 262 switch (ah->hw_version.devid) {263 case AR5416_AR9100_DEVID:264 ah->hw_version.macVersion = AR_SREV_VERSION_9100;265 break;266 case AR9300_DEVID_AR9330:267 ah->hw_version.macVersion = AR_SREV_VERSION_9330;268 if (!ah->get_mac_revision) {269 val = REG_READ(ah, AR_SREV(ah));270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);271 }272 return true;273 case AR9300_DEVID_AR9340:274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;275 return true;276 case AR9300_DEVID_QCA955X:277 ah->hw_version.macVersion = AR_SREV_VERSION_9550;278 return true;279 case AR9300_DEVID_AR953X:280 ah->hw_version.macVersion = AR_SREV_VERSION_9531;281 return true;282 case AR9300_DEVID_QCA956X:283 ah->hw_version.macVersion = AR_SREV_VERSION_9561;284 return true;285 }286 287 srev = REG_READ(ah, AR_SREV(ah));288 289 if (srev == -1) {290 ath_err(ath9k_hw_common(ah),291 "Failed to read SREV register");292 return false;293 }294 295 val = srev & AR_SREV_ID(ah);296 297 if (val == 0xFF) {298 val = srev;299 ah->hw_version.macVersion =300 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;301 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);302 303 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))304 ah->is_pciexpress = true;305 else306 ah->is_pciexpress = (val &307 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;308 } else {309 if (!AR_SREV_9100(ah))310 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);311 312 ah->hw_version.macRev = val & AR_SREV_REVISION;313 314 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)315 ah->is_pciexpress = true;316 }317 318 return true;319}320 321/************************************/322/* HW Attach, Detach, Init Routines */323/************************************/324 325static void ath9k_hw_disablepcie(struct ath_hw *ah)326{327 if (!AR_SREV_5416(ah))328 return;329 330 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);331 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);332 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);333 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);334 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);335 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);336 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);337 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);338 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);339 340 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);341}342 343/* This should work for all families including legacy */344static bool ath9k_hw_chip_test(struct ath_hw *ah)345{346 struct ath_common *common = ath9k_hw_common(ah);347 u32 regAddr[2] = { AR_STA_ID0 };348 u32 regHold[2];349 static const u32 patternData[4] = {350 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999351 };352 int i, j, loop_max;353 354 if (!AR_SREV_9300_20_OR_LATER(ah)) {355 loop_max = 2;356 regAddr[1] = AR_PHY_BASE + (8 << 2);357 } else358 loop_max = 1;359 360 for (i = 0; i < loop_max; i++) {361 u32 addr = regAddr[i];362 u32 wrData, rdData;363 364 regHold[i] = REG_READ(ah, addr);365 for (j = 0; j < 0x100; j++) {366 wrData = (j << 16) | j;367 REG_WRITE(ah, addr, wrData);368 rdData = REG_READ(ah, addr);369 if (rdData != wrData) {370 ath_err(common,371 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",372 addr, wrData, rdData);373 return false;374 }375 }376 for (j = 0; j < 4; j++) {377 wrData = patternData[j];378 REG_WRITE(ah, addr, wrData);379 rdData = REG_READ(ah, addr);380 if (wrData != rdData) {381 ath_err(common,382 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",383 addr, wrData, rdData);384 return false;385 }386 }387 REG_WRITE(ah, regAddr[i], regHold[i]);388 }389 udelay(100);390 391 return true;392}393 394static void ath9k_hw_init_config(struct ath_hw *ah)395{396 struct ath_common *common = ath9k_hw_common(ah);397 398 ah->config.dma_beacon_response_time = 1;399 ah->config.sw_beacon_response_time = 6;400 ah->config.cwm_ignore_extcca = false;401 ah->config.analog_shiftreg = 1;402 403 ah->config.rx_intr_mitigation = true;404 405 if (AR_SREV_9300_20_OR_LATER(ah)) {406 ah->config.rimt_last = 500;407 ah->config.rimt_first = 2000;408 } else {409 ah->config.rimt_last = 250;410 ah->config.rimt_first = 700;411 }412 413 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))414 ah->config.pll_pwrsave = 7;415 416 /*417 * We need this for PCI devices only (Cardbus, PCI, miniPCI)418 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).419 * This means we use it for all AR5416 devices, and the few420 * minor PCI AR9280 devices out there.421 *422 * Serialization is required because these devices do not handle423 * well the case of two concurrent reads/writes due to the latency424 * involved. During one read/write another read/write can be issued425 * on another CPU while the previous read/write may still be working426 * on our hardware, if we hit this case the hardware poops in a loop.427 * We prevent this by serializing reads and writes.428 *429 * This issue is not present on PCI-Express devices or pre-AR5416430 * devices (legacy, 802.11abg).431 */432 if (num_possible_cpus() > 1)433 ah->config.serialize_regmode = SER_REG_MODE_AUTO;434 435 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {436 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||437 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&438 !ah->is_pciexpress)) {439 ah->config.serialize_regmode = SER_REG_MODE_ON;440 } else {441 ah->config.serialize_regmode = SER_REG_MODE_OFF;442 }443 }444 445 ath_dbg(common, RESET, "serialize_regmode is %d\n",446 ah->config.serialize_regmode);447 448 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))449 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;450 else451 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;452}453 454static void ath9k_hw_init_defaults(struct ath_hw *ah)455{456 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);457 458 regulatory->country_code = CTRY_DEFAULT;459 regulatory->power_limit = MAX_COMBINED_POWER;460 461 ah->hw_version.magic = AR5416_MAGIC;462 ah->hw_version.subvendorid = 0;463 464 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |465 AR_STA_ID1_MCAST_KSRCH;466 if (AR_SREV_9100(ah))467 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;468 469 ah->slottime = 9;470 ah->globaltxtimeout = (u32) -1;471 ah->power_mode = ATH9K_PM_UNDEFINED;472 ah->htc_reset_init = true;473 474 ah->tpc_enabled = false;475 476 ah->ani_function = ATH9K_ANI_ALL;477 if (!AR_SREV_9300_20_OR_LATER(ah))478 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;479 480 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))481 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);482 else483 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);484}485 486static void ath9k_hw_init_macaddr(struct ath_hw *ah)487{488 struct ath_common *common = ath9k_hw_common(ah);489 int i;490 u16 eeval;491 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };492 493 /* MAC address may already be loaded via ath9k_platform_data */494 if (is_valid_ether_addr(common->macaddr))495 return;496 497 for (i = 0; i < 3; i++) {498 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);499 common->macaddr[2 * i] = eeval >> 8;500 common->macaddr[2 * i + 1] = eeval & 0xff;501 }502 503 if (is_valid_ether_addr(common->macaddr))504 return;505 506 ath_err(common, "eeprom contains invalid mac address: %pM\n",507 common->macaddr);508 509 eth_random_addr(common->macaddr);510 ath_err(common, "random mac address will be used: %pM\n",511 common->macaddr);512 513 return;514}515 516static int ath9k_hw_post_init(struct ath_hw *ah)517{518 struct ath_common *common = ath9k_hw_common(ah);519 int ecode;520 521 if (common->bus_ops->ath_bus_type != ATH_USB) {522 if (!ath9k_hw_chip_test(ah))523 return -ENODEV;524 }525 526 if (!AR_SREV_9300_20_OR_LATER(ah)) {527 ecode = ar9002_hw_rf_claim(ah);528 if (ecode != 0)529 return ecode;530 }531 532 ecode = ath9k_hw_eeprom_init(ah);533 if (ecode != 0)534 return ecode;535 536 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",537 ah->eep_ops->get_eeprom_ver(ah),538 ah->eep_ops->get_eeprom_rev(ah));539 540 ath9k_hw_ani_init(ah);541 542 /*543 * EEPROM needs to be initialized before we do this.544 * This is required for regulatory compliance.545 */546 if (AR_SREV_9300_20_OR_LATER(ah)) {547 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);548 if ((regdmn & 0xF0) == CTL_FCC) {549 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;550 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;551 }552 }553 554 return 0;555}556 557static int ath9k_hw_attach_ops(struct ath_hw *ah)558{559 if (!AR_SREV_9300_20_OR_LATER(ah))560 return ar9002_hw_attach_ops(ah);561 562 ar9003_hw_attach_ops(ah);563 return 0;564}565 566/* Called for all hardware families */567static int __ath9k_hw_init(struct ath_hw *ah)568{569 struct ath_common *common = ath9k_hw_common(ah);570 int r = 0;571 572 if (!ath9k_hw_read_revisions(ah)) {573 ath_err(common, "Could not read hardware revisions");574 return -EOPNOTSUPP;575 }576 577 switch (ah->hw_version.macVersion) {578 case AR_SREV_VERSION_5416_PCI:579 case AR_SREV_VERSION_5416_PCIE:580 case AR_SREV_VERSION_9160:581 case AR_SREV_VERSION_9100:582 case AR_SREV_VERSION_9280:583 case AR_SREV_VERSION_9285:584 case AR_SREV_VERSION_9287:585 case AR_SREV_VERSION_9271:586 case AR_SREV_VERSION_9300:587 case AR_SREV_VERSION_9330:588 case AR_SREV_VERSION_9485:589 case AR_SREV_VERSION_9340:590 case AR_SREV_VERSION_9462:591 case AR_SREV_VERSION_9550:592 case AR_SREV_VERSION_9565:593 case AR_SREV_VERSION_9531:594 case AR_SREV_VERSION_9561:595 break;596 default:597 ath_err(common,598 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",599 ah->hw_version.macVersion, ah->hw_version.macRev);600 return -EOPNOTSUPP;601 }602 603 /*604 * Read back AR_WA(ah) into a permanent copy and set bits 14 and 17.605 * We need to do this to avoid RMW of this register. We cannot606 * read the reg when chip is asleep.607 */608 if (AR_SREV_9300_20_OR_LATER(ah)) {609 ah->WARegVal = REG_READ(ah, AR_WA(ah));610 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |611 AR_WA_ASPM_TIMER_BASED_DISABLE);612 }613 614 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {615 ath_err(common, "Couldn't reset chip\n");616 return -EIO;617 }618 619 if (AR_SREV_9565(ah)) {620 ah->WARegVal |= AR_WA_BIT22;621 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);622 }623 624 ath9k_hw_init_defaults(ah);625 ath9k_hw_init_config(ah);626 627 r = ath9k_hw_attach_ops(ah);628 if (r)629 return r;630 631 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {632 ath_err(common, "Couldn't wakeup chip\n");633 return -EIO;634 }635 636 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||637 AR_SREV_9330(ah) || AR_SREV_9550(ah))638 ah->is_pciexpress = false;639 640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);641 ath9k_hw_init_cal_settings(ah);642 643 if (!ah->is_pciexpress)644 ath9k_hw_disablepcie(ah);645 646 r = ath9k_hw_post_init(ah);647 if (r)648 return r;649 650 ath9k_hw_init_mode_gain_regs(ah);651 r = ath9k_hw_fill_cap_info(ah);652 if (r)653 return r;654 655 ath9k_hw_init_macaddr(ah);656 ath9k_hw_init_hang_checks(ah);657 658 common->state = ATH_HW_INITIALIZED;659 660 return 0;661}662 663int ath9k_hw_init(struct ath_hw *ah)664{665 int ret;666 struct ath_common *common = ath9k_hw_common(ah);667 668 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */669 switch (ah->hw_version.devid) {670 case AR5416_DEVID_PCI:671 case AR5416_DEVID_PCIE:672 case AR5416_AR9100_DEVID:673 case AR9160_DEVID_PCI:674 case AR9280_DEVID_PCI:675 case AR9280_DEVID_PCIE:676 case AR9285_DEVID_PCIE:677 case AR9287_DEVID_PCI:678 case AR9287_DEVID_PCIE:679 case AR2427_DEVID_PCIE:680 case AR9300_DEVID_PCIE:681 case AR9300_DEVID_AR9485_PCIE:682 case AR9300_DEVID_AR9330:683 case AR9300_DEVID_AR9340:684 case AR9300_DEVID_QCA955X:685 case AR9300_DEVID_AR9580:686 case AR9300_DEVID_AR9462:687 case AR9485_DEVID_AR1111:688 case AR9300_DEVID_AR9565:689 case AR9300_DEVID_AR953X:690 case AR9300_DEVID_QCA956X:691 break;692 default:693 if (common->bus_ops->ath_bus_type == ATH_USB)694 break;695 ath_err(common, "Hardware device ID 0x%04x not supported\n",696 ah->hw_version.devid);697 return -EOPNOTSUPP;698 }699 700 ret = __ath9k_hw_init(ah);701 if (ret) {702 ath_err(common,703 "Unable to initialize hardware; initialization status: %d\n",704 ret);705 return ret;706 }707 708 ath_dynack_init(ah);709 710 return 0;711}712EXPORT_SYMBOL(ath9k_hw_init);713 714static void ath9k_hw_init_qos(struct ath_hw *ah)715{716 ENABLE_REGWRITE_BUFFER(ah);717 718 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);719 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);720 721 REG_WRITE(ah, AR_QOS_NO_ACK,722 SM(2, AR_QOS_NO_ACK_TWO_BIT) |723 SM(5, AR_QOS_NO_ACK_BIT_OFF) |724 SM(0, AR_QOS_NO_ACK_BYTE_OFF));725 726 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);727 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);728 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);729 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);730 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);731 732 REGWRITE_BUFFER_FLUSH(ah);733}734 735u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)736{737 struct ath_common *common = ath9k_hw_common(ah);738 int i = 0;739 740 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);741 udelay(100);742 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);743 744 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {745 746 udelay(100);747 748 if (WARN_ON_ONCE(i >= 100)) {749 ath_err(common, "PLL4 measurement not done\n");750 break;751 }752 753 i++;754 }755 756 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;757}758EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);759 760static void ath9k_hw_init_pll(struct ath_hw *ah,761 struct ath9k_channel *chan)762{763 u32 pll;764 765 pll = ath9k_hw_compute_pll_control(ah, chan);766 767 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {768 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,770 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,772 AR_CH0_DPLL2_KD, 0x40);773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,774 AR_CH0_DPLL2_KI, 0x4);775 776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,777 AR_CH0_BB_DPLL1_REFDIV, 0x5);778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,779 AR_CH0_BB_DPLL1_NINI, 0x58);780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,781 AR_CH0_BB_DPLL1_NFRAC, 0x0);782 783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,784 AR_CH0_BB_DPLL2_OUTDIV, 0x1);785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,786 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);787 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,788 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);789 790 /* program BB PLL phase_shift to 0x6 */791 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,792 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);793 794 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,795 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);796 udelay(1000);797 } else if (AR_SREV_9330(ah)) {798 u32 ddr_dpll2, pll_control2, kd;799 800 if (ah->is_clk_25mhz) {801 ddr_dpll2 = 0x18e82f01;802 pll_control2 = 0xe04a3d;803 kd = 0x1d;804 } else {805 ddr_dpll2 = 0x19e82f01;806 pll_control2 = 0x886666;807 kd = 0x3d;808 }809 810 /* program DDR PLL ki and kd value */811 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);812 813 /* program DDR PLL phase_shift */814 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,815 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);816 817 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),818 pll | AR_RTC_9300_PLL_BYPASS);819 udelay(1000);820 821 /* program refdiv, nint, frac to RTC register */822 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);823 824 /* program BB PLL kd and ki value */825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);827 828 /* program BB PLL phase_shift */829 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,830 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);831 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||832 AR_SREV_9561(ah)) {833 u32 regval, pll2_divint, pll2_divfrac, refdiv;834 835 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),836 pll | AR_RTC_9300_SOC_PLL_BYPASS);837 udelay(1000);838 839 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);840 udelay(100);841 842 if (ah->is_clk_25mhz) {843 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {844 pll2_divint = 0x1c;845 pll2_divfrac = 0xa3d2;846 refdiv = 1;847 } else {848 pll2_divint = 0x54;849 pll2_divfrac = 0x1eb85;850 refdiv = 3;851 }852 } else {853 if (AR_SREV_9340(ah)) {854 pll2_divint = 88;855 pll2_divfrac = 0;856 refdiv = 5;857 } else {858 pll2_divint = 0x11;859 pll2_divfrac = (AR_SREV_9531(ah) ||860 AR_SREV_9561(ah)) ?861 0x26665 : 0x26666;862 refdiv = 1;863 }864 }865 866 regval = REG_READ(ah, AR_PHY_PLL_MODE);867 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))868 regval |= (0x1 << 22);869 else870 regval |= (0x1 << 16);871 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);872 udelay(100);873 874 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |875 (pll2_divint << 18) | pll2_divfrac);876 udelay(100);877 878 regval = REG_READ(ah, AR_PHY_PLL_MODE);879 if (AR_SREV_9340(ah))880 regval = (regval & 0x80071fff) |881 (0x1 << 30) |882 (0x1 << 13) |883 (0x4 << 26) |884 (0x18 << 19);885 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {886 regval = (regval & 0x01c00fff) |887 (0x1 << 31) |888 (0x2 << 29) |889 (0xa << 25) |890 (0x1 << 19);891 892 if (AR_SREV_9531(ah))893 regval |= (0x6 << 12);894 } else895 regval = (regval & 0x80071fff) |896 (0x3 << 30) |897 (0x1 << 13) |898 (0x4 << 26) |899 (0x60 << 19);900 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);901 902 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))903 REG_WRITE(ah, AR_PHY_PLL_MODE,904 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);905 else906 REG_WRITE(ah, AR_PHY_PLL_MODE,907 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);908 909 udelay(1000);910 }911 912 if (AR_SREV_9565(ah))913 pll |= 0x40000;914 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), pll);915 916 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||917 AR_SREV_9550(ah))918 udelay(1000);919 920 /* Switch the core clock for ar9271 to 117Mhz */921 if (AR_SREV_9271(ah)) {922 udelay(500);923 REG_WRITE(ah, 0x50040, 0x304);924 }925 926 udelay(RTC_PLL_SETTLE_DELAY);927 928 REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), AR_RTC_FORCE_DERIVED_CLK);929}930 931static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,932 enum nl80211_iftype opmode)933{934 u32 sync_default = AR_INTR_SYNC_DEFAULT;935 u32 imr_reg = AR_IMR_TXERR |936 AR_IMR_TXURN |937 AR_IMR_RXERR |938 AR_IMR_RXORN |939 AR_IMR_BCNMISC;940 u32 msi_cfg = 0;941 942 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||943 AR_SREV_9561(ah))944 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;945 946 if (AR_SREV_9300_20_OR_LATER(ah)) {947 imr_reg |= AR_IMR_RXOK_HP;948 if (ah->config.rx_intr_mitigation) {949 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;950 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;951 } else {952 imr_reg |= AR_IMR_RXOK_LP;953 msi_cfg |= AR_INTCFG_MSI_RXOK;954 }955 } else {956 if (ah->config.rx_intr_mitigation) {957 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;958 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;959 } else {960 imr_reg |= AR_IMR_RXOK;961 msi_cfg |= AR_INTCFG_MSI_RXOK;962 }963 }964 965 if (ah->config.tx_intr_mitigation) {966 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;967 msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR;968 } else {969 imr_reg |= AR_IMR_TXOK;970 msi_cfg |= AR_INTCFG_MSI_TXOK;971 }972 973 ENABLE_REGWRITE_BUFFER(ah);974 975 REG_WRITE(ah, AR_IMR, imr_reg);976 ah->imrs2_reg |= AR_IMR_S2_GTT;977 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);978 979 if (ah->msi_enabled) {980 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah));981 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;982 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;983 REG_WRITE(ah, AR_INTCFG, msi_cfg);984 ath_dbg(ath9k_hw_common(ah), ANY,985 "value of AR_INTCFG=0x%X, msi_cfg=0x%X\n",986 REG_READ(ah, AR_INTCFG), msi_cfg);987 }988 989 if (!AR_SREV_9100(ah)) {990 REG_WRITE(ah, AR_INTR_SYNC_CAUSE(ah), 0xFFFFFFFF);991 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), sync_default);992 REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), 0);993 }994 995 REGWRITE_BUFFER_FLUSH(ah);996 997 if (AR_SREV_9300_20_OR_LATER(ah)) {998 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0);999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), 0);1000 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE(ah), 0);1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK(ah), 0);1002 }1003}1004 1005static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)1006{1007 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);1008 val = min(val, (u32) 0xFFFF);1009 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);1010}1011 1012void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)1013{1014 u32 val = ath9k_hw_mac_to_clks(ah, us);1015 val = min(val, (u32) 0xFFFF);1016 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);1017}1018 1019void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)1020{1021 u32 val = ath9k_hw_mac_to_clks(ah, us);1022 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));1023 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);1024}1025 1026void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)1027{1028 u32 val = ath9k_hw_mac_to_clks(ah, us);1029 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));1030 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);1031}1032 1033static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)1034{1035 if (tu > 0xFFFF) {1036 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",1037 tu);1038 ah->globaltxtimeout = (u32) -1;1039 return false;1040 } else {1041 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);1042 ah->globaltxtimeout = tu;1043 return true;1044 }1045}1046 1047void ath9k_hw_init_global_settings(struct ath_hw *ah)1048{1049 struct ath_common *common = ath9k_hw_common(ah);1050 const struct ath9k_channel *chan = ah->curchan;1051 int acktimeout, ctstimeout, ack_offset = 0;1052 int slottime;1053 int sifstime;1054 int rx_lat = 0, tx_lat = 0, eifs = 0, ack_shift = 0;1055 u32 reg;1056 1057 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",1058 ah->misc_mode);1059 1060 if (!chan)1061 return;1062 1063 if (ah->misc_mode != 0)1064 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);1065 1066 if (IS_CHAN_A_FAST_CLOCK(ah, chan))1067 rx_lat = 41;1068 else1069 rx_lat = 37;1070 tx_lat = 54;1071 1072 if (IS_CHAN_5GHZ(chan))1073 sifstime = 16;1074 else1075 sifstime = 10;1076 1077 if (IS_CHAN_HALF_RATE(chan)) {1078 eifs = 175;1079 rx_lat *= 2;1080 tx_lat *= 2;1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))1082 tx_lat += 11;1083 1084 sifstime = 32;1085 ack_offset = 16;1086 ack_shift = 3;1087 slottime = 13;1088 } else if (IS_CHAN_QUARTER_RATE(chan)) {1089 eifs = 340;1090 rx_lat = (rx_lat * 4) - 1;1091 tx_lat *= 4;1092 if (IS_CHAN_A_FAST_CLOCK(ah, chan))1093 tx_lat += 22;1094 1095 sifstime = 64;1096 ack_offset = 32;1097 ack_shift = 1;1098 slottime = 21;1099 } else {1100 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {1101 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;1102 reg = AR_USEC_ASYNC_FIFO;1103 } else {1104 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/1105 common->clockrate;1106 reg = REG_READ(ah, AR_USEC);1107 }1108 rx_lat = MS(reg, AR_USEC_RX_LAT);1109 tx_lat = MS(reg, AR_USEC_TX_LAT);1110 1111 slottime = ah->slottime;1112 }1113 1114 /* As defined by IEEE 802.11-2007 17.3.8.6 */1115 slottime += 3 * ah->coverage_class;1116 acktimeout = slottime + sifstime + ack_offset;1117 ctstimeout = acktimeout;1118 1119 /*1120 * Workaround for early ACK timeouts, add an offset to match the1121 * initval's 64us ack timeout value. Use 48us for the CTS timeout.1122 * This was initially only meant to work around an issue with delayed1123 * BA frames in some implementations, but it has been found to fix ACK1124 * timeout issues in other cases as well.1125 */1126 if (IS_CHAN_2GHZ(chan) &&1127 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {1128 acktimeout += 64 - sifstime - ah->slottime;1129 ctstimeout += 48 - sifstime - ah->slottime;1130 }1131 1132 if (ah->dynack.enabled) {1133 acktimeout = ah->dynack.ackto;1134 ctstimeout = acktimeout;1135 slottime = (acktimeout - 3) / 2;1136 } else {1137 ah->dynack.ackto = acktimeout;1138 }1139 1140 ath9k_hw_set_sifs_time(ah, sifstime);1141 ath9k_hw_setslottime(ah, slottime);1142 ath9k_hw_set_ack_timeout(ah, acktimeout);1143 ath9k_hw_set_cts_timeout(ah, ctstimeout);1144 if (ah->globaltxtimeout != (u32) -1)1145 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);1146 1147 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));1148 REG_RMW(ah, AR_USEC,1149 (common->clockrate - 1) |1150 SM(rx_lat, AR_USEC_RX_LAT) |1151 SM(tx_lat, AR_USEC_TX_LAT),1152 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);1153 1154 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))1155 REG_RMW(ah, AR_TXSIFS,1156 sifstime | SM(ack_shift, AR_TXSIFS_ACK_SHIFT),1157 (AR_TXSIFS_TIME | AR_TXSIFS_ACK_SHIFT));1158}1159EXPORT_SYMBOL(ath9k_hw_init_global_settings);1160 1161void ath9k_hw_deinit(struct ath_hw *ah)1162{1163 struct ath_common *common = ath9k_hw_common(ah);1164 1165 if (common->state < ATH_HW_INITIALIZED)1166 return;1167 1168 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);1169}1170EXPORT_SYMBOL(ath9k_hw_deinit);1171 1172/*******/1173/* INI */1174/*******/1175 1176u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)1177{1178 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);1179 1180 if (IS_CHAN_2GHZ(chan))1181 ctl |= CTL_11G;1182 else1183 ctl |= CTL_11A;1184 1185 return ctl;1186}1187 1188/****************************************/1189/* Reset and Channel Switching Routines */1190/****************************************/1191 1192static inline void ath9k_hw_set_dma(struct ath_hw *ah)1193{1194 struct ath_common *common = ath9k_hw_common(ah);1195 int txbuf_size;1196 1197 ENABLE_REGWRITE_BUFFER(ah);1198 1199 /*1200 * set AHB_MODE not to do cacheline prefetches1201 */1202 if (!AR_SREV_9300_20_OR_LATER(ah))1203 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);1204 1205 /*1206 * let mac dma reads be in 128 byte chunks1207 */1208 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);1209 1210 REGWRITE_BUFFER_FLUSH(ah);1211 1212 /*1213 * Restore TX Trigger Level to its pre-reset value.1214 * The initial value depends on whether aggregation is enabled, and is1215 * adjusted whenever underruns are detected.1216 */1217 if (!AR_SREV_9300_20_OR_LATER(ah))1218 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);1219 1220 ENABLE_REGWRITE_BUFFER(ah);1221 1222 /*1223 * let mac dma writes be in 128 byte chunks1224 */1225 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);1226 1227 /*1228 * Setup receive FIFO threshold to hold off TX activities1229 */1230 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);1231 1232 if (AR_SREV_9300_20_OR_LATER(ah)) {1233 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);1234 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);1235 1236 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -1237 ah->caps.rx_status_len);1238 }1239 1240 /*1241 * reduce the number of usable entries in PCU TXBUF to avoid1242 * wrap around issues.1243 */1244 if (AR_SREV_9285(ah)) {1245 /* For AR9285 the number of Fifos are reduced to half.1246 * So set the usable tx buf size also to half to1247 * avoid data/delimiter underruns1248 */1249 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;1250 } else if (AR_SREV_9340_13_OR_LATER(ah)) {1251 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */1252 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;1253 } else {1254 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;1255 }1256 1257 if (!AR_SREV_9271(ah))1258 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);1259 1260 REGWRITE_BUFFER_FLUSH(ah);1261 1262 if (AR_SREV_9300_20_OR_LATER(ah))1263 ath9k_hw_reset_txstatus_ring(ah);1264}1265 1266static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)1267{1268 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;1269 u32 set = AR_STA_ID1_KSRCH_MODE;1270 1271 ENABLE_REG_RMW_BUFFER(ah);1272 switch (opmode) {1273 case NL80211_IFTYPE_ADHOC:1274 if (!AR_SREV_9340_13(ah)) {1275 set |= AR_STA_ID1_ADHOC;1276 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);1277 break;1278 }1279 fallthrough;1280 case NL80211_IFTYPE_OCB:1281 case NL80211_IFTYPE_MESH_POINT:1282 case NL80211_IFTYPE_AP:1283 set |= AR_STA_ID1_STA_AP;1284 fallthrough;1285 case NL80211_IFTYPE_STATION:1286 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);1287 break;1288 default:1289 if (!ah->is_monitoring)1290 set = 0;1291 break;1292 }1293 REG_RMW(ah, AR_STA_ID1, set, mask);1294 REG_RMW_BUFFER_FLUSH(ah);1295}1296 1297void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,1298 u32 *coef_mantissa, u32 *coef_exponent)1299{1300 u32 coef_exp, coef_man;1301 1302 for (coef_exp = 31; coef_exp > 0; coef_exp--)1303 if ((coef_scaled >> coef_exp) & 0x1)1304 break;1305 1306 coef_exp = 14 - (coef_exp - COEF_SCALE_S);1307 1308 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));1309 1310 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);1311 *coef_exponent = coef_exp - 16;1312}1313 1314/* AR9330 WAR:1315 * call external reset function to reset WMAC if:1316 * - doing a cold reset1317 * - we have pending frames in the TX queues.1318 */1319static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)1320{1321 int i, npend = 0;1322 1323 for (i = 0; i < AR_NUM_QCU; i++) {1324 npend = ath9k_hw_numtxpending(ah, i);1325 if (npend)1326 break;1327 }1328 1329 if (ah->external_reset &&1330 (npend || type == ATH9K_RESET_COLD)) {1331 int reset_err = 0;1332 1333 ath_dbg(ath9k_hw_common(ah), RESET,1334 "reset MAC via external reset\n");1335 1336 reset_err = ah->external_reset();1337 if (reset_err) {1338 ath_err(ath9k_hw_common(ah),1339 "External reset failed, err=%d\n",1340 reset_err);1341 return false;1342 }1343 1344 REG_WRITE(ah, AR_RTC_RESET(ah), 1);1345 }1346 1347 return true;1348}1349 1350static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)1351{1352 u32 rst_flags;1353 u32 tmpReg;1354 1355 if (AR_SREV_9100(ah)) {1356 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK(ah),1357 AR_RTC_DERIVED_CLK_PERIOD, 1);1358 (void)REG_READ(ah, AR_RTC_DERIVED_CLK(ah));1359 }1360 1361 ENABLE_REGWRITE_BUFFER(ah);1362 1363 if (AR_SREV_9300_20_OR_LATER(ah)) {1364 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);1365 udelay(10);1366 }1367 1368 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |1369 AR_RTC_FORCE_WAKE_ON_INT);1370 1371 if (AR_SREV_9100(ah)) {1372 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |1373 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;1374 } else {1375 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah));1376 if (AR_SREV_9340(ah))1377 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;1378 else1379 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |1380 AR_INTR_SYNC_RADM_CPL_TIMEOUT;1381 1382 if (tmpReg) {1383 u32 val;1384 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0);1385 1386 val = AR_RC_HOSTIF;1387 if (!AR_SREV_9300_20_OR_LATER(ah))1388 val |= AR_RC_AHB;1389 REG_WRITE(ah, AR_RC, val);1390 1391 } else if (!AR_SREV_9300_20_OR_LATER(ah))1392 REG_WRITE(ah, AR_RC, AR_RC_AHB);1393 1394 rst_flags = AR_RTC_RC_MAC_WARM;1395 if (type == ATH9K_RESET_COLD)1396 rst_flags |= AR_RTC_RC_MAC_COLD;1397 }1398 1399 if (AR_SREV_9330(ah)) {1400 if (!ath9k_hw_ar9330_reset_war(ah, type))1401 return false;1402 }1403 1404 if (ath9k_hw_mci_is_enabled(ah))1405 ar9003_mci_check_gpm_offset(ah);1406 1407 /* DMA HALT added to resolve ar9300 and ar9580 bus error during1408 * RTC_RC reg read1409 */1410 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {1411 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);1412 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,1413 20 * AH_WAIT_TIMEOUT);1414 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);1415 }1416 1417 REG_WRITE(ah, AR_RTC_RC(ah), rst_flags);1418 1419 REGWRITE_BUFFER_FLUSH(ah);1420 1421 if (AR_SREV_9300_20_OR_LATER(ah))1422 udelay(50);1423 else if (AR_SREV_9100(ah))1424 mdelay(10);1425 else1426 udelay(100);1427 1428 REG_WRITE(ah, AR_RTC_RC(ah), 0);1429 if (!ath9k_hw_wait(ah, AR_RTC_RC(ah), AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {1430 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");1431 return false;1432 }1433 1434 if (!AR_SREV_9100(ah))1435 REG_WRITE(ah, AR_RC, 0);1436 1437 if (AR_SREV_9100(ah))1438 udelay(50);1439 1440 return true;1441}1442 1443static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)1444{1445 ENABLE_REGWRITE_BUFFER(ah);1446 1447 if (AR_SREV_9300_20_OR_LATER(ah)) {1448 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);1449 udelay(10);1450 }1451 1452 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |1453 AR_RTC_FORCE_WAKE_ON_INT);1454 1455 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))1456 REG_WRITE(ah, AR_RC, AR_RC_AHB);1457 1458 REG_WRITE(ah, AR_RTC_RESET(ah), 0);1459 1460 REGWRITE_BUFFER_FLUSH(ah);1461 1462 udelay(2);1463 1464 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))1465 REG_WRITE(ah, AR_RC, 0);1466 1467 REG_WRITE(ah, AR_RTC_RESET(ah), 1);1468 1469 if (!ath9k_hw_wait(ah,1470 AR_RTC_STATUS(ah),1471 AR_RTC_STATUS_M(ah),1472 AR_RTC_STATUS_ON,1473 AH_WAIT_TIMEOUT)) {1474 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");1475 return false;1476 }1477 1478 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);1479}1480 1481static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)1482{1483 bool ret = false;1484 1485 if (AR_SREV_9300_20_OR_LATER(ah)) {1486 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);1487 udelay(10);1488 }1489 1490 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),1491 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);1492 1493 if (!ah->reset_power_on)1494 type = ATH9K_RESET_POWER_ON;1495 1496 switch (type) {1497 case ATH9K_RESET_POWER_ON:1498 ret = ath9k_hw_set_reset_power_on(ah);1499 if (ret)1500 ah->reset_power_on = true;1501 break;1502 case ATH9K_RESET_WARM:1503 case ATH9K_RESET_COLD:1504 ret = ath9k_hw_set_reset(ah, type);1505 break;1506 default:1507 break;1508 }1509 1510 return ret;1511}1512 1513static bool ath9k_hw_chip_reset(struct ath_hw *ah,1514 struct ath9k_channel *chan)1515{1516 int reset_type = ATH9K_RESET_WARM;1517 1518 if (AR_SREV_9280(ah)) {1519 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))1520 reset_type = ATH9K_RESET_POWER_ON;1521 else1522 reset_type = ATH9K_RESET_COLD;1523 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||1524 (REG_READ(ah, AR_CR) & AR_CR_RXE(ah)))1525 reset_type = ATH9K_RESET_COLD;1526 1527 if (!ath9k_hw_set_reset_reg(ah, reset_type))1528 return false;1529 1530 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))1531 return false;1532 1533 ah->chip_fullsleep = false;1534 1535 if (AR_SREV_9330(ah))1536 ar9003_hw_internal_regulator_apply(ah);1537 ath9k_hw_init_pll(ah, chan);1538 1539 return true;1540}1541 1542static bool ath9k_hw_channel_change(struct ath_hw *ah,1543 struct ath9k_channel *chan)1544{1545 struct ath_common *common = ath9k_hw_common(ah);1546 struct ath9k_hw_capabilities *pCap = &ah->caps;1547 bool band_switch = false, mode_diff = false;1548 u8 ini_reloaded = 0;1549 u32 qnum;1550 int r;1551 1552 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {1553 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;1554 band_switch = !!(flags_diff & CHANNEL_5GHZ);1555 mode_diff = !!(flags_diff & ~CHANNEL_HT);1556 }1557 1558 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {1559 if (ath9k_hw_numtxpending(ah, qnum)) {1560 ath_dbg(common, QUEUE,1561 "Transmit frames pending on queue %d\n", qnum);1562 return false;1563 }1564 }1565 1566 if (!ath9k_hw_rfbus_req(ah)) {1567 ath_err(common, "Could not kill baseband RX\n");1568 return false;1569 }1570 1571 if (band_switch || mode_diff) {1572 ath9k_hw_mark_phy_inactive(ah);1573 udelay(5);1574 1575 if (band_switch)1576 ath9k_hw_init_pll(ah, chan);1577 1578 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {1579 ath_err(common, "Failed to do fast channel change\n");1580 return false;1581 }1582 }1583 1584 ath9k_hw_set_channel_regs(ah, chan);1585 1586 r = ath9k_hw_rf_set_freq(ah, chan);1587 if (r) {1588 ath_err(common, "Failed to set channel\n");1589 return false;1590 }1591 ath9k_hw_set_clockrate(ah);1592 ath9k_hw_apply_txpower(ah, chan, false);1593 1594 ath9k_hw_set_delta_slope(ah, chan);1595 ath9k_hw_spur_mitigate_freq(ah, chan);1596 1597 if (band_switch || ini_reloaded)1598 ah->eep_ops->set_board_values(ah, chan);1599 1600 ath9k_hw_init_bb(ah, chan);1601 ath9k_hw_rfbus_done(ah);1602 1603 if (band_switch || ini_reloaded) {1604 ah->ah_flags |= AH_FASTCC;1605 ath9k_hw_init_cal(ah, chan);1606 ah->ah_flags &= ~AH_FASTCC;1607 }1608 1609 return true;1610}1611 1612static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)1613{1614 u32 gpio_mask = ah->gpio_mask;1615 int i;1616 1617 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {1618 if (!(gpio_mask & 1))1619 continue;1620 1621 ath9k_hw_gpio_request_out(ah, i, NULL,1622 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);1623 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));1624 }1625}1626 1627void ath9k_hw_check_nav(struct ath_hw *ah)1628{1629 struct ath_common *common = ath9k_hw_common(ah);1630 u32 val;1631 1632 val = REG_READ(ah, AR_NAV);1633 if (val != 0xdeadbeef && val > 0x7fff) {1634 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);1635 REG_WRITE(ah, AR_NAV, 0);1636 }1637}1638EXPORT_SYMBOL(ath9k_hw_check_nav);1639 1640bool ath9k_hw_check_alive(struct ath_hw *ah)1641{1642 int count = 50;1643 u32 reg, last_val;1644 1645 /* Check if chip failed to wake up */1646 if (REG_READ(ah, AR_CFG) == 0xdeadbeef)1647 return false;1648 1649 if (AR_SREV_9300(ah))1650 return !ath9k_hw_detect_mac_hang(ah);1651 1652 if (AR_SREV_9285_12_OR_LATER(ah))1653 return true;1654 1655 last_val = REG_READ(ah, AR_OBS_BUS_1);1656 do {1657 reg = REG_READ(ah, AR_OBS_BUS_1);1658 if (reg != last_val)1659 return true;1660 1661 udelay(1);1662 last_val = reg;1663 if ((reg & 0x7E7FFFEF) == 0x00702400)1664 continue;1665 1666 switch (reg & 0x7E000B00) {1667 case 0x1E000000:1668 case 0x52000B00:1669 case 0x18000B00:1670 continue;1671 default:1672 return true;1673 }1674 } while (count-- > 0);1675 1676 return false;1677}1678EXPORT_SYMBOL(ath9k_hw_check_alive);1679 1680static void ath9k_hw_init_mfp(struct ath_hw *ah)1681{1682 /* Setup MFP options for CCMP */1683 if (AR_SREV_9280_20_OR_LATER(ah)) {1684 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt1685 * frames when constructing CCMP AAD. */1686 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,1687 0xc7ff);1688 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))1689 ah->sw_mgmt_crypto_tx = true;1690 else1691 ah->sw_mgmt_crypto_tx = false;1692 ah->sw_mgmt_crypto_rx = false;1693 } else if (AR_SREV_9160_10_OR_LATER(ah)) {1694 /* Disable hardware crypto for management frames */1695 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,1696 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);1697 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,1698 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);1699 ah->sw_mgmt_crypto_tx = true;1700 ah->sw_mgmt_crypto_rx = true;1701 } else {1702 ah->sw_mgmt_crypto_tx = true;1703 ah->sw_mgmt_crypto_rx = true;1704 }1705}1706 1707static void ath9k_hw_reset_opmode(struct ath_hw *ah,1708 u32 macStaId1, u32 saveDefAntenna)1709{1710 struct ath_common *common = ath9k_hw_common(ah);1711 1712 ENABLE_REGWRITE_BUFFER(ah);1713 1714 REG_RMW(ah, AR_STA_ID1, macStaId11715 | AR_STA_ID1_RTS_USE_DEF1716 | ah->sta_id1_defaults,1717 ~AR_STA_ID1_SADH_MASK);1718 ath_hw_setbssidmask(common);1719 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);1720 ath9k_hw_write_associd(ah);1721 REG_WRITE(ah, AR_ISR, ~0);1722 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);1723 1724 REGWRITE_BUFFER_FLUSH(ah);1725 1726 ath9k_hw_set_operating_mode(ah, ah->opmode);1727}1728 1729static void ath9k_hw_init_queues(struct ath_hw *ah)1730{1731 int i;1732 1733 ENABLE_REGWRITE_BUFFER(ah);1734 1735 for (i = 0; i < AR_NUM_DCU; i++)1736 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);1737 1738 REGWRITE_BUFFER_FLUSH(ah);1739 1740 ah->intr_txqs = 0;1741 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)1742 ath9k_hw_resettxqueue(ah, i);1743}1744 1745/*1746 * For big endian systems turn on swapping for descriptors1747 */1748static void ath9k_hw_init_desc(struct ath_hw *ah)1749{1750 struct ath_common *common = ath9k_hw_common(ah);1751 1752 if (AR_SREV_9100(ah)) {1753 u32 mask;1754 mask = REG_READ(ah, AR_CFG);1755 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {1756 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",1757 mask);1758 } else {1759 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;1760 REG_WRITE(ah, AR_CFG, mask);1761 ath_dbg(common, RESET, "Setting CFG 0x%x\n",1762 REG_READ(ah, AR_CFG));1763 }1764 } else {1765 if (common->bus_ops->ath_bus_type == ATH_USB) {1766 /* Configure AR9271 target WLAN */1767 if (AR_SREV_9271(ah))1768 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);1769 else1770 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);1771 }1772#ifdef __BIG_ENDIAN1773 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||1774 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||1775 AR_SREV_9561(ah))1776 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);1777 else1778 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);1779#endif1780 }1781}1782 1783/*1784 * Fast channel change:1785 * (Change synthesizer based on channel freq without resetting chip)1786 */1787static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)1788{1789 struct ath_common *common = ath9k_hw_common(ah);1790 struct ath9k_hw_capabilities *pCap = &ah->caps;1791 int ret;1792 1793 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)1794 goto fail;1795 1796 if (ah->chip_fullsleep)1797 goto fail;1798 1799 if (!ah->curchan)1800 goto fail;1801 1802 if (chan->channel == ah->curchan->channel)1803 goto fail;1804 1805 if ((ah->curchan->channelFlags | chan->channelFlags) &1806 (CHANNEL_HALF | CHANNEL_QUARTER))1807 goto fail;1808 1809 /*1810 * If cross-band fcc is not supoprted, bail out if channelFlags differ.1811 */1812 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&1813 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))1814 goto fail;1815 1816 if (!ath9k_hw_check_alive(ah))1817 goto fail;1818 1819 /*1820 * For AR9462, make sure that calibration data for1821 * re-using are present.1822 */1823 if (AR_SREV_9462(ah) && (ah->caldata &&1824 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||1825 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||1826 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))1827 goto fail;1828 1829 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",1830 ah->curchan->channel, chan->channel);1831 1832 ret = ath9k_hw_channel_change(ah, chan);1833 if (!ret)1834 goto fail;1835 1836 if (ath9k_hw_mci_is_enabled(ah))1837 ar9003_mci_2g5g_switch(ah, false);1838 1839 ath9k_hw_loadnf(ah, ah->curchan);1840 ath9k_hw_start_nfcal(ah, true);1841 1842 if (AR_SREV_9271(ah))1843 ar9002_hw_load_ani_reg(ah, chan);1844 1845 return 0;1846fail:1847 return -EINVAL;1848}1849 1850u32 ath9k_hw_get_tsf_offset(struct timespec64 *last, struct timespec64 *cur)1851{1852 struct timespec64 ts;1853 s64 usec;1854 1855 if (!cur) {1856 ktime_get_raw_ts64(&ts);1857 cur = &ts;1858 }1859 1860 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;1861 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;1862 1863 return (u32) usec;1864}1865EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);1866 1867int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,1868 struct ath9k_hw_cal_data *caldata, bool fastcc)1869{1870 struct ath_common *common = ath9k_hw_common(ah);1871 u32 saveLedState;1872 u32 saveDefAntenna;1873 u32 macStaId1;1874 struct timespec64 tsf_ts;1875 u32 tsf_offset;1876 u64 tsf = 0;1877 int r;1878 bool start_mci_reset = false;1879 bool save_fullsleep = ah->chip_fullsleep;1880 1881 if (ath9k_hw_mci_is_enabled(ah)) {1882 start_mci_reset = ar9003_mci_start_reset(ah, chan);1883 if (start_mci_reset)1884 return 0;1885 }1886 1887 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))1888 return -EIO;1889 1890 if (ah->curchan && !ah->chip_fullsleep)1891 ath9k_hw_getnf(ah, ah->curchan);1892 1893 ah->caldata = caldata;1894 if (caldata && (chan->channel != caldata->channel ||1895 chan->channelFlags != caldata->channelFlags)) {1896 /* Operating channel changed, reset channel calibration data */1897 memset(caldata, 0, sizeof(*caldata));1898 ath9k_init_nfcal_hist_buffer(ah, chan);1899 } else if (caldata) {1900 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);1901 }1902 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);1903 1904 if (fastcc) {1905 r = ath9k_hw_do_fastcc(ah, chan);1906 if (!r)1907 return r;1908 }1909 1910 if (ath9k_hw_mci_is_enabled(ah))1911 ar9003_mci_stop_bt(ah, save_fullsleep);1912 1913 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);1914 if (saveDefAntenna == 0)1915 saveDefAntenna = 1;1916 1917 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;1918 1919 /* Save TSF before chip reset, a cold reset clears it */1920 ktime_get_raw_ts64(&tsf_ts);1921 tsf = ath9k_hw_gettsf64(ah);1922 1923 saveLedState = REG_READ(ah, AR_CFG_LED) &1924 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |1925 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);1926 1927 ath9k_hw_mark_phy_inactive(ah);1928 1929 ah->paprd_table_write_done = false;1930 1931 /* Only required on the first reset */1932 if (AR_SREV_9271(ah) && ah->htc_reset_init) {1933 REG_WRITE(ah,1934 AR9271_RESET_POWER_DOWN_CONTROL,1935 AR9271_RADIO_RF_RST);1936 udelay(50);1937 }1938 1939 if (!ath9k_hw_chip_reset(ah, chan)) {1940 ath_err(common, "Chip reset failed\n");1941 return -EINVAL;1942 }1943 1944 /* Only required on the first reset */1945 if (AR_SREV_9271(ah) && ah->htc_reset_init) {1946 ah->htc_reset_init = false;1947 REG_WRITE(ah,1948 AR9271_RESET_POWER_DOWN_CONTROL,1949 AR9271_GATE_MAC_CTL);1950 udelay(50);1951 }1952 1953 /* Restore TSF */1954 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);1955 ath9k_hw_settsf64(ah, tsf + tsf_offset);1956 1957 if (AR_SREV_9280_20_OR_LATER(ah))1958 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE);1959 1960 if (!AR_SREV_9300_20_OR_LATER(ah))1961 ar9002_hw_enable_async_fifo(ah);1962 1963 r = ath9k_hw_process_ini(ah, chan);1964 if (r)1965 return r;1966 1967 ath9k_hw_set_rfmode(ah, chan);1968 1969 if (ath9k_hw_mci_is_enabled(ah))1970 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);1971 1972 /*1973 * Some AR91xx SoC devices frequently fail to accept TSF writes1974 * right after the chip reset. When that happens, write a new1975 * value after the initvals have been applied.1976 */1977 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {1978 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);1979 ath9k_hw_settsf64(ah, tsf + tsf_offset);1980 }1981 1982 ath9k_hw_init_mfp(ah);1983 1984 ath9k_hw_set_delta_slope(ah, chan);1985 ath9k_hw_spur_mitigate_freq(ah, chan);1986 ah->eep_ops->set_board_values(ah, chan);1987 1988 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);1989 1990 r = ath9k_hw_rf_set_freq(ah, chan);1991 if (r)1992 return r;1993 1994 ath9k_hw_set_clockrate(ah);1995 1996 ath9k_hw_init_queues(ah);1997 ath9k_hw_init_interrupt_masks(ah, ah->opmode);1998 ath9k_hw_ani_cache_ini_regs(ah);1999 ath9k_hw_init_qos(ah);2000 2001 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)2002 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");2003 2004 ath9k_hw_init_global_settings(ah);2005 2006 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {2007 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,2008 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);2009 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,2010 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);2011 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,2012 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);2013 }2014 2015 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);2016 2017 ath9k_hw_set_dma(ah);2018 2019 if (!ath9k_hw_mci_is_enabled(ah))2020 REG_WRITE(ah, AR_OBS(ah), 8);2021 2022 ENABLE_REG_RMW_BUFFER(ah);2023 if (ah->config.rx_intr_mitigation) {2024 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);2025 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);2026 }2027 2028 if (ah->config.tx_intr_mitigation) {2029 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);2030 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);2031 }2032 REG_RMW_BUFFER_FLUSH(ah);2033 2034 ath9k_hw_init_bb(ah, chan);2035 2036 if (caldata) {2037 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);2038 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);2039 }2040 if (!ath9k_hw_init_cal(ah, chan))2041 return -EIO;2042 2043 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))2044 return -EIO;2045 2046 ENABLE_REGWRITE_BUFFER(ah);2047 2048 ath9k_hw_restore_chainmask(ah);2049 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);2050 2051 REGWRITE_BUFFER_FLUSH(ah);2052 2053 ath9k_hw_gen_timer_start_tsf2(ah);2054 2055 ath9k_hw_init_desc(ah);2056 2057 if (ath9k_hw_btcoex_is_enabled(ah))2058 ath9k_hw_btcoex_enable(ah);2059 2060 if (ath9k_hw_mci_is_enabled(ah))2061 ar9003_mci_check_bt(ah);2062 2063 if (AR_SREV_9300_20_OR_LATER(ah)) {2064 ath9k_hw_loadnf(ah, chan);2065 ath9k_hw_start_nfcal(ah, true);2066 }2067 2068 if (AR_SREV_9300_20_OR_LATER(ah))2069 ar9003_hw_bb_watchdog_config(ah);2070 2071 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)2072 ar9003_hw_disable_phy_restart(ah);2073 2074 ath9k_hw_apply_gpio_override(ah);2075 2076 if (AR_SREV_9565(ah) && common->bt_ant_diversity)2077 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);2078 2079 if (ah->hw->conf.radar_enabled) {2080 /* set HW specific DFS configuration */2081 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);2082 ath9k_hw_set_radar_params(ah);2083 }2084 2085 return 0;2086}2087EXPORT_SYMBOL(ath9k_hw_reset);2088 2089/******************************/2090/* Power Management (Chipset) */2091/******************************/2092 2093/*2094 * Notify Power Mgt is disabled in self-generated frames.2095 * If requested, force chip to sleep.2096 */2097static void ath9k_set_power_sleep(struct ath_hw *ah)2098{2099 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);2100 2101 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {2102 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);2103 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);2104 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);2105 /* xxx Required for WLAN only case ? */2106 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);2107 udelay(100);2108 }2109 2110 /*2111 * Clear the RTC force wake bit to allow the2112 * mac to go to sleep.2113 */2114 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);2115 2116 if (ath9k_hw_mci_is_enabled(ah))2117 udelay(100);2118 2119 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))2120 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);2121 2122 /* Shutdown chip. Active low */2123 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {2124 REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN);2125 udelay(2);2126 }2127 2128 /* Clear Bit 14 of AR_WA(ah) after putting chip into Full Sleep mode. */2129 if (AR_SREV_9300_20_OR_LATER(ah))2130 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);2131}2132 2133/*2134 * Notify Power Management is enabled in self-generating2135 * frames. If request, set power mode of chip to2136 * auto/normal. Duration in units of 128us (1/8 TU).2137 */2138static void ath9k_set_power_network_sleep(struct ath_hw *ah)2139{2140 struct ath9k_hw_capabilities *pCap = &ah->caps;2141 2142 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);2143 2144 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {2145 /* Set WakeOnInterrupt bit; clear ForceWake bit */2146 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),2147 AR_RTC_FORCE_WAKE_ON_INT);2148 } else {2149 2150 /* When chip goes into network sleep, it could be waken2151 * up by MCI_INT interrupt caused by BT's HW messages2152 * (LNA_xxx, CONT_xxx) which chould be in a very fast2153 * rate (~100us). This will cause chip to leave and2154 * re-enter network sleep mode frequently, which in2155 * consequence will have WLAN MCI HW to generate lots of2156 * SYS_WAKING and SYS_SLEEPING messages which will make2157 * BT CPU to busy to process.2158 */2159 if (ath9k_hw_mci_is_enabled(ah))2160 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,2161 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);2162 /*2163 * Clear the RTC force wake bit to allow the2164 * mac to go to sleep.2165 */2166 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);2167 2168 if (ath9k_hw_mci_is_enabled(ah))2169 udelay(30);2170 }2171 2172 /* Clear Bit 14 of AR_WA(ah) after putting chip into Net Sleep mode. */2173 if (AR_SREV_9300_20_OR_LATER(ah))2174 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);2175}2176 2177static bool ath9k_hw_set_power_awake(struct ath_hw *ah)2178{2179 u32 val;2180 int i;2181 2182 /* Set Bits 14 and 17 of AR_WA(ah) before powering on the chip. */2183 if (AR_SREV_9300_20_OR_LATER(ah)) {2184 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);2185 udelay(10);2186 }2187 2188 if ((REG_READ(ah, AR_RTC_STATUS(ah)) &2189 AR_RTC_STATUS_M(ah)) == AR_RTC_STATUS_SHUTDOWN) {2190 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {2191 return false;2192 }2193 if (!AR_SREV_9300_20_OR_LATER(ah))2194 ath9k_hw_init_pll(ah, NULL);2195 }2196 if (AR_SREV_9100(ah))2197 REG_SET_BIT(ah, AR_RTC_RESET(ah),2198 AR_RTC_RESET_EN);2199 2200 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),2201 AR_RTC_FORCE_WAKE_EN);2202 if (AR_SREV_9100(ah))2203 mdelay(10);2204 else2205 udelay(50);2206 2207 for (i = POWER_UP_TIME / 50; i > 0; i--) {2208 val = REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah);2209 if (val == AR_RTC_STATUS_ON)2210 break;2211 udelay(50);2212 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),2213 AR_RTC_FORCE_WAKE_EN);2214 }2215 if (i == 0) {2216 ath_err(ath9k_hw_common(ah),2217 "Failed to wakeup in %uus\n",2218 POWER_UP_TIME / 20);2219 return false;2220 }2221 2222 if (ath9k_hw_mci_is_enabled(ah))2223 ar9003_mci_set_power_awake(ah);2224 2225 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);2226 2227 return true;2228}2229 2230bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)2231{2232 struct ath_common *common = ath9k_hw_common(ah);2233 int status = true;2234 static const char *modes[] = {2235 "AWAKE",2236 "FULL-SLEEP",2237 "NETWORK SLEEP",2238 "UNDEFINED"2239 };2240 2241 if (ah->power_mode == mode)2242 return status;2243 2244 ath_dbg(common, RESET, "%s -> %s\n",2245 modes[ah->power_mode], modes[mode]);2246 2247 switch (mode) {2248 case ATH9K_PM_AWAKE:2249 status = ath9k_hw_set_power_awake(ah);2250 break;2251 case ATH9K_PM_FULL_SLEEP:2252 if (ath9k_hw_mci_is_enabled(ah))2253 ar9003_mci_set_full_sleep(ah);2254 2255 ath9k_set_power_sleep(ah);2256 ah->chip_fullsleep = true;2257 break;2258 case ATH9K_PM_NETWORK_SLEEP:2259 ath9k_set_power_network_sleep(ah);2260 break;2261 default:2262 ath_err(common, "Unknown power mode %u\n", mode);2263 return false;2264 }2265 ah->power_mode = mode;2266 2267 /*2268 * XXX: If this warning never comes up after a while then2269 * simply keep the ATH_DBG_WARN_ON_ONCE() but make2270 * ath9k_hw_setpower() return type void.2271 */2272 2273 if (!(ah->ah_flags & AH_UNPLUGGED))2274 ATH_DBG_WARN_ON_ONCE(!status);2275 2276 return status;2277}2278EXPORT_SYMBOL(ath9k_hw_setpower);2279 2280/*******************/2281/* Beacon Handling */2282/*******************/2283 2284void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)2285{2286 int flags = 0;2287 2288 ENABLE_REGWRITE_BUFFER(ah);2289 2290 switch (ah->opmode) {2291 case NL80211_IFTYPE_ADHOC:2292 REG_SET_BIT(ah, AR_TXCFG,2293 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);2294 fallthrough;2295 case NL80211_IFTYPE_MESH_POINT:2296 case NL80211_IFTYPE_AP:2297 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);2298 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -2299 TU_TO_USEC(ah->config.dma_beacon_response_time));2300 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -2301 TU_TO_USEC(ah->config.sw_beacon_response_time));2302 flags |=2303 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;2304 break;2305 default:2306 ath_dbg(ath9k_hw_common(ah), BEACON,2307 "%s: unsupported opmode: %d\n", __func__, ah->opmode);2308 return;2309 }2310 2311 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);2312 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);2313 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);2314 2315 REGWRITE_BUFFER_FLUSH(ah);2316 2317 REG_SET_BIT(ah, AR_TIMER_MODE, flags);2318}2319EXPORT_SYMBOL(ath9k_hw_beaconinit);2320 2321void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,2322 const struct ath9k_beacon_state *bs)2323{2324 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;2325 struct ath9k_hw_capabilities *pCap = &ah->caps;2326 struct ath_common *common = ath9k_hw_common(ah);2327 2328 ENABLE_REGWRITE_BUFFER(ah);2329 2330 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);2331 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);2332 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);2333 2334 REGWRITE_BUFFER_FLUSH(ah);2335 2336 REG_RMW_FIELD(ah, AR_RSSI_THR,2337 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);2338 2339 beaconintval = bs->bs_intval;2340 2341 if (bs->bs_sleepduration > beaconintval)2342 beaconintval = bs->bs_sleepduration;2343 2344 dtimperiod = bs->bs_dtimperiod;2345 if (bs->bs_sleepduration > dtimperiod)2346 dtimperiod = bs->bs_sleepduration;2347 2348 if (beaconintval == dtimperiod)2349 nextTbtt = bs->bs_nextdtim;2350 else2351 nextTbtt = bs->bs_nexttbtt;2352 2353 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);2354 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);2355 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);2356 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);2357 2358 ENABLE_REGWRITE_BUFFER(ah);2359 2360 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);2361 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);2362 2363 REG_WRITE(ah, AR_SLEEP1,2364 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)2365 | AR_SLEEP1_ASSUME_DTIM);2366 2367 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)2368 beacontimeout = (BEACON_TIMEOUT_VAL << 3);2369 else2370 beacontimeout = MIN_BEACON_TIMEOUT_VAL;2371 2372 REG_WRITE(ah, AR_SLEEP2,2373 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));2374 2375 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);2376 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);2377 2378 REGWRITE_BUFFER_FLUSH(ah);2379 2380 REG_SET_BIT(ah, AR_TIMER_MODE,2381 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |2382 AR_DTIM_TIMER_EN);2383 2384 /* TSF Out of Range Threshold */2385 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);2386}2387EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);2388 2389/*******************/2390/* HW Capabilities */2391/*******************/2392 2393static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)2394{2395 eeprom_chainmask &= chip_chainmask;2396 if (eeprom_chainmask)2397 return eeprom_chainmask;2398 else2399 return chip_chainmask;2400}2401 2402/**2403 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset2404 * @ah: the atheros hardware data structure2405 *2406 * We enable DFS support upstream on chipsets which have passed a series2407 * of tests. The testing requirements are going to be documented. Desired2408 * test requirements are documented at:2409 *2410 * https://wireless.wiki.kernel.org/en/users/Drivers/ath9k/dfs2411 *2412 * Once a new chipset gets properly tested an individual commit can be used2413 * to document the testing for DFS for that chipset.2414 */2415static bool ath9k_hw_dfs_tested(struct ath_hw *ah)2416{2417 2418 switch (ah->hw_version.macVersion) {2419 /* for temporary testing DFS with 9280 */2420 case AR_SREV_VERSION_9280:2421 /* AR9580 will likely be our first target to get testing on */2422 case AR_SREV_VERSION_9580:2423 return true;2424 default:2425 return false;2426 }2427}2428 2429static void ath9k_gpio_cap_init(struct ath_hw *ah)2430{2431 struct ath9k_hw_capabilities *pCap = &ah->caps;2432 2433 if (AR_SREV_9271(ah)) {2434 pCap->num_gpio_pins = AR9271_NUM_GPIO;2435 pCap->gpio_mask = AR9271_GPIO_MASK;2436 } else if (AR_DEVID_7010(ah)) {2437 pCap->num_gpio_pins = AR7010_NUM_GPIO;2438 pCap->gpio_mask = AR7010_GPIO_MASK;2439 } else if (AR_SREV_9287(ah)) {2440 pCap->num_gpio_pins = AR9287_NUM_GPIO;2441 pCap->gpio_mask = AR9287_GPIO_MASK;2442 } else if (AR_SREV_9285(ah)) {2443 pCap->num_gpio_pins = AR9285_NUM_GPIO;2444 pCap->gpio_mask = AR9285_GPIO_MASK;2445 } else if (AR_SREV_9280(ah)) {2446 pCap->num_gpio_pins = AR9280_NUM_GPIO;2447 pCap->gpio_mask = AR9280_GPIO_MASK;2448 } else if (AR_SREV_9300(ah)) {2449 pCap->num_gpio_pins = AR9300_NUM_GPIO;2450 pCap->gpio_mask = AR9300_GPIO_MASK;2451 } else if (AR_SREV_9330(ah)) {2452 pCap->num_gpio_pins = AR9330_NUM_GPIO;2453 pCap->gpio_mask = AR9330_GPIO_MASK;2454 } else if (AR_SREV_9340(ah)) {2455 pCap->num_gpio_pins = AR9340_NUM_GPIO;2456 pCap->gpio_mask = AR9340_GPIO_MASK;2457 } else if (AR_SREV_9462(ah)) {2458 pCap->num_gpio_pins = AR9462_NUM_GPIO;2459 pCap->gpio_mask = AR9462_GPIO_MASK;2460 } else if (AR_SREV_9485(ah)) {2461 pCap->num_gpio_pins = AR9485_NUM_GPIO;2462 pCap->gpio_mask = AR9485_GPIO_MASK;2463 } else if (AR_SREV_9531(ah)) {2464 pCap->num_gpio_pins = AR9531_NUM_GPIO;2465 pCap->gpio_mask = AR9531_GPIO_MASK;2466 } else if (AR_SREV_9550(ah)) {2467 pCap->num_gpio_pins = AR9550_NUM_GPIO;2468 pCap->gpio_mask = AR9550_GPIO_MASK;2469 } else if (AR_SREV_9561(ah)) {2470 pCap->num_gpio_pins = AR9561_NUM_GPIO;2471 pCap->gpio_mask = AR9561_GPIO_MASK;2472 } else if (AR_SREV_9565(ah)) {2473 pCap->num_gpio_pins = AR9565_NUM_GPIO;2474 pCap->gpio_mask = AR9565_GPIO_MASK;2475 } else if (AR_SREV_9580(ah)) {2476 pCap->num_gpio_pins = AR9580_NUM_GPIO;2477 pCap->gpio_mask = AR9580_GPIO_MASK;2478 } else {2479 pCap->num_gpio_pins = AR_NUM_GPIO;2480 pCap->gpio_mask = AR_GPIO_MASK;2481 }2482}2483 2484int ath9k_hw_fill_cap_info(struct ath_hw *ah)2485{2486 struct ath9k_hw_capabilities *pCap = &ah->caps;2487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);2488 struct ath_common *common = ath9k_hw_common(ah);2489 2490 u16 eeval;2491 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;2492 2493 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);2494 regulatory->current_rd = eeval;2495 2496 if (ah->opmode != NL80211_IFTYPE_AP &&2497 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {2498 if (regulatory->current_rd == 0x64 ||2499 regulatory->current_rd == 0x65)2500 regulatory->current_rd += 5;2501 else if (regulatory->current_rd == 0x41)2502 regulatory->current_rd = 0x43;2503 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",2504 regulatory->current_rd);2505 }2506 2507 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);2508 2509 if (eeval & AR5416_OPFLAGS_11A) {2510 if (ah->disable_5ghz)2511 ath_warn(common, "disabling 5GHz band\n");2512 else2513 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;2514 }2515 2516 if (eeval & AR5416_OPFLAGS_11G) {2517 if (ah->disable_2ghz)2518 ath_warn(common, "disabling 2GHz band\n");2519 else2520 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;2521 }2522 2523 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {2524 ath_err(common, "both bands are disabled\n");2525 return -EINVAL;2526 }2527 2528 ath9k_gpio_cap_init(ah);2529 2530 if (AR_SREV_9485(ah) ||2531 AR_SREV_9285(ah) ||2532 AR_SREV_9330(ah) ||2533 AR_SREV_9565(ah))2534 pCap->chip_chainmask = 1;2535 else if (!AR_SREV_9280_20_OR_LATER(ah))2536 pCap->chip_chainmask = 7;2537 else if (!AR_SREV_9300_20_OR_LATER(ah) ||2538 AR_SREV_9340(ah) ||2539 AR_SREV_9462(ah) ||2540 AR_SREV_9531(ah))2541 pCap->chip_chainmask = 3;2542 else2543 pCap->chip_chainmask = 7;2544 2545 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);2546 /*2547 * For AR9271 we will temporarilly uses the rx chainmax as read from2548 * the EEPROM.2549 */2550 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&2551 !(eeval & AR5416_OPFLAGS_11A) &&2552 !(AR_SREV_9271(ah)))2553 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */2554 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;2555 else if (AR_SREV_9100(ah))2556 pCap->rx_chainmask = 0x7;2557 else2558 /* Use rx_chainmask from EEPROM. */2559 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);2560 2561 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);2562 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);2563 ah->txchainmask = pCap->tx_chainmask;2564 ah->rxchainmask = pCap->rx_chainmask;2565 2566 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;2567 2568 /* enable key search for every frame in an aggregate */2569 if (AR_SREV_9300_20_OR_LATER(ah))2570 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;2571 2572 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;2573 2574 if (ah->hw_version.devid != AR2427_DEVID_PCIE)2575 pCap->hw_caps |= ATH9K_HW_CAP_HT;2576 else2577 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;2578 2579 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))2580 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;2581 else2582 pCap->rts_aggr_limit = (8 * 1024);2583 2584#ifdef CONFIG_ATH9K_RFKILL2585 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);2586 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {2587 ah->rfkill_gpio =2588 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);2589 ah->rfkill_polarity =2590 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);2591 2592 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;2593 }2594#endif2595 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))2596 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;2597 else2598 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;2599 2600 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))2601 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;2602 else2603 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;2604 2605 if (AR_SREV_9300_20_OR_LATER(ah)) {2606 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;2607 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&2608 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))2609 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;2610 2611 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;2612 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;2613 pCap->rx_status_len = sizeof(struct ar9003_rxs);2614 pCap->tx_desc_len = sizeof(struct ar9003_txc);2615 pCap->txs_len = sizeof(struct ar9003_txs);2616 } else {2617 pCap->tx_desc_len = sizeof(struct ath_desc);2618 if (AR_SREV_9280_20(ah))2619 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;2620 }2621 2622 if (AR_SREV_9300_20_OR_LATER(ah))2623 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;2624 2625 if (AR_SREV_9561(ah))2626 ah->ent_mode = 0x3BDA000;2627 else if (AR_SREV_9300_20_OR_LATER(ah))2628 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);2629 2630 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))2631 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;2632 2633 if (AR_SREV_9285(ah)) {2634 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {2635 ant_div_ctl1 =2636 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);2637 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {2638 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;2639 ath_info(common, "Enable LNA combining\n");2640 }2641 }2642 }2643 2644 if (AR_SREV_9300_20_OR_LATER(ah)) {2645 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))2646 pCap->hw_caps |= ATH9K_HW_CAP_APM;2647 }2648 2649 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {2650 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);2651 if ((ant_div_ctl1 >> 0x6) == 0x3) {2652 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;2653 ath_info(common, "Enable LNA combining\n");2654 }2655 }2656 2657 if (ath9k_hw_dfs_tested(ah))2658 pCap->hw_caps |= ATH9K_HW_CAP_DFS;2659 2660 tx_chainmask = pCap->tx_chainmask;2661 rx_chainmask = pCap->rx_chainmask;2662 while (tx_chainmask || rx_chainmask) {2663 if (tx_chainmask & BIT(0))2664 pCap->max_txchains++;2665 if (rx_chainmask & BIT(0))2666 pCap->max_rxchains++;2667 2668 tx_chainmask >>= 1;2669 rx_chainmask >>= 1;2670 }2671 2672 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {2673 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))2674 pCap->hw_caps |= ATH9K_HW_CAP_MCI;2675 2676 if (AR_SREV_9462_20_OR_LATER(ah))2677 pCap->hw_caps |= ATH9K_HW_CAP_RTT;2678 }2679 2680 if (AR_SREV_9300_20_OR_LATER(ah) &&2681 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))2682 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;2683 2684#ifdef CONFIG_ATH9K_WOW2685 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))2686 ah->wow.max_patterns = MAX_NUM_PATTERN;2687 else2688 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;2689#endif2690 2691 return 0;2692}2693 2694/****************************/2695/* GPIO / RFKILL / Antennae */2696/****************************/2697 2698static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)2699{2700 int addr;2701 u32 gpio_shift, tmp;2702 2703 if (gpio > 11)2704 addr = AR_GPIO_OUTPUT_MUX3(ah);2705 else if (gpio > 5)2706 addr = AR_GPIO_OUTPUT_MUX2(ah);2707 else2708 addr = AR_GPIO_OUTPUT_MUX1(ah);2709 2710 gpio_shift = (gpio % 6) * 5;2711 2712 if (AR_SREV_9280_20_OR_LATER(ah) ||2713 (addr != AR_GPIO_OUTPUT_MUX1(ah))) {2714 REG_RMW(ah, addr, (type << gpio_shift),2715 (0x1f << gpio_shift));2716 } else {2717 tmp = REG_READ(ah, addr);2718 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);2719 tmp &= ~(0x1f << gpio_shift);2720 tmp |= (type << gpio_shift);2721 REG_WRITE(ah, addr, tmp);2722 }2723}2724 2725/* BSP should set the corresponding MUX register correctly.2726 */2727static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,2728 const char *label)2729{2730 int err;2731 2732 if (ah->caps.gpio_requested & BIT(gpio))2733 return;2734 2735 err = devm_gpio_request_one(ah->dev, gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label);2736 if (err) {2737 ath_err(ath9k_hw_common(ah), "request GPIO%d failed:%d\n",2738 gpio, err);2739 return;2740 }2741 2742 ah->caps.gpio_requested |= BIT(gpio);2743}2744 2745static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,2746 u32 ah_signal_type)2747{2748 u32 gpio_set, gpio_shift = gpio;2749 2750 if (AR_DEVID_7010(ah)) {2751 gpio_set = out ?2752 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;2753 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,2754 AR7010_GPIO_OE_MASK << gpio_shift);2755 } else if (AR_SREV_SOC(ah)) {2756 gpio_set = out ? 1 : 0;2757 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,2758 gpio_set << gpio_shift);2759 } else {2760 gpio_shift = gpio << 1;2761 gpio_set = out ?2762 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;2763 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,2764 AR_GPIO_OE_OUT_DRV << gpio_shift);2765 2766 if (out)2767 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);2768 }2769}2770 2771static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,2772 const char *label, u32 ah_signal_type)2773{2774 WARN_ON(gpio >= ah->caps.num_gpio_pins);2775 2776 if (BIT(gpio) & ah->caps.gpio_mask)2777 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);2778 else if (AR_SREV_SOC(ah))2779 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);2780 else2781 WARN_ON(1);2782}2783 2784void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)2785{2786 ath9k_hw_gpio_request(ah, gpio, false, label, 0);2787}2788EXPORT_SYMBOL(ath9k_hw_gpio_request_in);2789 2790void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,2791 u32 ah_signal_type)2792{2793 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);2794}2795EXPORT_SYMBOL(ath9k_hw_gpio_request_out);2796 2797void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)2798{2799 if (!AR_SREV_SOC(ah))2800 return;2801 2802 WARN_ON(gpio >= ah->caps.num_gpio_pins);2803 2804 if (ah->caps.gpio_requested & BIT(gpio))2805 ah->caps.gpio_requested &= ~BIT(gpio);2806}2807EXPORT_SYMBOL(ath9k_hw_gpio_free);2808 2809u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)2810{2811 u32 val = 0xffffffff;2812 2813#define MS_REG_READ(x, y) \2814 (MS(REG_READ(ah, AR_GPIO_IN_OUT(ah)), x##_GPIO_IN_VAL) & BIT(y))2815 2816 WARN_ON(gpio >= ah->caps.num_gpio_pins);2817 2818 if (BIT(gpio) & ah->caps.gpio_mask) {2819 if (AR_SREV_9271(ah))2820 val = MS_REG_READ(AR9271, gpio);2821 else if (AR_SREV_9287(ah))2822 val = MS_REG_READ(AR9287, gpio);2823 else if (AR_SREV_9285(ah))2824 val = MS_REG_READ(AR9285, gpio);2825 else if (AR_SREV_9280(ah))2826 val = MS_REG_READ(AR928X, gpio);2827 else if (AR_DEVID_7010(ah))2828 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);2829 else if (AR_SREV_9300_20_OR_LATER(ah))2830 val = REG_READ(ah, AR_GPIO_IN(ah)) & BIT(gpio);2831 else2832 val = MS_REG_READ(AR, gpio);2833 } else if (BIT(gpio) & ah->caps.gpio_requested) {2834 val = gpio_get_value(gpio) & BIT(gpio);2835 } else {2836 WARN_ON(1);2837 }2838 2839 return !!val;2840}2841EXPORT_SYMBOL(ath9k_hw_gpio_get);2842 2843void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)2844{2845 WARN_ON(gpio >= ah->caps.num_gpio_pins);2846 2847 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))2848 val = !val;2849 else2850 val = !!val;2851 2852 if (BIT(gpio) & ah->caps.gpio_mask) {2853 u32 out_addr = AR_DEVID_7010(ah) ?2854 AR7010_GPIO_OUT : AR_GPIO_IN_OUT(ah);2855 2856 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));2857 } else if (BIT(gpio) & ah->caps.gpio_requested) {2858 gpio_set_value(gpio, val);2859 } else {2860 WARN_ON(1);2861 }2862}2863EXPORT_SYMBOL(ath9k_hw_set_gpio);2864 2865void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)2866{2867 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));2868}2869EXPORT_SYMBOL(ath9k_hw_setantenna);2870 2871/*********************/2872/* General Operation */2873/*********************/2874 2875u32 ath9k_hw_getrxfilter(struct ath_hw *ah)2876{2877 u32 bits = REG_READ(ah, AR_RX_FILTER);2878 u32 phybits = REG_READ(ah, AR_PHY_ERR);2879 2880 if (phybits & AR_PHY_ERR_RADAR)2881 bits |= ATH9K_RX_FILTER_PHYRADAR;2882 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))2883 bits |= ATH9K_RX_FILTER_PHYERR;2884 2885 return bits;2886}2887EXPORT_SYMBOL(ath9k_hw_getrxfilter);2888 2889void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)2890{2891 u32 phybits;2892 2893 ENABLE_REGWRITE_BUFFER(ah);2894 2895 REG_WRITE(ah, AR_RX_FILTER, bits);2896 2897 phybits = 0;2898 if (bits & ATH9K_RX_FILTER_PHYRADAR)2899 phybits |= AR_PHY_ERR_RADAR;2900 if (bits & ATH9K_RX_FILTER_PHYERR)2901 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;2902 REG_WRITE(ah, AR_PHY_ERR, phybits);2903 2904 if (phybits)2905 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);2906 else2907 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);2908 2909 REGWRITE_BUFFER_FLUSH(ah);2910}2911EXPORT_SYMBOL(ath9k_hw_setrxfilter);2912 2913bool ath9k_hw_phy_disable(struct ath_hw *ah)2914{2915 if (ath9k_hw_mci_is_enabled(ah))2916 ar9003_mci_bt_gain_ctrl(ah);2917 2918 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))2919 return false;2920 2921 ath9k_hw_init_pll(ah, NULL);2922 ah->htc_reset_init = true;2923 return true;2924}2925EXPORT_SYMBOL(ath9k_hw_phy_disable);2926 2927bool ath9k_hw_disable(struct ath_hw *ah)2928{2929 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))2930 return false;2931 2932 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))2933 return false;2934 2935 ath9k_hw_init_pll(ah, NULL);2936 return true;2937}2938EXPORT_SYMBOL(ath9k_hw_disable);2939 2940static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)2941{2942 enum eeprom_param gain_param;2943 2944 if (IS_CHAN_2GHZ(chan))2945 gain_param = EEP_ANTENNA_GAIN_2G;2946 else2947 gain_param = EEP_ANTENNA_GAIN_5G;2948 2949 return ah->eep_ops->get_eeprom(ah, gain_param);2950}2951 2952void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,2953 bool test)2954{2955 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);2956 struct ieee80211_channel *channel;2957 int chan_pwr, new_pwr;2958 u16 ctl = NO_CTL;2959 2960 if (!chan)2961 return;2962 2963 if (!test)2964 ctl = ath9k_regd_get_ctl(reg, chan);2965 2966 channel = chan->chan;2967 chan_pwr = min_t(int, channel->max_power * 2, MAX_COMBINED_POWER);2968 new_pwr = min_t(int, chan_pwr, reg->power_limit);2969 2970 ah->eep_ops->set_txpower(ah, chan, ctl,2971 get_antenna_gain(ah, chan), new_pwr, test);2972}2973 2974void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)2975{2976 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);2977 struct ath9k_channel *chan = ah->curchan;2978 struct ieee80211_channel *channel = chan->chan;2979 2980 reg->power_limit = min_t(u32, limit, MAX_COMBINED_POWER);2981 if (test)2982 channel->max_power = MAX_COMBINED_POWER / 2;2983 2984 ath9k_hw_apply_txpower(ah, chan, test);2985 2986 if (test)2987 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);2988}2989EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);2990 2991void ath9k_hw_setopmode(struct ath_hw *ah)2992{2993 ath9k_hw_set_operating_mode(ah, ah->opmode);2994}2995EXPORT_SYMBOL(ath9k_hw_setopmode);2996 2997void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)2998{2999 REG_WRITE(ah, AR_MCAST_FIL0, filter0);3000 REG_WRITE(ah, AR_MCAST_FIL1, filter1);3001}3002EXPORT_SYMBOL(ath9k_hw_setmcastfilter);3003 3004void ath9k_hw_write_associd(struct ath_hw *ah)3005{3006 struct ath_common *common = ath9k_hw_common(ah);3007 3008 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));3009 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |3010 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));3011}3012EXPORT_SYMBOL(ath9k_hw_write_associd);3013 3014#define ATH9K_MAX_TSF_READ 103015 3016u64 ath9k_hw_gettsf64(struct ath_hw *ah)3017{3018 u32 tsf_lower, tsf_upper1, tsf_upper2;3019 int i;3020 3021 tsf_upper1 = REG_READ(ah, AR_TSF_U32);3022 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {3023 tsf_lower = REG_READ(ah, AR_TSF_L32);3024 tsf_upper2 = REG_READ(ah, AR_TSF_U32);3025 if (tsf_upper2 == tsf_upper1)3026 break;3027 tsf_upper1 = tsf_upper2;3028 }3029 3030 WARN_ON( i == ATH9K_MAX_TSF_READ );3031 3032 return (((u64)tsf_upper1 << 32) | tsf_lower);3033}3034EXPORT_SYMBOL(ath9k_hw_gettsf64);3035 3036void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)3037{3038 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);3039 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);3040}3041EXPORT_SYMBOL(ath9k_hw_settsf64);3042 3043void ath9k_hw_reset_tsf(struct ath_hw *ah)3044{3045 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,3046 AH_TSF_WRITE_TIMEOUT))3047 ath_dbg(ath9k_hw_common(ah), RESET,3048 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");3049 3050 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);3051}3052EXPORT_SYMBOL(ath9k_hw_reset_tsf);3053 3054void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)3055{3056 if (set)3057 ah->misc_mode |= AR_PCU_TX_ADD_TSF;3058 else3059 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;3060}3061EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);3062 3063void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)3064{3065 u32 macmode;3066 3067 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)3068 macmode = AR_2040_JOINED_RX_CLEAR;3069 else3070 macmode = 0;3071 3072 REG_WRITE(ah, AR_2040_MODE, macmode);3073}3074 3075/* HW Generic timers configuration */3076 3077static const struct ath_gen_timer_configuration gen_tmr_configuration[] =3078{3079 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3080 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3081 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3082 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3083 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3084 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3085 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3086 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},3087 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},3088 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,3089 AR_NDP2_TIMER_MODE, 0x0002},3090 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,3091 AR_NDP2_TIMER_MODE, 0x0004},3092 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,3093 AR_NDP2_TIMER_MODE, 0x0008},3094 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,3095 AR_NDP2_TIMER_MODE, 0x0010},3096 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,3097 AR_NDP2_TIMER_MODE, 0x0020},3098 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,3099 AR_NDP2_TIMER_MODE, 0x0040},3100 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,3101 AR_NDP2_TIMER_MODE, 0x0080}3102};3103 3104/* HW generic timer primitives */3105 3106u32 ath9k_hw_gettsf32(struct ath_hw *ah)3107{3108 return REG_READ(ah, AR_TSF_L32);3109}3110EXPORT_SYMBOL(ath9k_hw_gettsf32);3111 3112void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)3113{3114 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;3115 3116 if (timer_table->tsf2_enabled) {3117 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);3118 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);3119 }3120}3121 3122struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,3123 void (*trigger)(void *),3124 void (*overflow)(void *),3125 void *arg,3126 u8 timer_index)3127{3128 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;3129 struct ath_gen_timer *timer;3130 3131 if ((timer_index < AR_FIRST_NDP_TIMER) ||3132 (timer_index >= ATH_MAX_GEN_TIMER))3133 return NULL;3134 3135 if ((timer_index > AR_FIRST_NDP_TIMER) &&3136 !AR_SREV_9300_20_OR_LATER(ah))3137 return NULL;3138 3139 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);3140 if (timer == NULL)3141 return NULL;3142 3143 /* allocate a hardware generic timer slot */3144 timer_table->timers[timer_index] = timer;3145 timer->index = timer_index;3146 timer->trigger = trigger;3147 timer->overflow = overflow;3148 timer->arg = arg;3149 3150 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {3151 timer_table->tsf2_enabled = true;3152 ath9k_hw_gen_timer_start_tsf2(ah);3153 }3154 3155 return timer;3156}3157EXPORT_SYMBOL(ath_gen_timer_alloc);3158 3159void ath9k_hw_gen_timer_start(struct ath_hw *ah,3160 struct ath_gen_timer *timer,3161 u32 timer_next,3162 u32 timer_period)3163{3164 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;3165 u32 mask = 0;3166 3167 timer_table->timer_mask |= BIT(timer->index);3168 3169 /*3170 * Program generic timer registers3171 */3172 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,3173 timer_next);3174 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,3175 timer_period);3176 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,3177 gen_tmr_configuration[timer->index].mode_mask);3178 3179 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {3180 /*3181 * Starting from AR9462, each generic timer can select which tsf3182 * to use. But we still follow the old rule, 0 - 7 use tsf and3183 * 8 - 15 use tsf2.3184 */3185 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))3186 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,3187 (1 << timer->index));3188 else3189 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,3190 (1 << timer->index));3191 }3192 3193 if (timer->trigger)3194 mask |= SM(AR_GENTMR_BIT(timer->index),3195 AR_IMR_S5_GENTIMER_TRIG);3196 if (timer->overflow)3197 mask |= SM(AR_GENTMR_BIT(timer->index),3198 AR_IMR_S5_GENTIMER_THRESH);3199 3200 REG_SET_BIT(ah, AR_IMR_S5, mask);3201 3202 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {3203 ah->imask |= ATH9K_INT_GENTIMER;3204 ath9k_hw_set_interrupts(ah);3205 }3206}3207EXPORT_SYMBOL(ath9k_hw_gen_timer_start);3208 3209void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)3210{3211 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;3212 3213 /* Clear generic timer enable bits. */3214 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,3215 gen_tmr_configuration[timer->index].mode_mask);3216 3217 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {3218 /*3219 * Need to switch back to TSF if it was using TSF2.3220 */3221 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {3222 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,3223 (1 << timer->index));3224 }3225 }3226 3227 /* Disable both trigger and thresh interrupt masks */3228 REG_CLR_BIT(ah, AR_IMR_S5,3229 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |3230 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));3231 3232 timer_table->timer_mask &= ~BIT(timer->index);3233 3234 if (timer_table->timer_mask == 0) {3235 ah->imask &= ~ATH9K_INT_GENTIMER;3236 ath9k_hw_set_interrupts(ah);3237 }3238}3239EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);3240 3241void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)3242{3243 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;3244 3245 /* free the hardware generic timer slot */3246 timer_table->timers[timer->index] = NULL;3247 kfree(timer);3248}3249EXPORT_SYMBOL(ath_gen_timer_free);3250 3251/*3252 * Generic Timer Interrupts handling3253 */3254void ath_gen_timer_isr(struct ath_hw *ah)3255{3256 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;3257 struct ath_gen_timer *timer;3258 unsigned long trigger_mask, thresh_mask;3259 unsigned int index;3260 3261 /* get hardware generic timer interrupt status */3262 trigger_mask = ah->intr_gen_timer_trigger;3263 thresh_mask = ah->intr_gen_timer_thresh;3264 trigger_mask &= timer_table->timer_mask;3265 thresh_mask &= timer_table->timer_mask;3266 3267 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {3268 timer = timer_table->timers[index];3269 if (!timer)3270 continue;3271 if (!timer->overflow)3272 continue;3273 3274 trigger_mask &= ~BIT(index);3275 timer->overflow(timer->arg);3276 }3277 3278 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {3279 timer = timer_table->timers[index];3280 if (!timer)3281 continue;3282 if (!timer->trigger)3283 continue;3284 timer->trigger(timer->arg);3285 }3286}3287EXPORT_SYMBOL(ath_gen_timer_isr);3288 3289/********/3290/* HTC */3291/********/3292 3293static struct {3294 u32 version;3295 const char * name;3296} ath_mac_bb_names[] = {3297 /* Devices with external radios */3298 { AR_SREV_VERSION_5416_PCI, "5416" },3299 { AR_SREV_VERSION_5416_PCIE, "5418" },3300 { AR_SREV_VERSION_9100, "9100" },3301 { AR_SREV_VERSION_9160, "9160" },3302 /* Single-chip solutions */3303 { AR_SREV_VERSION_9280, "9280" },3304 { AR_SREV_VERSION_9285, "9285" },3305 { AR_SREV_VERSION_9287, "9287" },3306 { AR_SREV_VERSION_9271, "9271" },3307 { AR_SREV_VERSION_9300, "9300" },3308 { AR_SREV_VERSION_9330, "9330" },3309 { AR_SREV_VERSION_9340, "9340" },3310 { AR_SREV_VERSION_9485, "9485" },3311 { AR_SREV_VERSION_9462, "9462" },3312 { AR_SREV_VERSION_9550, "9550" },3313 { AR_SREV_VERSION_9565, "9565" },3314 { AR_SREV_VERSION_9531, "9531" },3315 { AR_SREV_VERSION_9561, "9561" },3316};3317 3318/* For devices with external radios */3319static struct {3320 u16 version;3321 const char * name;3322} ath_rf_names[] = {3323 { 0, "5133" },3324 { AR_RAD5133_SREV_MAJOR, "5133" },3325 { AR_RAD5122_SREV_MAJOR, "5122" },3326 { AR_RAD2133_SREV_MAJOR, "2133" },3327 { AR_RAD2122_SREV_MAJOR, "2122" }3328};3329 3330/*3331 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.3332 */3333static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)3334{3335 int i;3336 3337 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {3338 if (ath_mac_bb_names[i].version == mac_bb_version) {3339 return ath_mac_bb_names[i].name;3340 }3341 }3342 3343 return "????";3344}3345 3346/*3347 * Return the RF name. "????" is returned if the RF is unknown.3348 * Used for devices with external radios.3349 */3350static const char *ath9k_hw_rf_name(u16 rf_version)3351{3352 int i;3353 3354 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {3355 if (ath_rf_names[i].version == rf_version) {3356 return ath_rf_names[i].name;3357 }3358 }3359 3360 return "????";3361}3362 3363void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)3364{3365 int used;3366 3367 /* chipsets >= AR9280 are single-chip */3368 if (AR_SREV_9280_20_OR_LATER(ah)) {3369 used = scnprintf(hw_name, len,3370 "Atheros AR%s Rev:%x",3371 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),3372 ah->hw_version.macRev);3373 }3374 else {3375 used = scnprintf(hw_name, len,3376 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",3377 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),3378 ah->hw_version.macRev,3379 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev3380 & AR_RADIO_SREV_MAJOR)),3381 ah->hw_version.phyRev);3382 }3383 3384 hw_name[used] = '\0';3385}3386EXPORT_SYMBOL(ath9k_hw_name);3387