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1/*2 * Copyright (c) 2008-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt18 19#include <linux/dma-mapping.h>20#include <linux/slab.h>21#include <linux/ath9k_platform.h>22#include <linux/module.h>23#include <linux/of.h>24#include <linux/of_net.h>25#include <linux/nvmem-consumer.h>26#include <linux/relay.h>27#include <linux/dmi.h>28#include <net/ieee80211_radiotap.h>29 30#include "ath9k.h"31 32struct ath9k_eeprom_ctx {33 struct completion complete;34 struct ath_hw *ah;35};36 37static char *dev_info = "ath9k";38 39MODULE_AUTHOR("Atheros Communications");40MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");41MODULE_LICENSE("Dual BSD/GPL");42 43static unsigned int ath9k_debug = ATH_DBG_DEFAULT;44module_param_named(debug, ath9k_debug, uint, 0);45MODULE_PARM_DESC(debug, "Debugging mask");46 47int ath9k_modparam_nohwcrypt;48module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);49MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");50 51int ath9k_led_blink;52module_param_named(blink, ath9k_led_blink, int, 0444);53MODULE_PARM_DESC(blink, "Enable LED blink on activity");54 55static int ath9k_led_active_high = -1;56module_param_named(led_active_high, ath9k_led_active_high, int, 0444);57MODULE_PARM_DESC(led_active_high, "Invert LED polarity");58 59static int ath9k_btcoex_enable;60module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);61MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");62 63static int ath9k_bt_ant_diversity;64module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);65MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");66 67static int ath9k_ps_enable;68module_param_named(ps_enable, ath9k_ps_enable, int, 0444);69MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");70 71#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT72 73int ath9k_use_chanctx;74module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);75MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");76 77#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */78 79int ath9k_use_msi;80module_param_named(use_msi, ath9k_use_msi, int, 0444);81MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible");82 83bool is_ath9k_unloaded;84 85#ifdef CONFIG_MAC80211_LEDS86static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {87 { .throughput = 0 * 1024, .blink_time = 334 },88 { .throughput = 1 * 1024, .blink_time = 260 },89 { .throughput = 5 * 1024, .blink_time = 220 },90 { .throughput = 10 * 1024, .blink_time = 190 },91 { .throughput = 20 * 1024, .blink_time = 170 },92 { .throughput = 50 * 1024, .blink_time = 150 },93 { .throughput = 70 * 1024, .blink_time = 130 },94 { .throughput = 100 * 1024, .blink_time = 110 },95 { .throughput = 200 * 1024, .blink_time = 80 },96 { .throughput = 300 * 1024, .blink_time = 50 },97};98#endif99 100static int __init set_use_msi(const struct dmi_system_id *dmi)101{102 ath9k_use_msi = 1;103 return 1;104}105 106static const struct dmi_system_id ath9k_quirks[] __initconst = {107 {108 .callback = set_use_msi,109 .ident = "Dell Inspiron 24-3460",110 .matches = {111 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),112 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"),113 },114 },115 {116 .callback = set_use_msi,117 .ident = "Dell Vostro 3262",118 .matches = {119 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),120 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"),121 },122 },123 {124 .callback = set_use_msi,125 .ident = "Dell Inspiron 3472",126 .matches = {127 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),128 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"),129 },130 },131 {132 .callback = set_use_msi,133 .ident = "Dell Vostro 15-3572",134 .matches = {135 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),136 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"),137 },138 },139 {140 .callback = set_use_msi,141 .ident = "Dell Inspiron 14-3473",142 .matches = {143 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),144 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"),145 },146 },147 {}148};149 150static void ath9k_deinit_softc(struct ath_softc *sc);151 152static void ath9k_op_ps_wakeup(struct ath_common *common)153{154 ath9k_ps_wakeup(common->priv);155}156 157static void ath9k_op_ps_restore(struct ath_common *common)158{159 ath9k_ps_restore(common->priv);160}161 162static const struct ath_ps_ops ath9k_ps_ops = {163 .wakeup = ath9k_op_ps_wakeup,164 .restore = ath9k_op_ps_restore,165};166 167/*168 * Read and write, they both share the same lock. We do this to serialize169 * reads and writes on Atheros 802.11n PCI devices only. This is required170 * as the FIFO on these devices can only accept sanely 2 requests.171 */172 173static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)174{175 struct ath_hw *ah = hw_priv;176 struct ath_common *common = ath9k_hw_common(ah);177 struct ath_softc *sc = common->priv;178 179 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {180 unsigned long flags;181 spin_lock_irqsave(&sc->sc_serial_rw, flags);182 iowrite32(val, sc->mem + reg_offset);183 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);184 } else185 iowrite32(val, sc->mem + reg_offset);186}187 188static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)189{190 struct ath_hw *ah = hw_priv;191 struct ath_common *common = ath9k_hw_common(ah);192 struct ath_softc *sc = common->priv;193 u32 val;194 195 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {196 unsigned long flags;197 spin_lock_irqsave(&sc->sc_serial_rw, flags);198 val = ioread32(sc->mem + reg_offset);199 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);200 } else201 val = ioread32(sc->mem + reg_offset);202 return val;203}204 205static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,206 u32 *val, u16 count)207{208 int i;209 210 for (i = 0; i < count; i++)211 val[i] = ath9k_ioread32(hw_priv, addr[i]);212}213 214 215static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,216 u32 set, u32 clr)217{218 u32 val;219 220 val = ioread32(sc->mem + reg_offset);221 val &= ~clr;222 val |= set;223 iowrite32(val, sc->mem + reg_offset);224 225 return val;226}227 228static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)229{230 struct ath_hw *ah = hw_priv;231 struct ath_common *common = ath9k_hw_common(ah);232 struct ath_softc *sc = common->priv;233 unsigned long flags;234 u32 val;235 236 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {237 spin_lock_irqsave(&sc->sc_serial_rw, flags);238 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);239 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);240 } else241 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);242 243 return val;244}245 246/**************************/247/* Initialization */248/**************************/249 250static void ath9k_reg_notifier(struct wiphy *wiphy,251 struct regulatory_request *request)252{253 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);254 struct ath_softc *sc = hw->priv;255 struct ath_hw *ah = sc->sc_ah;256 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);257 258 ath_reg_notifier_apply(wiphy, request, reg);259 260 /* synchronize DFS detector if regulatory domain changed */261 if (sc->dfs_detector != NULL)262 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,263 request->dfs_region);264 265 /* Set tx power */266 if (!ah->curchan)267 return;268 269 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;270 ath9k_ps_wakeup(sc);271 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);272 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,273 sc->cur_chan->txpower,274 &sc->cur_chan->cur_txpower);275 ath9k_ps_restore(sc);276}277 278/*279 * This function will allocate both the DMA descriptor structure, and the280 * buffers it contains. These are used to contain the descriptors used281 * by the system.282*/283int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,284 struct list_head *head, const char *name,285 int nbuf, int ndesc, bool is_tx)286{287 struct ath_common *common = ath9k_hw_common(sc->sc_ah);288 u8 *ds;289 int i, bsize, desc_len;290 291 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",292 name, nbuf, ndesc);293 294 INIT_LIST_HEAD(head);295 296 if (is_tx)297 desc_len = sc->sc_ah->caps.tx_desc_len;298 else299 desc_len = sizeof(struct ath_desc);300 301 /* ath_desc must be a multiple of DWORDs */302 if ((desc_len % 4) != 0) {303 ath_err(common, "ath_desc not DWORD aligned\n");304 BUG_ON((desc_len % 4) != 0);305 return -ENOMEM;306 }307 308 dd->dd_desc_len = desc_len * nbuf * ndesc;309 310 /*311 * Need additional DMA memory because we can't use312 * descriptors that cross the 4K page boundary. Assume313 * one skipped descriptor per 4K page.314 */315 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {316 u32 ndesc_skipped =317 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);318 u32 dma_len;319 320 while (ndesc_skipped) {321 dma_len = ndesc_skipped * desc_len;322 dd->dd_desc_len += dma_len;323 324 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);325 }326 }327 328 /* allocate descriptors */329 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,330 &dd->dd_desc_paddr, GFP_KERNEL);331 if (!dd->dd_desc)332 return -ENOMEM;333 334 ds = dd->dd_desc;335 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",336 name, ds, (u32) dd->dd_desc_len,337 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);338 339 /* allocate buffers */340 if (is_tx) {341 struct ath_buf *bf;342 343 bsize = sizeof(struct ath_buf) * nbuf;344 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);345 if (!bf)346 return -ENOMEM;347 348 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {349 bf->bf_desc = ds;350 bf->bf_daddr = DS2PHYS(dd, ds);351 352 if (!(sc->sc_ah->caps.hw_caps &353 ATH9K_HW_CAP_4KB_SPLITTRANS)) {354 /*355 * Skip descriptor addresses which can cause 4KB356 * boundary crossing (addr + length) with a 32 dword357 * descriptor fetch.358 */359 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {360 BUG_ON((caddr_t) bf->bf_desc >=361 ((caddr_t) dd->dd_desc +362 dd->dd_desc_len));363 364 ds += (desc_len * ndesc);365 bf->bf_desc = ds;366 bf->bf_daddr = DS2PHYS(dd, ds);367 }368 }369 list_add_tail(&bf->list, head);370 }371 } else {372 struct ath_rxbuf *bf;373 374 bsize = sizeof(struct ath_rxbuf) * nbuf;375 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);376 if (!bf)377 return -ENOMEM;378 379 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {380 bf->bf_desc = ds;381 bf->bf_daddr = DS2PHYS(dd, ds);382 383 if (!(sc->sc_ah->caps.hw_caps &384 ATH9K_HW_CAP_4KB_SPLITTRANS)) {385 /*386 * Skip descriptor addresses which can cause 4KB387 * boundary crossing (addr + length) with a 32 dword388 * descriptor fetch.389 */390 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {391 BUG_ON((caddr_t) bf->bf_desc >=392 ((caddr_t) dd->dd_desc +393 dd->dd_desc_len));394 395 ds += (desc_len * ndesc);396 bf->bf_desc = ds;397 bf->bf_daddr = DS2PHYS(dd, ds);398 }399 }400 list_add_tail(&bf->list, head);401 }402 }403 return 0;404}405 406static int ath9k_init_queues(struct ath_softc *sc)407{408 int i = 0;409 410 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);411 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);412 ath_cabq_update(sc);413 414 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);415 416 for (i = 0; i < IEEE80211_NUM_ACS; i++) {417 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);418 sc->tx.txq_map[i]->mac80211_qnum = i;419 }420 return 0;421}422 423static void ath9k_init_misc(struct ath_softc *sc)424{425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);426 int i = 0;427 428 timer_setup(&common->ani.timer, ath_ani_calibrate, 0);429 430 common->last_rssi = ATH_RSSI_DUMMY_MARKER;431 eth_broadcast_addr(common->bssidmask);432 sc->beacon.slottime = 9;433 434 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)435 sc->beacon.bslot[i] = NULL;436 437 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)438 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;439 440 sc->spec_priv.ah = sc->sc_ah;441 sc->spec_priv.spec_config.enabled = 0;442 sc->spec_priv.spec_config.short_repeat = true;443 sc->spec_priv.spec_config.count = 8;444 sc->spec_priv.spec_config.endless = false;445 sc->spec_priv.spec_config.period = 0xFF;446 sc->spec_priv.spec_config.fft_period = 0xF;447}448 449static void ath9k_init_pcoem_platform(struct ath_softc *sc)450{451 struct ath_hw *ah = sc->sc_ah;452 struct ath9k_hw_capabilities *pCap = &ah->caps;453 struct ath_common *common = ath9k_hw_common(ah);454 455 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))456 return;457 458 if (common->bus_ops->ath_bus_type != ATH_PCI)459 return;460 461 if (sc->driver_data & (ATH9K_PCI_CUS198 |462 ATH9K_PCI_CUS230)) {463 ah->config.xlna_gpio = 9;464 ah->config.xatten_margin_cfg = true;465 ah->config.alt_mingainidx = true;466 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;467 sc->ant_comb.low_rssi_thresh = 20;468 sc->ant_comb.fast_div_bias = 3;469 470 ath_info(common, "Set parameters for %s\n",471 (sc->driver_data & ATH9K_PCI_CUS198) ?472 "CUS198" : "CUS230");473 }474 475 if (sc->driver_data & ATH9K_PCI_CUS217)476 ath_info(common, "CUS217 card detected\n");477 478 if (sc->driver_data & ATH9K_PCI_CUS252)479 ath_info(common, "CUS252 card detected\n");480 481 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)482 ath_info(common, "WB335 1-ANT card detected\n");483 484 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)485 ath_info(common, "WB335 2-ANT card detected\n");486 487 if (sc->driver_data & ATH9K_PCI_KILLER)488 ath_info(common, "Killer Wireless card detected\n");489 490 /*491 * Some WB335 cards do not support antenna diversity. Since492 * we use a hardcoded value for AR9565 instead of using the493 * EEPROM/OTP data, remove the combining feature from494 * the HW capabilities bitmap.495 */496 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {497 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))498 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;499 }500 501 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {502 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;503 ath_info(common, "Set BT/WLAN RX diversity capability\n");504 }505 506 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {507 ah->config.pcie_waen = 0x0040473b;508 ath_info(common, "Enable WAR for ASPM D3/L1\n");509 }510 511 /*512 * The default value of pll_pwrsave is 1.513 * For certain AR9485 cards, it is set to 0.514 * For AR9462, AR9565 it's set to 7.515 */516 ah->config.pll_pwrsave = 1;517 518 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {519 ah->config.pll_pwrsave = 0;520 ath_info(common, "Disable PLL PowerSave\n");521 }522 523 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)524 ah->config.led_active_high = true;525}526 527static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,528 void *ctx)529{530 struct ath9k_eeprom_ctx *ec = ctx;531 532 if (eeprom_blob)533 ec->ah->eeprom_blob = eeprom_blob;534 535 complete(&ec->complete);536}537 538static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)539{540 struct ath9k_eeprom_ctx ec;541 struct ath_hw *ah = sc->sc_ah;542 int err;543 544 /* try to load the EEPROM content asynchronously */545 init_completion(&ec.complete);546 ec.ah = sc->sc_ah;547 548 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,549 &ec, ath9k_eeprom_request_cb);550 if (err < 0) {551 ath_err(ath9k_hw_common(ah),552 "EEPROM request failed\n");553 return err;554 }555 556 wait_for_completion(&ec.complete);557 558 if (!ah->eeprom_blob) {559 ath_err(ath9k_hw_common(ah),560 "Unable to load EEPROM file %s\n", name);561 return -EINVAL;562 }563 564 return 0;565}566 567static void ath9k_eeprom_release(struct ath_softc *sc)568{569 release_firmware(sc->sc_ah->eeprom_blob);570}571 572static int ath9k_nvmem_request_eeprom(struct ath_softc *sc)573{574 struct ath_hw *ah = sc->sc_ah;575 struct nvmem_cell *cell;576 void *buf;577 size_t len;578 int err;579 580 cell = devm_nvmem_cell_get(sc->dev, "calibration");581 if (IS_ERR(cell)) {582 err = PTR_ERR(cell);583 584 /* nvmem cell might not be defined, or the nvmem585 * subsystem isn't included. In this case, follow586 * the established "just return 0;" convention of587 * ath9k_init_platform to say:588 * "All good. Nothing to see here. Please go on."589 */590 if (err == -ENOENT || err == -EOPNOTSUPP)591 return 0;592 593 return err;594 }595 596 buf = nvmem_cell_read(cell, &len);597 if (IS_ERR(buf))598 return PTR_ERR(buf);599 600 /* run basic sanity checks on the returned nvram cell length.601 * That length has to be a multiple of a "u16" (i.e.: & 1).602 * Furthermore, it has to be more than "let's say" 512 bytes603 * but less than the maximum of AR9300_EEPROM_SIZE (16kb).604 */605 if ((len & 1) == 1 || len < 512 || len >= AR9300_EEPROM_SIZE) {606 kfree(buf);607 return -EINVAL;608 }609 610 /* devres manages the calibration values release on shutdown */611 ah->nvmem_blob = devm_kmemdup(sc->dev, buf, len, GFP_KERNEL);612 kfree(buf);613 if (!ah->nvmem_blob)614 return -ENOMEM;615 616 ah->nvmem_blob_len = len;617 ah->ah_flags &= ~AH_USE_EEPROM;618 ah->ah_flags |= AH_NO_EEP_SWAP;619 620 return 0;621}622 623static int ath9k_init_platform(struct ath_softc *sc)624{625 struct ath9k_platform_data *pdata = sc->dev->platform_data;626 struct ath_hw *ah = sc->sc_ah;627 struct ath_common *common = ath9k_hw_common(ah);628 int ret;629 630 if (!pdata)631 return 0;632 633 if (!pdata->use_eeprom) {634 ah->ah_flags &= ~AH_USE_EEPROM;635 ah->gpio_mask = pdata->gpio_mask;636 ah->gpio_val = pdata->gpio_val;637 ah->led_pin = pdata->led_pin;638 ah->is_clk_25mhz = pdata->is_clk_25mhz;639 ah->get_mac_revision = pdata->get_mac_revision;640 ah->external_reset = pdata->external_reset;641 ah->disable_2ghz = pdata->disable_2ghz;642 ah->disable_5ghz = pdata->disable_5ghz;643 644 if (!pdata->endian_check)645 ah->ah_flags |= AH_NO_EEP_SWAP;646 }647 648 if (pdata->eeprom_name) {649 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);650 if (ret)651 return ret;652 }653 654 if (pdata->led_active_high)655 ah->config.led_active_high = true;656 657 if (pdata->tx_gain_buffalo)658 ah->config.tx_gain_buffalo = true;659 660 if (pdata->macaddr)661 ether_addr_copy(common->macaddr, pdata->macaddr);662 663 return 0;664}665 666static int ath9k_of_init(struct ath_softc *sc)667{668 struct device_node *np = sc->dev->of_node;669 struct ath_hw *ah = sc->sc_ah;670 struct ath_common *common = ath9k_hw_common(ah);671 enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;672 char eeprom_name[100];673 int ret;674 675 if (!of_device_is_available(np))676 return 0;677 678 ath_dbg(common, CONFIG, "parsing configuration from OF node\n");679 680 if (of_property_read_bool(np, "qca,no-eeprom")) {681 /* ath9k-eeprom-<bus>-<id>.bin */682 scnprintf(eeprom_name, sizeof(eeprom_name),683 "ath9k-eeprom-%s-%s.bin",684 ath_bus_type_to_string(bus_type), dev_name(ah->dev));685 686 ret = ath9k_eeprom_request(sc, eeprom_name);687 if (ret)688 return ret;689 690 ah->ah_flags &= ~AH_USE_EEPROM;691 ah->ah_flags |= AH_NO_EEP_SWAP;692 }693 694 of_get_mac_address(np, common->macaddr);695 696 return 0;697}698 699static int ath9k_init_softc(u16 devid, struct ath_softc *sc,700 const struct ath_bus_ops *bus_ops)701{702 struct ath_hw *ah = NULL;703 struct ath9k_hw_capabilities *pCap;704 struct ath_common *common;705 int ret = 0, i;706 int csz = 0;707 708 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);709 if (!ah)710 return -ENOMEM;711 712 ah->dev = sc->dev;713 ah->hw = sc->hw;714 ah->hw_version.devid = devid;715 ah->ah_flags |= AH_USE_EEPROM;716 ah->led_pin = -1;717 ah->reg_ops.read = ath9k_ioread32;718 ah->reg_ops.multi_read = ath9k_multi_ioread32;719 ah->reg_ops.write = ath9k_iowrite32;720 ah->reg_ops.rmw = ath9k_reg_rmw;721 pCap = &ah->caps;722 723 common = ath9k_hw_common(ah);724 725 /* Will be cleared in ath9k_start() */726 set_bit(ATH_OP_INVALID, &common->op_flags);727 728 sc->sc_ah = ah;729 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);730 sc->tx99_power = MAX_RATE_POWER + 1;731 init_waitqueue_head(&sc->tx_wait);732 sc->cur_chan = &sc->chanctx[0];733 if (!ath9k_is_chanctx_enabled())734 sc->cur_chan->hw_queue_base = 0;735 736 common->ops = &ah->reg_ops;737 common->bus_ops = bus_ops;738 common->ps_ops = &ath9k_ps_ops;739 common->ah = ah;740 common->hw = sc->hw;741 common->priv = sc;742 common->debug_mask = ath9k_debug;743 common->btcoex_enabled = ath9k_btcoex_enable == 1;744 common->disable_ani = false;745 746 /*747 * Platform quirks.748 */749 ath9k_init_pcoem_platform(sc);750 751 ret = ath9k_init_platform(sc);752 if (ret)753 return ret;754 755 ret = ath9k_of_init(sc);756 if (ret)757 return ret;758 759 ret = ath9k_nvmem_request_eeprom(sc);760 if (ret)761 return ret;762 763 if (ath9k_led_active_high != -1)764 ah->config.led_active_high = ath9k_led_active_high == 1;765 766 /*767 * Enable WLAN/BT RX Antenna diversity only when:768 *769 * - BTCOEX is disabled.770 * - the user manually requests the feature.771 * - the HW cap is set using the platform data.772 */773 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&774 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))775 common->bt_ant_diversity = 1;776 777 spin_lock_init(&common->cc_lock);778 spin_lock_init(&sc->intr_lock);779 spin_lock_init(&sc->sc_serial_rw);780 spin_lock_init(&sc->sc_pm_lock);781 spin_lock_init(&sc->chan_lock);782 mutex_init(&sc->mutex);783 tasklet_setup(&sc->intr_tq, ath9k_tasklet);784 tasklet_setup(&sc->bcon_tasklet, ath9k_beacon_tasklet);785 786 timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0);787 INIT_WORK(&sc->hw_reset_work, ath_reset_work);788 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);789 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);790 INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work);791 792 ath9k_init_channel_context(sc);793 794 /*795 * Cache line size is used to size and align various796 * structures used to communicate with the hardware.797 */798 ath_read_cachesize(common, &csz);799 common->cachelsz = csz << 2; /* convert to bytes */800 801 /* Initializes the hardware for all supported chipsets */802 ret = ath9k_hw_init(ah);803 if (ret)804 goto err_hw;805 806 ret = ath9k_init_queues(sc);807 if (ret)808 goto err_queues;809 810 ret = ath9k_init_btcoex(sc);811 if (ret)812 goto err_btcoex;813 814 ret = ath9k_cmn_init_channels_rates(common);815 if (ret)816 goto err_btcoex;817 818 ret = ath9k_init_p2p(sc);819 if (ret)820 goto err_btcoex;821 822 ath9k_cmn_init_crypto(sc->sc_ah);823 ath9k_init_misc(sc);824 ath_chanctx_init(sc);825 ath9k_offchannel_init(sc);826 827 if (common->bus_ops->aspm_init)828 common->bus_ops->aspm_init(common);829 830 return 0;831 832err_btcoex:833 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)834 if (ATH_TXQ_SETUP(sc, i))835 ath_tx_cleanupq(sc, &sc->tx.txq[i]);836err_queues:837 ath9k_hw_deinit(ah);838err_hw:839 ath9k_eeprom_release(sc);840 dev_kfree_skb_any(sc->tx99_skb);841 return ret;842}843 844static void ath9k_init_band_txpower(struct ath_softc *sc, int band)845{846 struct ieee80211_supported_band *sband;847 struct ieee80211_channel *chan;848 struct ath_hw *ah = sc->sc_ah;849 struct ath_common *common = ath9k_hw_common(ah);850 struct cfg80211_chan_def chandef;851 int i;852 853 sband = &common->sbands[band];854 for (i = 0; i < sband->n_channels; i++) {855 chan = &sband->channels[i];856 ah->curchan = &ah->channels[chan->hw_value];857 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);858 ath9k_cmn_get_channel(sc->hw, ah, &chandef);859 ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true);860 }861}862 863static void ath9k_init_txpower_limits(struct ath_softc *sc)864{865 struct ath_hw *ah = sc->sc_ah;866 struct ath9k_channel *curchan = ah->curchan;867 868 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)869 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);870 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)871 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);872 873 ah->curchan = curchan;874}875 876static const struct ieee80211_iface_limit if_limits[] = {877 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },878 { .max = 8, .types =879#ifdef CONFIG_MAC80211_MESH880 BIT(NL80211_IFTYPE_MESH_POINT) |881#endif882 BIT(NL80211_IFTYPE_AP) },883 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |884 BIT(NL80211_IFTYPE_P2P_GO) },885};886 887#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT888 889static const struct ieee80211_iface_limit if_limits_multi[] = {890 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |891 BIT(NL80211_IFTYPE_AP) |892 BIT(NL80211_IFTYPE_P2P_CLIENT) |893 BIT(NL80211_IFTYPE_P2P_GO) },894 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },895 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },896};897 898static const struct ieee80211_iface_combination if_comb_multi[] = {899 {900 .limits = if_limits_multi,901 .n_limits = ARRAY_SIZE(if_limits_multi),902 .max_interfaces = 3,903 .num_different_channels = 2,904 .beacon_int_infra_match = true,905 },906};907 908#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */909 910static const struct ieee80211_iface_combination if_comb[] = {911 {912 .limits = if_limits,913 .n_limits = ARRAY_SIZE(if_limits),914 .max_interfaces = 2048,915 .num_different_channels = 1,916 .beacon_int_infra_match = true,917#ifdef CONFIG_ATH9K_DFS_CERTIFIED918 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |919 BIT(NL80211_CHAN_WIDTH_20) |920 BIT(NL80211_CHAN_WIDTH_40),921#endif922 },923};924 925#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT926static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)927{928 struct ath_hw *ah = sc->sc_ah;929 struct ath_common *common = ath9k_hw_common(ah);930 931 if (!ath9k_is_chanctx_enabled())932 return;933 934 ieee80211_hw_set(hw, QUEUE_CONTROL);935 hw->queues = ATH9K_NUM_TX_QUEUES;936 hw->offchannel_tx_hw_queue = hw->queues - 1;937 hw->wiphy->iface_combinations = if_comb_multi;938 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);939 hw->wiphy->max_scan_ssids = 255;940 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;941 hw->wiphy->max_remain_on_channel_duration = 10000;942 hw->chanctx_data_size = sizeof(void *);943 hw->extra_beacon_tailroom =944 sizeof(struct ieee80211_p2p_noa_attr) + 9;945 946 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");947}948#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */949 950static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)951{952 struct ath_hw *ah = sc->sc_ah;953 struct ath_common *common = ath9k_hw_common(ah);954 955 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);956 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);957 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);958 ieee80211_hw_set(hw, SPECTRUM_MGMT);959 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);960 ieee80211_hw_set(hw, SIGNAL_DBM);961 ieee80211_hw_set(hw, RX_INCLUDES_FCS);962 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);963 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);964 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);965 966 if (ath9k_ps_enable)967 ieee80211_hw_set(hw, SUPPORTS_PS);968 969 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {970 ieee80211_hw_set(hw, AMPDU_AGGREGATION);971 972 if (AR_SREV_9280_20_OR_LATER(ah))973 hw->radiotap_mcs_details |=974 IEEE80211_RADIOTAP_MCS_HAVE_STBC;975 }976 977 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)978 ieee80211_hw_set(hw, MFP_CAPABLE);979 980 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |981 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |982 NL80211_FEATURE_P2P_GO_CTWIN;983 984 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {985 hw->wiphy->interface_modes =986 BIT(NL80211_IFTYPE_P2P_GO) |987 BIT(NL80211_IFTYPE_P2P_CLIENT) |988 BIT(NL80211_IFTYPE_AP) |989 BIT(NL80211_IFTYPE_STATION) |990 BIT(NL80211_IFTYPE_ADHOC) |991 BIT(NL80211_IFTYPE_MESH_POINT) |992 BIT(NL80211_IFTYPE_OCB);993 994 if (ath9k_is_chanctx_enabled())995 hw->wiphy->interface_modes |=996 BIT(NL80211_IFTYPE_P2P_DEVICE);997 998 hw->wiphy->iface_combinations = if_comb;999 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);1000 }1001 1002 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;1003 1004 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;1005 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;1006 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;1007 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;1008 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;1009 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;1010 1011 hw->queues = 4;1012 hw->max_rates = 4;1013 hw->max_listen_interval = 10;1014 hw->max_rate_tries = 10;1015 hw->sta_data_size = sizeof(struct ath_node);1016 hw->vif_data_size = sizeof(struct ath_vif);1017 hw->txq_data_size = sizeof(struct ath_atx_tid);1018 hw->extra_tx_headroom = 4;1019 1020 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;1021 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;1022 1023 /* single chain devices with rx diversity */1024 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)1025 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);1026 1027 sc->ant_rx = hw->wiphy->available_antennas_rx;1028 sc->ant_tx = hw->wiphy->available_antennas_tx;1029 1030 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)1031 hw->wiphy->bands[NL80211_BAND_2GHZ] =1032 &common->sbands[NL80211_BAND_2GHZ];1033 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)1034 hw->wiphy->bands[NL80211_BAND_5GHZ] =1035 &common->sbands[NL80211_BAND_5GHZ];1036 1037#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT1038 ath9k_set_mcc_capab(sc, hw);1039#endif1040 ath9k_init_wow(hw);1041 ath9k_cmn_reload_chainmask(ah);1042 1043 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);1044 1045 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);1046 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);1047 wiphy_ext_feature_set(hw->wiphy,1048 NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS);1049 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);1050}1051 1052int ath9k_init_device(u16 devid, struct ath_softc *sc,1053 const struct ath_bus_ops *bus_ops)1054{1055 struct ieee80211_hw *hw = sc->hw;1056 struct ath_common *common;1057 struct ath_hw *ah;1058 int error = 0;1059 struct ath_regulatory *reg;1060 1061 /* Bring up device */1062 error = ath9k_init_softc(devid, sc, bus_ops);1063 if (error)1064 return error;1065 1066 ah = sc->sc_ah;1067 common = ath9k_hw_common(ah);1068 ath9k_set_hw_capab(sc, hw);1069 1070 /* Initialize regulatory */1071 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,1072 ath9k_reg_notifier);1073 if (error)1074 goto deinit;1075 1076 reg = &common->regulatory;1077 1078 /* Setup TX DMA */1079 error = ath_tx_init(sc, ATH_TXBUF);1080 if (error != 0)1081 goto deinit;1082 1083 /* Setup RX DMA */1084 error = ath_rx_init(sc, ATH_RXBUF);1085 if (error != 0)1086 goto deinit;1087 1088 ath9k_init_txpower_limits(sc);1089 1090#ifdef CONFIG_MAC80211_LEDS1091 /* must be initialized before ieee80211_register_hw */1092 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,1093 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,1094 ARRAY_SIZE(ath9k_tpt_blink));1095#endif1096 1097 wiphy_read_of_freq_limits(hw->wiphy);1098 1099 /* Register with mac80211 */1100 error = ieee80211_register_hw(hw);1101 if (error)1102 goto rx_cleanup;1103 1104 error = ath9k_init_debug(ah);1105 if (error) {1106 ath_err(common, "Unable to create debugfs files\n");1107 goto unregister;1108 }1109 1110 /* Handle world regulatory */1111 if (!ath_is_world_regd(reg)) {1112 error = regulatory_hint(hw->wiphy, reg->alpha2);1113 if (error)1114 goto debug_cleanup;1115 }1116 1117 ath_init_leds(sc);1118 ath_start_rfkill_poll(sc);1119 1120 return 0;1121 1122debug_cleanup:1123 ath9k_deinit_debug(sc);1124unregister:1125 ieee80211_unregister_hw(hw);1126rx_cleanup:1127 ath_rx_cleanup(sc);1128deinit:1129 ath9k_deinit_softc(sc);1130 return error;1131}1132 1133/*****************************/1134/* De-Initialization */1135/*****************************/1136 1137static void ath9k_deinit_softc(struct ath_softc *sc)1138{1139 int i = 0;1140 1141 ath9k_deinit_p2p(sc);1142 ath9k_deinit_btcoex(sc);1143 1144 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)1145 if (ATH_TXQ_SETUP(sc, i))1146 ath_tx_cleanupq(sc, &sc->tx.txq[i]);1147 1148 del_timer_sync(&sc->sleep_timer);1149 ath9k_hw_deinit(sc->sc_ah);1150 if (sc->dfs_detector != NULL)1151 sc->dfs_detector->exit(sc->dfs_detector);1152 1153 ath9k_eeprom_release(sc);1154}1155 1156void ath9k_deinit_device(struct ath_softc *sc)1157{1158 struct ieee80211_hw *hw = sc->hw;1159 1160 ath9k_ps_wakeup(sc);1161 1162 wiphy_rfkill_stop_polling(sc->hw->wiphy);1163 ath_deinit_leds(sc);1164 1165 ath9k_ps_restore(sc);1166 1167 ath9k_deinit_debug(sc);1168 ath9k_deinit_wow(hw);1169 ieee80211_unregister_hw(hw);1170 ath_rx_cleanup(sc);1171 ath9k_deinit_softc(sc);1172}1173 1174/************************/1175/* Module Hooks */1176/************************/1177 1178static int __init ath9k_init(void)1179{1180 int error;1181 1182 error = ath_pci_init();1183 if (error < 0) {1184 pr_err("No PCI devices found, driver not installed\n");1185 error = -ENODEV;1186 goto err_out;1187 }1188 1189 error = ath_ahb_init();1190 if (error < 0) {1191 error = -ENODEV;1192 goto err_pci_exit;1193 }1194 1195 dmi_check_system(ath9k_quirks);1196 1197 return 0;1198 1199 err_pci_exit:1200 ath_pci_exit();1201 err_out:1202 return error;1203}1204module_init(ath9k_init);1205 1206static void __exit ath9k_exit(void)1207{1208 is_ath9k_unloaded = true;1209 ath_ahb_exit();1210 ath_pci_exit();1211 pr_info("%s: Driver unloaded\n", dev_info);1212}1213module_exit(ath9k_exit);1214