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1/*2 * Copyright (c) 2008-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef MAC_H18#define MAC_H19#include <net/cfg80211.h>20 21#define set11nTries(_series, _index) \22 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))23 24#define set11nRate(_series, _index) \25 (SM((_series)[_index].Rate, AR_XmitRate##_index))26 27#define set11nPktDurRTSCTS(_series, _index) \28 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \29 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \30 AR_RTSCTSQual##_index : 0))31 32#define set11nRateFlags(_series, _index) \33 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \34 AR_2040_##_index : 0) \35 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \36 AR_GI##_index : 0) \37 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \38 AR_STBC##_index : 0))39 40#define set11nChainSel(_series, _index) \41 (SM((_series)[_index].ChSel, AR_ChainSel##_index))42 43#define CCK_SIFS_TIME 1044#define CCK_PREAMBLE_BITS 14445#define CCK_PLCP_BITS 4846 47#define OFDM_SIFS_TIME 1648#define OFDM_PREAMBLE_TIME 2049#define OFDM_PLCP_BITS 2250#define OFDM_SYMBOL_TIME 451 52#define OFDM_SIFS_TIME_HALF 3253#define OFDM_PREAMBLE_TIME_HALF 4054#define OFDM_PLCP_BITS_HALF 2255#define OFDM_SYMBOL_TIME_HALF 856 57#define OFDM_SIFS_TIME_QUARTER 6458#define OFDM_PREAMBLE_TIME_QUARTER 8059#define OFDM_PLCP_BITS_QUARTER 2260#define OFDM_SYMBOL_TIME_QUARTER 1661 62#define INIT_AIFS 263#define INIT_CWMIN 1564#define INIT_CWMIN_11B 3165#define INIT_CWMAX 102366#define INIT_SH_RETRY 1067#define INIT_LG_RETRY 1068#define INIT_SSH_RETRY 3269#define INIT_SLG_RETRY 3270 71#define ATH9K_TXERR_XRETRY 0x0172#define ATH9K_TXERR_FILT 0x0273#define ATH9K_TXERR_FIFO 0x0474#define ATH9K_TXERR_XTXOP 0x0875#define ATH9K_TXERR_TIMER_EXPIRED 0x1076#define ATH9K_TX_ACKED 0x2077#define ATH9K_TX_FLUSH 0x4078#define ATH9K_TXERR_MASK \79 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \80 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH)81 82#define ATH9K_TX_BA 0x0183#define ATH9K_TX_PWRMGMT 0x0284#define ATH9K_TX_DESC_CFG_ERR 0x0485#define ATH9K_TX_DATA_UNDERRUN 0x0886#define ATH9K_TX_DELIM_UNDERRUN 0x1087#define ATH9K_TX_SW_FILTERED 0x8088 89/* 64 bytes */90#define MIN_TX_FIFO_THRESHOLD 0x191 92/*93 * Single stream device AR9285 and AR9271 require 2 KB94 * to work around a hardware issue, all other devices95 * have can use the max 4 KB limit.96 */97#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)98 99struct ath_tx_status {100 u32 ts_tstamp;101 u16 ts_seqnum;102 u8 ts_status;103 u8 ts_rateindex;104 int8_t ts_rssi;105 u8 ts_shortretry;106 u8 ts_longretry;107 u8 ts_virtcol;108 u8 ts_flags;109 int8_t ts_rssi_ctl0;110 int8_t ts_rssi_ctl1;111 int8_t ts_rssi_ctl2;112 int8_t ts_rssi_ext0;113 int8_t ts_rssi_ext1;114 int8_t ts_rssi_ext2;115 u8 qid;116 u16 desc_id;117 u8 tid;118 struct_group(ba,119 u32 ba_low;120 u32 ba_high;121 );122 u32 evm0;123 u32 evm1;124 u32 evm2;125 u32 duration;126};127 128struct ath_rx_status {129 u32 rs_tstamp;130 u16 rs_datalen;131 u8 rs_status;132 u8 rs_phyerr;133 int8_t rs_rssi;134 u8 rs_keyix;135 u8 rs_rate;136 u8 rs_antenna;137 u8 rs_more;138 int8_t rs_rssi_ctl[3];139 int8_t rs_rssi_ext[3];140 u8 rs_isaggr;141 u8 rs_firstaggr;142 u8 rs_moreaggr;143 u8 rs_num_delims;144 u8 rs_flags;145 bool is_mybeacon;146 u32 evm0;147 u32 evm1;148 u32 evm2;149 u32 evm3;150 u32 evm4;151 u16 enc_flags;152 enum rate_info_bw bw;153};154 155struct ath_htc_rx_status {156 __be64 rs_tstamp;157 __be16 rs_datalen;158 u8 rs_status;159 u8 rs_phyerr;160 int8_t rs_rssi;161 int8_t rs_rssi_ctl[3];162 int8_t rs_rssi_ext[3];163 u8 rs_keyix;164 u8 rs_rate;165 u8 rs_antenna;166 u8 rs_more;167 u8 rs_isaggr;168 u8 rs_moreaggr;169 u8 rs_num_delims;170 u8 rs_flags;171 u8 rs_dummy;172 /* FIXME: evm* never used? */173 __be32 evm0;174 __be32 evm1;175 __be32 evm2;176};177 178#define ATH9K_RXERR_CRC 0x01179#define ATH9K_RXERR_PHY 0x02180#define ATH9K_RXERR_FIFO 0x04181#define ATH9K_RXERR_DECRYPT 0x08182#define ATH9K_RXERR_MIC 0x10183#define ATH9K_RXERR_KEYMISS 0x20184#define ATH9K_RXERR_CORRUPT_DESC 0x40185 186#define ATH9K_RX_MORE 0x01187#define ATH9K_RX_MORE_AGGR 0x02188#define ATH9K_RX_GI 0x04189#define ATH9K_RX_2040 0x08190#define ATH9K_RX_DELIM_CRC_PRE 0x10191#define ATH9K_RX_DELIM_CRC_POST 0x20192#define ATH9K_RX_DECRYPT_BUSY 0x40193 194#define ATH9K_RXKEYIX_INVALID ((u8)-1)195#define ATH9K_TXKEYIX_INVALID ((u8)-1)196 197enum ath9k_phyerr {198 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */199 ATH9K_PHYERR_TIMING = 1, /* Timing error */200 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */201 ATH9K_PHYERR_RATE = 3, /* Illegal rate */202 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */203 ATH9K_PHYERR_RADAR = 5, /* Radar detect */204 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */205 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */206 207 ATH9K_PHYERR_OFDM_TIMING = 17,208 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18,209 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19,210 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,211 ATH9K_PHYERR_OFDM_POWER_DROP = 21,212 ATH9K_PHYERR_OFDM_SERVICE = 22,213 ATH9K_PHYERR_OFDM_RESTART = 23,214 215 ATH9K_PHYERR_CCK_BLOCKER = 24,216 ATH9K_PHYERR_CCK_TIMING = 25,217 ATH9K_PHYERR_CCK_HEADER_CRC = 26,218 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27,219 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 28,220 ATH9K_PHYERR_CCK_POWER_DROP = 29,221 ATH9K_PHYERR_CCK_SERVICE = 30,222 ATH9K_PHYERR_CCK_RESTART = 31,223 224 ATH9K_PHYERR_HT_CRC_ERROR = 32,225 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 33,226 ATH9K_PHYERR_HT_RATE_ILLEGAL = 34,227 ATH9K_PHYERR_HT_ZLF = 35,228 229 ATH9K_PHYERR_FALSE_RADAR_EXT = 36,230 ATH9K_PHYERR_GREEN_FIELD = 37,231 ATH9K_PHYERR_SPECTRAL = 38,232 233 ATH9K_PHYERR_MAX = 39,234};235 236struct ath_desc {237 u32 ds_link;238 u32 ds_data;239 u32 ds_ctl0;240 u32 ds_ctl1;241 u32 ds_hw[20];242 void *ds_vdata;243} __packed __aligned(4);244 245#define ATH9K_TXDESC_NOACK 0x0002246#define ATH9K_TXDESC_RTSENA 0x0004247#define ATH9K_TXDESC_CTSENA 0x0008248/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for249 * the descriptor its marked on. We take a tx interrupt to reap250 * descriptors when the h/w hits an EOL condition or251 * when the descriptor is specifically marked to generate252 * an interrupt with this flag. Descriptors should be253 * marked periodically to insure timely replenishing of the254 * supply needed for sending frames. Defering interrupts255 * reduces system load and potentially allows more concurrent256 * work to be done but if done to aggressively can cause257 * senders to backup. When the hardware queue is left too258 * large rate control information may also be too out of259 * date. An Alternative for this is TX interrupt mitigation260 * but this needs more testing. */261#define ATH9K_TXDESC_INTREQ 0x0010262#define ATH9K_TXDESC_VEOL 0x0020263#define ATH9K_TXDESC_EXT_ONLY 0x0040264#define ATH9K_TXDESC_EXT_AND_CTL 0x0080265#define ATH9K_TXDESC_VMF 0x0100266#define ATH9K_TXDESC_FRAG_IS_ON 0x0200267#define ATH9K_TXDESC_LOWRXCHAIN 0x0400268#define ATH9K_TXDESC_LDPC 0x0800269#define ATH9K_TXDESC_CLRDMASK 0x1000270 271#define ATH9K_TXDESC_PAPRD 0x70000272#define ATH9K_TXDESC_PAPRD_S 16273 274#define ATH9K_RXDESC_INTREQ 0x0020275 276struct ar5416_desc {277 u32 ds_link;278 u32 ds_data;279 u32 ds_ctl0;280 u32 ds_ctl1;281 union {282 struct {283 u32 ctl2;284 u32 ctl3;285 u32 ctl4;286 u32 ctl5;287 u32 ctl6;288 u32 ctl7;289 u32 ctl8;290 u32 ctl9;291 u32 ctl10;292 u32 ctl11;293 u32 status0;294 u32 status1;295 u32 status2;296 u32 status3;297 u32 status4;298 u32 status5;299 u32 status6;300 u32 status7;301 u32 status8;302 u32 status9;303 } tx;304 struct {305 u32 status0;306 u32 status1;307 u32 status2;308 u32 status3;309 u32 status4;310 u32 status5;311 u32 status6;312 u32 status7;313 u32 status8;314 } rx;315 } u;316} __packed __aligned(4);317 318#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))319#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))320 321#define ds_ctl2 u.tx.ctl2322#define ds_ctl3 u.tx.ctl3323#define ds_ctl4 u.tx.ctl4324#define ds_ctl5 u.tx.ctl5325#define ds_ctl6 u.tx.ctl6326#define ds_ctl7 u.tx.ctl7327#define ds_ctl8 u.tx.ctl8328#define ds_ctl9 u.tx.ctl9329#define ds_ctl10 u.tx.ctl10330#define ds_ctl11 u.tx.ctl11331 332#define ds_txstatus0 u.tx.status0333#define ds_txstatus1 u.tx.status1334#define ds_txstatus2 u.tx.status2335#define ds_txstatus3 u.tx.status3336#define ds_txstatus4 u.tx.status4337#define ds_txstatus5 u.tx.status5338#define ds_txstatus6 u.tx.status6339#define ds_txstatus7 u.tx.status7340#define ds_txstatus8 u.tx.status8341#define ds_txstatus9 u.tx.status9342 343#define ds_rxstatus0 u.rx.status0344#define ds_rxstatus1 u.rx.status1345#define ds_rxstatus2 u.rx.status2346#define ds_rxstatus3 u.rx.status3347#define ds_rxstatus4 u.rx.status4348#define ds_rxstatus5 u.rx.status5349#define ds_rxstatus6 u.rx.status6350#define ds_rxstatus7 u.rx.status7351#define ds_rxstatus8 u.rx.status8352 353#define AR_FrameLen 0x00000fff354#define AR_VirtMoreFrag 0x00001000355#define AR_TxCtlRsvd00 0x0000e000356#define AR_XmitPower0 0x003f0000357#define AR_XmitPower0_S 16358#define AR_XmitPower1 0x3f000000359#define AR_XmitPower1_S 24360#define AR_XmitPower2 0x3f000000361#define AR_XmitPower2_S 24362#define AR_XmitPower3 0x3f000000363#define AR_XmitPower3_S 24364#define AR_RTSEnable 0x00400000365#define AR_VEOL 0x00800000366#define AR_ClrDestMask 0x01000000367#define AR_TxCtlRsvd01 0x1e000000368#define AR_TxIntrReq 0x20000000369#define AR_DestIdxValid 0x40000000370#define AR_CTSEnable 0x80000000371 372#define AR_TxMore 0x00001000373#define AR_DestIdx 0x000fe000374#define AR_DestIdx_S 13375#define AR_FrameType 0x00f00000376#define AR_FrameType_S 20377#define AR_NoAck 0x01000000378#define AR_InsertTS 0x02000000379#define AR_CorruptFCS 0x04000000380#define AR_ExtOnly 0x08000000381#define AR_ExtAndCtl 0x10000000382#define AR_MoreAggr 0x20000000383#define AR_IsAggr 0x40000000384 385#define AR_BurstDur 0x00007fff386#define AR_BurstDur_S 0387#define AR_DurUpdateEna 0x00008000388#define AR_XmitDataTries0 0x000f0000389#define AR_XmitDataTries0_S 16390#define AR_XmitDataTries1 0x00f00000391#define AR_XmitDataTries1_S 20392#define AR_XmitDataTries2 0x0f000000393#define AR_XmitDataTries2_S 24394#define AR_XmitDataTries3 0xf0000000395#define AR_XmitDataTries3_S 28396 397#define AR_XmitRate0 0x000000ff398#define AR_XmitRate0_S 0399#define AR_XmitRate1 0x0000ff00400#define AR_XmitRate1_S 8401#define AR_XmitRate2 0x00ff0000402#define AR_XmitRate2_S 16403#define AR_XmitRate3 0xff000000404#define AR_XmitRate3_S 24405 406#define AR_PacketDur0 0x00007fff407#define AR_PacketDur0_S 0408#define AR_RTSCTSQual0 0x00008000409#define AR_PacketDur1 0x7fff0000410#define AR_PacketDur1_S 16411#define AR_RTSCTSQual1 0x80000000412 413#define AR_PacketDur2 0x00007fff414#define AR_PacketDur2_S 0415#define AR_RTSCTSQual2 0x00008000416#define AR_PacketDur3 0x7fff0000417#define AR_PacketDur3_S 16418#define AR_RTSCTSQual3 0x80000000419 420#define AR_AggrLen 0x0000ffff421#define AR_AggrLen_S 0422#define AR_TxCtlRsvd60 0x00030000423#define AR_PadDelim 0x03fc0000424#define AR_PadDelim_S 18425#define AR_EncrType 0x0c000000426#define AR_EncrType_S 26427#define AR_TxCtlRsvd61 0xf0000000428#define AR_LDPC 0x80000000429 430#define AR_2040_0 0x00000001431#define AR_GI0 0x00000002432#define AR_ChainSel0 0x0000001c433#define AR_ChainSel0_S 2434#define AR_2040_1 0x00000020435#define AR_GI1 0x00000040436#define AR_ChainSel1 0x00000380437#define AR_ChainSel1_S 7438#define AR_2040_2 0x00000400439#define AR_GI2 0x00000800440#define AR_ChainSel2 0x00007000441#define AR_ChainSel2_S 12442#define AR_2040_3 0x00008000443#define AR_GI3 0x00010000444#define AR_ChainSel3 0x000e0000445#define AR_ChainSel3_S 17446#define AR_RTSCTSRate 0x0ff00000447#define AR_RTSCTSRate_S 20448#define AR_STBC0 0x10000000449#define AR_STBC1 0x20000000450#define AR_STBC2 0x40000000451#define AR_STBC3 0x80000000452 453#define AR_TxRSSIAnt00 0x000000ff454#define AR_TxRSSIAnt00_S 0455#define AR_TxRSSIAnt01 0x0000ff00456#define AR_TxRSSIAnt01_S 8457#define AR_TxRSSIAnt02 0x00ff0000458#define AR_TxRSSIAnt02_S 16459#define AR_TxStatusRsvd00 0x3f000000460#define AR_TxBaStatus 0x40000000461#define AR_TxStatusRsvd01 0x80000000462 463/*464 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was465 * transmitted successfully. If clear, no ACK or BA was received to indicate466 * successful transmission when we were expecting an ACK or BA.467 */468#define AR_FrmXmitOK 0x00000001469#define AR_ExcessiveRetries 0x00000002470#define AR_FIFOUnderrun 0x00000004471#define AR_Filtered 0x00000008472#define AR_RTSFailCnt 0x000000f0473#define AR_RTSFailCnt_S 4474#define AR_DataFailCnt 0x00000f00475#define AR_DataFailCnt_S 8476#define AR_VirtRetryCnt 0x0000f000477#define AR_VirtRetryCnt_S 12478#define AR_TxDelimUnderrun 0x00010000479#define AR_TxDataUnderrun 0x00020000480#define AR_DescCfgErr 0x00040000481#define AR_TxTimerExpired 0x00080000482#define AR_TxStatusRsvd10 0xfff00000483 484#define AR_SendTimestamp ds_txstatus2485#define AR_BaBitmapLow ds_txstatus3486#define AR_BaBitmapHigh ds_txstatus4487 488#define AR_TxRSSIAnt10 0x000000ff489#define AR_TxRSSIAnt10_S 0490#define AR_TxRSSIAnt11 0x0000ff00491#define AR_TxRSSIAnt11_S 8492#define AR_TxRSSIAnt12 0x00ff0000493#define AR_TxRSSIAnt12_S 16494#define AR_TxRSSICombined 0xff000000495#define AR_TxRSSICombined_S 24496 497#define AR_TxTid 0xf0000000498#define AR_TxTid_S 28499 500#define AR_TxEVM0 ds_txstatus5501#define AR_TxEVM1 ds_txstatus6502#define AR_TxEVM2 ds_txstatus7503 504#define AR_TxDone 0x00000001505#define AR_SeqNum 0x00001ffe506#define AR_SeqNum_S 1507#define AR_TxStatusRsvd80 0x0001e000508#define AR_TxOpExceeded 0x00020000509#define AR_TxStatusRsvd81 0x001c0000510#define AR_FinalTxIdx 0x00600000511#define AR_FinalTxIdx_S 21512#define AR_TxStatusRsvd82 0x01800000513#define AR_PowerMgmt 0x02000000514#define AR_TxStatusRsvd83 0xfc000000515 516#define AR_RxCTLRsvd00 0xffffffff517 518#define AR_RxCtlRsvd00 0x00001000519#define AR_RxIntrReq 0x00002000520#define AR_RxCtlRsvd01 0xffffc000521 522#define AR_RxRSSIAnt00 0x000000ff523#define AR_RxRSSIAnt00_S 0524#define AR_RxRSSIAnt01 0x0000ff00525#define AR_RxRSSIAnt01_S 8526#define AR_RxRSSIAnt02 0x00ff0000527#define AR_RxRSSIAnt02_S 16528#define AR_RxRate 0xff000000529#define AR_RxRate_S 24530#define AR_RxStatusRsvd00 0xff000000531 532#define AR_DataLen 0x00000fff533#define AR_RxMore 0x00001000534#define AR_NumDelim 0x003fc000535#define AR_NumDelim_S 14536#define AR_RxStatusRsvd10 0xff800000537 538#define AR_RcvTimestamp ds_rxstatus2539 540#define AR_GI 0x00000001541#define AR_2040 0x00000002542#define AR_Parallel40 0x00000004543#define AR_Parallel40_S 2544#define AR_STBC 0x00000008 /* on ar9280 and later */545#define AR_RxStatusRsvd30 0x000000f0546#define AR_RxAntenna 0xffffff00547#define AR_RxAntenna_S 8548 549#define AR_RxRSSIAnt10 0x000000ff550#define AR_RxRSSIAnt10_S 0551#define AR_RxRSSIAnt11 0x0000ff00552#define AR_RxRSSIAnt11_S 8553#define AR_RxRSSIAnt12 0x00ff0000554#define AR_RxRSSIAnt12_S 16555#define AR_RxRSSICombined 0xff000000556#define AR_RxRSSICombined_S 24557 558#define AR_RxEVM0 ds_rxstatus4559#define AR_RxEVM1 ds_rxstatus5560#define AR_RxEVM2 ds_rxstatus6561 562#define AR_RxDone 0x00000001563#define AR_RxFrameOK 0x00000002564#define AR_CRCErr 0x00000004565#define AR_DecryptCRCErr 0x00000008566#define AR_PHYErr 0x00000010567#define AR_MichaelErr 0x00000020568#define AR_PreDelimCRCErr 0x00000040569#define AR_RxStatusRsvd70 0x00000080570#define AR_RxKeyIdxValid 0x00000100571#define AR_KeyIdx 0x0000fe00572#define AR_KeyIdx_S 9573#define AR_PHYErrCode 0x0000ff00574#define AR_PHYErrCode_S 8575#define AR_RxMoreAggr 0x00010000576#define AR_RxAggr 0x00020000577#define AR_PostDelimCRCErr 0x00040000578#define AR_RxStatusRsvd71 0x3ff80000579#define AR_RxFirstAggr 0x20000000580#define AR_DecryptBusyErr 0x40000000581#define AR_KeyMiss 0x80000000582 583enum ath9k_tx_queue {584 ATH9K_TX_QUEUE_INACTIVE = 0,585 ATH9K_TX_QUEUE_DATA,586 ATH9K_TX_QUEUE_BEACON,587 ATH9K_TX_QUEUE_CAB,588 ATH9K_TX_QUEUE_UAPSD,589 ATH9K_TX_QUEUE_PSPOLL590};591 592#define ATH9K_NUM_TX_QUEUES 10593 594/* Used as a queue subtype instead of a WMM AC */595#define ATH9K_WME_UPSD 4596 597enum ath9k_tx_queue_flags {598 TXQ_FLAG_TXINT_ENABLE = 0x0001,599 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,600 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,601 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,602 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,603 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,604 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,605 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,606};607 608#define ATH9K_TXQ_USEDEFAULT ((u32) -1)609#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001610 611#define ATH9K_DECOMP_MASK_SIZE 128612 613enum ath9k_pkt_type {614 ATH9K_PKT_TYPE_NORMAL = 0,615 ATH9K_PKT_TYPE_ATIM,616 ATH9K_PKT_TYPE_PSPOLL,617 ATH9K_PKT_TYPE_BEACON,618 ATH9K_PKT_TYPE_PROBE_RESP,619 ATH9K_PKT_TYPE_CHIRP,620 ATH9K_PKT_TYPE_GRP_POLL,621};622 623struct ath9k_tx_queue_info {624 u32 tqi_ver;625 enum ath9k_tx_queue tqi_type;626 int tqi_subtype;627 enum ath9k_tx_queue_flags tqi_qflags;628 u32 tqi_priority;629 u32 tqi_aifs;630 u32 tqi_cwmin;631 u32 tqi_cwmax;632 u16 tqi_shretry;633 u16 tqi_lgretry;634 u32 tqi_cbrPeriod;635 u32 tqi_cbrOverflowLimit;636 u32 tqi_burstTime;637 u32 tqi_readyTime;638 u32 tqi_physCompBuf;639 u32 tqi_intFlags;640};641 642enum ath9k_rx_filter {643 ATH9K_RX_FILTER_UCAST = 0x00000001,644 ATH9K_RX_FILTER_MCAST = 0x00000002,645 ATH9K_RX_FILTER_BCAST = 0x00000004,646 ATH9K_RX_FILTER_CONTROL = 0x00000008,647 ATH9K_RX_FILTER_BEACON = 0x00000010,648 ATH9K_RX_FILTER_PROM = 0x00000020,649 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,650 ATH9K_RX_FILTER_PHYERR = 0x00000100,651 ATH9K_RX_FILTER_MYBEACON = 0x00000200,652 ATH9K_RX_FILTER_COMP_BAR = 0x00000400,653 ATH9K_RX_FILTER_COMP_BA = 0x00000800,654 ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000,655 ATH9K_RX_FILTER_PSPOLL = 0x00004000,656 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,657 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,658 ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000,659 ATH9K_RX_FILTER_4ADDRESS = 0x00100000,660};661 662#define ATH9K_RATESERIES_RTS_CTS 0x0001663#define ATH9K_RATESERIES_2040 0x0002664#define ATH9K_RATESERIES_HALFGI 0x0004665#define ATH9K_RATESERIES_STBC 0x0008666 667struct ath9k_11n_rate_series {668 u32 Tries;669 u32 Rate;670 u32 PktDuration;671 u32 ChSel;672 u32 RateFlags;673};674 675enum aggr_type {676 AGGR_BUF_NONE,677 AGGR_BUF_FIRST,678 AGGR_BUF_MIDDLE,679 AGGR_BUF_LAST,680};681 682enum ath9k_key_type {683 ATH9K_KEY_TYPE_CLEAR,684 ATH9K_KEY_TYPE_WEP,685 ATH9K_KEY_TYPE_AES,686 ATH9K_KEY_TYPE_TKIP,687};688 689struct ath_tx_info {690 u8 qcu;691 692 bool is_first;693 bool is_last;694 695 enum aggr_type aggr;696 u8 ndelim;697 u16 aggr_len;698 699 dma_addr_t link;700 int pkt_len;701 u32 flags;702 703 dma_addr_t buf_addr[4];704 int buf_len[4];705 706 struct ath9k_11n_rate_series rates[4];707 u8 rtscts_rate;708 bool dur_update;709 710 enum ath9k_pkt_type type;711 enum ath9k_key_type keytype;712 u8 keyix;713 u8 txpower[4];714};715 716struct ath_hw;717struct ath9k_channel;718enum ath9k_int;719 720u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);721void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);722void ath9k_hw_txstart(struct ath_hw *ah, u32 q);723u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);724bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);725bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q);726void ath9k_hw_abort_tx_dma(struct ath_hw *ah);727bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,728 const struct ath9k_tx_queue_info *qinfo);729bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,730 struct ath9k_tx_queue_info *qinfo);731int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,732 const struct ath9k_tx_queue_info *qinfo);733bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);734bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);735int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,736 struct ath_rx_status *rs);737void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,738 u32 size, u32 flags);739bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);740void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);741void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);742void ath9k_hw_abortpcurecv(struct ath_hw *ah);743bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset);744int ath9k_hw_beaconq_setup(struct ath_hw *ah);745void ath9k_hw_set_tx_filter(struct ath_hw *ah, u8 destidx, bool set);746 747/* Interrupt Handling */748bool ath9k_hw_intrpend(struct ath_hw *ah);749void ath9k_hw_set_interrupts(struct ath_hw *ah);750void ath9k_hw_enable_interrupts(struct ath_hw *ah);751void ath9k_hw_disable_interrupts(struct ath_hw *ah);752void ath9k_hw_kill_interrupts(struct ath_hw *ah);753void ath9k_hw_resume_interrupts(struct ath_hw *ah);754 755void ar9002_hw_attach_mac_ops(struct ath_hw *ah);756 757#endif /* MAC_H */758