2840 lines · c
1/*2 * Copyright (c) 2008-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#include <linux/nl80211.h>18#include <linux/delay.h>19#include "ath9k.h"20#include "btcoex.h"21 22static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,23 u32 queues, bool drop);24 25u8 ath9k_parse_mpdudensity(u8 mpdudensity)26{27 /*28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":29 * 0 for no restriction30 * 1 for 1/4 us31 * 2 for 1/2 us32 * 3 for 1 us33 * 4 for 2 us34 * 5 for 4 us35 * 6 for 8 us36 * 7 for 16 us37 */38 switch (mpdudensity) {39 case 0:40 return 0;41 case 1:42 case 2:43 case 3:44 /* Our lower layer calculations limit our precision to45 1 microsecond */46 return 1;47 case 4:48 return 2;49 case 5:50 return 4;51 case 6:52 return 8;53 case 7:54 return 16;55 default:56 return 0;57 }58}59 60static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,61 bool sw_pending)62{63 bool pending = false;64 65 spin_lock_bh(&txq->axq_lock);66 67 if (txq->axq_depth) {68 pending = true;69 goto out;70 }71 72 if (!sw_pending)73 goto out;74 75 if (txq->mac80211_qnum >= 0) {76 struct ath_acq *acq;77 78 acq = &sc->cur_chan->acq[txq->mac80211_qnum];79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))80 pending = true;81 }82out:83 spin_unlock_bh(&txq->axq_lock);84 return pending;85}86 87static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)88{89 unsigned long flags;90 bool ret;91 92 spin_lock_irqsave(&sc->sc_pm_lock, flags);93 ret = ath9k_hw_setpower(sc->sc_ah, mode);94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);95 96 return ret;97}98 99void ath_ps_full_sleep(struct timer_list *t)100{101 struct ath_softc *sc = from_timer(sc, t, sleep_timer);102 struct ath_common *common = ath9k_hw_common(sc->sc_ah);103 unsigned long flags;104 bool reset;105 106 spin_lock_irqsave(&common->cc_lock, flags);107 ath_hw_cycle_counters_update(common);108 spin_unlock_irqrestore(&common->cc_lock, flags);109 110 ath9k_hw_setrxabort(sc->sc_ah, 1);111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);112 113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);114}115 116void ath9k_ps_wakeup(struct ath_softc *sc)117{118 struct ath_common *common = ath9k_hw_common(sc->sc_ah);119 unsigned long flags;120 enum ath9k_power_mode power_mode;121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags);123 if (++sc->ps_usecount != 1)124 goto unlock;125 126 del_timer_sync(&sc->sleep_timer);127 power_mode = sc->sc_ah->power_mode;128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);129 130 /*131 * While the hardware is asleep, the cycle counters contain no132 * useful data. Better clear them now so that they don't mess up133 * survey data results.134 */135 if (power_mode != ATH9K_PM_AWAKE) {136 spin_lock(&common->cc_lock);137 ath_hw_cycle_counters_update(common);138 memset(&common->cc, 0, sizeof(common->cc));139 spin_unlock(&common->cc_lock);140 }141 142 unlock:143 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);144}145 146void ath9k_ps_restore(struct ath_softc *sc)147{148 struct ath_common *common = ath9k_hw_common(sc->sc_ah);149 enum ath9k_power_mode mode;150 unsigned long flags;151 152 spin_lock_irqsave(&sc->sc_pm_lock, flags);153 if (--sc->ps_usecount != 0)154 goto unlock;155 156 if (sc->ps_idle) {157 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);158 goto unlock;159 }160 161 if (sc->ps_enabled &&162 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |163 PS_WAIT_FOR_CAB |164 PS_WAIT_FOR_PSPOLL_DATA |165 PS_WAIT_FOR_TX_ACK |166 PS_WAIT_FOR_ANI))) {167 mode = ATH9K_PM_NETWORK_SLEEP;168 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))169 ath9k_btcoex_stop_gen_timer(sc);170 } else {171 goto unlock;172 }173 174 spin_lock(&common->cc_lock);175 ath_hw_cycle_counters_update(common);176 spin_unlock(&common->cc_lock);177 178 ath9k_hw_setpower(sc->sc_ah, mode);179 180 unlock:181 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);182}183 184static void __ath_cancel_work(struct ath_softc *sc)185{186 cancel_work_sync(&sc->paprd_work);187 cancel_delayed_work_sync(&sc->hw_check_work);188 cancel_delayed_work_sync(&sc->hw_pll_work);189 190#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT191 if (ath9k_hw_mci_is_enabled(sc->sc_ah))192 cancel_work_sync(&sc->mci_work);193#endif194}195 196void ath_cancel_work(struct ath_softc *sc)197{198 __ath_cancel_work(sc);199 cancel_work_sync(&sc->hw_reset_work);200}201 202void ath_restart_work(struct ath_softc *sc)203{204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,205 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));206 207 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))208 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,209 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));210 211 ath_start_ani(sc);212}213 214static bool ath_prepare_reset(struct ath_softc *sc)215{216 struct ath_hw *ah = sc->sc_ah;217 bool ret = true;218 219 ieee80211_stop_queues(sc->hw);220 ath_stop_ani(sc);221 ath9k_hw_disable_interrupts(ah);222 223 if (AR_SREV_9300_20_OR_LATER(ah)) {224 ret &= ath_stoprecv(sc);225 ret &= ath_drain_all_txq(sc);226 } else {227 ret &= ath_drain_all_txq(sc);228 ret &= ath_stoprecv(sc);229 }230 231 return ret;232}233 234static bool ath_complete_reset(struct ath_softc *sc, bool start)235{236 struct ath_hw *ah = sc->sc_ah;237 struct ath_common *common = ath9k_hw_common(ah);238 unsigned long flags;239 240 ath9k_calculate_summary_state(sc, sc->cur_chan);241 ath_startrecv(sc);242 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,243 sc->cur_chan->txpower,244 &sc->cur_chan->cur_txpower);245 clear_bit(ATH_OP_HW_RESET, &common->op_flags);246 247 if (!sc->cur_chan->offchannel && start) {248 /* restore per chanctx TSF timer */249 if (sc->cur_chan->tsf_val) {250 u32 offset;251 252 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,253 NULL);254 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);255 }256 257 258 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))259 goto work;260 261 if (ah->opmode == NL80211_IFTYPE_STATION &&262 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {263 spin_lock_irqsave(&sc->sc_pm_lock, flags);264 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;265 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);266 } else {267 ath9k_set_beacon(sc);268 }269 work:270 ath_restart_work(sc);271 ath_txq_schedule_all(sc);272 }273 274 sc->gtt_cnt = 0;275 276 ath9k_hw_set_interrupts(ah);277 ath9k_hw_enable_interrupts(ah);278 ieee80211_wake_queues(sc->hw);279 ath9k_p2p_ps_timer(sc);280 281 return true;282}283 284static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)285{286 struct ath_hw *ah = sc->sc_ah;287 struct ath_common *common = ath9k_hw_common(ah);288 struct ath9k_hw_cal_data *caldata = NULL;289 bool fastcc = true;290 int r;291 292 __ath_cancel_work(sc);293 294 disable_irq(sc->irq);295 tasklet_disable(&sc->intr_tq);296 tasklet_disable(&sc->bcon_tasklet);297 spin_lock_bh(&sc->sc_pcu_lock);298 299 if (!sc->cur_chan->offchannel) {300 fastcc = false;301 caldata = &sc->cur_chan->caldata;302 }303 304 if (!hchan) {305 fastcc = false;306 hchan = ah->curchan;307 }308 309 if (!hchan) {310 fastcc = false;311 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);312 }313 314 if (!ath_prepare_reset(sc))315 fastcc = false;316 317 if (ath9k_is_chanctx_enabled())318 fastcc = false;319 320 spin_lock_bh(&sc->chan_lock);321 sc->cur_chandef = sc->cur_chan->chandef;322 spin_unlock_bh(&sc->chan_lock);323 324 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",325 hchan->channel, IS_CHAN_HT40(hchan), fastcc);326 327 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);328 if (r) {329 ath_err(common,330 "Unable to reset channel, reset status %d\n", r);331 332 ath9k_hw_enable_interrupts(ah);333 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);334 335 goto out;336 }337 338 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&339 sc->cur_chan->offchannel)340 ath9k_mci_set_txpower(sc, true, false);341 342 if (!ath_complete_reset(sc, true))343 r = -EIO;344 345out:346 enable_irq(sc->irq);347 spin_unlock_bh(&sc->sc_pcu_lock);348 tasklet_enable(&sc->bcon_tasklet);349 tasklet_enable(&sc->intr_tq);350 351 return r;352}353 354static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,355 struct ieee80211_vif *vif)356{357 struct ath_node *an;358 an = (struct ath_node *)sta->drv_priv;359 360 an->sc = sc;361 an->sta = sta;362 an->vif = vif;363 memset(&an->key_idx, 0, sizeof(an->key_idx));364 365 ath_tx_node_init(sc, an);366 367 ath_dynack_node_init(sc->sc_ah, an);368}369 370static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)371{372 struct ath_node *an = (struct ath_node *)sta->drv_priv;373 ath_tx_node_cleanup(sc, an);374 375 ath_dynack_node_deinit(sc->sc_ah, an);376}377 378void ath9k_tasklet(struct tasklet_struct *t)379{380 struct ath_softc *sc = from_tasklet(sc, t, intr_tq);381 struct ath_hw *ah = sc->sc_ah;382 struct ath_common *common = ath9k_hw_common(ah);383 enum ath_reset_type type;384 unsigned long flags;385 u32 status;386 u32 rxmask;387 388 spin_lock_irqsave(&sc->intr_lock, flags);389 status = sc->intrstatus;390 sc->intrstatus = 0;391 spin_unlock_irqrestore(&sc->intr_lock, flags);392 393 ath9k_ps_wakeup(sc);394 spin_lock(&sc->sc_pcu_lock);395 396 if (status & ATH9K_INT_FATAL) {397 type = RESET_TYPE_FATAL_INT;398 ath9k_queue_reset(sc, type);399 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");400 goto out;401 }402 403 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&404 (status & ATH9K_INT_BB_WATCHDOG)) {405 spin_lock_irqsave(&common->cc_lock, flags);406 ath_hw_cycle_counters_update(common);407 ar9003_hw_bb_watchdog_dbg_info(ah);408 spin_unlock_irqrestore(&common->cc_lock, flags);409 410 if (ar9003_hw_bb_watchdog_check(ah)) {411 type = RESET_TYPE_BB_WATCHDOG;412 ath9k_queue_reset(sc, type);413 414 ath_dbg(common, RESET,415 "BB_WATCHDOG: Skipping interrupts\n");416 goto out;417 }418 }419 420 if (status & ATH9K_INT_GTT) {421 sc->gtt_cnt++;422 423 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {424 type = RESET_TYPE_TX_GTT;425 ath9k_queue_reset(sc, type);426 ath_dbg(common, RESET,427 "GTT: Skipping interrupts\n");428 goto out;429 }430 }431 432 spin_lock_irqsave(&sc->sc_pm_lock, flags);433 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {434 /*435 * TSF sync does not look correct; remain awake to sync with436 * the next Beacon.437 */438 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");439 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;440 }441 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);442 443 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)444 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |445 ATH9K_INT_RXORN);446 else447 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);448 449 if (status & rxmask) {450 /* Check for high priority Rx first */451 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&452 (status & ATH9K_INT_RXHP))453 ath_rx_tasklet(sc, 0, true);454 455 ath_rx_tasklet(sc, 0, false);456 }457 458 if (status & ATH9K_INT_TX) {459 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {460 /*461 * For EDMA chips, TX completion is enabled for the462 * beacon queue, so if a beacon has been transmitted463 * successfully after a GTT interrupt, the GTT counter464 * gets reset to zero here.465 */466 sc->gtt_cnt = 0;467 468 ath_tx_edma_tasklet(sc);469 } else {470 ath_tx_tasklet(sc);471 }472 473 wake_up(&sc->tx_wait);474 }475 476 if (status & ATH9K_INT_GENTIMER)477 ath_gen_timer_isr(sc->sc_ah);478 479 ath9k_btcoex_handle_interrupt(sc, status);480 481 /* re-enable hardware interrupt */482 ath9k_hw_resume_interrupts(ah);483out:484 spin_unlock(&sc->sc_pcu_lock);485 ath9k_ps_restore(sc);486}487 488irqreturn_t ath_isr(int irq, void *dev)489{490#define SCHED_INTR ( \491 ATH9K_INT_FATAL | \492 ATH9K_INT_BB_WATCHDOG | \493 ATH9K_INT_RXORN | \494 ATH9K_INT_RXEOL | \495 ATH9K_INT_RX | \496 ATH9K_INT_RXLP | \497 ATH9K_INT_RXHP | \498 ATH9K_INT_TX | \499 ATH9K_INT_BMISS | \500 ATH9K_INT_CST | \501 ATH9K_INT_GTT | \502 ATH9K_INT_TSFOOR | \503 ATH9K_INT_GENTIMER | \504 ATH9K_INT_MCI)505 506 struct ath_softc *sc = dev;507 struct ath_hw *ah = sc->sc_ah;508 struct ath_common *common = ath9k_hw_common(ah);509 enum ath9k_int status;510 u32 sync_cause = 0;511 bool sched = false;512 513 /*514 * The hardware is not ready/present, don't515 * touch anything. Note this can happen early516 * on if the IRQ is shared.517 */518 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))519 return IRQ_NONE;520 521 /* shared irq, not for us */522 if (!ath9k_hw_intrpend(ah))523 return IRQ_NONE;524 525 /*526 * Figure out the reason(s) for the interrupt. Note527 * that the hal returns a pseudo-ISR that may include528 * bits we haven't explicitly enabled so we mask the529 * value to insure we only process bits we requested.530 */531 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */532 ath9k_debug_sync_cause(sc, sync_cause);533 status &= ah->imask; /* discard unasked-for bits */534 535 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {536 ath9k_hw_kill_interrupts(sc->sc_ah);537 return IRQ_HANDLED;538 }539 540 /*541 * If there are no status bits set, then this interrupt was not542 * for me (should have been caught above).543 */544 if (!status)545 return IRQ_NONE;546 547 /* Cache the status */548 spin_lock(&sc->intr_lock);549 sc->intrstatus |= status;550 spin_unlock(&sc->intr_lock);551 552 if (status & SCHED_INTR)553 sched = true;554 555 /*556 * If a FATAL interrupt is received, we have to reset the chip557 * immediately.558 */559 if (status & ATH9K_INT_FATAL)560 goto chip_reset;561 562 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&563 (status & ATH9K_INT_BB_WATCHDOG))564 goto chip_reset;565 566 if (status & ATH9K_INT_SWBA)567 tasklet_schedule(&sc->bcon_tasklet);568 569 if (status & ATH9K_INT_TXURN)570 ath9k_hw_updatetxtriglevel(ah, true);571 572 if (status & ATH9K_INT_RXEOL) {573 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);574 ath9k_hw_set_interrupts(ah);575 }576 577 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))578 if (status & ATH9K_INT_TIM_TIMER) {579 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))580 goto chip_reset;581 /* Clear RxAbort bit so that we can582 * receive frames */583 ath9k_setpower(sc, ATH9K_PM_AWAKE);584 spin_lock(&sc->sc_pm_lock);585 ath9k_hw_setrxabort(sc->sc_ah, 0);586 sc->ps_flags |= PS_WAIT_FOR_BEACON;587 spin_unlock(&sc->sc_pm_lock);588 }589 590chip_reset:591 592 ath_debug_stat_interrupt(sc, status);593 594 if (sched) {595 /* turn off every interrupt */596 ath9k_hw_kill_interrupts(ah);597 tasklet_schedule(&sc->intr_tq);598 }599 600 return IRQ_HANDLED;601 602#undef SCHED_INTR603}604 605/*606 * This function is called when a HW reset cannot be deferred607 * and has to be immediate.608 */609int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)610{611 struct ath_common *common = ath9k_hw_common(sc->sc_ah);612 int r;613 614 ath9k_hw_kill_interrupts(sc->sc_ah);615 set_bit(ATH_OP_HW_RESET, &common->op_flags);616 617 ath9k_ps_wakeup(sc);618 r = ath_reset_internal(sc, hchan);619 ath9k_ps_restore(sc);620 621 return r;622}623 624/*625 * When a HW reset can be deferred, it is added to the626 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before627 * queueing.628 */629void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)630{631 struct ath_common *common = ath9k_hw_common(sc->sc_ah);632#ifdef CONFIG_ATH9K_DEBUGFS633 RESET_STAT_INC(sc, type);634#endif635 ath9k_hw_kill_interrupts(sc->sc_ah);636 set_bit(ATH_OP_HW_RESET, &common->op_flags);637 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);638}639 640void ath_reset_work(struct work_struct *work)641{642 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);643 644 ath9k_ps_wakeup(sc);645 ath_reset_internal(sc, NULL);646 ath9k_ps_restore(sc);647}648 649/**********************/650/* mac80211 callbacks */651/**********************/652 653static int ath9k_start(struct ieee80211_hw *hw)654{655 struct ath_softc *sc = hw->priv;656 struct ath_hw *ah = sc->sc_ah;657 struct ath_common *common = ath9k_hw_common(ah);658 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;659 struct ath_chanctx *ctx = sc->cur_chan;660 struct ath9k_channel *init_channel;661 int r;662 663 ath_dbg(common, CONFIG,664 "Starting driver with initial channel: %d MHz\n",665 curchan->center_freq);666 667 ath9k_ps_wakeup(sc);668 mutex_lock(&sc->mutex);669 670 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);671 sc->cur_chandef = hw->conf.chandef;672 673 /* Reset SERDES registers */674 ath9k_hw_configpcipowersave(ah, false);675 676 /*677 * The basic interface to setting the hardware in a good678 * state is ``reset''. On return the hardware is known to679 * be powered up and with interrupts disabled. This must680 * be followed by initialization of the appropriate bits681 * and then setup of the interrupt mask.682 */683 spin_lock_bh(&sc->sc_pcu_lock);684 685 atomic_set(&ah->intr_ref_cnt, -1);686 687 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);688 if (r) {689 ath_err(common,690 "Unable to reset hardware; reset status %d (freq %u MHz)\n",691 r, curchan->center_freq);692 ah->reset_power_on = false;693 }694 695 /* Setup our intr mask. */696 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |697 ATH9K_INT_RXORN | ATH9K_INT_FATAL |698 ATH9K_INT_GLOBAL;699 700 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)701 ah->imask |= ATH9K_INT_RXHP |702 ATH9K_INT_RXLP;703 else704 ah->imask |= ATH9K_INT_RX;705 706 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)707 ah->imask |= ATH9K_INT_BB_WATCHDOG;708 709 /*710 * Enable GTT interrupts only for AR9003/AR9004 chips711 * for now.712 */713 if (AR_SREV_9300_20_OR_LATER(ah))714 ah->imask |= ATH9K_INT_GTT;715 716 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)717 ah->imask |= ATH9K_INT_CST;718 719 ath_mci_enable(sc);720 721 clear_bit(ATH_OP_INVALID, &common->op_flags);722 sc->sc_ah->is_monitoring = false;723 724 if (!ath_complete_reset(sc, false))725 ah->reset_power_on = false;726 727 if (ah->led_pin >= 0) {728 ath9k_hw_set_gpio(ah, ah->led_pin,729 (ah->config.led_active_high) ? 1 : 0);730 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,731 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);732 }733 734 /*735 * Reset key cache to sane defaults (all entries cleared) instead of736 * semi-random values after suspend/resume.737 */738 ath9k_cmn_init_crypto(sc->sc_ah);739 740 ath9k_hw_reset_tsf(ah);741 742 spin_unlock_bh(&sc->sc_pcu_lock);743 744 ath9k_rng_start(sc);745 746 mutex_unlock(&sc->mutex);747 748 ath9k_ps_restore(sc);749 750 return 0;751}752 753static void ath9k_tx(struct ieee80211_hw *hw,754 struct ieee80211_tx_control *control,755 struct sk_buff *skb)756{757 struct ath_softc *sc = hw->priv;758 struct ath_common *common = ath9k_hw_common(sc->sc_ah);759 struct ath_tx_control txctl;760 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;761 unsigned long flags;762 763 if (sc->ps_enabled) {764 /*765 * mac80211 does not set PM field for normal data frames, so we766 * need to update that based on the current PS mode.767 */768 if (ieee80211_is_data(hdr->frame_control) &&769 !ieee80211_is_nullfunc(hdr->frame_control) &&770 !ieee80211_has_pm(hdr->frame_control)) {771 ath_dbg(common, PS,772 "Add PM=1 for a TX frame while in PS mode\n");773 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);774 }775 }776 777 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {778 /*779 * We are using PS-Poll and mac80211 can request TX while in780 * power save mode. Need to wake up hardware for the TX to be781 * completed and if needed, also for RX of buffered frames.782 */783 ath9k_ps_wakeup(sc);784 spin_lock_irqsave(&sc->sc_pm_lock, flags);785 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))786 ath9k_hw_setrxabort(sc->sc_ah, 0);787 if (ieee80211_is_pspoll(hdr->frame_control)) {788 ath_dbg(common, PS,789 "Sending PS-Poll to pick a buffered frame\n");790 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;791 } else {792 ath_dbg(common, PS, "Wake up to complete TX\n");793 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;794 }795 /*796 * The actual restore operation will happen only after797 * the ps_flags bit is cleared. We are just dropping798 * the ps_usecount here.799 */800 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);801 ath9k_ps_restore(sc);802 }803 804 /*805 * Cannot tx while the hardware is in full sleep, it first needs a full806 * chip reset to recover from that807 */808 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {809 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");810 goto exit;811 }812 813 memset(&txctl, 0, sizeof(struct ath_tx_control));814 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];815 txctl.sta = control->sta;816 817 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);818 819 if (ath_tx_start(hw, skb, &txctl) != 0) {820 ath_dbg(common, XMIT, "TX failed\n");821 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);822 goto exit;823 }824 825 return;826exit:827 ieee80211_free_txskb(hw, skb);828}829 830static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)831{832 struct ath_buf *bf;833 struct ieee80211_tx_info *txinfo;834 struct ath_frame_info *fi;835 836 list_for_each_entry(bf, txq_list, list) {837 if (bf->bf_state.stale || !bf->bf_mpdu)838 continue;839 840 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);841 fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];842 if (fi->keyix == keyix)843 return true;844 }845 846 return false;847}848 849static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)850{851 struct ath_hw *ah = sc->sc_ah;852 int i, j;853 struct ath_txq *txq;854 bool key_in_use = false;855 856 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {857 if (!ATH_TXQ_SETUP(sc, i))858 continue;859 txq = &sc->tx.txq[i];860 if (!txq->axq_depth)861 continue;862 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))863 continue;864 865 ath_txq_lock(sc, txq);866 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);867 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {868 int idx = txq->txq_tailidx;869 870 for (j = 0; !key_in_use &&871 !list_empty(&txq->txq_fifo[idx]) &&872 j < ATH_TXFIFO_DEPTH; j++) {873 key_in_use = ath9k_txq_list_has_key(874 &txq->txq_fifo[idx], keyix);875 INCR(idx, ATH_TXFIFO_DEPTH);876 }877 }878 ath_txq_unlock(sc, txq);879 }880 881 return key_in_use;882}883 884static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)885{886 struct ath_hw *ah = sc->sc_ah;887 struct ath_common *common = ath9k_hw_common(ah);888 889 if (!test_bit(keyix, ah->pending_del_keymap) ||890 ath9k_txq_has_key(sc, keyix))891 return;892 893 /* No more TXQ frames point to this key cache entry, so delete it. */894 clear_bit(keyix, ah->pending_del_keymap);895 ath_key_delete(common, keyix);896}897 898static void ath9k_stop(struct ieee80211_hw *hw, bool suspend)899{900 struct ath_softc *sc = hw->priv;901 struct ath_hw *ah = sc->sc_ah;902 struct ath_common *common = ath9k_hw_common(ah);903 bool prev_idle;904 int i;905 906 ath9k_deinit_channel_context(sc);907 908 mutex_lock(&sc->mutex);909 910 ath9k_rng_stop(sc);911 912 ath_cancel_work(sc);913 914 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {915 ath_dbg(common, ANY, "Device not present\n");916 mutex_unlock(&sc->mutex);917 return;918 }919 920 /* Ensure HW is awake when we try to shut it down. */921 ath9k_ps_wakeup(sc);922 923 spin_lock_bh(&sc->sc_pcu_lock);924 925 /* prevent tasklets to enable interrupts once we disable them */926 ah->imask &= ~ATH9K_INT_GLOBAL;927 928 /* make sure h/w will not generate any interrupt929 * before setting the invalid flag. */930 ath9k_hw_disable_interrupts(ah);931 932 spin_unlock_bh(&sc->sc_pcu_lock);933 934 /* we can now sync irq and kill any running tasklets, since we already935 * disabled interrupts and not holding a spin lock */936 synchronize_irq(sc->irq);937 tasklet_kill(&sc->intr_tq);938 tasklet_kill(&sc->bcon_tasklet);939 940 prev_idle = sc->ps_idle;941 sc->ps_idle = true;942 943 spin_lock_bh(&sc->sc_pcu_lock);944 945 if (ah->led_pin >= 0) {946 ath9k_hw_set_gpio(ah, ah->led_pin,947 (ah->config.led_active_high) ? 0 : 1);948 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);949 }950 951 ath_prepare_reset(sc);952 953 if (sc->rx.frag) {954 dev_kfree_skb_any(sc->rx.frag);955 sc->rx.frag = NULL;956 }957 958 if (!ah->curchan)959 ah->curchan = ath9k_cmn_get_channel(hw, ah,960 &sc->cur_chan->chandef);961 962 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);963 964 set_bit(ATH_OP_INVALID, &common->op_flags);965 966 ath9k_hw_phy_disable(ah);967 968 ath9k_hw_configpcipowersave(ah, true);969 970 spin_unlock_bh(&sc->sc_pcu_lock);971 972 for (i = 0; i < ATH_KEYMAX; i++)973 ath9k_pending_key_del(sc, i);974 975 /* Clear key cache entries explicitly to get rid of any potentially976 * remaining keys.977 */978 ath9k_cmn_init_crypto(sc->sc_ah);979 980 ath9k_ps_restore(sc);981 982 sc->ps_idle = prev_idle;983 984 mutex_unlock(&sc->mutex);985 986 ath_dbg(common, CONFIG, "Driver halt\n");987}988 989static bool ath9k_uses_beacons(int type)990{991 switch (type) {992 case NL80211_IFTYPE_AP:993 case NL80211_IFTYPE_ADHOC:994 case NL80211_IFTYPE_MESH_POINT:995 return true;996 default:997 return false;998 }999}1000 1001static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,1002 struct ieee80211_vif *vif)1003{1004 /* Use the first (configured) interface, but prefering AP interfaces. */1005 if (!iter_data->primary_beacon_vif) {1006 iter_data->primary_beacon_vif = vif;1007 } else {1008 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&1009 vif->type == NL80211_IFTYPE_AP)1010 iter_data->primary_beacon_vif = vif;1011 }1012 1013 iter_data->beacons = true;1014 iter_data->nbcnvifs += 1;1015}1016 1017static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,1018 u8 *mac, struct ieee80211_vif *vif)1019{1020 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;1021 int i;1022 1023 if (iter_data->has_hw_macaddr) {1024 for (i = 0; i < ETH_ALEN; i++)1025 iter_data->mask[i] &=1026 ~(iter_data->hw_macaddr[i] ^ mac[i]);1027 } else {1028 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);1029 iter_data->has_hw_macaddr = true;1030 }1031 1032 if (!vif->bss_conf.use_short_slot)1033 iter_data->slottime = 20;1034 1035 switch (vif->type) {1036 case NL80211_IFTYPE_AP:1037 iter_data->naps++;1038 if (vif->bss_conf.enable_beacon)1039 ath9k_vif_iter_set_beacon(iter_data, vif);1040 break;1041 case NL80211_IFTYPE_STATION:1042 iter_data->nstations++;1043 if (avp->assoc && !iter_data->primary_sta)1044 iter_data->primary_sta = vif;1045 break;1046 case NL80211_IFTYPE_OCB:1047 iter_data->nocbs++;1048 break;1049 case NL80211_IFTYPE_ADHOC:1050 iter_data->nadhocs++;1051 if (vif->bss_conf.enable_beacon)1052 ath9k_vif_iter_set_beacon(iter_data, vif);1053 break;1054 case NL80211_IFTYPE_MESH_POINT:1055 iter_data->nmeshes++;1056 if (vif->bss_conf.enable_beacon)1057 ath9k_vif_iter_set_beacon(iter_data, vif);1058 break;1059 default:1060 break;1061 }1062}1063 1064static void ath9k_update_bssid_mask(struct ath_softc *sc,1065 struct ath_chanctx *ctx,1066 struct ath9k_vif_iter_data *iter_data)1067{1068 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1069 struct ath_vif *avp;1070 int i;1071 1072 if (!ath9k_is_chanctx_enabled())1073 return;1074 1075 list_for_each_entry(avp, &ctx->vifs, list) {1076 if (ctx->nvifs_assigned != 1)1077 continue;1078 1079 if (!iter_data->has_hw_macaddr)1080 continue;1081 1082 ether_addr_copy(common->curbssid, avp->bssid);1083 1084 /* perm_addr will be used as the p2p device address. */1085 for (i = 0; i < ETH_ALEN; i++)1086 iter_data->mask[i] &=1087 ~(iter_data->hw_macaddr[i] ^1088 sc->hw->wiphy->perm_addr[i]);1089 }1090}1091 1092/* Called with sc->mutex held. */1093void ath9k_calculate_iter_data(struct ath_softc *sc,1094 struct ath_chanctx *ctx,1095 struct ath9k_vif_iter_data *iter_data)1096{1097 struct ath_vif *avp;1098 1099 /*1100 * The hardware will use primary station addr together with the1101 * BSSID mask when matching addresses.1102 */1103 memset(iter_data, 0, sizeof(*iter_data));1104 eth_broadcast_addr(iter_data->mask);1105 iter_data->slottime = 9;1106 1107 list_for_each_entry(avp, &ctx->vifs, list)1108 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);1109 1110 ath9k_update_bssid_mask(sc, ctx, iter_data);1111}1112 1113static void ath9k_set_assoc_state(struct ath_softc *sc,1114 struct ieee80211_vif *vif, bool changed)1115{1116 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1117 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;1118 unsigned long flags;1119 1120 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);1121 1122 ether_addr_copy(common->curbssid, avp->bssid);1123 common->curaid = avp->aid;1124 ath9k_hw_write_associd(sc->sc_ah);1125 1126 if (changed) {1127 common->last_rssi = ATH_RSSI_DUMMY_MARKER;1128 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;1129 1130 spin_lock_irqsave(&sc->sc_pm_lock, flags);1131 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;1132 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);1133 }1134 1135 if (ath9k_hw_mci_is_enabled(sc->sc_ah))1136 ath9k_mci_update_wlan_channels(sc, false);1137 1138 ath_dbg(common, CONFIG,1139 "Primary Station interface: %pM, BSSID: %pM\n",1140 vif->addr, common->curbssid);1141}1142 1143#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT1144static void ath9k_set_offchannel_state(struct ath_softc *sc)1145{1146 struct ath_hw *ah = sc->sc_ah;1147 struct ath_common *common = ath9k_hw_common(ah);1148 struct ieee80211_vif *vif = NULL;1149 1150 ath9k_ps_wakeup(sc);1151 1152 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)1153 vif = sc->offchannel.scan_vif;1154 else1155 vif = sc->offchannel.roc_vif;1156 1157 if (WARN_ON(!vif))1158 goto exit;1159 1160 eth_zero_addr(common->curbssid);1161 eth_broadcast_addr(common->bssidmask);1162 memcpy(common->macaddr, vif->addr, ETH_ALEN);1163 common->curaid = 0;1164 ah->opmode = vif->type;1165 ah->imask &= ~ATH9K_INT_SWBA;1166 ah->imask &= ~ATH9K_INT_TSFOOR;1167 ah->slottime = 9;1168 1169 ath_hw_setbssidmask(common);1170 ath9k_hw_setopmode(ah);1171 ath9k_hw_write_associd(sc->sc_ah);1172 ath9k_hw_set_interrupts(ah);1173 ath9k_hw_init_global_settings(ah);1174 1175exit:1176 ath9k_ps_restore(sc);1177}1178#endif1179 1180/* Called with sc->mutex held. */1181void ath9k_calculate_summary_state(struct ath_softc *sc,1182 struct ath_chanctx *ctx)1183{1184 struct ath_hw *ah = sc->sc_ah;1185 struct ath_common *common = ath9k_hw_common(ah);1186 struct ath9k_vif_iter_data iter_data;1187 1188 ath_chanctx_check_active(sc, ctx);1189 1190 if (ctx != sc->cur_chan)1191 return;1192 1193#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT1194 if (ctx == &sc->offchannel.chan)1195 return ath9k_set_offchannel_state(sc);1196#endif1197 1198 ath9k_ps_wakeup(sc);1199 ath9k_calculate_iter_data(sc, ctx, &iter_data);1200 1201 if (iter_data.has_hw_macaddr)1202 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);1203 1204 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);1205 ath_hw_setbssidmask(common);1206 1207 if (iter_data.naps > 0) {1208 ath9k_hw_set_tsfadjust(ah, true);1209 ah->opmode = NL80211_IFTYPE_AP;1210 } else {1211 ath9k_hw_set_tsfadjust(ah, false);1212 if (iter_data.beacons)1213 ath9k_beacon_ensure_primary_slot(sc);1214 1215 if (iter_data.nmeshes)1216 ah->opmode = NL80211_IFTYPE_MESH_POINT;1217 else if (iter_data.nocbs)1218 ah->opmode = NL80211_IFTYPE_OCB;1219 else if (iter_data.nadhocs)1220 ah->opmode = NL80211_IFTYPE_ADHOC;1221 else1222 ah->opmode = NL80211_IFTYPE_STATION;1223 }1224 1225 ath9k_hw_setopmode(ah);1226 1227 ctx->switch_after_beacon = false;1228 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)1229 ah->imask |= ATH9K_INT_TSFOOR;1230 else {1231 ah->imask &= ~ATH9K_INT_TSFOOR;1232 if (iter_data.naps == 1 && iter_data.beacons)1233 ctx->switch_after_beacon = true;1234 }1235 1236 if (ah->opmode == NL80211_IFTYPE_STATION) {1237 bool changed = (iter_data.primary_sta != ctx->primary_sta);1238 1239 if (iter_data.primary_sta) {1240 iter_data.primary_beacon_vif = iter_data.primary_sta;1241 iter_data.beacons = true;1242 ath9k_set_assoc_state(sc, iter_data.primary_sta,1243 changed);1244 ctx->primary_sta = iter_data.primary_sta;1245 } else {1246 ctx->primary_sta = NULL;1247 eth_zero_addr(common->curbssid);1248 common->curaid = 0;1249 ath9k_hw_write_associd(sc->sc_ah);1250 if (ath9k_hw_mci_is_enabled(sc->sc_ah))1251 ath9k_mci_update_wlan_channels(sc, true);1252 }1253 }1254 sc->nbcnvifs = iter_data.nbcnvifs;1255 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,1256 iter_data.beacons);1257 ath9k_hw_set_interrupts(ah);1258 1259 if (ah->slottime != iter_data.slottime) {1260 ah->slottime = iter_data.slottime;1261 ath9k_hw_init_global_settings(ah);1262 }1263 1264 if (iter_data.primary_sta)1265 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);1266 else1267 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);1268 1269 ath_dbg(common, CONFIG,1270 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",1271 common->macaddr, common->curbssid, common->bssidmask);1272 1273 ath9k_ps_restore(sc);1274}1275 1276static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)1277{1278 int *power = data;1279 1280 if (vif->bss_conf.txpower == INT_MIN)1281 return;1282 1283 if (*power < vif->bss_conf.txpower)1284 *power = vif->bss_conf.txpower;1285}1286 1287/* Called with sc->mutex held. */1288void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)1289{1290 int power;1291 struct ath_hw *ah = sc->sc_ah;1292 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);1293 1294 ath9k_ps_wakeup(sc);1295 if (ah->tpc_enabled) {1296 power = (vif) ? vif->bss_conf.txpower : -1;1297 ieee80211_iterate_active_interfaces_atomic(1298 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,1299 ath9k_tpc_vif_iter, &power);1300 if (power == -1)1301 power = sc->hw->conf.power_level;1302 } else {1303 power = sc->hw->conf.power_level;1304 }1305 sc->cur_chan->txpower = 2 * power;1306 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);1307 sc->cur_chan->cur_txpower = reg->max_power_level;1308 ath9k_ps_restore(sc);1309}1310 1311static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,1312 struct ieee80211_vif *vif)1313{1314 int i;1315 1316 if (!ath9k_is_chanctx_enabled())1317 return;1318 1319 for (i = 0; i < IEEE80211_NUM_ACS; i++)1320 vif->hw_queue[i] = i;1321 1322 if (vif->type == NL80211_IFTYPE_AP ||1323 vif->type == NL80211_IFTYPE_MESH_POINT)1324 vif->cab_queue = hw->queues - 2;1325 else1326 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;1327}1328 1329static int ath9k_add_interface(struct ieee80211_hw *hw,1330 struct ieee80211_vif *vif)1331{1332 struct ath_softc *sc = hw->priv;1333 struct ath_hw *ah = sc->sc_ah;1334 struct ath_common *common = ath9k_hw_common(ah);1335 struct ath_vif *avp = (void *)vif->drv_priv;1336 struct ath_node *an = &avp->mcast_node;1337 1338 mutex_lock(&sc->mutex);1339 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {1340 if (sc->cur_chan->nvifs >= 1) {1341 mutex_unlock(&sc->mutex);1342 return -EOPNOTSUPP;1343 }1344 sc->tx99_vif = vif;1345 }1346 1347 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);1348 sc->cur_chan->nvifs++;1349 1350 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())1351 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;1352 1353 if (ath9k_uses_beacons(vif->type))1354 ath9k_beacon_assign_slot(sc, vif);1355 1356 avp->vif = vif;1357 if (!ath9k_is_chanctx_enabled()) {1358 avp->chanctx = sc->cur_chan;1359 list_add_tail(&avp->list, &avp->chanctx->vifs);1360 }1361 1362 ath9k_calculate_summary_state(sc, avp->chanctx);1363 1364 ath9k_assign_hw_queues(hw, vif);1365 1366 ath9k_set_txpower(sc, vif);1367 1368 an->sc = sc;1369 an->sta = NULL;1370 an->vif = vif;1371 an->no_ps_filter = true;1372 ath_tx_node_init(sc, an);1373 1374 mutex_unlock(&sc->mutex);1375 return 0;1376}1377 1378static int ath9k_change_interface(struct ieee80211_hw *hw,1379 struct ieee80211_vif *vif,1380 enum nl80211_iftype new_type,1381 bool p2p)1382{1383 struct ath_softc *sc = hw->priv;1384 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1385 struct ath_vif *avp = (void *)vif->drv_priv;1386 1387 mutex_lock(&sc->mutex);1388 1389 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {1390 mutex_unlock(&sc->mutex);1391 return -EOPNOTSUPP;1392 }1393 1394 ath_dbg(common, CONFIG, "Change Interface\n");1395 1396 if (ath9k_uses_beacons(vif->type))1397 ath9k_beacon_remove_slot(sc, vif);1398 1399 vif->type = new_type;1400 vif->p2p = p2p;1401 1402 if (ath9k_uses_beacons(vif->type))1403 ath9k_beacon_assign_slot(sc, vif);1404 1405 ath9k_assign_hw_queues(hw, vif);1406 ath9k_calculate_summary_state(sc, avp->chanctx);1407 1408 ath9k_set_txpower(sc, vif);1409 1410 mutex_unlock(&sc->mutex);1411 return 0;1412}1413 1414static void ath9k_remove_interface(struct ieee80211_hw *hw,1415 struct ieee80211_vif *vif)1416{1417 struct ath_softc *sc = hw->priv;1418 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1419 struct ath_vif *avp = (void *)vif->drv_priv;1420 1421 ath_dbg(common, CONFIG, "Detach Interface\n");1422 1423 mutex_lock(&sc->mutex);1424 1425 ath9k_p2p_remove_vif(sc, vif);1426 1427 sc->cur_chan->nvifs--;1428 sc->tx99_vif = NULL;1429 if (!ath9k_is_chanctx_enabled())1430 list_del(&avp->list);1431 1432 if (ath9k_uses_beacons(vif->type))1433 ath9k_beacon_remove_slot(sc, vif);1434 1435 ath_tx_node_cleanup(sc, &avp->mcast_node);1436 1437 ath9k_calculate_summary_state(sc, avp->chanctx);1438 1439 ath9k_set_txpower(sc, NULL);1440 1441 mutex_unlock(&sc->mutex);1442}1443 1444static void ath9k_enable_ps(struct ath_softc *sc)1445{1446 struct ath_hw *ah = sc->sc_ah;1447 struct ath_common *common = ath9k_hw_common(ah);1448 1449 if (IS_ENABLED(CONFIG_ATH9K_TX99))1450 return;1451 1452 sc->ps_enabled = true;1453 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {1454 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {1455 ah->imask |= ATH9K_INT_TIM_TIMER;1456 ath9k_hw_set_interrupts(ah);1457 }1458 ath9k_hw_setrxabort(ah, 1);1459 }1460 ath_dbg(common, PS, "PowerSave enabled\n");1461}1462 1463static void ath9k_disable_ps(struct ath_softc *sc)1464{1465 struct ath_hw *ah = sc->sc_ah;1466 struct ath_common *common = ath9k_hw_common(ah);1467 1468 if (IS_ENABLED(CONFIG_ATH9K_TX99))1469 return;1470 1471 sc->ps_enabled = false;1472 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);1473 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {1474 ath9k_hw_setrxabort(ah, 0);1475 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |1476 PS_WAIT_FOR_CAB |1477 PS_WAIT_FOR_PSPOLL_DATA |1478 PS_WAIT_FOR_TX_ACK);1479 if (ah->imask & ATH9K_INT_TIM_TIMER) {1480 ah->imask &= ~ATH9K_INT_TIM_TIMER;1481 ath9k_hw_set_interrupts(ah);1482 }1483 }1484 ath_dbg(common, PS, "PowerSave disabled\n");1485}1486 1487static int ath9k_config(struct ieee80211_hw *hw, u32 changed)1488{1489 struct ath_softc *sc = hw->priv;1490 struct ath_hw *ah = sc->sc_ah;1491 struct ath_common *common = ath9k_hw_common(ah);1492 struct ieee80211_conf *conf = &hw->conf;1493 struct ath_chanctx *ctx = sc->cur_chan;1494 1495 ath9k_ps_wakeup(sc);1496 mutex_lock(&sc->mutex);1497 1498 if (changed & IEEE80211_CONF_CHANGE_IDLE) {1499 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);1500 if (sc->ps_idle) {1501 ath_cancel_work(sc);1502 ath9k_stop_btcoex(sc);1503 } else {1504 ath9k_start_btcoex(sc);1505 /*1506 * The chip needs a reset to properly wake up from1507 * full sleep1508 */1509 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);1510 }1511 }1512 1513 /*1514 * We just prepare to enable PS. We have to wait until our AP has1515 * ACK'd our null data frame to disable RX otherwise we'll ignore1516 * those ACKs and end up retransmitting the same null data frames.1517 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.1518 */1519 if (changed & IEEE80211_CONF_CHANGE_PS) {1520 unsigned long flags;1521 spin_lock_irqsave(&sc->sc_pm_lock, flags);1522 if (conf->flags & IEEE80211_CONF_PS)1523 ath9k_enable_ps(sc);1524 else1525 ath9k_disable_ps(sc);1526 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);1527 }1528 1529 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {1530 if (conf->flags & IEEE80211_CONF_MONITOR) {1531 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");1532 sc->sc_ah->is_monitoring = true;1533 } else {1534 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");1535 sc->sc_ah->is_monitoring = false;1536 }1537 }1538 1539 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {1540 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);1541 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);1542 }1543 1544 if (changed & IEEE80211_CONF_CHANGE_POWER)1545 ath9k_set_txpower(sc, NULL);1546 1547 mutex_unlock(&sc->mutex);1548 ath9k_ps_restore(sc);1549 1550 return 0;1551}1552 1553#define SUPPORTED_FILTERS \1554 (FIF_ALLMULTI | \1555 FIF_CONTROL | \1556 FIF_PSPOLL | \1557 FIF_OTHER_BSS | \1558 FIF_BCN_PRBRESP_PROMISC | \1559 FIF_PROBE_REQ | \1560 FIF_MCAST_ACTION | \1561 FIF_FCSFAIL)1562 1563/* FIXME: sc->sc_full_reset ? */1564static void ath9k_configure_filter(struct ieee80211_hw *hw,1565 unsigned int changed_flags,1566 unsigned int *total_flags,1567 u64 multicast)1568{1569 struct ath_softc *sc = hw->priv;1570 struct ath_chanctx *ctx;1571 u32 rfilt;1572 1573 *total_flags &= SUPPORTED_FILTERS;1574 1575 spin_lock_bh(&sc->chan_lock);1576 ath_for_each_chanctx(sc, ctx)1577 ctx->rxfilter = *total_flags;1578#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT1579 sc->offchannel.chan.rxfilter = *total_flags;1580#endif1581 spin_unlock_bh(&sc->chan_lock);1582 1583 ath9k_ps_wakeup(sc);1584 rfilt = ath_calcrxfilter(sc);1585 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);1586 ath9k_ps_restore(sc);1587 1588 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",1589 rfilt);1590}1591 1592static int ath9k_sta_add(struct ieee80211_hw *hw,1593 struct ieee80211_vif *vif,1594 struct ieee80211_sta *sta)1595{1596 struct ath_softc *sc = hw->priv;1597 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1598 struct ath_node *an = (struct ath_node *) sta->drv_priv;1599 struct ieee80211_key_conf ps_key = { };1600 int key;1601 1602 ath_node_attach(sc, sta, vif);1603 1604 if (vif->type != NL80211_IFTYPE_AP &&1605 vif->type != NL80211_IFTYPE_AP_VLAN)1606 return 0;1607 1608 key = ath_key_config(common, vif, sta, &ps_key);1609 if (key > 0) {1610 an->ps_key = key;1611 an->key_idx[0] = key;1612 }1613 1614 return 0;1615}1616 1617static void ath9k_del_ps_key(struct ath_softc *sc,1618 struct ieee80211_vif *vif,1619 struct ieee80211_sta *sta)1620{1621 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1622 struct ath_node *an = (struct ath_node *) sta->drv_priv;1623 1624 if (!an->ps_key)1625 return;1626 1627 ath_key_delete(common, an->ps_key);1628 an->ps_key = 0;1629 an->key_idx[0] = 0;1630}1631 1632static int ath9k_sta_remove(struct ieee80211_hw *hw,1633 struct ieee80211_vif *vif,1634 struct ieee80211_sta *sta)1635{1636 struct ath_softc *sc = hw->priv;1637 1638 ath9k_del_ps_key(sc, vif, sta);1639 ath_node_detach(sc, sta);1640 1641 return 0;1642}1643 1644static int ath9k_sta_state(struct ieee80211_hw *hw,1645 struct ieee80211_vif *vif,1646 struct ieee80211_sta *sta,1647 enum ieee80211_sta_state old_state,1648 enum ieee80211_sta_state new_state)1649{1650 struct ath_softc *sc = hw->priv;1651 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1652 int ret = 0;1653 1654 if (old_state == IEEE80211_STA_NOTEXIST &&1655 new_state == IEEE80211_STA_NONE) {1656 ret = ath9k_sta_add(hw, vif, sta);1657 ath_dbg(common, CONFIG,1658 "Add station: %pM\n", sta->addr);1659 } else if (old_state == IEEE80211_STA_NONE &&1660 new_state == IEEE80211_STA_NOTEXIST) {1661 ret = ath9k_sta_remove(hw, vif, sta);1662 ath_dbg(common, CONFIG,1663 "Remove station: %pM\n", sta->addr);1664 }1665 1666 if (ath9k_is_chanctx_enabled()) {1667 if (vif->type == NL80211_IFTYPE_STATION) {1668 if (old_state == IEEE80211_STA_ASSOC &&1669 new_state == IEEE80211_STA_AUTHORIZED)1670 ath_chanctx_event(sc, vif,1671 ATH_CHANCTX_EVENT_AUTHORIZED);1672 }1673 }1674 1675 return ret;1676}1677 1678static void ath9k_sta_set_tx_filter(struct ath_hw *ah,1679 struct ath_node *an,1680 bool set)1681{1682 int i;1683 1684 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {1685 if (!an->key_idx[i])1686 continue;1687 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);1688 }1689}1690 1691static void ath9k_sta_notify(struct ieee80211_hw *hw,1692 struct ieee80211_vif *vif,1693 enum sta_notify_cmd cmd,1694 struct ieee80211_sta *sta)1695{1696 struct ath_softc *sc = hw->priv;1697 struct ath_node *an = (struct ath_node *) sta->drv_priv;1698 1699 switch (cmd) {1700 case STA_NOTIFY_SLEEP:1701 an->sleeping = true;1702 ath_tx_aggr_sleep(sta, sc, an);1703 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);1704 break;1705 case STA_NOTIFY_AWAKE:1706 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);1707 an->sleeping = false;1708 ath_tx_aggr_wakeup(sc, an);1709 break;1710 }1711}1712 1713static int ath9k_conf_tx(struct ieee80211_hw *hw,1714 struct ieee80211_vif *vif,1715 unsigned int link_id, u16 queue,1716 const struct ieee80211_tx_queue_params *params)1717{1718 struct ath_softc *sc = hw->priv;1719 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1720 struct ath_txq *txq;1721 struct ath9k_tx_queue_info qi;1722 int ret = 0;1723 1724 if (queue >= IEEE80211_NUM_ACS)1725 return 0;1726 1727 txq = sc->tx.txq_map[queue];1728 1729 ath9k_ps_wakeup(sc);1730 mutex_lock(&sc->mutex);1731 1732 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));1733 1734 qi.tqi_aifs = params->aifs;1735 qi.tqi_cwmin = params->cw_min;1736 qi.tqi_cwmax = params->cw_max;1737 qi.tqi_burstTime = params->txop * 32;1738 1739 ath_dbg(common, CONFIG,1740 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",1741 queue, txq->axq_qnum, params->aifs, params->cw_min,1742 params->cw_max, params->txop);1743 1744 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);1745 ret = ath_txq_update(sc, txq->axq_qnum, &qi);1746 if (ret)1747 ath_err(common, "TXQ Update failed\n");1748 1749 mutex_unlock(&sc->mutex);1750 ath9k_ps_restore(sc);1751 1752 return ret;1753}1754 1755static int ath9k_set_key(struct ieee80211_hw *hw,1756 enum set_key_cmd cmd,1757 struct ieee80211_vif *vif,1758 struct ieee80211_sta *sta,1759 struct ieee80211_key_conf *key)1760{1761 struct ath_softc *sc = hw->priv;1762 struct ath_common *common = ath9k_hw_common(sc->sc_ah);1763 struct ath_node *an = NULL;1764 int ret = 0, i;1765 1766 if (ath9k_modparam_nohwcrypt)1767 return -ENOSPC;1768 1769 if ((vif->type == NL80211_IFTYPE_ADHOC ||1770 vif->type == NL80211_IFTYPE_MESH_POINT) &&1771 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||1772 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&1773 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {1774 /*1775 * For now, disable hw crypto for the RSN IBSS group keys. This1776 * could be optimized in the future to use a modified key cache1777 * design to support per-STA RX GTK, but until that gets1778 * implemented, use of software crypto for group addressed1779 * frames is a acceptable to allow RSN IBSS to be used.1780 */1781 return -EOPNOTSUPP;1782 }1783 1784 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to1785 * make sure these are not send unencrypted or with a wrong (new) key1786 */1787 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {1788 ieee80211_stop_queues(hw);1789 ath9k_flush(hw, vif, 0, true);1790 ieee80211_wake_queues(hw);1791 }1792 1793 mutex_lock(&sc->mutex);1794 ath9k_ps_wakeup(sc);1795 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);1796 if (sta)1797 an = (struct ath_node *)sta->drv_priv;1798 1799 /* Delete pending key cache entries if no more frames are pointing to1800 * them in TXQs.1801 */1802 for (i = 0; i < ATH_KEYMAX; i++)1803 ath9k_pending_key_del(sc, i);1804 1805 switch (cmd) {1806 case SET_KEY:1807 if (sta)1808 ath9k_del_ps_key(sc, vif, sta);1809 1810 key->hw_key_idx = 0;1811 ret = ath_key_config(common, vif, sta, key);1812 if (ret >= 0) {1813 key->hw_key_idx = ret;1814 /* push IV and Michael MIC generation to stack */1815 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;1816 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)1817 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;1818 if (sc->sc_ah->sw_mgmt_crypto_tx &&1819 key->cipher == WLAN_CIPHER_SUITE_CCMP)1820 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;1821 ret = 0;1822 }1823 if (an && key->hw_key_idx) {1824 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {1825 if (an->key_idx[i])1826 continue;1827 an->key_idx[i] = key->hw_key_idx;1828 break;1829 }1830 WARN_ON(i == ARRAY_SIZE(an->key_idx));1831 }1832 break;1833 case DISABLE_KEY:1834 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {1835 /* Delay key cache entry deletion until there are no1836 * remaining TXQ frames pointing to this entry.1837 */1838 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);1839 ath_hw_keysetmac(common, key->hw_key_idx, NULL);1840 } else {1841 ath_key_delete(common, key->hw_key_idx);1842 }1843 if (an) {1844 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {1845 if (an->key_idx[i] != key->hw_key_idx)1846 continue;1847 an->key_idx[i] = 0;1848 break;1849 }1850 }1851 key->hw_key_idx = 0;1852 break;1853 default:1854 ret = -EINVAL;1855 }1856 1857 ath9k_ps_restore(sc);1858 mutex_unlock(&sc->mutex);1859 1860 return ret;1861}1862 1863static void ath9k_bss_info_changed(struct ieee80211_hw *hw,1864 struct ieee80211_vif *vif,1865 struct ieee80211_bss_conf *bss_conf,1866 u64 changed)1867{1868#define CHECK_ANI \1869 (BSS_CHANGED_ASSOC | \1870 BSS_CHANGED_IBSS | \1871 BSS_CHANGED_BEACON_ENABLED)1872 1873 struct ath_softc *sc = hw->priv;1874 struct ath_hw *ah = sc->sc_ah;1875 struct ath_common *common = ath9k_hw_common(ah);1876 struct ath_vif *avp = (void *)vif->drv_priv;1877 int slottime;1878 1879 ath9k_ps_wakeup(sc);1880 mutex_lock(&sc->mutex);1881 1882 if (changed & BSS_CHANGED_ASSOC) {1883 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",1884 bss_conf->bssid, vif->cfg.assoc);1885 1886 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);1887 avp->aid = vif->cfg.aid;1888 avp->assoc = vif->cfg.assoc;1889 1890 ath9k_calculate_summary_state(sc, avp->chanctx);1891 }1892 1893 if ((changed & BSS_CHANGED_IBSS) ||1894 (changed & BSS_CHANGED_OCB)) {1895 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);1896 common->curaid = vif->cfg.aid;1897 ath9k_hw_write_associd(sc->sc_ah);1898 }1899 1900 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||1901 (changed & BSS_CHANGED_BEACON_INT) ||1902 (changed & BSS_CHANGED_BEACON_INFO)) {1903 ath9k_calculate_summary_state(sc, avp->chanctx);1904 }1905 1906 if ((avp->chanctx == sc->cur_chan) &&1907 (changed & BSS_CHANGED_ERP_SLOT)) {1908 if (bss_conf->use_short_slot)1909 slottime = 9;1910 else1911 slottime = 20;1912 1913 if (vif->type == NL80211_IFTYPE_AP) {1914 /*1915 * Defer update, so that connected stations can adjust1916 * their settings at the same time.1917 * See beacon.c for more details1918 */1919 sc->beacon.slottime = slottime;1920 sc->beacon.updateslot = UPDATE;1921 } else {1922 ah->slottime = slottime;1923 ath9k_hw_init_global_settings(ah);1924 }1925 }1926 1927 if (changed & BSS_CHANGED_P2P_PS)1928 ath9k_p2p_bss_info_changed(sc, vif);1929 1930 if (changed & CHECK_ANI)1931 ath_check_ani(sc);1932 1933 if (changed & BSS_CHANGED_TXPOWER) {1934 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",1935 vif->addr, bss_conf->txpower, bss_conf->txpower_type);1936 ath9k_set_txpower(sc, vif);1937 }1938 1939 mutex_unlock(&sc->mutex);1940 ath9k_ps_restore(sc);1941 1942#undef CHECK_ANI1943}1944 1945static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)1946{1947 struct ath_softc *sc = hw->priv;1948 struct ath_vif *avp = (void *)vif->drv_priv;1949 u64 tsf;1950 1951 mutex_lock(&sc->mutex);1952 ath9k_ps_wakeup(sc);1953 /* Get current TSF either from HW or kernel time. */1954 if (sc->cur_chan == avp->chanctx) {1955 tsf = ath9k_hw_gettsf64(sc->sc_ah);1956 } else {1957 tsf = sc->cur_chan->tsf_val +1958 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);1959 }1960 tsf += le64_to_cpu(avp->tsf_adjust);1961 ath9k_ps_restore(sc);1962 mutex_unlock(&sc->mutex);1963 1964 return tsf;1965}1966 1967static void ath9k_set_tsf(struct ieee80211_hw *hw,1968 struct ieee80211_vif *vif,1969 u64 tsf)1970{1971 struct ath_softc *sc = hw->priv;1972 struct ath_vif *avp = (void *)vif->drv_priv;1973 1974 mutex_lock(&sc->mutex);1975 ath9k_ps_wakeup(sc);1976 tsf -= le64_to_cpu(avp->tsf_adjust);1977 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);1978 if (sc->cur_chan == avp->chanctx)1979 ath9k_hw_settsf64(sc->sc_ah, tsf);1980 avp->chanctx->tsf_val = tsf;1981 ath9k_ps_restore(sc);1982 mutex_unlock(&sc->mutex);1983}1984 1985static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)1986{1987 struct ath_softc *sc = hw->priv;1988 struct ath_vif *avp = (void *)vif->drv_priv;1989 1990 mutex_lock(&sc->mutex);1991 1992 ath9k_ps_wakeup(sc);1993 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);1994 if (sc->cur_chan == avp->chanctx)1995 ath9k_hw_reset_tsf(sc->sc_ah);1996 avp->chanctx->tsf_val = 0;1997 ath9k_ps_restore(sc);1998 1999 mutex_unlock(&sc->mutex);2000}2001 2002static int ath9k_ampdu_action(struct ieee80211_hw *hw,2003 struct ieee80211_vif *vif,2004 struct ieee80211_ampdu_params *params)2005{2006 struct ath_softc *sc = hw->priv;2007 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2008 bool flush = false;2009 int ret = 0;2010 struct ieee80211_sta *sta = params->sta;2011 struct ath_node *an = (struct ath_node *)sta->drv_priv;2012 enum ieee80211_ampdu_mlme_action action = params->action;2013 u16 tid = params->tid;2014 u16 *ssn = ¶ms->ssn;2015 struct ath_atx_tid *atid;2016 2017 mutex_lock(&sc->mutex);2018 2019 switch (action) {2020 case IEEE80211_AMPDU_RX_START:2021 break;2022 case IEEE80211_AMPDU_RX_STOP:2023 break;2024 case IEEE80211_AMPDU_TX_START:2025 if (ath9k_is_chanctx_enabled()) {2026 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {2027 ret = -EBUSY;2028 break;2029 }2030 }2031 ath9k_ps_wakeup(sc);2032 ret = ath_tx_aggr_start(sc, sta, tid, ssn);2033 if (!ret)2034 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;2035 ath9k_ps_restore(sc);2036 break;2037 case IEEE80211_AMPDU_TX_STOP_FLUSH:2038 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:2039 flush = true;2040 fallthrough;2041 case IEEE80211_AMPDU_TX_STOP_CONT:2042 ath9k_ps_wakeup(sc);2043 ath_tx_aggr_stop(sc, sta, tid);2044 if (!flush)2045 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);2046 ath9k_ps_restore(sc);2047 break;2048 case IEEE80211_AMPDU_TX_OPERATIONAL:2049 atid = ath_node_to_tid(an, tid);2050 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<2051 sta->deflink.ht_cap.ampdu_factor;2052 break;2053 default:2054 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");2055 }2056 2057 mutex_unlock(&sc->mutex);2058 2059 return ret;2060}2061 2062static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,2063 struct survey_info *survey)2064{2065 struct ath_softc *sc = hw->priv;2066 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2067 struct ieee80211_supported_band *sband;2068 struct ieee80211_channel *chan;2069 unsigned long flags;2070 int pos;2071 2072 if (IS_ENABLED(CONFIG_ATH9K_TX99))2073 return -EOPNOTSUPP;2074 2075 spin_lock_irqsave(&common->cc_lock, flags);2076 if (idx == 0)2077 ath_update_survey_stats(sc);2078 2079 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];2080 if (sband && idx >= sband->n_channels) {2081 idx -= sband->n_channels;2082 sband = NULL;2083 }2084 2085 if (!sband)2086 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];2087 2088 if (!sband || idx >= sband->n_channels) {2089 spin_unlock_irqrestore(&common->cc_lock, flags);2090 return -ENOENT;2091 }2092 2093 chan = &sband->channels[idx];2094 pos = chan->hw_value;2095 memcpy(survey, &sc->survey[pos], sizeof(*survey));2096 survey->channel = chan;2097 spin_unlock_irqrestore(&common->cc_lock, flags);2098 2099 return 0;2100}2101 2102static void ath9k_enable_dynack(struct ath_softc *sc)2103{2104#ifdef CONFIG_ATH9K_DYNACK2105 u32 rfilt;2106 struct ath_hw *ah = sc->sc_ah;2107 2108 ath_dynack_reset(ah);2109 2110 ah->dynack.enabled = true;2111 rfilt = ath_calcrxfilter(sc);2112 ath9k_hw_setrxfilter(ah, rfilt);2113#endif2114}2115 2116static void ath9k_set_coverage_class(struct ieee80211_hw *hw,2117 s16 coverage_class)2118{2119 struct ath_softc *sc = hw->priv;2120 struct ath_hw *ah = sc->sc_ah;2121 2122 if (IS_ENABLED(CONFIG_ATH9K_TX99))2123 return;2124 2125 mutex_lock(&sc->mutex);2126 2127 if (coverage_class >= 0) {2128 ah->coverage_class = coverage_class;2129 if (ah->dynack.enabled) {2130 u32 rfilt;2131 2132 ah->dynack.enabled = false;2133 rfilt = ath_calcrxfilter(sc);2134 ath9k_hw_setrxfilter(ah, rfilt);2135 }2136 ath9k_ps_wakeup(sc);2137 ath9k_hw_init_global_settings(ah);2138 ath9k_ps_restore(sc);2139 } else if (!ah->dynack.enabled) {2140 ath9k_enable_dynack(sc);2141 }2142 2143 mutex_unlock(&sc->mutex);2144}2145 2146static bool ath9k_has_tx_pending(struct ath_softc *sc,2147 bool sw_pending)2148{2149 int i, npend = 0;2150 2151 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {2152 if (!ATH_TXQ_SETUP(sc, i))2153 continue;2154 2155 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],2156 sw_pending);2157 if (npend)2158 break;2159 }2160 2161 return !!npend;2162}2163 2164static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,2165 u32 queues, bool drop)2166{2167 struct ath_softc *sc = hw->priv;2168 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2169 2170 if (ath9k_is_chanctx_enabled()) {2171 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))2172 goto flush;2173 2174 /*2175 * If MCC is active, extend the flush timeout2176 * and wait for the HW/SW queues to become2177 * empty. This needs to be done outside the2178 * sc->mutex lock to allow the channel scheduler2179 * to switch channel contexts.2180 *2181 * The vif queues have been stopped in mac80211,2182 * so there won't be any incoming frames.2183 */2184 __ath9k_flush(hw, queues, drop, true, true);2185 return;2186 }2187flush:2188 mutex_lock(&sc->mutex);2189 __ath9k_flush(hw, queues, drop, true, false);2190 mutex_unlock(&sc->mutex);2191}2192 2193void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,2194 bool sw_pending, bool timeout_override)2195{2196 struct ath_softc *sc = hw->priv;2197 struct ath_hw *ah = sc->sc_ah;2198 struct ath_common *common = ath9k_hw_common(ah);2199 int timeout;2200 bool drain_txq;2201 2202 cancel_delayed_work_sync(&sc->hw_check_work);2203 2204 if (ah->ah_flags & AH_UNPLUGGED) {2205 ath_dbg(common, ANY, "Device has been unplugged!\n");2206 return;2207 }2208 2209 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {2210 ath_dbg(common, ANY, "Device not present\n");2211 return;2212 }2213 2214 spin_lock_bh(&sc->chan_lock);2215 if (timeout_override)2216 timeout = HZ / 5;2217 else2218 timeout = sc->cur_chan->flush_timeout;2219 spin_unlock_bh(&sc->chan_lock);2220 2221 ath_dbg(common, CHAN_CTX,2222 "Flush timeout: %d\n", jiffies_to_msecs(timeout));2223 2224 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),2225 timeout) > 0)2226 drop = false;2227 2228 if (drop) {2229 ath9k_ps_wakeup(sc);2230 spin_lock_bh(&sc->sc_pcu_lock);2231 drain_txq = ath_drain_all_txq(sc);2232 spin_unlock_bh(&sc->sc_pcu_lock);2233 2234 if (!drain_txq)2235 ath_reset(sc, NULL);2236 2237 ath9k_ps_restore(sc);2238 }2239 2240 ieee80211_queue_delayed_work(hw, &sc->hw_check_work,2241 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));2242}2243 2244static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)2245{2246 struct ath_softc *sc = hw->priv;2247 2248 return ath9k_has_tx_pending(sc, true);2249}2250 2251static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)2252{2253 struct ath_softc *sc = hw->priv;2254 struct ath_hw *ah = sc->sc_ah;2255 struct ieee80211_vif *vif;2256 struct ath_vif *avp;2257 struct ath_buf *bf;2258 struct ath_tx_status ts;2259 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);2260 int status;2261 2262 vif = sc->beacon.bslot[0];2263 if (!vif)2264 return 0;2265 2266 if (!vif->bss_conf.enable_beacon)2267 return 0;2268 2269 avp = (void *)vif->drv_priv;2270 2271 if (!sc->beacon.tx_processed && !edma) {2272 tasklet_disable(&sc->bcon_tasklet);2273 2274 bf = avp->av_bcbuf;2275 if (!bf || !bf->bf_mpdu)2276 goto skip;2277 2278 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);2279 if (status == -EINPROGRESS)2280 goto skip;2281 2282 sc->beacon.tx_processed = true;2283 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);2284 2285skip:2286 tasklet_enable(&sc->bcon_tasklet);2287 }2288 2289 return sc->beacon.tx_last;2290}2291 2292static int ath9k_get_stats(struct ieee80211_hw *hw,2293 struct ieee80211_low_level_stats *stats)2294{2295 struct ath_softc *sc = hw->priv;2296 struct ath_hw *ah = sc->sc_ah;2297 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;2298 2299 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;2300 stats->dot11RTSFailureCount = mib_stats->rts_bad;2301 stats->dot11FCSErrorCount = mib_stats->fcs_bad;2302 stats->dot11RTSSuccessCount = mib_stats->rts_good;2303 return 0;2304}2305 2306static u32 fill_chainmask(u32 cap, u32 new)2307{2308 u32 filled = 0;2309 int i;2310 2311 for (i = 0; cap && new; i++, cap >>= 1) {2312 if (!(cap & BIT(0)))2313 continue;2314 2315 if (new & BIT(0))2316 filled |= BIT(i);2317 2318 new >>= 1;2319 }2320 2321 return filled;2322}2323 2324static bool validate_antenna_mask(struct ath_hw *ah, u32 val)2325{2326 if (AR_SREV_9300_20_OR_LATER(ah))2327 return true;2328 2329 switch (val & 0x7) {2330 case 0x1:2331 case 0x3:2332 case 0x7:2333 return true;2334 case 0x2:2335 return (ah->caps.rx_chainmask == 1);2336 default:2337 return false;2338 }2339}2340 2341static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)2342{2343 struct ath_softc *sc = hw->priv;2344 struct ath_hw *ah = sc->sc_ah;2345 2346 if (ah->caps.rx_chainmask != 1)2347 rx_ant |= tx_ant;2348 2349 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)2350 return -EINVAL;2351 2352 sc->ant_rx = rx_ant;2353 sc->ant_tx = tx_ant;2354 2355 if (ah->caps.rx_chainmask == 1)2356 return 0;2357 2358 /* AR9100 runs into calibration issues if not all rx chains are enabled */2359 if (AR_SREV_9100(ah))2360 ah->rxchainmask = 0x7;2361 else2362 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);2363 2364 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);2365 ath9k_cmn_reload_chainmask(ah);2366 2367 return 0;2368}2369 2370static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)2371{2372 struct ath_softc *sc = hw->priv;2373 2374 *tx_ant = sc->ant_tx;2375 *rx_ant = sc->ant_rx;2376 return 0;2377}2378 2379static void ath9k_sw_scan_start(struct ieee80211_hw *hw,2380 struct ieee80211_vif *vif,2381 const u8 *mac_addr)2382{2383 struct ath_softc *sc = hw->priv;2384 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2385 struct cfg80211_chan_def *chandef = &sc->cur_chan->chandef;2386 struct ieee80211_channel *chan = chandef->chan;2387 int pos = chan->hw_value;2388 set_bit(ATH_OP_SCANNING, &common->op_flags);2389 2390 /* Reset current survey */2391 if (!sc->cur_chan->offchannel) {2392 if (sc->cur_survey != &sc->survey[pos]) {2393 if (sc->cur_survey)2394 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;2395 sc->cur_survey = &sc->survey[pos];2396 }2397 2398 memset(sc->cur_survey, 0, sizeof(struct survey_info));2399 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;2400 }2401}2402 2403static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,2404 struct ieee80211_vif *vif)2405{2406 struct ath_softc *sc = hw->priv;2407 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2408 clear_bit(ATH_OP_SCANNING, &common->op_flags);2409}2410 2411#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT2412 2413static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)2414{2415 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2416 2417 if (sc->offchannel.roc_vif) {2418 ath_dbg(common, CHAN_CTX,2419 "%s: Aborting RoC\n", __func__);2420 2421 del_timer_sync(&sc->offchannel.timer);2422 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)2423 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);2424 }2425 2426 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {2427 ath_dbg(common, CHAN_CTX,2428 "%s: Aborting HW scan\n", __func__);2429 2430 del_timer_sync(&sc->offchannel.timer);2431 ath_scan_complete(sc, true);2432 }2433}2434 2435static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,2436 struct ieee80211_scan_request *hw_req)2437{2438 struct cfg80211_scan_request *req = &hw_req->req;2439 struct ath_softc *sc = hw->priv;2440 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2441 int ret = 0;2442 2443 mutex_lock(&sc->mutex);2444 2445 if (WARN_ON(sc->offchannel.scan_req)) {2446 ret = -EBUSY;2447 goto out;2448 }2449 2450 ath9k_ps_wakeup(sc);2451 set_bit(ATH_OP_SCANNING, &common->op_flags);2452 sc->offchannel.scan_vif = vif;2453 sc->offchannel.scan_req = req;2454 sc->offchannel.scan_idx = 0;2455 2456 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",2457 vif->addr);2458 2459 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {2460 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");2461 ath_offchannel_next(sc);2462 }2463 2464out:2465 mutex_unlock(&sc->mutex);2466 2467 return ret;2468}2469 2470static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,2471 struct ieee80211_vif *vif)2472{2473 struct ath_softc *sc = hw->priv;2474 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2475 2476 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);2477 2478 mutex_lock(&sc->mutex);2479 del_timer_sync(&sc->offchannel.timer);2480 ath_scan_complete(sc, true);2481 mutex_unlock(&sc->mutex);2482}2483 2484static int ath9k_remain_on_channel(struct ieee80211_hw *hw,2485 struct ieee80211_vif *vif,2486 struct ieee80211_channel *chan, int duration,2487 enum ieee80211_roc_type type)2488{2489 struct ath_softc *sc = hw->priv;2490 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2491 int ret = 0;2492 2493 mutex_lock(&sc->mutex);2494 2495 if (WARN_ON(sc->offchannel.roc_vif)) {2496 ret = -EBUSY;2497 goto out;2498 }2499 2500 ath9k_ps_wakeup(sc);2501 sc->offchannel.roc_vif = vif;2502 sc->offchannel.roc_chan = chan;2503 sc->offchannel.roc_duration = duration;2504 2505 ath_dbg(common, CHAN_CTX,2506 "RoC request on vif: %pM, type: %d duration: %d\n",2507 vif->addr, type, duration);2508 2509 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {2510 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");2511 ath_offchannel_next(sc);2512 }2513 2514out:2515 mutex_unlock(&sc->mutex);2516 2517 return ret;2518}2519 2520static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,2521 struct ieee80211_vif *vif)2522{2523 struct ath_softc *sc = hw->priv;2524 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2525 2526 mutex_lock(&sc->mutex);2527 2528 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");2529 del_timer_sync(&sc->offchannel.timer);2530 2531 if (sc->offchannel.roc_vif) {2532 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)2533 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);2534 }2535 2536 mutex_unlock(&sc->mutex);2537 2538 return 0;2539}2540 2541static int ath9k_add_chanctx(struct ieee80211_hw *hw,2542 struct ieee80211_chanctx_conf *conf)2543{2544 struct ath_softc *sc = hw->priv;2545 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2546 struct ath_chanctx *ctx, **ptr;2547 int pos;2548 2549 mutex_lock(&sc->mutex);2550 2551 ath_for_each_chanctx(sc, ctx) {2552 if (ctx->assigned)2553 continue;2554 2555 ptr = (void *) conf->drv_priv;2556 *ptr = ctx;2557 ctx->assigned = true;2558 pos = ctx - &sc->chanctx[0];2559 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;2560 2561 ath_dbg(common, CHAN_CTX,2562 "Add channel context: %d MHz\n",2563 conf->def.chan->center_freq);2564 2565 ath_chanctx_set_channel(sc, ctx, &conf->def);2566 2567 mutex_unlock(&sc->mutex);2568 return 0;2569 }2570 2571 mutex_unlock(&sc->mutex);2572 return -ENOSPC;2573}2574 2575 2576static void ath9k_remove_chanctx(struct ieee80211_hw *hw,2577 struct ieee80211_chanctx_conf *conf)2578{2579 struct ath_softc *sc = hw->priv;2580 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2581 struct ath_chanctx *ctx = ath_chanctx_get(conf);2582 2583 mutex_lock(&sc->mutex);2584 2585 ath_dbg(common, CHAN_CTX,2586 "Remove channel context: %d MHz\n",2587 conf->def.chan->center_freq);2588 2589 ctx->assigned = false;2590 ctx->hw_queue_base = 0;2591 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);2592 2593 mutex_unlock(&sc->mutex);2594}2595 2596static void ath9k_change_chanctx(struct ieee80211_hw *hw,2597 struct ieee80211_chanctx_conf *conf,2598 u32 changed)2599{2600 struct ath_softc *sc = hw->priv;2601 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2602 struct ath_chanctx *ctx = ath_chanctx_get(conf);2603 2604 mutex_lock(&sc->mutex);2605 ath_dbg(common, CHAN_CTX,2606 "Change channel context: %d MHz\n",2607 conf->def.chan->center_freq);2608 ath_chanctx_set_channel(sc, ctx, &conf->def);2609 mutex_unlock(&sc->mutex);2610}2611 2612static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,2613 struct ieee80211_vif *vif,2614 struct ieee80211_bss_conf *link_conf,2615 struct ieee80211_chanctx_conf *conf)2616{2617 struct ath_softc *sc = hw->priv;2618 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2619 struct ath_vif *avp = (void *)vif->drv_priv;2620 struct ath_chanctx *ctx = ath_chanctx_get(conf);2621 int i;2622 2623 ath9k_cancel_pending_offchannel(sc);2624 2625 mutex_lock(&sc->mutex);2626 2627 ath_dbg(common, CHAN_CTX,2628 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",2629 vif->addr, vif->type, vif->p2p,2630 conf->def.chan->center_freq);2631 2632 avp->chanctx = ctx;2633 ctx->nvifs_assigned++;2634 list_add_tail(&avp->list, &ctx->vifs);2635 ath9k_calculate_summary_state(sc, ctx);2636 for (i = 0; i < IEEE80211_NUM_ACS; i++)2637 vif->hw_queue[i] = ctx->hw_queue_base + i;2638 2639 mutex_unlock(&sc->mutex);2640 2641 return 0;2642}2643 2644static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,2645 struct ieee80211_vif *vif,2646 struct ieee80211_bss_conf *link_conf,2647 struct ieee80211_chanctx_conf *conf)2648{2649 struct ath_softc *sc = hw->priv;2650 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2651 struct ath_vif *avp = (void *)vif->drv_priv;2652 struct ath_chanctx *ctx = ath_chanctx_get(conf);2653 int ac;2654 2655 ath9k_cancel_pending_offchannel(sc);2656 2657 mutex_lock(&sc->mutex);2658 2659 ath_dbg(common, CHAN_CTX,2660 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",2661 vif->addr, vif->type, vif->p2p,2662 conf->def.chan->center_freq);2663 2664 avp->chanctx = NULL;2665 ctx->nvifs_assigned--;2666 list_del(&avp->list);2667 ath9k_calculate_summary_state(sc, ctx);2668 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)2669 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;2670 2671 mutex_unlock(&sc->mutex);2672}2673 2674static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,2675 struct ieee80211_vif *vif,2676 struct ieee80211_prep_tx_info *info)2677{2678 struct ath_softc *sc = hw->priv;2679 struct ath_common *common = ath9k_hw_common(sc->sc_ah);2680 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;2681 struct ath_beacon_config *cur_conf;2682 struct ath_chanctx *go_ctx;2683 unsigned long timeout;2684 bool changed = false;2685 u32 beacon_int;2686 2687 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))2688 return;2689 2690 if (!avp->chanctx)2691 return;2692 2693 mutex_lock(&sc->mutex);2694 2695 spin_lock_bh(&sc->chan_lock);2696 if (sc->next_chan || (sc->cur_chan != avp->chanctx))2697 changed = true;2698 spin_unlock_bh(&sc->chan_lock);2699 2700 if (!changed)2701 goto out;2702 2703 ath9k_cancel_pending_offchannel(sc);2704 2705 go_ctx = ath_is_go_chanctx_present(sc);2706 2707 if (go_ctx) {2708 /*2709 * Wait till the GO interface gets a chance2710 * to send out an NoA.2711 */2712 spin_lock_bh(&sc->chan_lock);2713 sc->sched.mgd_prepare_tx = true;2714 cur_conf = &go_ctx->beacon;2715 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);2716 spin_unlock_bh(&sc->chan_lock);2717 2718 timeout = usecs_to_jiffies(beacon_int * 2);2719 init_completion(&sc->go_beacon);2720 2721 mutex_unlock(&sc->mutex);2722 2723 if (wait_for_completion_timeout(&sc->go_beacon,2724 timeout) == 0) {2725 ath_dbg(common, CHAN_CTX,2726 "Failed to send new NoA\n");2727 2728 spin_lock_bh(&sc->chan_lock);2729 sc->sched.mgd_prepare_tx = false;2730 spin_unlock_bh(&sc->chan_lock);2731 }2732 2733 mutex_lock(&sc->mutex);2734 }2735 2736 ath_dbg(common, CHAN_CTX,2737 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",2738 __func__, vif->addr);2739 2740 spin_lock_bh(&sc->chan_lock);2741 sc->next_chan = avp->chanctx;2742 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;2743 spin_unlock_bh(&sc->chan_lock);2744 2745 ath_chanctx_set_next(sc, true);2746out:2747 mutex_unlock(&sc->mutex);2748}2749 2750void ath9k_fill_chanctx_ops(void)2751{2752 if (!ath9k_is_chanctx_enabled())2753 return;2754 2755 ath9k_ops.hw_scan = ath9k_hw_scan;2756 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;2757 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;2758 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;2759 ath9k_ops.add_chanctx = ath9k_add_chanctx;2760 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;2761 ath9k_ops.change_chanctx = ath9k_change_chanctx;2762 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;2763 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;2764 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;2765}2766 2767#endif2768 2769static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,2770 int *dbm)2771{2772 struct ath_softc *sc = hw->priv;2773 struct ath_vif *avp = (void *)vif->drv_priv;2774 2775 mutex_lock(&sc->mutex);2776 if (avp->chanctx)2777 *dbm = avp->chanctx->cur_txpower;2778 else2779 *dbm = sc->cur_chan->cur_txpower;2780 mutex_unlock(&sc->mutex);2781 2782 *dbm /= 2;2783 2784 return 0;2785}2786 2787struct ieee80211_ops ath9k_ops = {2788 .add_chanctx = ieee80211_emulate_add_chanctx,2789 .remove_chanctx = ieee80211_emulate_remove_chanctx,2790 .change_chanctx = ieee80211_emulate_change_chanctx,2791 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx,2792 .tx = ath9k_tx,2793 .start = ath9k_start,2794 .stop = ath9k_stop,2795 .add_interface = ath9k_add_interface,2796 .change_interface = ath9k_change_interface,2797 .remove_interface = ath9k_remove_interface,2798 .config = ath9k_config,2799 .configure_filter = ath9k_configure_filter,2800 .sta_state = ath9k_sta_state,2801 .sta_notify = ath9k_sta_notify,2802 .conf_tx = ath9k_conf_tx,2803 .bss_info_changed = ath9k_bss_info_changed,2804 .set_key = ath9k_set_key,2805 .get_tsf = ath9k_get_tsf,2806 .set_tsf = ath9k_set_tsf,2807 .reset_tsf = ath9k_reset_tsf,2808 .ampdu_action = ath9k_ampdu_action,2809 .get_survey = ath9k_get_survey,2810 .rfkill_poll = ath9k_rfkill_poll_state,2811 .set_coverage_class = ath9k_set_coverage_class,2812 .flush = ath9k_flush,2813 .tx_frames_pending = ath9k_tx_frames_pending,2814 .tx_last_beacon = ath9k_tx_last_beacon,2815 .release_buffered_frames = ath9k_release_buffered_frames,2816 .get_stats = ath9k_get_stats,2817 .set_antenna = ath9k_set_antenna,2818 .get_antenna = ath9k_get_antenna,2819 2820#ifdef CONFIG_ATH9K_WOW2821 .suspend = ath9k_suspend,2822 .resume = ath9k_resume,2823 .set_wakeup = ath9k_set_wakeup,2824#endif2825 2826#ifdef CONFIG_ATH9K_DEBUGFS2827 .get_et_sset_count = ath9k_get_et_sset_count,2828 .get_et_stats = ath9k_get_et_stats,2829 .get_et_strings = ath9k_get_et_strings,2830#endif2831 2832#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)2833 .sta_add_debugfs = ath9k_sta_add_debugfs,2834#endif2835 .sw_scan_start = ath9k_sw_scan_start,2836 .sw_scan_complete = ath9k_sw_scan_complete,2837 .get_txpower = ath9k_get_txpower,2838 .wake_tx_queue = ath9k_wake_tx_queue,2839};2840