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1/*2 * Copyright (c) 2008-2011 Atheros Communications Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef REG_H18#define REG_H19 20#include "../reg.h"21 22#define AR_CR 0x000823#define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)24#define AR_CR_RXD 0x0000002025#define AR_CR_SWI 0x0000004026 27#define AR_RXDP 0x000C28 29#define AR_CFG 0x001430#define AR_CFG_SWTD 0x0000000131#define AR_CFG_SWTB 0x0000000232#define AR_CFG_SWRD 0x0000000433#define AR_CFG_SWRB 0x0000000834#define AR_CFG_SWRG 0x0000001035#define AR_CFG_AP_ADHOC_INDICATION 0x0000002036#define AR_CFG_PHOK 0x0000010037#define AR_CFG_EEBS 0x0000020038#define AR_CFG_CLK_GATE_DIS 0x0000040039#define AR_CFG_HALT_REQ 0x0000080040#define AR_CFG_HALT_ACK 0x0000100041#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x0006000042#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 1743 44#define AR_RXBP_THRESH 0x001845#define AR_RXBP_THRESH_HP 0x0000000f46#define AR_RXBP_THRESH_HP_S 047#define AR_RXBP_THRESH_LP 0x00003f0048#define AR_RXBP_THRESH_LP_S 849 50#define AR_MIRT 0x002051#define AR_MIRT_VAL 0x0000ffff52#define AR_MIRT_VAL_S 1653 54#define AR_IER 0x002455#define AR_IER_ENABLE 0x0000000156#define AR_IER_DISABLE 0x0000000057 58#define AR_TIMT 0x002859#define AR_TIMT_LAST 0x0000ffff60#define AR_TIMT_LAST_S 061#define AR_TIMT_FIRST 0xffff000062#define AR_TIMT_FIRST_S 1663 64#define AR_RIMT 0x002C65#define AR_RIMT_LAST 0x0000ffff66#define AR_RIMT_LAST_S 067#define AR_RIMT_FIRST 0xffff000068#define AR_RIMT_FIRST_S 1669 70#define AR_DMASIZE_4B 0x0000000071#define AR_DMASIZE_8B 0x0000000172#define AR_DMASIZE_16B 0x0000000273#define AR_DMASIZE_32B 0x0000000374#define AR_DMASIZE_64B 0x0000000475#define AR_DMASIZE_128B 0x0000000576#define AR_DMASIZE_256B 0x0000000677#define AR_DMASIZE_512B 0x0000000778 79#define AR_TXCFG 0x003080#define AR_TXCFG_DMASZ_MASK 0x0000000781#define AR_TXCFG_DMASZ_4B 082#define AR_TXCFG_DMASZ_8B 183#define AR_TXCFG_DMASZ_16B 284#define AR_TXCFG_DMASZ_32B 385#define AR_TXCFG_DMASZ_64B 486#define AR_TXCFG_DMASZ_128B 587#define AR_TXCFG_DMASZ_256B 688#define AR_TXCFG_DMASZ_512B 789#define AR_FTRIG 0x000003F090#define AR_FTRIG_S 491#define AR_FTRIG_IMMED 0x0000000092#define AR_FTRIG_64B 0x0000001093#define AR_FTRIG_128B 0x0000002094#define AR_FTRIG_192B 0x0000003095#define AR_FTRIG_256B 0x0000004096#define AR_FTRIG_512B 0x0000008097#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x0000080098 99#define AR_RXCFG 0x0034100#define AR_RXCFG_CHIRP 0x00000008101#define AR_RXCFG_ZLFDMA 0x00000010102#define AR_RXCFG_DMASZ_MASK 0x00000007103#define AR_RXCFG_DMASZ_4B 0104#define AR_RXCFG_DMASZ_8B 1105#define AR_RXCFG_DMASZ_16B 2106#define AR_RXCFG_DMASZ_32B 3107#define AR_RXCFG_DMASZ_64B 4108#define AR_RXCFG_DMASZ_128B 5109#define AR_RXCFG_DMASZ_256B 6110#define AR_RXCFG_DMASZ_512B 7111 112#define AR_TOPS 0x0044113#define AR_TOPS_MASK 0x0000FFFF114 115#define AR_RXNPTO 0x0048116#define AR_RXNPTO_MASK 0x000003FF117 118#define AR_TXNPTO 0x004C119#define AR_TXNPTO_MASK 0x000003FF120#define AR_TXNPTO_QCU_MASK 0x000FFC00121 122#define AR_RPGTO 0x0050123#define AR_RPGTO_MASK 0x000003FF124 125#define AR_RPCNT 0x0054126#define AR_RPCNT_MASK 0x0000001F127 128#define AR_MACMISC 0x0058129#define AR_MACMISC_PCI_EXT_FORCE 0x00000010130#define AR_MACMISC_DMA_OBS 0x000001E0131#define AR_MACMISC_DMA_OBS_S 5132#define AR_MACMISC_DMA_OBS_LINE_0 0133#define AR_MACMISC_DMA_OBS_LINE_1 1134#define AR_MACMISC_DMA_OBS_LINE_2 2135#define AR_MACMISC_DMA_OBS_LINE_3 3136#define AR_MACMISC_DMA_OBS_LINE_4 4137#define AR_MACMISC_DMA_OBS_LINE_5 5138#define AR_MACMISC_DMA_OBS_LINE_6 6139#define AR_MACMISC_DMA_OBS_LINE_7 7140#define AR_MACMISC_DMA_OBS_LINE_8 8141#define AR_MACMISC_MISC_OBS 0x00000E00142#define AR_MACMISC_MISC_OBS_S 9143#define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000144#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12145#define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000146#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15147#define AR_MACMISC_MISC_OBS_BUS_1 1148 149#define AR_INTCFG 0x005C150#define AR_INTCFG_MSI_RXOK 0x00000000151#define AR_INTCFG_MSI_RXINTM 0x00000004152#define AR_INTCFG_MSI_RXMINTR 0x00000006153#define AR_INTCFG_MSI_TXOK 0x00000000154#define AR_INTCFG_MSI_TXINTM 0x00000010155#define AR_INTCFG_MSI_TXMINTR 0x00000018156 157#define AR_DATABUF_SIZE 0x0060158#define AR_DATABUF_SIZE_MASK 0x00000FFF159 160#define AR_GTXTO 0x0064161#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF162#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000163#define AR_GTXTO_TIMEOUT_LIMIT_S 16164 165#define AR_GTTM 0x0068166#define AR_GTTM_USEC 0x00000001167#define AR_GTTM_IGNORE_IDLE 0x00000002168#define AR_GTTM_RESET_IDLE 0x00000004169#define AR_GTTM_CST_USEC 0x00000008170 171#define AR_CST 0x006C172#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF173#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000174#define AR_CST_TIMEOUT_LIMIT_S 16175 176#define AR_HP_RXDP 0x0074177#define AR_LP_RXDP 0x0078178 179#define AR_ISR 0x0080180#define AR_ISR_RXOK 0x00000001181#define AR_ISR_RXDESC 0x00000002182#define AR_ISR_HP_RXOK 0x00000001183#define AR_ISR_LP_RXOK 0x00000002184#define AR_ISR_RXERR 0x00000004185#define AR_ISR_RXNOPKT 0x00000008186#define AR_ISR_RXEOL 0x00000010187#define AR_ISR_RXORN 0x00000020188#define AR_ISR_TXOK 0x00000040189#define AR_ISR_TXDESC 0x00000080190#define AR_ISR_TXERR 0x00000100191#define AR_ISR_TXNOPKT 0x00000200192#define AR_ISR_TXEOL 0x00000400193#define AR_ISR_TXURN 0x00000800194#define AR_ISR_MIB 0x00001000195#define AR_ISR_SWI 0x00002000196#define AR_ISR_RXPHY 0x00004000197#define AR_ISR_RXKCM 0x00008000198#define AR_ISR_SWBA 0x00010000199#define AR_ISR_BRSSI 0x00020000200#define AR_ISR_BMISS 0x00040000201#define AR_ISR_BNR 0x00100000202#define AR_ISR_RXCHIRP 0x00200000203#define AR_ISR_BCNMISC 0x00800000204#define AR_ISR_TIM 0x00800000205#define AR_ISR_QCBROVF 0x02000000206#define AR_ISR_QCBRURN 0x04000000207#define AR_ISR_QTRIG 0x08000000208#define AR_ISR_GENTMR 0x10000000209 210#define AR_ISR_TXMINTR 0x00080000211#define AR_ISR_RXMINTR 0x01000000212#define AR_ISR_TXINTM 0x40000000213#define AR_ISR_RXINTM 0x80000000214 215#define AR_ISR_S0 0x0084216#define AR_ISR_S0_QCU_TXOK 0x000003FF217#define AR_ISR_S0_QCU_TXOK_S 0218#define AR_ISR_S0_QCU_TXDESC 0x03FF0000219#define AR_ISR_S0_QCU_TXDESC_S 16220 221#define AR_ISR_S1 0x0088222#define AR_ISR_S1_QCU_TXERR 0x000003FF223#define AR_ISR_S1_QCU_TXERR_S 0224#define AR_ISR_S1_QCU_TXEOL 0x03FF0000225#define AR_ISR_S1_QCU_TXEOL_S 16226 227#define AR_ISR_S2 0x008c228#define AR_ISR_S2_QCU_TXURN 0x000003FF229#define AR_ISR_S2_BB_WATCHDOG 0x00010000230#define AR_ISR_S2_CST 0x00400000231#define AR_ISR_S2_GTT 0x00800000232#define AR_ISR_S2_TIM 0x01000000233#define AR_ISR_S2_CABEND 0x02000000234#define AR_ISR_S2_DTIMSYNC 0x04000000235#define AR_ISR_S2_BCNTO 0x08000000236#define AR_ISR_S2_CABTO 0x10000000237#define AR_ISR_S2_DTIM 0x20000000238#define AR_ISR_S2_TSFOOR 0x40000000239#define AR_ISR_S2_TBTT_TIME 0x80000000240 241#define AR_ISR_S3 0x0090242#define AR_ISR_S3_QCU_QCBROVF 0x000003FF243#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000244 245#define AR_ISR_S4 0x0094246#define AR_ISR_S4_QCU_QTRIG 0x000003FF247#define AR_ISR_S4_RESV0 0xFFFFFC00248 249#define AR_ISR_S5 0x0098250#define AR_ISR_S5_TIMER_TRIG 0x000000FF251#define AR_ISR_S5_TIMER_THRESH 0x0007FE00252#define AR_ISR_S5_TIM_TIMER 0x00000010253#define AR_ISR_S5_DTIM_TIMER 0x00000020254#define AR_IMR_S5 0x00b8255#define AR_IMR_S5_TIM_TIMER 0x00000010256#define AR_IMR_S5_DTIM_TIMER 0x00000020257#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80258#define AR_ISR_S5_GENTIMER_TRIG_S 0259#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000260#define AR_ISR_S5_GENTIMER_THRESH_S 16261#define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80262#define AR_IMR_S5_GENTIMER_TRIG_S 0263#define AR_IMR_S5_GENTIMER_THRESH 0xFF800000264#define AR_IMR_S5_GENTIMER_THRESH_S 16265 266#define AR_IMR 0x00a0267#define AR_IMR_RXOK 0x00000001268#define AR_IMR_RXDESC 0x00000002269#define AR_IMR_RXOK_HP 0x00000001270#define AR_IMR_RXOK_LP 0x00000002271#define AR_IMR_RXERR 0x00000004272#define AR_IMR_RXNOPKT 0x00000008273#define AR_IMR_RXEOL 0x00000010274#define AR_IMR_RXORN 0x00000020275#define AR_IMR_TXOK 0x00000040276#define AR_IMR_TXDESC 0x00000080277#define AR_IMR_TXERR 0x00000100278#define AR_IMR_TXNOPKT 0x00000200279#define AR_IMR_TXEOL 0x00000400280#define AR_IMR_TXURN 0x00000800281#define AR_IMR_MIB 0x00001000282#define AR_IMR_SWI 0x00002000283#define AR_IMR_RXPHY 0x00004000284#define AR_IMR_RXKCM 0x00008000285#define AR_IMR_SWBA 0x00010000286#define AR_IMR_BRSSI 0x00020000287#define AR_IMR_BMISS 0x00040000288#define AR_IMR_BNR 0x00100000289#define AR_IMR_RXCHIRP 0x00200000290#define AR_IMR_BCNMISC 0x00800000291#define AR_IMR_TIM 0x00800000292#define AR_IMR_QCBROVF 0x02000000293#define AR_IMR_QCBRURN 0x04000000294#define AR_IMR_QTRIG 0x08000000295#define AR_IMR_GENTMR 0x10000000296 297#define AR_IMR_TXMINTR 0x00080000298#define AR_IMR_RXMINTR 0x01000000299#define AR_IMR_TXINTM 0x40000000300#define AR_IMR_RXINTM 0x80000000301 302#define AR_IMR_S0 0x00a4303#define AR_IMR_S0_QCU_TXOK 0x000003FF304#define AR_IMR_S0_QCU_TXOK_S 0305#define AR_IMR_S0_QCU_TXDESC 0x03FF0000306#define AR_IMR_S0_QCU_TXDESC_S 16307 308#define AR_IMR_S1 0x00a8309#define AR_IMR_S1_QCU_TXERR 0x000003FF310#define AR_IMR_S1_QCU_TXERR_S 0311#define AR_IMR_S1_QCU_TXEOL 0x03FF0000312#define AR_IMR_S1_QCU_TXEOL_S 16313 314#define AR_IMR_S2 0x00ac315#define AR_IMR_S2_QCU_TXURN 0x000003FF316#define AR_IMR_S2_QCU_TXURN_S 0317#define AR_IMR_S2_BB_WATCHDOG 0x00010000318#define AR_IMR_S2_CST 0x00400000319#define AR_IMR_S2_GTT 0x00800000320#define AR_IMR_S2_TIM 0x01000000321#define AR_IMR_S2_CABEND 0x02000000322#define AR_IMR_S2_DTIMSYNC 0x04000000323#define AR_IMR_S2_BCNTO 0x08000000324#define AR_IMR_S2_CABTO 0x10000000325#define AR_IMR_S2_DTIM 0x20000000326#define AR_IMR_S2_TSFOOR 0x40000000327 328#define AR_IMR_S3 0x00b0329#define AR_IMR_S3_QCU_QCBROVF 0x000003FF330#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000331#define AR_IMR_S3_QCU_QCBRURN_S 16332 333#define AR_IMR_S4 0x00b4334#define AR_IMR_S4_QCU_QTRIG 0x000003FF335#define AR_IMR_S4_RESV0 0xFFFFFC00336 337#define AR_IMR_S5 0x00b8338#define AR_IMR_S5_TIMER_TRIG 0x000000FF339#define AR_IMR_S5_TIMER_THRESH 0x0000FF00340 341 342#define AR_ISR_RAC 0x00c0343#define AR_ISR_S0_S 0x00c4344#define AR_ISR_S0_QCU_TXOK 0x000003FF345#define AR_ISR_S0_QCU_TXOK_S 0346#define AR_ISR_S0_QCU_TXDESC 0x03FF0000347#define AR_ISR_S0_QCU_TXDESC_S 16348 349#define AR_ISR_S1_S 0x00c8350#define AR_ISR_S1_QCU_TXERR 0x000003FF351#define AR_ISR_S1_QCU_TXERR_S 0352#define AR_ISR_S1_QCU_TXEOL 0x03FF0000353#define AR_ISR_S1_QCU_TXEOL_S 16354 355#define AR_ISR_S2_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d0 : 0x00cc)356#define AR_ISR_S3_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d4 : 0x00d0)357#define AR_ISR_S4_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d8 : 0x00d4)358#define AR_ISR_S5_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00dc : 0x00d8)359#define AR_DMADBG_0 0x00e0360#define AR_DMADBG_1 0x00e4361#define AR_DMADBG_2 0x00e8362#define AR_DMADBG_3 0x00ec363#define AR_DMADBG_4 0x00f0364#define AR_DMADBG_5 0x00f4365#define AR_DMADBG_6 0x00f8366#define AR_DMADBG_7 0x00fc367 368#define AR_NUM_QCU 10369#define AR_QCU_0 0x0001370#define AR_QCU_1 0x0002371#define AR_QCU_2 0x0004372#define AR_QCU_3 0x0008373#define AR_QCU_4 0x0010374#define AR_QCU_5 0x0020375#define AR_QCU_6 0x0040376#define AR_QCU_7 0x0080377#define AR_QCU_8 0x0100378#define AR_QCU_9 0x0200379 380#define AR_Q0_TXDP 0x0800381#define AR_Q1_TXDP 0x0804382#define AR_Q2_TXDP 0x0808383#define AR_Q3_TXDP 0x080c384#define AR_Q4_TXDP 0x0810385#define AR_Q5_TXDP 0x0814386#define AR_Q6_TXDP 0x0818387#define AR_Q7_TXDP 0x081c388#define AR_Q8_TXDP 0x0820389#define AR_Q9_TXDP 0x0824390#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))391 392#define AR_Q_STATUS_RING_START 0x830393#define AR_Q_STATUS_RING_END 0x834394 395#define AR_Q_TXE 0x0840396#define AR_Q_TXE_M 0x000003FF397 398#define AR_Q_TXD 0x0880399#define AR_Q_TXD_M 0x000003FF400 401#define AR_Q0_CBRCFG 0x08c0402#define AR_Q1_CBRCFG 0x08c4403#define AR_Q2_CBRCFG 0x08c8404#define AR_Q3_CBRCFG 0x08cc405#define AR_Q4_CBRCFG 0x08d0406#define AR_Q5_CBRCFG 0x08d4407#define AR_Q6_CBRCFG 0x08d8408#define AR_Q7_CBRCFG 0x08dc409#define AR_Q8_CBRCFG 0x08e0410#define AR_Q9_CBRCFG 0x08e4411#define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2))412#define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF413#define AR_Q_CBRCFG_INTERVAL_S 0414#define AR_Q_CBRCFG_OVF_THRESH 0xFF000000415#define AR_Q_CBRCFG_OVF_THRESH_S 24416 417#define AR_Q0_RDYTIMECFG 0x0900418#define AR_Q1_RDYTIMECFG 0x0904419#define AR_Q2_RDYTIMECFG 0x0908420#define AR_Q3_RDYTIMECFG 0x090c421#define AR_Q4_RDYTIMECFG 0x0910422#define AR_Q5_RDYTIMECFG 0x0914423#define AR_Q6_RDYTIMECFG 0x0918424#define AR_Q7_RDYTIMECFG 0x091c425#define AR_Q8_RDYTIMECFG 0x0920426#define AR_Q9_RDYTIMECFG 0x0924427#define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2))428#define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF429#define AR_Q_RDYTIMECFG_DURATION_S 0430#define AR_Q_RDYTIMECFG_EN 0x01000000431 432#define AR_Q_ONESHOTARM_SC 0x0940433#define AR_Q_ONESHOTARM_SC_M 0x000003FF434#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00435 436#define AR_Q_ONESHOTARM_CC 0x0980437#define AR_Q_ONESHOTARM_CC_M 0x000003FF438#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00439 440#define AR_Q0_MISC 0x09c0441#define AR_Q1_MISC 0x09c4442#define AR_Q2_MISC 0x09c8443#define AR_Q3_MISC 0x09cc444#define AR_Q4_MISC 0x09d0445#define AR_Q5_MISC 0x09d4446#define AR_Q6_MISC 0x09d8447#define AR_Q7_MISC 0x09dc448#define AR_Q8_MISC 0x09e0449#define AR_Q9_MISC 0x09e4450#define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2))451#define AR_Q_MISC_FSP 0x0000000F452#define AR_Q_MISC_FSP_ASAP 0453#define AR_Q_MISC_FSP_CBR 1454#define AR_Q_MISC_FSP_DBA_GATED 2455#define AR_Q_MISC_FSP_TIM_GATED 3456#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4457#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5458#define AR_Q_MISC_ONE_SHOT_EN 0x00000010459#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020460#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040461#define AR_Q_MISC_BEACON_USE 0x00000080462#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100463#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200464#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400465#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800466#define AR_Q_MISC_RESV0 0xFFFFF000467 468#define AR_Q0_STS 0x0a00469#define AR_Q1_STS 0x0a04470#define AR_Q2_STS 0x0a08471#define AR_Q3_STS 0x0a0c472#define AR_Q4_STS 0x0a10473#define AR_Q5_STS 0x0a14474#define AR_Q6_STS 0x0a18475#define AR_Q7_STS 0x0a1c476#define AR_Q8_STS 0x0a20477#define AR_Q9_STS 0x0a24478#define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2))479#define AR_Q_STS_PEND_FR_CNT 0x00000003480#define AR_Q_STS_RESV0 0x000000FC481#define AR_Q_STS_CBR_EXP_CNT 0x0000FF00482#define AR_Q_STS_RESV1 0xFFFF0000483 484#define AR_Q_RDYTIMESHDN 0x0a40485#define AR_Q_RDYTIMESHDN_M 0x000003FF486 487/* MAC Descriptor CRC check */488#define AR_Q_DESC_CRCCHK 0xa44489/* Enable CRC check on the descriptor fetched from host */490#define AR_Q_DESC_CRCCHK_EN 1491 492#define AR_NUM_DCU 10493#define AR_DCU_0 0x0001494#define AR_DCU_1 0x0002495#define AR_DCU_2 0x0004496#define AR_DCU_3 0x0008497#define AR_DCU_4 0x0010498#define AR_DCU_5 0x0020499#define AR_DCU_6 0x0040500#define AR_DCU_7 0x0080501#define AR_DCU_8 0x0100502#define AR_DCU_9 0x0200503 504#define AR_D0_QCUMASK 0x1000505#define AR_D1_QCUMASK 0x1004506#define AR_D2_QCUMASK 0x1008507#define AR_D3_QCUMASK 0x100c508#define AR_D4_QCUMASK 0x1010509#define AR_D5_QCUMASK 0x1014510#define AR_D6_QCUMASK 0x1018511#define AR_D7_QCUMASK 0x101c512#define AR_D8_QCUMASK 0x1020513#define AR_D9_QCUMASK 0x1024514#define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2))515#define AR_D_QCUMASK 0x000003FF516#define AR_D_QCUMASK_RESV0 0xFFFFFC00517 518#define AR_D0_LCL_IFS 0x1040519#define AR_D1_LCL_IFS 0x1044520#define AR_D2_LCL_IFS 0x1048521#define AR_D3_LCL_IFS 0x104c522#define AR_D4_LCL_IFS 0x1050523#define AR_D5_LCL_IFS 0x1054524#define AR_D6_LCL_IFS 0x1058525#define AR_D7_LCL_IFS 0x105c526#define AR_D8_LCL_IFS 0x1060527#define AR_D9_LCL_IFS 0x1064528#define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2))529#define AR_D_LCL_IFS_CWMIN 0x000003FF530#define AR_D_LCL_IFS_CWMIN_S 0531#define AR_D_LCL_IFS_CWMAX 0x000FFC00532#define AR_D_LCL_IFS_CWMAX_S 10533#define AR_D_LCL_IFS_AIFS 0x0FF00000534#define AR_D_LCL_IFS_AIFS_S 20535 536#define AR_D_LCL_IFS_RESV0 0xF0000000537 538#define AR_D0_RETRY_LIMIT 0x1080539#define AR_D1_RETRY_LIMIT 0x1084540#define AR_D2_RETRY_LIMIT 0x1088541#define AR_D3_RETRY_LIMIT 0x108c542#define AR_D4_RETRY_LIMIT 0x1090543#define AR_D5_RETRY_LIMIT 0x1094544#define AR_D6_RETRY_LIMIT 0x1098545#define AR_D7_RETRY_LIMIT 0x109c546#define AR_D8_RETRY_LIMIT 0x10a0547#define AR_D9_RETRY_LIMIT 0x10a4548#define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2))549#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F550#define AR_D_RETRY_LIMIT_FR_SH_S 0551#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00552#define AR_D_RETRY_LIMIT_STA_SH_S 8553#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000554#define AR_D_RETRY_LIMIT_STA_LG_S 14555#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000556 557#define AR_D0_CHNTIME 0x10c0558#define AR_D1_CHNTIME 0x10c4559#define AR_D2_CHNTIME 0x10c8560#define AR_D3_CHNTIME 0x10cc561#define AR_D4_CHNTIME 0x10d0562#define AR_D5_CHNTIME 0x10d4563#define AR_D6_CHNTIME 0x10d8564#define AR_D7_CHNTIME 0x10dc565#define AR_D8_CHNTIME 0x10e0566#define AR_D9_CHNTIME 0x10e4567#define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2))568#define AR_D_CHNTIME_DUR 0x000FFFFF569#define AR_D_CHNTIME_DUR_S 0570#define AR_D_CHNTIME_EN 0x00100000571#define AR_D_CHNTIME_RESV0 0xFFE00000572 573#define AR_D0_MISC 0x1100574#define AR_D1_MISC 0x1104575#define AR_D2_MISC 0x1108576#define AR_D3_MISC 0x110c577#define AR_D4_MISC 0x1110578#define AR_D5_MISC 0x1114579#define AR_D6_MISC 0x1118580#define AR_D7_MISC 0x111c581#define AR_D8_MISC 0x1120582#define AR_D9_MISC 0x1124583#define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2))584#define AR_D_MISC_BKOFF_THRESH 0x0000003F585#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040586#define AR_D_MISC_CW_RESET_EN 0x00000080587#define AR_D_MISC_FRAG_WAIT_EN 0x00000100588#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200589#define AR_D_MISC_CW_BKOFF_EN 0x00001000590#define AR_D_MISC_VIR_COL_HANDLING 0x0000C000591#define AR_D_MISC_VIR_COL_HANDLING_S 14592#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0593#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1594#define AR_D_MISC_BEACON_USE 0x00010000595#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000596#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17597#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0598#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1599#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2600#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000601#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000602#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000603#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000604#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000605#define AR_D_MISC_RESV0 0xFF000000606 607#define AR_D_SEQNUM 0x1140608 609#define AR_D_GBL_IFS_SIFS 0x1030610#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF611#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF612 613#define AR_D_TXBLK_BASE 0x1038614#define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF615#define AR_D_TXBLK_WRITE_BITMASK_S 0616#define AR_D_TXBLK_WRITE_SLICE 0x000F0000617#define AR_D_TXBLK_WRITE_SLICE_S 16618#define AR_D_TXBLK_WRITE_DCU 0x00F00000619#define AR_D_TXBLK_WRITE_DCU_S 20620#define AR_D_TXBLK_WRITE_COMMAND 0x0F000000621#define AR_D_TXBLK_WRITE_COMMAND_S 24622 623#define AR_D_GBL_IFS_SLOT 0x1070624#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF625#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000626 627#define AR_D_GBL_IFS_EIFS 0x10b0628#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF629#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000630#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO 363631 632#define AR_D_GBL_IFS_MISC 0x10f0633#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007634#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008635#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00636#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000637#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000638#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000639#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000640#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000641 642#define AR_D_FPCTL 0x1230643#define AR_D_FPCTL_DCU 0x0000000F644#define AR_D_FPCTL_DCU_S 0645#define AR_D_FPCTL_PREFETCH_EN 0x00000010646#define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0647#define AR_D_FPCTL_BURST_PREFETCH_S 5648 649#define AR_D_TXPSE 0x1270650#define AR_D_TXPSE_CTRL 0x000003FF651#define AR_D_TXPSE_RESV0 0x0000FC00652#define AR_D_TXPSE_STATUS 0x00010000653#define AR_D_TXPSE_RESV1 0xFFFE0000654 655#define AR_D_TXSLOTMASK 0x12f0656#define AR_D_TXSLOTMASK_NUM 0x0000000F657 658#define AR_CFG_LED 0x1f04659#define AR_CFG_SCLK_RATE_IND 0x00000003660#define AR_CFG_SCLK_RATE_IND_S 0661#define AR_CFG_SCLK_32MHZ 0x00000000662#define AR_CFG_SCLK_4MHZ 0x00000001663#define AR_CFG_SCLK_1MHZ 0x00000002664#define AR_CFG_SCLK_32KHZ 0x00000003665#define AR_CFG_LED_BLINK_SLOW 0x00000008666#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070667#define AR_CFG_LED_MODE_SEL 0x00000380668#define AR_CFG_LED_MODE_SEL_S 7669#define AR_CFG_LED_POWER 0x00000280670#define AR_CFG_LED_POWER_S 7671#define AR_CFG_LED_NETWORK 0x00000300672#define AR_CFG_LED_NETWORK_S 7673#define AR_CFG_LED_MODE_PROP 0x0674#define AR_CFG_LED_MODE_RPROP 0x1675#define AR_CFG_LED_MODE_SPLIT 0x2676#define AR_CFG_LED_MODE_RAND 0x3677#define AR_CFG_LED_MODE_POWER_OFF 0x4678#define AR_CFG_LED_MODE_POWER_ON 0x5679#define AR_CFG_LED_MODE_NETWORK_OFF 0x4680#define AR_CFG_LED_MODE_NETWORK_ON 0x6681#define AR_CFG_LED_ASSOC_CTL 0x00000c00682#define AR_CFG_LED_ASSOC_CTL_S 10683#define AR_CFG_LED_ASSOC_NONE 0x0684#define AR_CFG_LED_ASSOC_ACTIVE 0x1685#define AR_CFG_LED_ASSOC_PENDING 0x2686 687#define AR_CFG_LED_BLINK_SLOW 0x00000008688#define AR_CFG_LED_BLINK_SLOW_S 3689 690#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070691#define AR_CFG_LED_BLINK_THRESH_SEL_S 4692 693#define AR_MAC_SLEEP 0x1f00694#define AR_MAC_SLEEP_MAC_AWAKE 0x00000000695#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001696 697#define AR_RC 0x4000698#define AR_RC_AHB 0x00000001699#define AR_RC_APB 0x00000002700#define AR_RC_HOSTIF 0x00000100701 702#define AR_WA(_ah) (AR_SREV_9340(_ah) ? 0x40c4 : 0x4004)703#define AR_WA_BIT6 (1 << 6)704#define AR_WA_BIT7 (1 << 7)705#define AR_WA_BIT23 (1 << 23)706#define AR_WA_D3_L1_DISABLE (1 << 14)707#define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset708 to POR (power-on-reset) */709#define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16)710#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17)711#define AR_WA_RESET_EN (1 << 18) /* Enable PCI-Reset to712 POR (bit 15) */713#define AR_WA_ANALOG_SHIFT (1 << 20)714#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */715#define AR_WA_BIT22 (1 << 22)716#define AR9285_WA_DEFAULT 0x004a050b717#define AR9280_WA_DEFAULT 0x0040073b718#define AR_WA_DEFAULT 0x0000073f719 720 721#define AR_PM_STATE 0x4008722#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000723 724#define AR_HOST_TIMEOUT(_ah) (AR_SREV_9340(_ah) ? 0x4008 : 0x4018)725#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF726#define AR_HOST_TIMEOUT_APB_CNTR_S 0727#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000728#define AR_HOST_TIMEOUT_LCL_CNTR_S 16729 730#define AR_EEPROM 0x401c731#define AR_EEPROM_ABSENT 0x00000100732#define AR_EEPROM_CORRUPT 0x00000200733#define AR_EEPROM_PROT_MASK 0x03FFFC00734#define AR_EEPROM_PROT_MASK_S 10735 736#define EEPROM_PROTECT_RP_0_31 0x0001737#define EEPROM_PROTECT_WP_0_31 0x0002738#define EEPROM_PROTECT_RP_32_63 0x0004739#define EEPROM_PROTECT_WP_32_63 0x0008740#define EEPROM_PROTECT_RP_64_127 0x0010741#define EEPROM_PROTECT_WP_64_127 0x0020742#define EEPROM_PROTECT_RP_128_191 0x0040743#define EEPROM_PROTECT_WP_128_191 0x0080744#define EEPROM_PROTECT_RP_192_255 0x0100745#define EEPROM_PROTECT_WP_192_255 0x0200746#define EEPROM_PROTECT_RP_256_511 0x0400747#define EEPROM_PROTECT_WP_256_511 0x0800748#define EEPROM_PROTECT_RP_512_1023 0x1000749#define EEPROM_PROTECT_WP_512_1023 0x2000750#define EEPROM_PROTECT_RP_1024_2047 0x4000751#define EEPROM_PROTECT_WP_1024_2047 0x8000752 753#define AR_SREV(_ah) \754 ((AR_SREV_9100(_ah)) ? 0x0600 : (AR_SREV_9340(_ah) \755 ? 0x400c : 0x4020))756 757#define AR_SREV_ID(_ah) \758 ((AR_SREV_9100(_ah)) ? 0x00000FFF : 0x000000FF)759#define AR_SREV_VERSION 0x000000F0760#define AR_SREV_VERSION_S 4761#define AR_SREV_REVISION 0x00000007762 763#define AR_SREV_ID2 0xFFFFFFFF764#define AR_SREV_VERSION2 0xFFFC0000765#define AR_SREV_VERSION2_S 18766#define AR_SREV_TYPE2 0x0003F000767#define AR_SREV_TYPE2_S 12768#define AR_SREV_TYPE2_CHAIN 0x00001000769#define AR_SREV_TYPE2_HOST_MODE 0x00002000770#define AR_SREV_REVISION2 0x00000F00771#define AR_SREV_REVISION2_S 8772 773#define AR_SREV_VERSION_5416_PCI 0xD774#define AR_SREV_VERSION_5416_PCIE 0xC775#define AR_SREV_REVISION_5416_10 0776#define AR_SREV_REVISION_5416_20 1777#define AR_SREV_REVISION_5416_22 2778#define AR_SREV_VERSION_9100 0x14779#define AR_SREV_VERSION_9160 0x40780#define AR_SREV_REVISION_9160_10 0781#define AR_SREV_REVISION_9160_11 1782#define AR_SREV_VERSION_9280 0x80783#define AR_SREV_REVISION_9280_10 0784#define AR_SREV_REVISION_9280_20 1785#define AR_SREV_REVISION_9280_21 2786#define AR_SREV_VERSION_9285 0xC0787#define AR_SREV_REVISION_9285_10 0788#define AR_SREV_REVISION_9285_11 1789#define AR_SREV_REVISION_9285_12 2790#define AR_SREV_VERSION_9287 0x180791#define AR_SREV_REVISION_9287_10 0792#define AR_SREV_REVISION_9287_11 1793#define AR_SREV_REVISION_9287_12 2794#define AR_SREV_REVISION_9287_13 3795#define AR_SREV_VERSION_9271 0x140796#define AR_SREV_REVISION_9271_10 0797#define AR_SREV_REVISION_9271_11 1798#define AR_SREV_VERSION_9300 0x1c0799#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */800#define AR_SREV_REVISION_9300_22 3801#define AR_SREV_VERSION_9330 0x200802#define AR_SREV_REVISION_9330_10 0803#define AR_SREV_REVISION_9330_11 1804#define AR_SREV_REVISION_9330_12 2805#define AR_SREV_VERSION_9485 0x240806#define AR_SREV_REVISION_9485_10 0807#define AR_SREV_REVISION_9485_11 1808#define AR_SREV_VERSION_9340 0x300809#define AR_SREV_REVISION_9340_10 0810#define AR_SREV_REVISION_9340_11 1811#define AR_SREV_REVISION_9340_12 2812#define AR_SREV_REVISION_9340_13 3813#define AR_SREV_VERSION_9580 0x1C0814#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */815#define AR_SREV_VERSION_9462 0x280816#define AR_SREV_REVISION_9462_20 2817#define AR_SREV_REVISION_9462_21 3818#define AR_SREV_VERSION_9565 0x2C0819#define AR_SREV_REVISION_9565_10 0820#define AR_SREV_REVISION_9565_101 1821#define AR_SREV_REVISION_9565_11 2822#define AR_SREV_VERSION_9550 0x400823#define AR_SREV_VERSION_9531 0x500824#define AR_SREV_REVISION_9531_10 0825#define AR_SREV_REVISION_9531_11 1826#define AR_SREV_REVISION_9531_20 2827#define AR_SREV_VERSION_9561 0x600828 829#define AR_SREV_5416(_ah) \830 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \831 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))832#define AR_SREV_5416_22_OR_LATER(_ah) \833 (((AR_SREV_5416(_ah)) && \834 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \835 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))836 837#define AR_SREV_9100(_ah) \838 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9100))839#define AR_SREV_9100_OR_LATER(_ah) \840 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))841 842#define AR_SREV_9160(_ah) \843 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160))844#define AR_SREV_9160_10_OR_LATER(_ah) \845 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160))846#define AR_SREV_9160_11(_ah) \847 (AR_SREV_9160(_ah) && \848 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))849#define AR_SREV_9280(_ah) \850 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))851#define AR_SREV_9280_20_OR_LATER(_ah) \852 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))853#define AR_SREV_9280_20(_ah) \854 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))855 856#define AR_SREV_9285(_ah) \857 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))858#define AR_SREV_9285_12_OR_LATER(_ah) \859 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))860 861#define AR_SREV_9287(_ah) \862 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))863#define AR_SREV_9287_11_OR_LATER(_ah) \864 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))865#define AR_SREV_9287_11(_ah) \866 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \867 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))868#define AR_SREV_9287_12(_ah) \869 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \870 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))871#define AR_SREV_9287_12_OR_LATER(_ah) \872 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \873 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \874 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))875#define AR_SREV_9287_13_OR_LATER(_ah) \876 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \877 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \878 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))879 880#define AR_SREV_9271(_ah) \881 (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)882#define AR_SREV_9271_10(_ah) \883 (AR_SREV_9271(_ah) && \884 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10))885#define AR_SREV_9271_11(_ah) \886 (AR_SREV_9271(_ah) && \887 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))888 889#define AR_SREV_9300(_ah) \890 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))891#define AR_SREV_9300_20_OR_LATER(_ah) \892 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)893#define AR_SREV_9300_22(_ah) \894 (AR_SREV_9300((_ah)) && \895 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_22))896 897#define AR_SREV_9330(_ah) \898 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))899#define AR_SREV_9330_11(_ah) \900 (AR_SREV_9330((_ah)) && \901 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))902#define AR_SREV_9330_12(_ah) \903 (AR_SREV_9330((_ah)) && \904 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_12))905 906#ifdef CONFIG_ATH9K_PCOEM907#define AR_SREV_9462(_ah) \908 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462))909#define AR_SREV_9485(_ah) \910 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))911#define AR_SREV_9565(_ah) \912 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))913#define AR_SREV_9003_PCOEM(_ah) \914 (AR_SREV_9462(_ah) || AR_SREV_9485(_ah) || AR_SREV_9565(_ah))915#else916#define AR_SREV_9462(_ah) 0917#define AR_SREV_9485(_ah) 0918#define AR_SREV_9565(_ah) 0919#define AR_SREV_9003_PCOEM(_ah) 0920#endif921 922#define AR_SREV_9485_11_OR_LATER(_ah) \923 (AR_SREV_9485(_ah) && \924 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9485_11))925#define AR_SREV_9485_OR_LATER(_ah) \926 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))927 928#define AR_SREV_9340(_ah) \929 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))930 931#define AR_SREV_9340_13(_ah) \932 (AR_SREV_9340((_ah)) && \933 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9340_13))934 935#define AR_SREV_9340_13_OR_LATER(_ah) \936 (AR_SREV_9340((_ah)) && \937 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))938 939#define AR_SREV_9285E_20(_ah) \940 (AR_SREV_9285_12_OR_LATER(_ah) && \941 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))942 943#define AR_SREV_9462_20(_ah) \944 (AR_SREV_9462(_ah) && \945 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_20))946#define AR_SREV_9462_21(_ah) \947 (AR_SREV_9462(_ah) && \948 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_21))949#define AR_SREV_9462_20_OR_LATER(_ah) \950 (AR_SREV_9462(_ah) && \951 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))952#define AR_SREV_9462_21_OR_LATER(_ah) \953 (AR_SREV_9462(_ah) && \954 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_21))955 956#define AR_SREV_9565_10(_ah) \957 (AR_SREV_9565(_ah) && \958 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))959#define AR_SREV_9565_101(_ah) \960 (AR_SREV_9565(_ah) && \961 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101))962#define AR_SREV_9565_11(_ah) \963 (AR_SREV_9565(_ah) && \964 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11))965#define AR_SREV_9565_11_OR_LATER(_ah) \966 (AR_SREV_9565(_ah) && \967 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11))968 969#define AR_SREV_9550(_ah) \970 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))971#define AR_SREV_9550_OR_LATER(_ah) \972 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9550))973 974#define AR_SREV_9580(_ah) \975 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \976 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10))977#define AR_SREV_9580_10(_ah) \978 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \979 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9580_10))980 981#define AR_SREV_9531(_ah) \982 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531))983#define AR_SREV_9531_10(_ah) \984 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \985 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_10))986#define AR_SREV_9531_11(_ah) \987 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \988 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_11))989#define AR_SREV_9531_20(_ah) \990 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \991 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_20))992 993#define AR_SREV_9561(_ah) \994 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9561))995 996#define AR_SREV_SOC(_ah) \997 (AR_SREV_9340(_ah) || AR_SREV_9531(_ah) || AR_SREV_9550(_ah) || \998 AR_SREV_9561(_ah))999 1000/* NOTE: When adding chips newer than Peacock, add chip check here */1001#define AR_SREV_9580_10_OR_LATER(_ah) \1002 (AR_SREV_9580(_ah))1003 1004enum ath_usb_dev {1005 AR9280_USB = 1, /* AR7010 + AR9280, UB94 */1006 AR9287_USB = 2, /* AR7010 + AR9287, UB95 */1007 STORAGE_DEVICE = 3,1008};1009 1010#define AR_DEVID_7010(_ah) \1011 (((_ah)->hw_version.usbdev == AR9280_USB) || \1012 ((_ah)->hw_version.usbdev == AR9287_USB))1013 1014#define AR_RADIO_SREV_MAJOR 0xf01015#define AR_RAD5133_SREV_MAJOR 0xc01016#define AR_RAD2133_SREV_MAJOR 0xd01017#define AR_RAD5122_SREV_MAJOR 0xe01018#define AR_RAD2122_SREV_MAJOR 0xf01019 1020#define AR_AHB_MODE 0x40241021#define AR_AHB_EXACT_WR_EN 0x000000001022#define AR_AHB_BUF_WR_EN 0x000000011023#define AR_AHB_EXACT_RD_EN 0x000000001024#define AR_AHB_CACHELINE_RD_EN 0x000000021025#define AR_AHB_PREFETCH_RD_EN 0x000000041026#define AR_AHB_PAGE_SIZE_1K 0x000000001027#define AR_AHB_PAGE_SIZE_2K 0x000000081028#define AR_AHB_PAGE_SIZE_4K 0x000000101029#define AR_AHB_CUSTOM_BURST_EN 0x000000C01030#define AR_AHB_CUSTOM_BURST_EN_S 61031#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 31032 1033#define AR_INTR_RTC_IRQ 0x000000011034#define AR_INTR_MAC_IRQ 0x000000021035#define AR_INTR_EEP_PROT_ACCESS 0x000000041036#define AR_INTR_MAC_AWAKE 0x000200001037#define AR_INTR_MAC_ASLEEP 0x000400001038#define AR_INTR_SPURIOUS 0xFFFFFFFF1039 1040 1041#define AR_INTR_SYNC_CAUSE(_ah) (AR_SREV_9340(_ah) ? 0x4010 : 0x4028)1042#define AR_INTR_SYNC_CAUSE_CLR(_ah) (AR_SREV_9340(_ah) ? 0x4010 : 0x4028)1043 1044 1045#define AR_INTR_SYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4014 : 0x402c)1046#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC00001047#define AR_INTR_SYNC_ENABLE_GPIO_S 181048 1049enum {1050 AR_INTR_SYNC_RTC_IRQ = 0x00000001,1051 AR_INTR_SYNC_MAC_IRQ = 0x00000002,1052 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,1053 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008,1054 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,1055 AR_INTR_SYNC_HOST1_FATAL = 0x00000020,1056 AR_INTR_SYNC_HOST1_PERR = 0x00000040,1057 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,1058 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100,1059 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,1060 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400,1061 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,1062 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,1063 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,1064 AR_INTR_SYNC_PM_ACCESS = 0x00004000,1065 AR_INTR_SYNC_MAC_AWAKE = 0x00008000,1066 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000,1067 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,1068 AR_INTR_SYNC_ALL = 0x0003FFFF,1069 1070 1071 AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL |1072 AR_INTR_SYNC_HOST1_PERR |1073 AR_INTR_SYNC_RADM_CPL_EP |1074 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT |1075 AR_INTR_SYNC_RADM_CPL_TLP_ABORT |1076 AR_INTR_SYNC_RADM_CPL_ECRC_ERR |1077 AR_INTR_SYNC_RADM_CPL_TIMEOUT |1078 AR_INTR_SYNC_LOCAL_TIMEOUT |1079 AR_INTR_SYNC_MAC_SLEEP_ACCESS),1080 1081 AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010,1082 1083 AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,1084 1085};1086 1087#define AR_INTR_ASYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x4018 : 0x4030)1088#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC00001089#define AR_INTR_ASYNC_MASK_GPIO_S 181090#define AR_INTR_ASYNC_MASK_MCI 0x000000801091#define AR_INTR_ASYNC_MASK_MCI_S 71092 1093#define AR_INTR_SYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x401c : 0x4034)1094#define AR_INTR_SYNC_MASK_GPIO 0xFFFC00001095#define AR_INTR_SYNC_MASK_GPIO_S 181096 1097#define AR_INTR_ASYNC_CAUSE_CLR(_ah) (AR_SREV_9340(_ah) ? 0x4020 : 0x4038)1098#define AR_INTR_ASYNC_CAUSE(_ah) (AR_SREV_9340(_ah) ? 0x4020 : 0x4038)1099#define AR_INTR_ASYNC_CAUSE_MCI 0x000000801100#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | \1101 AR_INTR_ASYNC_CAUSE_MCI)1102 1103/* Asynchronous Interrupt Enable Register */1104#define AR_INTR_ASYNC_ENABLE_MCI 0x000000801105#define AR_INTR_ASYNC_ENABLE_MCI_S 71106 1107 1108#define AR_INTR_ASYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4024 : 0x403c)1109#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC00001110#define AR_INTR_ASYNC_ENABLE_GPIO_S 181111 1112#define AR_PCIE_SERDES 0x40401113#define AR_PCIE_SERDES2 0x40441114#define AR_PCIE_PM_CTRL(_ah) (AR_SREV_9340(_ah) ? 0x4004 : 0x4014)1115#define AR_PCIE_PM_CTRL_ENA 0x000800001116 1117#define AR_PCIE_PHY_REG3 0x18c081118 1119/* Define correct GPIO numbers and MASK bits to indicate the WMAC1120 * GPIO resource.1121 * Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs1122 * which rely on gpiolib framework. But restrict SOC AR9330 only to1123 * access WMAC GPIO which has the same design with the old chips.1124 */1125#define AR_NUM_GPIO 141126#define AR9280_NUM_GPIO 101127#define AR9285_NUM_GPIO 121128#define AR9287_NUM_GPIO 101129#define AR9271_NUM_GPIO 161130#define AR9300_NUM_GPIO 161131#define AR9330_NUM_GPIO 161132#define AR9340_NUM_GPIO 231133#define AR9462_NUM_GPIO 141134#define AR9485_NUM_GPIO 121135#define AR9531_NUM_GPIO 181136#define AR9550_NUM_GPIO 241137#define AR9561_NUM_GPIO 231138#define AR9565_NUM_GPIO 141139#define AR9580_NUM_GPIO 161140#define AR7010_NUM_GPIO 161141 1142#define AR_GPIO_MASK 0x00003FFF1143#define AR9271_GPIO_MASK 0x0000FFFF1144#define AR9280_GPIO_MASK 0x000003FF1145#define AR9285_GPIO_MASK 0x00000FFF1146#define AR9287_GPIO_MASK 0x000003FF1147#define AR9300_GPIO_MASK 0x0000F4FF1148#define AR9330_GPIO_MASK 0x0000F4FF1149#define AR9340_GPIO_MASK 0x0000000F1150#define AR9462_GPIO_MASK 0x00003FFF1151#define AR9485_GPIO_MASK 0x00000FFF1152#define AR9531_GPIO_MASK 0x0000000F1153#define AR9550_GPIO_MASK 0x0000000F1154#define AR9561_GPIO_MASK 0x0000000F1155#define AR9565_GPIO_MASK 0x00003FFF1156#define AR9580_GPIO_MASK 0x0000F4FF1157#define AR7010_GPIO_MASK 0x0000FFFF1158 1159#define AR_GPIO_IN_OUT(_ah) (AR_SREV_9340(_ah) ? 0x4028 : 0x4048)1160#define AR_GPIO_IN_VAL 0x0FFFC0001161#define AR_GPIO_IN_VAL_S 141162#define AR928X_GPIO_IN_VAL 0x000FFC001163#define AR928X_GPIO_IN_VAL_S 101164#define AR9285_GPIO_IN_VAL 0x00FFF0001165#define AR9285_GPIO_IN_VAL_S 121166#define AR9287_GPIO_IN_VAL 0x003FF8001167#define AR9287_GPIO_IN_VAL_S 111168#define AR9271_GPIO_IN_VAL 0xFFFF00001169#define AR9271_GPIO_IN_VAL_S 161170#define AR7010_GPIO_IN_VAL 0x0000FFFF1171#define AR7010_GPIO_IN_VAL_S 01172 1173#define AR_GPIO_IN(_ah) (AR_SREV_9340(_ah) ? 0x402c : 0x404c)1174#define AR9300_GPIO_IN_VAL 0x0001FFFF1175#define AR9300_GPIO_IN_VAL_S 01176 1177#define AR_GPIO_OE_OUT(_ah) (AR_SREV_9340(_ah) ? 0x4030 : \1178 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4050 : 0x404c))1179#define AR_GPIO_OE_OUT_DRV 0x31180#define AR_GPIO_OE_OUT_DRV_NO 0x01181#define AR_GPIO_OE_OUT_DRV_LOW 0x11182#define AR_GPIO_OE_OUT_DRV_HI 0x21183#define AR_GPIO_OE_OUT_DRV_ALL 0x31184 1185#define AR7010_GPIO_OE 0x520001186#define AR7010_GPIO_OE_MASK 0x11187#define AR7010_GPIO_OE_AS_OUTPUT 0x01188#define AR7010_GPIO_OE_AS_INPUT 0x11189#define AR7010_GPIO_IN 0x520041190#define AR7010_GPIO_OUT 0x520081191#define AR7010_GPIO_SET 0x5200C1192#define AR7010_GPIO_CLEAR 0x520101193#define AR7010_GPIO_INT 0x520141194#define AR7010_GPIO_INT_TYPE 0x520181195#define AR7010_GPIO_INT_POLARITY 0x5201C1196#define AR7010_GPIO_PENDING 0x520201197#define AR7010_GPIO_INT_MASK 0x520241198#define AR7010_GPIO_FUNCTION 0x520281199 1200#define AR_GPIO_INTR_POL(_ah) (AR_SREV_9340(_ah) ? 0x4038 : \1201 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4058 : 0x4050))1202#define AR_GPIO_INTR_POL_VAL 0x0001FFFF1203#define AR_GPIO_INTR_POL_VAL_S 01204 1205#define AR_GPIO_INPUT_EN_VAL(_ah) (AR_SREV_9340(_ah) ? 0x403c : \1206 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x405c : 0x4054))1207#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x000000041208#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 21209#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x000000081210#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 31211#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x000000101212#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 41213#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x000000801214#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 71215#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x000004001216#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 101217#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x000010001218#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 121219#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x000080001220#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 151221#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x000100001222#define AR_GPIO_JTAG_DISABLE 0x000200001223 1224#define AR_GPIO_INPUT_MUX1(_ah) (AR_SREV_9340(_ah) ? 0x4040 : \1225 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4060 : 0x4058))1226#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f00001227#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 161228#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f001229#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 81230 1231#define AR_GPIO_INPUT_MUX2(_ah) (AR_SREV_9340(_ah) ? 0x4044 : \1232 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4064 : 0x405c))1233#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f1234#define AR_GPIO_INPUT_MUX2_CLK25_S 01235#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f01236#define AR_GPIO_INPUT_MUX2_RFSILENT_S 41237#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f001238#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 81239 1240#define AR_GPIO_OUTPUT_MUX1(_ah) (AR_SREV_9340(_ah) ? 0x4048 : \1241 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4068 : 0x4060))1242#define AR_GPIO_OUTPUT_MUX2(_ah) (AR_SREV_9340(_ah) ? 0x404c : \1243 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x406c : 0x4064))1244#define AR_GPIO_OUTPUT_MUX3(_ah) (AR_SREV_9340(_ah) ? 0x4050 : \1245 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4070 : 0x4068))1246 1247#define AR_INPUT_STATE(_ah) (AR_SREV_9340(_ah) ? 0x4054 : \1248 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4074 : 0x406c))1249 1250#define AR_EEPROM_STATUS_DATA(_ah) (AR_SREV_9340(_ah) ? 0x40c8 : \1251 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4084 : 0x407c))1252#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff1253#define AR_EEPROM_STATUS_DATA_VAL_S 01254#define AR_EEPROM_STATUS_DATA_BUSY 0x000100001255#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x000200001256#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x000400001257#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x000800001258 1259#define AR_OBS(_ah) (AR_SREV_9340(_ah) ? 0x405c : \1260 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4088 : 0x4080))1261 1262#define AR_GPIO_PDPU(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4090 : 0x4088)1263 1264#define AR_PCIE_MSI(_ah) (AR_SREV_9340(_ah) ? 0x40d8 : \1265 (AR_SREV_9300_20_OR_LATER(_ah) ? 0x40a4 : 0x4094))1266#define AR_PCIE_MSI_ENABLE 0x000000011267#define AR_PCIE_MSI_HW_DBI_WR_EN 0x020000001268#define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF /* bits 8..11: value must be 0x5060 */1269#define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF /* bits 8..11: value must be 0x5064 */1270 1271#define AR_INTR_PRIO_TX 0x000000011272#define AR_INTR_PRIO_RXLP 0x000000021273#define AR_INTR_PRIO_RXHP 0x000000041274 1275#define AR_INTR_PRIO_SYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4088 : 0x40c4)1276#define AR_INTR_PRIO_ASYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x408c : 0x40c8)1277#define AR_INTR_PRIO_SYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x4090 : 0x40cc)1278#define AR_INTR_PRIO_ASYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4094 : 0x40d4)1279#define AR_ENT_OTP 0x40d81280#define AR_ENT_OTP_CHAIN2_DISABLE 0x000200001281#define AR_ENT_OTP_49GHZ_DISABLE 0x001000001282#define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x008000001283 1284#define AR_CH0_BB_DPLL1 0x161801285#define AR_CH0_BB_DPLL1_REFDIV 0xF80000001286#define AR_CH0_BB_DPLL1_REFDIV_S 271287#define AR_CH0_BB_DPLL1_NINI 0x07FC00001288#define AR_CH0_BB_DPLL1_NINI_S 181289#define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF1290#define AR_CH0_BB_DPLL1_NFRAC_S 01291 1292#define AR_CH0_BB_DPLL2 0x161841293#define AR_CH0_BB_DPLL2_LOCAL_PLL 0x400000001294#define AR_CH0_BB_DPLL2_LOCAL_PLL_S 301295#define AR_CH0_DPLL2_KI 0x3C0000001296#define AR_CH0_DPLL2_KI_S 261297#define AR_CH0_DPLL2_KD 0x03F800001298#define AR_CH0_DPLL2_KD_S 191299#define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x000400001300#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 181301#define AR_CH0_BB_DPLL2_PLL_PWD 0x000100001302#define AR_CH0_BB_DPLL2_PLL_PWD_S 161303#define AR_CH0_BB_DPLL2_OUTDIV 0x0000E0001304#define AR_CH0_BB_DPLL2_OUTDIV_S 131305 1306#define AR_CH0_BB_DPLL3 0x161881307#define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F8000001308#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 231309 1310#define AR_CH0_DDR_DPLL2 0x162441311#define AR_CH0_DDR_DPLL3 0x162481312#define AR_CH0_DPLL3_PHASE_SHIFT 0x3F8000001313#define AR_CH0_DPLL3_PHASE_SHIFT_S 231314#define AR_PHY_CCA_NOM_VAL_2GHZ -1181315 1316#define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f1317#define AR_RTC_9300_SOC_PLL_DIV_INT_S 01318#define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc01319#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 61320#define AR_RTC_9300_SOC_PLL_REFDIV 0x01f000001321#define AR_RTC_9300_SOC_PLL_REFDIV_S 201322#define AR_RTC_9300_SOC_PLL_CLKSEL 0x060000001323#define AR_RTC_9300_SOC_PLL_CLKSEL_S 251324#define AR_RTC_9300_SOC_PLL_BYPASS 0x080000001325 1326#define AR_RTC_9300_PLL_DIV 0x000003ff1327#define AR_RTC_9300_PLL_DIV_S 01328#define AR_RTC_9300_PLL_REFDIV 0x00003C001329#define AR_RTC_9300_PLL_REFDIV_S 101330#define AR_RTC_9300_PLL_CLKSEL 0x0000C0001331#define AR_RTC_9300_PLL_CLKSEL_S 141332#define AR_RTC_9300_PLL_BYPASS 0x000100001333 1334#define AR_RTC_9160_PLL_DIV 0x000003ff1335#define AR_RTC_9160_PLL_DIV_S 01336#define AR_RTC_9160_PLL_REFDIV 0x00003C001337#define AR_RTC_9160_PLL_REFDIV_S 101338#define AR_RTC_9160_PLL_CLKSEL 0x0000C0001339#define AR_RTC_9160_PLL_CLKSEL_S 141340 1341#define AR_RTC_BASE 0x000200001342#define AR_RTC_RC(_ah) \1343 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)1344#define AR_RTC_RC_M 0x000000031345#define AR_RTC_RC_MAC_WARM 0x000000011346#define AR_RTC_RC_MAC_COLD 0x000000021347#define AR_RTC_RC_COLD_RESET 0x000000041348#define AR_RTC_RC_WARM_RESET 0x000000081349 1350/* Crystal Control */1351#define AR_RTC_XTAL_CONTROL 0x70041352 1353/* Reg Control 0 */1354#define AR_RTC_REG_CONTROL0 0x70081355 1356/* Reg Control 1 */1357#define AR_RTC_REG_CONTROL1 0x700c1358#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x000000011359 1360#define AR_RTC_PLL_CONTROL(_ah) \1361 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)1362 1363#define AR_RTC_PLL_CONTROL2 0x703c1364 1365#define AR_RTC_PLL_DIV 0x0000001f1366#define AR_RTC_PLL_DIV_S 01367#define AR_RTC_PLL_DIV2 0x000000201368#define AR_RTC_PLL_REFDIV_5 0x000000c01369#define AR_RTC_PLL_CLKSEL 0x000003001370#define AR_RTC_PLL_CLKSEL_S 81371#define AR_RTC_PLL_BYPASS 0x000100001372#define AR_RTC_PLL_NOPWD 0x000400001373#define AR_RTC_PLL_NOPWD_S 181374 1375#define PLL3 0x161881376#define PLL3_DO_MEAS_MASK 0x400000001377#define PLL4 0x1618c1378#define PLL4_MEAS_DONE 0x81379#define SQSUM_DVC_MASK 0x007ffff81380 1381#define AR_RTC_RESET(_ah) \1382 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)1383#define AR_RTC_RESET_EN (0x00000001)1384 1385#define AR_RTC_STATUS(_ah) \1386 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)1387 1388#define AR_RTC_STATUS_M(_ah) \1389 ((AR_SREV_9100(_ah)) ? 0x0000003f : 0x0000000f)1390 1391#define AR_RTC_PM_STATUS_M 0x0000000f1392 1393#define AR_RTC_STATUS_SHUTDOWN 0x000000011394#define AR_RTC_STATUS_ON 0x000000021395#define AR_RTC_STATUS_SLEEP 0x000000041396#define AR_RTC_STATUS_WAKEUP 0x000000081397 1398#define AR_RTC_SLEEP_CLK(_ah) \1399 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)1400#define AR_RTC_FORCE_DERIVED_CLK 0x21401#define AR_RTC_FORCE_SWREG_PRD 0x000000041402 1403#define AR_RTC_FORCE_WAKE(_ah) \1404 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)1405#define AR_RTC_FORCE_WAKE_EN 0x000000011406#define AR_RTC_FORCE_WAKE_ON_INT 0x000000021407 1408 1409#define AR_RTC_INTR_CAUSE(_ah) \1410 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)1411 1412#define AR_RTC_INTR_ENABLE(_ah) \1413 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)1414 1415#define AR_RTC_INTR_MASK(_ah) \1416 ((AR_SREV_9100(_ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)1417 1418#define AR_RTC_KEEP_AWAKE 0x70341419 1420/* RTC_DERIVED_* - only for AR9100 */1421 1422#define AR_RTC_DERIVED_CLK(_ah) \1423 (AR_SREV_9100(_ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)1424#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe1425#define AR_RTC_DERIVED_CLK_PERIOD_S 11426 1427#define AR_SEQ_MASK 0x80601428 1429#define AR_AN_RF2G1_CH0 0x78101430#define AR_AN_RF2G1_CH0_OB 0x038000001431#define AR_AN_RF2G1_CH0_OB_S 231432#define AR_AN_RF2G1_CH0_DB 0x1C0000001433#define AR_AN_RF2G1_CH0_DB_S 261434 1435#define AR_AN_RF5G1_CH0 0x78181436#define AR_AN_RF5G1_CH0_OB5 0x000700001437#define AR_AN_RF5G1_CH0_OB5_S 161438#define AR_AN_RF5G1_CH0_DB5 0x003800001439#define AR_AN_RF5G1_CH0_DB5_S 191440 1441#define AR_AN_RF2G1_CH1 0x78341442#define AR_AN_RF2G1_CH1_OB 0x038000001443#define AR_AN_RF2G1_CH1_OB_S 231444#define AR_AN_RF2G1_CH1_DB 0x1C0000001445#define AR_AN_RF2G1_CH1_DB_S 261446 1447#define AR_AN_RF5G1_CH1 0x783C1448#define AR_AN_RF5G1_CH1_OB5 0x000700001449#define AR_AN_RF5G1_CH1_OB5_S 161450#define AR_AN_RF5G1_CH1_DB5 0x003800001451#define AR_AN_RF5G1_CH1_DB5_S 191452 1453#define AR_AN_TOP1 0x78901454#define AR_AN_TOP1_DACIPMODE 0x000400001455#define AR_AN_TOP1_DACIPMODE_S 181456 1457#define AR_AN_TOP2 0x78941458#define AR_AN_TOP2_XPABIAS_LVL 0xC00000001459#define AR_AN_TOP2_XPABIAS_LVL_S 301460#define AR_AN_TOP2_LOCALBIAS 0x002000001461#define AR_AN_TOP2_LOCALBIAS_S 211462#define AR_AN_TOP2_PWDCLKIND 0x004000001463#define AR_AN_TOP2_PWDCLKIND_S 221464 1465#define AR_AN_SYNTH9 0x78681466#define AR_AN_SYNTH9_REFDIVA 0xf80000001467#define AR_AN_SYNTH9_REFDIVA_S 271468 1469#define AR9285_AN_RF2G1 0x78201470#define AR9285_AN_RF2G1_ENPACAL 0x000008001471#define AR9285_AN_RF2G1_ENPACAL_S 111472#define AR9285_AN_RF2G1_PDPADRV1 0x020000001473#define AR9285_AN_RF2G1_PDPADRV1_S 251474#define AR9285_AN_RF2G1_PDPADRV2 0x010000001475#define AR9285_AN_RF2G1_PDPADRV2_S 241476#define AR9285_AN_RF2G1_PDPAOUT 0x008000001477#define AR9285_AN_RF2G1_PDPAOUT_S 231478 1479 1480#define AR9285_AN_RF2G2 0x78241481#define AR9285_AN_RF2G2_OFFCAL 0x000010001482#define AR9285_AN_RF2G2_OFFCAL_S 121483 1484#define AR9285_AN_RF2G3 0x78281485#define AR9285_AN_RF2G3_PDVCCOMP 0x020000001486#define AR9285_AN_RF2G3_PDVCCOMP_S 251487#define AR9285_AN_RF2G3_OB_0 0x00E000001488#define AR9285_AN_RF2G3_OB_0_S 211489#define AR9285_AN_RF2G3_OB_1 0x001C00001490#define AR9285_AN_RF2G3_OB_1_S 181491#define AR9285_AN_RF2G3_OB_2 0x000380001492#define AR9285_AN_RF2G3_OB_2_S 151493#define AR9285_AN_RF2G3_OB_3 0x000070001494#define AR9285_AN_RF2G3_OB_3_S 121495#define AR9285_AN_RF2G3_OB_4 0x00000E001496#define AR9285_AN_RF2G3_OB_4_S 91497 1498#define AR9285_AN_RF2G3_DB1_0 0x000001C01499#define AR9285_AN_RF2G3_DB1_0_S 61500#define AR9285_AN_RF2G3_DB1_1 0x000000381501#define AR9285_AN_RF2G3_DB1_1_S 31502#define AR9285_AN_RF2G3_DB1_2 0x000000071503#define AR9285_AN_RF2G3_DB1_2_S 01504#define AR9285_AN_RF2G4 0x782C1505#define AR9285_AN_RF2G4_DB1_3 0xE00000001506#define AR9285_AN_RF2G4_DB1_3_S 291507#define AR9285_AN_RF2G4_DB1_4 0x1C0000001508#define AR9285_AN_RF2G4_DB1_4_S 261509 1510#define AR9285_AN_RF2G4_DB2_0 0x038000001511#define AR9285_AN_RF2G4_DB2_0_S 231512#define AR9285_AN_RF2G4_DB2_1 0x007000001513#define AR9285_AN_RF2G4_DB2_1_S 201514#define AR9285_AN_RF2G4_DB2_2 0x000E00001515#define AR9285_AN_RF2G4_DB2_2_S 171516#define AR9285_AN_RF2G4_DB2_3 0x0001C0001517#define AR9285_AN_RF2G4_DB2_3_S 141518#define AR9285_AN_RF2G4_DB2_4 0x000038001519#define AR9285_AN_RF2G4_DB2_4_S 111520 1521#define AR9285_RF2G5 0x78301522#define AR9285_RF2G5_IC50TX 0xfffff8ff1523#define AR9285_RF2G5_IC50TX_SET 0x000004001524#define AR9285_RF2G5_IC50TX_XE_SET 0x000005001525#define AR9285_RF2G5_IC50TX_CLEAR 0x000007001526#define AR9285_RF2G5_IC50TX_CLEAR_S 81527 1528/* AR9271 : 0x7828, 0x782c different setting from AR9285 */1529#define AR9271_AN_RF2G3_OB_cck 0x001C00001530#define AR9271_AN_RF2G3_OB_cck_S 181531#define AR9271_AN_RF2G3_OB_psk 0x000380001532#define AR9271_AN_RF2G3_OB_psk_S 151533#define AR9271_AN_RF2G3_OB_qam 0x000070001534#define AR9271_AN_RF2G3_OB_qam_S 121535 1536#define AR9271_AN_RF2G3_DB_1 0x00E000001537#define AR9271_AN_RF2G3_DB_1_S 211538 1539#define AR9271_AN_RF2G3_CCOMP 0xFFF1540#define AR9271_AN_RF2G3_CCOMP_S 01541 1542#define AR9271_AN_RF2G4_DB_2 0xE00000001543#define AR9271_AN_RF2G4_DB_2_S 291544 1545#define AR9285_AN_RF2G6 0x78341546#define AR9285_AN_RF2G6_CCOMP 0x000078001547#define AR9285_AN_RF2G6_CCOMP_S 111548#define AR9285_AN_RF2G6_OFFS 0x03f000001549#define AR9285_AN_RF2G6_OFFS_S 201550 1551#define AR9271_AN_RF2G6_OFFS 0x07f000001552#define AR9271_AN_RF2G6_OFFS_S 201553 1554#define AR9285_AN_RF2G7 0x78381555#define AR9285_AN_RF2G7_PWDDB 0x000000021556#define AR9285_AN_RF2G7_PWDDB_S 11557#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE00000001558#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 291559 1560#define AR9285_AN_RF2G8 0x783C1561#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C0001562#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 141563 1564 1565#define AR9285_AN_RF2G9 0x78401566#define AR9285_AN_RXTXBB1 0x78541567#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x000000201568#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 51569#define AR9285_AN_RXTXBB1_PDV2I 0x000000801570#define AR9285_AN_RXTXBB1_PDV2I_S 71571#define AR9285_AN_RXTXBB1_PDDACIF 0x000001001572#define AR9285_AN_RXTXBB1_PDDACIF_S 81573#define AR9285_AN_RXTXBB1_SPARE9 0x000000011574#define AR9285_AN_RXTXBB1_SPARE9_S 01575 1576#define AR9285_AN_TOP2 0x78681577 1578#define AR9285_AN_TOP3 0x786c1579#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C1580#define AR9285_AN_TOP3_XPABIAS_LVL_S 21581#define AR9285_AN_TOP3_PWDDAC 0x008000001582#define AR9285_AN_TOP3_PWDDAC_S 231583 1584#define AR9285_AN_TOP4 0x78701585#define AR9285_AN_TOP4_DEFAULT 0x10142c001586 1587#define AR9287_AN_RF2G3_CH0 0x78081588#define AR9287_AN_RF2G3_CH1 0x785c1589#define AR9287_AN_RF2G3_DB1 0xE00000001590#define AR9287_AN_RF2G3_DB1_S 291591#define AR9287_AN_RF2G3_DB2 0x1C0000001592#define AR9287_AN_RF2G3_DB2_S 261593#define AR9287_AN_RF2G3_OB_CCK 0x038000001594#define AR9287_AN_RF2G3_OB_CCK_S 231595#define AR9287_AN_RF2G3_OB_PSK 0x007000001596#define AR9287_AN_RF2G3_OB_PSK_S 201597#define AR9287_AN_RF2G3_OB_QAM 0x000E00001598#define AR9287_AN_RF2G3_OB_QAM_S 171599#define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C0001600#define AR9287_AN_RF2G3_OB_PAL_OFF_S 141601 1602#define AR9287_AN_TXPC0 0x78981603#define AR9287_AN_TXPC0_TXPCMODE 0x0000C0001604#define AR9287_AN_TXPC0_TXPCMODE_S 141605#define AR9287_AN_TXPC0_TXPCMODE_NORMAL 01606#define AR9287_AN_TXPC0_TXPCMODE_TEST 11607#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 21608#define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 31609 1610#define AR9287_AN_TOP2 0x78b41611#define AR9287_AN_TOP2_XPABIAS_LVL 0xC00000001612#define AR9287_AN_TOP2_XPABIAS_LVL_S 301613 1614/* AR9271 specific stuff */1615#define AR9271_RESET_POWER_DOWN_CONTROL 0x500441616#define AR9271_RADIO_RF_RST 0x201617#define AR9271_GATE_MAC_CTL 0x40001618 1619#define AR_STA_ID1_STA_AP 0x000100001620#define AR_STA_ID1_ADHOC 0x000200001621#define AR_STA_ID1_PWR_SAV 0x000400001622#define AR_STA_ID1_KSRCHDIS 0x000800001623#define AR_STA_ID1_PCF 0x001000001624#define AR_STA_ID1_USE_DEFANT 0x002000001625#define AR_STA_ID1_DEFANT_UPDATE 0x004000001626#define AR_STA_ID1_AR9100_BA_FIX 0x004000001627#define AR_STA_ID1_RTS_USE_DEF 0x008000001628#define AR_STA_ID1_ACKCTS_6MB 0x010000001629#define AR_STA_ID1_BASE_RATE_11B 0x020000001630#define AR_STA_ID1_SECTOR_SELF_GEN 0x040000001631#define AR_STA_ID1_CRPT_MIC_ENABLE 0x080000001632#define AR_STA_ID1_KSRCH_MODE 0x100000001633#define AR_STA_ID1_PRESERVE_SEQNUM 0x200000001634#define AR_STA_ID1_CBCIV_ENDIAN 0x400000001635#define AR_STA_ID1_MCAST_KSRCH 0x800000001636 1637#define AR_BSS_ID0 0x80081638#define AR_BSS_ID1 0x800C1639#define AR_BSS_ID1_U16 0x0000FFFF1640#define AR_BSS_ID1_AID 0x07FF00001641#define AR_BSS_ID1_AID_S 161642 1643#define AR_BCN_RSSI_AVE 0x80101644#define AR_BCN_RSSI_AVE_MASK 0x00000FFF1645 1646#define AR_TIME_OUT 0x80141647#define AR_TIME_OUT_ACK 0x00003FFF1648#define AR_TIME_OUT_ACK_S 01649#define AR_TIME_OUT_CTS 0x3FFF00001650#define AR_TIME_OUT_CTS_S 161651 1652#define AR_RSSI_THR 0x80181653#define AR_RSSI_THR_MASK 0x000000FF1654#define AR_RSSI_THR_BM_THR 0x0000FF001655#define AR_RSSI_THR_BM_THR_S 81656#define AR_RSSI_BCN_WEIGHT 0x1F0000001657#define AR_RSSI_BCN_WEIGHT_S 241658#define AR_RSSI_BCN_RSSI_RST 0x200000001659 1660#define AR_USEC 0x801c1661#define AR_USEC_USEC 0x0000007F1662#define AR_USEC_TX_LAT 0x007FC0001663#define AR_USEC_TX_LAT_S 141664#define AR_USEC_RX_LAT 0x1F8000001665#define AR_USEC_RX_LAT_S 231666#define AR_USEC_ASYNC_FIFO 0x12E000741667 1668#define AR_RESET_TSF 0x80201669#define AR_RESET_TSF_ONCE 0x010000001670#define AR_RESET_TSF2_ONCE 0x020000001671 1672#define AR_MAX_CFP_DUR 0x80381673#define AR_CFP_VAL 0x0000FFFF1674 1675#define AR_RX_FILTER 0x803C1676 1677#define AR_MCAST_FIL0 0x80401678#define AR_MCAST_FIL1 0x80441679 1680/*1681 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes.1682 *1683 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with1684 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down1685 * receive. The force RX abort bit will kill any frame which is currently being1686 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS)1687 * will prevent any new frames from getting started.1688 */1689#define AR_DIAG_SW 0x80481690#define AR_DIAG_CACHE_ACK 0x000000011691#define AR_DIAG_ACK_DIS 0x000000021692#define AR_DIAG_CTS_DIS 0x000000041693#define AR_DIAG_ENCRYPT_DIS 0x000000081694#define AR_DIAG_DECRYPT_DIS 0x000000101695#define AR_DIAG_RX_DIS 0x00000020 /* RX block */1696#define AR_DIAG_LOOP_BACK 0x000000401697#define AR_DIAG_CORR_FCS 0x000000801698#define AR_DIAG_CHAN_INFO 0x000001001699#define AR_DIAG_SCRAM_SEED 0x0001FE001700#define AR_DIAG_SCRAM_SEED_S 81701#define AR_DIAG_FRAME_NV0 0x000200001702#define AR_DIAG_OBS_PT_SEL1 0x000C00001703#define AR_DIAG_OBS_PT_SEL1_S 181704#define AR_DIAG_OBS_PT_SEL2 0x080000001705#define AR_DIAG_OBS_PT_SEL2_S 271706#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */1707#define AR_DIAG_IGNORE_VIRT_CS 0x002000001708#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x004000001709#define AR_DIAG_EIFS_CTRL_ENA 0x008000001710#define AR_DIAG_DUAL_CHAIN_INFO 0x010000001711#define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */1712#define AR_DIAG_SATURATE_CYCLE_CNT 0x040000001713#define AR_DIAG_OBS_PT_SEL2 0x080000001714#define AR_DIAG_RX_CLEAR_CTL_LOW 0x100000001715#define AR_DIAG_RX_CLEAR_EXT_LOW 0x200000001716 1717#define AR_TSF_L32 0x804c1718#define AR_TSF_U32 0x80501719 1720#define AR_TST_ADDAC 0x80541721#define AR_DEF_ANTENNA 0x80581722 1723#define AR_AES_MUTE_MASK0 0x805c1724#define AR_AES_MUTE_MASK0_FC 0x0000FFFF1725#define AR_AES_MUTE_MASK0_QOS 0xFFFF00001726#define AR_AES_MUTE_MASK0_QOS_S 161727 1728#define AR_AES_MUTE_MASK1 0x80601729#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF1730#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF00001731#define AR_AES_MUTE_MASK1_FC_MGMT_S 161732 1733#define AR_GATED_CLKS 0x80641734#define AR_GATED_CLKS_TX 0x000000021735#define AR_GATED_CLKS_RX 0x000000041736#define AR_GATED_CLKS_REG 0x000000081737 1738#define AR_OBS_BUS_CTRL 0x80681739#define AR_OBS_BUS_SEL_1 0x000400001740#define AR_OBS_BUS_SEL_2 0x000800001741#define AR_OBS_BUS_SEL_3 0x000C00001742#define AR_OBS_BUS_SEL_4 0x080400001743#define AR_OBS_BUS_SEL_5 0x080800001744 1745#define AR_OBS_BUS_1 0x806c1746#define AR_OBS_BUS_1_PCU 0x000000011747#define AR_OBS_BUS_1_RX_END 0x000000021748#define AR_OBS_BUS_1_RX_WEP 0x000000041749#define AR_OBS_BUS_1_RX_BEACON 0x000000081750#define AR_OBS_BUS_1_RX_FILTER 0x000000101751#define AR_OBS_BUS_1_TX_HCF 0x000000201752#define AR_OBS_BUS_1_QUIET_TIME 0x000000401753#define AR_OBS_BUS_1_CHAN_IDLE 0x000000801754#define AR_OBS_BUS_1_TX_HOLD 0x000001001755#define AR_OBS_BUS_1_TX_FRAME 0x000002001756#define AR_OBS_BUS_1_RX_FRAME 0x000004001757#define AR_OBS_BUS_1_RX_CLEAR 0x000008001758#define AR_OBS_BUS_1_WEP_STATE 0x0003F0001759#define AR_OBS_BUS_1_WEP_STATE_S 121760#define AR_OBS_BUS_1_RX_STATE 0x01F000001761#define AR_OBS_BUS_1_RX_STATE_S 201762#define AR_OBS_BUS_1_TX_STATE 0x7E0000001763#define AR_OBS_BUS_1_TX_STATE_S 251764 1765#define AR_LAST_TSTP 0x80801766#define AR_NAV 0x80841767#define AR_RTS_OK 0x80881768#define AR_RTS_FAIL 0x808c1769#define AR_ACK_FAIL 0x80901770#define AR_FCS_FAIL 0x80941771#define AR_BEACON_CNT 0x80981772 1773#define AR_SLEEP1 0x80d41774#define AR_SLEEP1_ASSUME_DTIM 0x000800001775#define AR_SLEEP1_CAB_TIMEOUT 0xFFE000001776#define AR_SLEEP1_CAB_TIMEOUT_S 211777 1778#define AR_SLEEP2 0x80d81779#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE000001780#define AR_SLEEP2_BEACON_TIMEOUT_S 211781 1782#define AR_TPC 0x80e81783#define AR_TPC_ACK 0x0000003f1784#define AR_TPC_ACK_S 01785#define AR_TPC_CTS 0x00003f001786#define AR_TPC_CTS_S 81787#define AR_TPC_CHIRP 0x003f00001788#define AR_TPC_CHIRP_S 161789#define AR_TPC_RPT 0x3f0000001790#define AR_TPC_RPT_S 241791 1792#define AR_QUIET1 0x80fc1793#define AR_QUIET1_NEXT_QUIET_S 01794#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff1795#define AR_QUIET1_QUIET_ENABLE 0x000100001796#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x000200001797#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 171798#define AR_QUIET2 0x81001799#define AR_QUIET2_QUIET_PERIOD_S 01800#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff1801#define AR_QUIET2_QUIET_DUR_S 161802#define AR_QUIET2_QUIET_DUR 0xffff00001803 1804#define AR_TSF_PARM 0x81041805#define AR_TSF_INCREMENT_M 0x000000ff1806#define AR_TSF_INCREMENT_S 0x001807 1808#define AR_QOS_NO_ACK 0x81081809#define AR_QOS_NO_ACK_TWO_BIT 0x0000000f1810#define AR_QOS_NO_ACK_TWO_BIT_S 01811#define AR_QOS_NO_ACK_BIT_OFF 0x000000701812#define AR_QOS_NO_ACK_BIT_OFF_S 41813#define AR_QOS_NO_ACK_BYTE_OFF 0x000001801814#define AR_QOS_NO_ACK_BYTE_OFF_S 71815 1816#define AR_PHY_ERR 0x810c1817 1818#define AR_PHY_ERR_DCHIRP 0x000000081819#define AR_PHY_ERR_RADAR 0x000000201820#define AR_PHY_ERR_OFDM_TIMING 0x000200001821#define AR_PHY_ERR_CCK_TIMING 0x020000001822 1823#define AR_RXFIFO_CFG 0x81141824 1825 1826#define AR_MIC_QOS_CONTROL 0x81181827#define AR_MIC_QOS_SELECT 0x811c1828 1829#define AR_PCU_MISC 0x81201830#define AR_PCU_FORCE_BSSID_MATCH 0x000000011831#define AR_PCU_MIC_NEW_LOC_ENA 0x000000041832#define AR_PCU_TX_ADD_TSF 0x000000081833#define AR_PCU_CCK_SIFS_MODE 0x000000101834#define AR_PCU_RX_ANT_UPDT 0x000008001835#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x000010001836#define AR_PCU_MISS_BCN_IN_SLEEP 0x000040001837#define AR_PCU_BUG_12306_FIX_ENA 0x000200001838#define AR_PCU_FORCE_QUIET_COLL 0x000400001839#define AR_PCU_TBTT_PROTECT 0x002000001840#define AR_PCU_CLEAR_VMF 0x010000001841#define AR_PCU_CLEAR_BA_VALID 0x040000001842#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x100000001843 1844#define AR_PCU_BT_ANT_PREVENT_RX 0x001000001845#define AR_PCU_BT_ANT_PREVENT_RX_S 201846 1847#define AR_FILT_OFDM 0x81241848#define AR_FILT_OFDM_COUNT 0x00FFFFFF1849 1850#define AR_FILT_CCK 0x81281851#define AR_FILT_CCK_COUNT 0x00FFFFFF1852 1853#define AR_PHY_ERR_1 0x812c1854#define AR_PHY_ERR_1_COUNT 0x00FFFFFF1855#define AR_PHY_ERR_MASK_1 0x81301856 1857#define AR_PHY_ERR_2 0x81341858#define AR_PHY_ERR_2_COUNT 0x00FFFFFF1859#define AR_PHY_ERR_MASK_2 0x81381860 1861#define AR_PHY_COUNTMAX (3 << 22)1862#define AR_MIBCNT_INTRMASK (3 << 22)1863 1864#define AR_TSFOOR_THRESHOLD 0x813c1865#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF1866 1867#define AR_PHY_ERR_EIFS_MASK 0x81441868 1869#define AR_PHY_ERR_3 0x81681870#define AR_PHY_ERR_3_COUNT 0x00FFFFFF1871#define AR_PHY_ERR_MASK_3 0x816c1872 1873#define AR_BT_COEX_MODE 0x81701874#define AR_BT_TIME_EXTEND 0x000000ff1875#define AR_BT_TIME_EXTEND_S 01876#define AR_BT_TXSTATE_EXTEND 0x000001001877#define AR_BT_TXSTATE_EXTEND_S 81878#define AR_BT_TX_FRAME_EXTEND 0x000002001879#define AR_BT_TX_FRAME_EXTEND_S 91880#define AR_BT_MODE 0x00000c001881#define AR_BT_MODE_S 101882#define AR_BT_QUIET 0x000010001883#define AR_BT_QUIET_S 121884#define AR_BT_QCU_THRESH 0x0001e0001885#define AR_BT_QCU_THRESH_S 131886#define AR_BT_RX_CLEAR_POLARITY 0x000200001887#define AR_BT_RX_CLEAR_POLARITY_S 171888#define AR_BT_PRIORITY_TIME 0x00fc00001889#define AR_BT_PRIORITY_TIME_S 181890#define AR_BT_FIRST_SLOT_TIME 0xff0000001891#define AR_BT_FIRST_SLOT_TIME_S 241892 1893#define AR_BT_COEX_WEIGHT 0x81741894#define AR_BT_COEX_WGHT 0xff551895#define AR_STOMP_ALL_WLAN_WGHT 0xfcfc1896#define AR_STOMP_LOW_WLAN_WGHT 0xa8a81897#define AR_STOMP_NONE_WLAN_WGHT 0x00001898#define AR_BTCOEX_BT_WGHT 0x0000ffff1899#define AR_BTCOEX_BT_WGHT_S 01900#define AR_BTCOEX_WL_WGHT 0xffff00001901#define AR_BTCOEX_WL_WGHT_S 161902 1903#define AR_BT_COEX_WL_WEIGHTS0 0x81741904#define AR_BT_COEX_WL_WEIGHTS1 0x81c41905#define AR_MCI_COEX_WL_WEIGHTS(_i) (0x18b0 + (_i << 2))1906#define AR_BT_COEX_BT_WEIGHTS(_i) (0x83ac + (_i << 2))1907 1908#define AR9300_BT_WGHT 0xcccc44441909 1910#define AR_BT_COEX_MODE2 0x817c1911#define AR_BT_BCN_MISS_THRESH 0x000000ff1912#define AR_BT_BCN_MISS_THRESH_S 01913#define AR_BT_BCN_MISS_CNT 0x0000ff001914#define AR_BT_BCN_MISS_CNT_S 81915#define AR_BT_HOLD_RX_CLEAR 0x000100001916#define AR_BT_HOLD_RX_CLEAR_S 161917#define AR_BT_PROTECT_BT_AFTER_WAKEUP 0x000800001918#define AR_BT_PROTECT_BT_AFTER_WAKEUP_S 191919#define AR_BT_DISABLE_BT_ANT 0x001000001920#define AR_BT_DISABLE_BT_ANT_S 201921#define AR_BT_QUIET_2_WIRE 0x002000001922#define AR_BT_QUIET_2_WIRE_S 211923#define AR_BT_WL_ACTIVE_MODE 0x00c000001924#define AR_BT_WL_ACTIVE_MODE_S 221925#define AR_BT_WL_TXRX_SEPARATE 0x010000001926#define AR_BT_WL_TXRX_SEPARATE_S 241927#define AR_BT_RS_DISCARD_EXTEND 0x020000001928#define AR_BT_RS_DISCARD_EXTEND_S 251929#define AR_BT_TSF_BT_ACTIVE_CTRL 0x0c0000001930#define AR_BT_TSF_BT_ACTIVE_CTRL_S 261931#define AR_BT_TSF_BT_PRIORITY_CTRL 0x300000001932#define AR_BT_TSF_BT_PRIORITY_CTRL_S 281933#define AR_BT_INTERRUPT_ENABLE 0x400000001934#define AR_BT_INTERRUPT_ENABLE_S 301935#define AR_BT_PHY_ERR_BT_COLL_ENABLE 0x800000001936#define AR_BT_PHY_ERR_BT_COLL_ENABLE_S 311937 1938#define AR_TXSIFS 0x81d01939#define AR_TXSIFS_TIME 0x000000FF1940#define AR_TXSIFS_TX_LATENCY 0x00000F001941#define AR_TXSIFS_TX_LATENCY_S 81942#define AR_TXSIFS_ACK_SHIFT 0x000070001943#define AR_TXSIFS_ACK_SHIFT_S 121944 1945#define AR_BT_COEX_MODE3 0x81d41946#define AR_BT_WL_ACTIVE_TIME 0x000000ff1947#define AR_BT_WL_ACTIVE_TIME_S 01948#define AR_BT_WL_QC_TIME 0x0000ff001949#define AR_BT_WL_QC_TIME_S 81950#define AR_BT_ALLOW_CONCURRENT_ACCESS 0x000f00001951#define AR_BT_ALLOW_CONCURRENT_ACCESS_S 161952#define AR_BT_AGC_SATURATION_CNT_ENABLE 0x001000001953#define AR_BT_AGC_SATURATION_CNT_ENABLE_S 201954 1955#define AR_TXOP_X 0x81ec1956#define AR_TXOP_X_VAL 0x000000FF1957 1958 1959#define AR_TXOP_0_3 0x81f01960#define AR_TXOP_4_7 0x81f41961#define AR_TXOP_8_11 0x81f81962#define AR_TXOP_12_15 0x81fc1963 1964#define AR_NEXT_NDP2_TIMER 0x81801965#define AR_GEN_TIMER_BANK_1_LEN 81966#define AR_FIRST_NDP_TIMER 71967#define AR_NDP2_PERIOD 0x81a01968#define AR_NDP2_TIMER_MODE 0x81c01969#define AR_GEN_TIMERS2_MODE_ENABLE_MASK 0x000000FF1970 1971#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))1972#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)1973#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1)1974#define AR_NEXT_SWBA AR_GEN_TIMERS(2)1975#define AR_NEXT_CFP AR_GEN_TIMERS(2)1976#define AR_NEXT_HCF AR_GEN_TIMERS(3)1977#define AR_NEXT_TIM AR_GEN_TIMERS(4)1978#define AR_NEXT_DTIM AR_GEN_TIMERS(5)1979#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6)1980#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7)1981 1982#define AR_BEACON_PERIOD AR_GEN_TIMERS(8)1983#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9)1984#define AR_SWBA_PERIOD AR_GEN_TIMERS(10)1985#define AR_HCF_PERIOD AR_GEN_TIMERS(11)1986#define AR_TIM_PERIOD AR_GEN_TIMERS(12)1987#define AR_DTIM_PERIOD AR_GEN_TIMERS(13)1988#define AR_QUIET_PERIOD AR_GEN_TIMERS(14)1989#define AR_NDP_PERIOD AR_GEN_TIMERS(15)1990 1991#define AR_TIMER_MODE 0x82401992#define AR_TBTT_TIMER_EN 0x000000011993#define AR_DBA_TIMER_EN 0x000000021994#define AR_SWBA_TIMER_EN 0x000000041995#define AR_HCF_TIMER_EN 0x000000081996#define AR_TIM_TIMER_EN 0x000000101997#define AR_DTIM_TIMER_EN 0x000000201998#define AR_QUIET_TIMER_EN 0x000000401999#define AR_NDP_TIMER_EN 0x000000802000#define AR_TIMER_OVERFLOW_INDEX 0x000007002001#define AR_TIMER_OVERFLOW_INDEX_S 82002#define AR_TIMER_THRESH 0xFFFFF0002003#define AR_TIMER_THRESH_S 122004 2005#define AR_SLP32_MODE 0x82442006#define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF2007#define AR_SLP32_ENA 0x001000002008#define AR_SLP32_TSF_WRITE_STATUS 0x002000002009 2010#define AR_SLP32_WAKE 0x82482011#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF2012 2013#define AR_SLP32_INC 0x824c2014#define AR_SLP32_TST_INC 0x000FFFFF2015 2016#define AR_SLP_CNT 0x82502017#define AR_SLP_CYCLE_CNT 0x82542018 2019#define AR_SLP_MIB_CTRL 0x82582020#define AR_SLP_MIB_CLEAR 0x000000012021#define AR_SLP_MIB_PENDING 0x000000022022 2023#define AR_MAC_PCU_LOGIC_ANALYZER 0x82642024#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x200000002025 2026 2027#define AR_2040_MODE 0x83182028#define AR_2040_JOINED_RX_CLEAR 0x000000012029 2030 2031#define AR_EXTRCCNT 0x83282032 2033#define AR_SELFGEN_MASK 0x832c2034 2035#define AR_PCU_TXBUF_CTRL 0x83402036#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF2037#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x7002038#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x3802039#define AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE 0x5002040 2041#define AR_PCU_MISC_MODE2 0x83442042#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x000000022043#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x000000042044 2045#define AR_PCU_MISC_MODE2_RESERVED 0x000000382046#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x000000402047#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x000000802048#define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF002049#define AR_PCU_MISC_MODE2_MGMT_QOS_S 82050#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x000100002051#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x000200002052#define AR_PCU_MISC_MODE2_HWWAR1 0x001000002053#define AR_PCU_MISC_MODE2_HWWAR2 0x020000002054#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE00002055 2056#define AR_PCU_MISC_MODE3 0x83d02057 2058#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x83582059#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x000004002060#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x800000002061#define AR_MAC_PCU_GEN_TIMER_TSF_SEL 0x83d82062 2063#define AR_DIRECT_CONNECT 0x83a02064#define AR_DC_AP_STA_EN 0x000000012065#define AR_DC_TSF2_ENABLE 0x000000012066 2067#define AR_AES_MUTE_MASK0 0x805c2068#define AR_AES_MUTE_MASK0_FC 0x0000FFFF2069#define AR_AES_MUTE_MASK0_QOS 0xFFFF00002070#define AR_AES_MUTE_MASK0_QOS_S 162071 2072#define AR_AES_MUTE_MASK1 0x80602073#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF2074#define AR_AES_MUTE_MASK1_SEQ_S 02075#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF00002076#define AR_AES_MUTE_MASK1_FC_MGMT_S 162077 2078#define AR_RATE_DURATION_0 0x87002079#define AR_RATE_DURATION_31 0x87CC2080#define AR_RATE_DURATION_32 0x87802081#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2))2082 2083/* WoW - Wake On Wireless */2084 2085#define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */2086#define AR_PMCTRL_D3COLD_VAUX 0x008000002087#define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW2088 event */2089#define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */2090#define AR_PMCTRL_PWR_STATE_MASK 0x0f000000 /* Power State Mask */2091#define AR_PMCTRL_PWR_STATE_D1D3 0x0f000000 /* Activate D1 and D3 */2092#define AR_PMCTRL_PWR_STATE_D1D3_REAL 0x0f000000 /* Activate D1 and D3 */2093#define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */2094#define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power mgmt */2095 2096#define AR_WOW_BEACON_TIMO_MAX 0xffffffff2097 2098#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */2099#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */2100 2101#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */2102#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search2103 * based on both MAC Address and Key ID.2104 * If bit is 0, then Multicast search is2105 * based on MAC address only.2106 * For Merlin and above only.2107 */2108#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,2109 * when it is enable, AGG_WEP would takes2110 * charge of the encryption interface of2111 * pcu_txsm.2112 */2113 2114#define AR9300_SM_BASE 0xa2002115#define AR9002_PHY_AGC_CONTROL 0x98602116#define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc42117#define AR_PHY_AGC_CONTROL(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)2118#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */2119#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */2120#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */2121#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */2122#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */2123#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */2124#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */2125#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */2126#define AR_PHY_AGC_CONTROL_PKDET_CAL 0x001000002127#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c02128#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 62129 2130#endif2131