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1/*2 * Copyright (c) 2015 Qualcomm Atheros Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef REG_AIC_H18#define REG_AIC_H19 20#define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)21#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)22#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)23#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)24#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)25 26#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)27#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)28#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)29 30#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)31#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)32#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)33 34#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + 0x4c4)35#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + 0x4c8)36#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)37 38#define AR_PHY_AIC_SRAM_ADDR_B0 (AR_SM_BASE + 0x5f0)39#define AR_PHY_AIC_SRAM_DATA_B0 (AR_SM_BASE + 0x5f4)40 41#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)42#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)43 44#define AR_PHY_BT_COEX_4 (AR_AGC_BASE + 0x60)45#define AR_PHY_BT_COEX_5 (AR_AGC_BASE + 0x64)46 47/* AIC fields */48#define AR_PHY_AIC_MON_ENABLE 0x8000000049#define AR_PHY_AIC_MON_ENABLE_S 3150#define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F00000051#define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 2452#define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE000053#define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 1754#define AR_PHY_AIC_F_WLAN 0x0001FC0055#define AR_PHY_AIC_F_WLAN_S 1056#define AR_PHY_AIC_CAL_CH_VALID_RESET 0x0000020057#define AR_PHY_AIC_CAL_CH_VALID_RESET_S 958#define AR_PHY_AIC_CAL_ENABLE 0x0000010059#define AR_PHY_AIC_CAL_ENABLE_S 860#define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE61#define AR_PHY_AIC_BTTX_PWR_THR_S 162#define AR_PHY_AIC_ENABLE 0x0000000163#define AR_PHY_AIC_ENABLE_S 064#define AR_PHY_AIC_CAL_BT_REF_DELAY 0x00F0000065#define AR_PHY_AIC_CAL_BT_REF_DELAY_S 2066#define AR_PHY_AIC_BT_IDLE_CFG 0x0008000067#define AR_PHY_AIC_BT_IDLE_CFG_S 1968#define AR_PHY_AIC_STDBY_COND 0x0006000069#define AR_PHY_AIC_STDBY_COND_S 1770#define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F80071#define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 1172#define AR_PHY_AIC_STDBY_COM_ATT_DB 0x0000070073#define AR_PHY_AIC_STDBY_COM_ATT_DB_S 874#define AR_PHY_AIC_RSSI_MAX 0x000000F075#define AR_PHY_AIC_RSSI_MAX_S 476#define AR_PHY_AIC_RSSI_MIN 0x0000000F77#define AR_PHY_AIC_RSSI_MIN_S 078#define AR_PHY_AIC_RADIO_DELAY 0x7F00000079#define AR_PHY_AIC_RADIO_DELAY_S 2480#define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F0000081#define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 2082#define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F800083#define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 1584#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x0000600085#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 1386#define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C0087#define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 1088#define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x0000020089#define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 990#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x0000010091#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 892#define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF93#define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 094#define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x07F0000095#define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 2096#define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x000FE00097#define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 1398#define AR_PHY_AIC_MON_PWR_EST_LONG 0x0000100099#define AR_PHY_AIC_MON_PWR_EST_LONG_S 12100#define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00000C00101#define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 10102#define AR_PHY_AIC_MON_PERF_THR 0x000003E0103#define AR_PHY_AIC_MON_PERF_THR_S 5104#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018105#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3106#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006107#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1108#define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001109#define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0110#define AR_PHY_AIC_MON_DONE 0x80000000111#define AR_PHY_AIC_MON_DONE_S 31112#define AR_PHY_AIC_MON_ACTIVE 0x40000000113#define AR_PHY_AIC_MON_ACTIVE_S 30114#define AR_PHY_AIC_MEAS_COUNT 0x3F000000115#define AR_PHY_AIC_MEAS_COUNT_S 24116#define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000117#define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18118#define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800119#define AR_PHY_AIC_CAL_HOP_COUNT_S 11120#define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0121#define AR_PHY_AIC_CAL_VALID_COUNT_S 4122#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008123#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3124#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004125#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2126#define AR_PHY_AIC_CAL_DONE 0x00000002127#define AR_PHY_AIC_CAL_DONE_S 1128#define AR_PHY_AIC_CAL_ACTIVE 0x00000001129#define AR_PHY_AIC_CAL_ACTIVE_S 0130 131#define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000132#define AR_PHY_AIC_MEAS_MAG_MIN_S 22133#define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000134#define AR_PHY_AIC_MON_STALE_COUNT_S 15135#define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00136#define AR_PHY_AIC_MON_HOP_COUNT_S 8137#define AR_PHY_AIC_CAL_AIC_SM 0x000000F8138#define AR_PHY_AIC_CAL_AIC_SM_S 3139#define AR_PHY_AIC_SM 0x00000007140#define AR_PHY_AIC_SM_S 0141#define AR_PHY_AIC_SRAM_VALID 0x00000001142#define AR_PHY_AIC_SRAM_VALID_S 0143#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E144#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1145#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080146#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7147#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00148#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8149#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000150#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14151#define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000152#define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15153#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x0000E000154#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 13155#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00001E00156#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 9157#define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING 0x000001F8158#define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING_S 3159#define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF 0x00000006160#define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF_S 1161#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000001162#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 0163 164#endif /* REG_AIC_H */165