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1/*2 * Copyright (c) 2015 Qualcomm Atheros Inc.3 *4 * Permission to use, copy, modify, and/or distribute this software for any5 * purpose with or without fee is hereby granted, provided that the above6 * copyright notice and this permission notice appear in all copies.7 *8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.15 */16 17#ifndef REG_MCI_H18#define REG_MCI_H19 20#define AR_MCI_COMMAND0 0x180021#define AR_MCI_COMMAND0_HEADER 0xFF22#define AR_MCI_COMMAND0_HEADER_S 023#define AR_MCI_COMMAND0_LEN 0x1f0024#define AR_MCI_COMMAND0_LEN_S 825#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x200026#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 1327 28#define AR_MCI_COMMAND1 0x180429 30#define AR_MCI_COMMAND2 0x180831#define AR_MCI_COMMAND2_RESET_TX 0x0132#define AR_MCI_COMMAND2_RESET_TX_S 033#define AR_MCI_COMMAND2_RESET_RX 0x0234#define AR_MCI_COMMAND2_RESET_RX_S 135#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC36#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 237#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x40038#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 1039 40#define AR_MCI_RX_CTRL 0x180c41 42#define AR_MCI_TX_CTRL 0x181043/*44 * 0 = no division,45 * 1 = divide by 2,46 * 2 = divide by 4,47 * 3 = divide by 848 */49#define AR_MCI_TX_CTRL_CLK_DIV 0x0350#define AR_MCI_TX_CTRL_CLK_DIV_S 051#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x0452#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 253#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF854#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 355#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF00000056#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 2457 58#define AR_MCI_MSG_ATTRIBUTES_TABLE 0x181459#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF60#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 061#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF000062#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 1663 64#define AR_MCI_SCHD_TABLE_0 0x181865#define AR_MCI_SCHD_TABLE_1 0x181c66#define AR_MCI_GPM_0 0x182067#define AR_MCI_GPM_1 0x182468#define AR_MCI_GPM_WRITE_PTR 0xFFFF000069#define AR_MCI_GPM_WRITE_PTR_S 1670#define AR_MCI_GPM_BUF_LEN 0x0000FFFF71#define AR_MCI_GPM_BUF_LEN_S 072 73#define AR_MCI_INTERRUPT_RAW 0x182874 75#define AR_MCI_INTERRUPT_EN 0x182c76#define AR_MCI_INTERRUPT_SW_MSG_DONE 0x0000000177#define AR_MCI_INTERRUPT_SW_MSG_DONE_S 078#define AR_MCI_INTERRUPT_CPU_INT_MSG 0x0000000279#define AR_MCI_INTERRUPT_CPU_INT_MSG_S 180#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x0000000481#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 282#define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x0000000883#define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 384#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x0000001085#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 486#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x0000002087#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 588#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x0000008089#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 790#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x0000010091#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 892#define AR_MCI_INTERRUPT_RX_MSG 0x0000020093#define AR_MCI_INTERRUPT_RX_MSG_S 994#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x0000040095#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 1096#define AR_MCI_INTERRUPT_BT_PRI 0x07fff80097#define AR_MCI_INTERRUPT_BT_PRI_S 1198#define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x0800000099#define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27100#define AR_MCI_INTERRUPT_BT_FREQ 0x10000000101#define AR_MCI_INTERRUPT_BT_FREQ_S 28102#define AR_MCI_INTERRUPT_BT_STOMP 0x20000000103#define AR_MCI_INTERRUPT_BT_STOMP_S 29104#define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000105#define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30106#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000107#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31108 109#define AR_MCI_REMOTE_CPU_INT 0x1830110#define AR_MCI_REMOTE_CPU_INT_EN 0x1834111#define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838112#define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c113#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001114#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0115#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002116#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1117#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004118#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2119#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008120#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3121#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010122#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4123#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020124#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5125#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040126#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6127#define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100128#define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8129#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200130#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9131#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400132#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10133#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800134#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11135#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000136#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12137 138#define AR_MCI_CPU_INT 0x1840139 140#define AR_MCI_RX_STATUS 0x1844141#define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00142#define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8143#define AR_MCI_RX_REMOTE_SLEEP 0x00001000144#define AR_MCI_RX_REMOTE_SLEEP_S 12145#define AR_MCI_RX_MCI_CLK_REQ 0x00002000146#define AR_MCI_RX_MCI_CLK_REQ_S 13147 148#define AR_MCI_CONT_STATUS 0x1848149#define AR_MCI_CONT_RSSI_POWER 0x000000FF150#define AR_MCI_CONT_RSSI_POWER_S 0151#define AR_MCI_CONT_PRIORITY 0x0000FF00152#define AR_MCI_CONT_PRIORITY_S 8153#define AR_MCI_CONT_TXRX 0x00010000154#define AR_MCI_CONT_TXRX_S 16155 156#define AR_MCI_BT_PRI0 0x184c157#define AR_MCI_BT_PRI1 0x1850158#define AR_MCI_BT_PRI2 0x1854159#define AR_MCI_BT_PRI3 0x1858160#define AR_MCI_BT_PRI 0x185c161#define AR_MCI_WL_FREQ0 0x1860162#define AR_MCI_WL_FREQ1 0x1864163#define AR_MCI_WL_FREQ2 0x1868164#define AR_MCI_GAIN 0x186c165#define AR_MCI_WBTIMER1 0x1870166#define AR_MCI_WBTIMER2 0x1874167#define AR_MCI_WBTIMER3 0x1878168#define AR_MCI_WBTIMER4 0x187c169#define AR_MCI_MAXGAIN 0x1880170#define AR_MCI_HW_SCHD_TBL_CTL 0x1884171#define AR_MCI_HW_SCHD_TBL_D0 0x1888172#define AR_MCI_HW_SCHD_TBL_D1 0x188c173#define AR_MCI_HW_SCHD_TBL_D2 0x1890174#define AR_MCI_HW_SCHD_TBL_D3 0x1894175#define AR_MCI_TX_PAYLOAD0 0x1898176#define AR_MCI_TX_PAYLOAD1 0x189c177#define AR_MCI_TX_PAYLOAD2 0x18a0178#define AR_MCI_TX_PAYLOAD3 0x18a4179#define AR_BTCOEX_WBTIMER 0x18a8180 181#define AR_BTCOEX_CTRL 0x18ac182#define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001183#define AR_BTCOEX_CTRL_AR9462_MODE_S 0184#define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002185#define AR_BTCOEX_CTRL_WBTIMER_EN_S 1186#define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004187#define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2188#define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008189#define AR_BTCOEX_CTRL_LNA_SHARED_S 3190#define AR_BTCOEX_CTRL_PA_SHARED 0x00000010191#define AR_BTCOEX_CTRL_PA_SHARED_S 4192#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020193#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5194#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040195#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6196#define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180197#define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7198#define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00199#define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9200#define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000201#define AR_BTCOEX_CTRL_AGGR_THRESH_S 12202#define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000203#define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19204#define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000205#define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20206#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000207#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28208#define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000209#define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29210#define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000211#define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30212#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000213#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31214 215#define AR_BTCOEX_WL_WEIGHTS0 0x18b0216#define AR_BTCOEX_WL_WEIGHTS1 0x18b4217#define AR_BTCOEX_WL_WEIGHTS2 0x18b8218#define AR_BTCOEX_WL_WEIGHTS3 0x18bc219 220#define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2))221#define AR_BTCOEX_WL_LNA 0x1940222#define AR_BTCOEX_RFGAIN_CTRL 0x1944223#define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF224#define AR_BTCOEX_WL_LNA_TIMEOUT_S 0225 226#define AR_BTCOEX_CTRL2 0x1948227#define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800228#define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11229#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000230#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19231#define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000232#define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22233#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000234#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23235#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000236#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24237#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000238#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25239 240#define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001241#define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0242#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002243#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1244#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004245#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2246#define AR_GLB_WLAN_UART_INTF_EN 0x00020000247#define AR_GLB_WLAN_UART_INTF_EN_S 17248#define AR_GLB_DS_JTAG_DISABLE 0x00040000249#define AR_GLB_DS_JTAG_DISABLE_S 18250 251#define AR_BTCOEX_RC 0x194c252#define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2))253#define AR_BTCOEX_DBG 0x1a50254#define AR_MCI_LAST_HW_MSG_HDR 0x1a54255#define AR_MCI_LAST_HW_MSG_BDY 0x1a58256 257#define AR_MCI_SCHD_TABLE_2 0x1a5c258#define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001259#define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0260#define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002261#define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1262 263#define AR_BTCOEX_CTRL3 0x1a60264#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff265#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0266 267#define AR_GLB_SWREG_DISCONT_MODE 0x2002c268#define AR_GLB_SWREG_DISCONT_EN_BT_WLAN 0x3269 270#define AR_MCI_MISC 0x1a74271#define AR_MCI_MISC_HW_FIX_EN 0x00000001272#define AR_MCI_MISC_HW_FIX_EN_S 0273 274#define AR_MCI_DBG_CNT_CTRL 0x1a78275#define AR_MCI_DBG_CNT_CTRL_ENABLE 0x00000001276#define AR_MCI_DBG_CNT_CTRL_ENABLE_S 0277#define AR_MCI_DBG_CNT_CTRL_BT_LINKID 0x000007f8278#define AR_MCI_DBG_CNT_CTRL_BT_LINKID_S 3279 280#define MCI_STAT_ALL_BT_LINKID 0xffff281 282#define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \283 AR_MCI_INTERRUPT_RX_INVALID_HDR | \284 AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \285 AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \286 AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \287 AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \288 AR_MCI_INTERRUPT_RX_MSG | \289 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \290 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)291 292#define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \293 AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \294 AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \295 AR_MCI_INTERRUPT_TX_SW_MSG_FAIL)296 297#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \298 AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \299 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \300 AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \301 AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \302 AR_MCI_INTERRUPT_RX_MSG_CONT_RST)303 304#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \305 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | \306 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \307 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING | \308 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)309 310#endif /* REG_MCI_H */311