565 lines · c
1/*2 * Shared Atheros AR9170 Header3 *4 * PHY register map5 *6 * Copyright (c) 2008-2009 Atheros Communications Inc.7 *8 * Permission to use, copy, modify, and/or distribute this software for any9 * purpose with or without fee is hereby granted, provided that the above10 * copyright notice and this permission notice appear in all copies.11 *12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.19 */20 21#ifndef __CARL9170_SHARED_PHY_H22#define __CARL9170_SHARED_PHY_H23 24#define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)25#define AR9170_PHY_REG(_n) (AR9170_PHY_REG_BASE + \26 ((_n) << 2))27 28#define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)29#define AR9170_PHY_TEST_AGC_CLR 0x1000000030#define AR9170_PHY_TEST_RFSILENT_BB 0x0000200031 32#define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)33#define AR9170_PHY_TURBO_FC_TURBO_MODE 0x0000000134#define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x0000000235#define AR9170_PHY_TURBO_FC_DYN2040_EN 0x0000000436#define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x0000000837#define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x0000001038/* For 25 MHz channel spacing -- not used but supported by hw */39#define AR9170_PHY_TURBO_FC_DYN2040_EXT_CH 0x0000002040#define AR9170_PHY_TURBO_FC_HT_EN 0x0000004041#define AR9170_PHY_TURBO_FC_SHORT_GI_40 0x0000008042#define AR9170_PHY_TURBO_FC_WALSH 0x0000010043#define AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 0x0000020044#define AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO 0x0000080045 46#define AR9170_PHY_REG_TEST2 (AR9170_PHY_REG_BASE + 0x0008)47 48#define AR9170_PHY_REG_TIMING2 (AR9170_PHY_REG_BASE + 0x0010)49#define AR9170_PHY_TIMING2_USE_FORCE 0x0000100050#define AR9170_PHY_TIMING2_FORCE 0x00000fff51#define AR9170_PHY_TIMING2_FORCE_S 052 53#define AR9170_PHY_REG_TIMING3 (AR9170_PHY_REG_BASE + 0x0014)54#define AR9170_PHY_TIMING3_DSC_EXP 0x0001e00055#define AR9170_PHY_TIMING3_DSC_EXP_S 1356#define AR9170_PHY_TIMING3_DSC_MAN 0xfffe000057#define AR9170_PHY_TIMING3_DSC_MAN_S 1758 59#define AR9170_PHY_REG_CHIP_ID (AR9170_PHY_REG_BASE + 0x0018)60#define AR9170_PHY_CHIP_ID_REV_0 0x8061#define AR9170_PHY_CHIP_ID_REV_1 0x8162#define AR9170_PHY_CHIP_ID_9160_REV_0 0xb063 64#define AR9170_PHY_REG_ACTIVE (AR9170_PHY_REG_BASE + 0x001c)65#define AR9170_PHY_ACTIVE_EN 0x0000000166#define AR9170_PHY_ACTIVE_DIS 0x0000000067 68#define AR9170_PHY_REG_RF_CTL2 (AR9170_PHY_REG_BASE + 0x0024)69#define AR9170_PHY_RF_CTL2_TX_END_DATA_START 0x000000ff70#define AR9170_PHY_RF_CTL2_TX_END_DATA_START_S 071#define AR9170_PHY_RF_CTL2_TX_END_PA_ON 0x0000ff0072#define AR9170_PHY_RF_CTL2_TX_END_PA_ON_S 873 74#define AR9170_PHY_REG_RF_CTL3 (AR9170_PHY_REG_BASE + 0x0028)75#define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON 0x00ff000076#define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S 1677 78#define AR9170_PHY_REG_ADC_CTL (AR9170_PHY_REG_BASE + 0x002c)79#define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN 0x0000000380#define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S 081#define AR9170_PHY_ADC_CTL_OFF_PWDDAC 0x0000200082#define AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP 0x0000400083#define AR9170_PHY_ADC_CTL_OFF_PWDADC 0x0000800084#define AR9170_PHY_ADC_CTL_ON_INBUFGAIN 0x0003000085#define AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S 1686 87#define AR9170_PHY_REG_ADC_SERIAL_CTL (AR9170_PHY_REG_BASE + 0x0030)88#define AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC 0x0000000089#define AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO 0x0000000190 91#define AR9170_PHY_REG_RF_CTL4 (AR9170_PHY_REG_BASE + 0x0034)92#define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF 0xff00000093#define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S 2494#define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00ff000095#define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S 1696#define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000ff0097#define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S 898#define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000ff99#define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S 0100 101#define AR9170_PHY_REG_TSTDAC_CONST (AR9170_PHY_REG_BASE + 0x003c)102 103#define AR9170_PHY_REG_SETTLING (AR9170_PHY_REG_BASE + 0x0044)104#define AR9170_PHY_SETTLING_SWITCH 0x00003f80105#define AR9170_PHY_SETTLING_SWITCH_S 7106 107#define AR9170_PHY_REG_RXGAIN (AR9170_PHY_REG_BASE + 0x0048)108#define AR9170_PHY_REG_RXGAIN_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2048)109#define AR9170_PHY_RXGAIN_TXRX_ATTEN 0x0003f000110#define AR9170_PHY_RXGAIN_TXRX_ATTEN_S 12111#define AR9170_PHY_RXGAIN_TXRX_RF_MAX 0x007c0000112#define AR9170_PHY_RXGAIN_TXRX_RF_MAX_S 18113 114#define AR9170_PHY_REG_DESIRED_SZ (AR9170_PHY_REG_BASE + 0x0050)115#define AR9170_PHY_DESIRED_SZ_ADC 0x000000ff116#define AR9170_PHY_DESIRED_SZ_ADC_S 0117#define AR9170_PHY_DESIRED_SZ_PGA 0x0000ff00118#define AR9170_PHY_DESIRED_SZ_PGA_S 8119#define AR9170_PHY_DESIRED_SZ_TOT_DES 0x0ff00000120#define AR9170_PHY_DESIRED_SZ_TOT_DES_S 20121 122#define AR9170_PHY_REG_FIND_SIG (AR9170_PHY_REG_BASE + 0x0058)123#define AR9170_PHY_FIND_SIG_FIRSTEP 0x0003f000124#define AR9170_PHY_FIND_SIG_FIRSTEP_S 12125#define AR9170_PHY_FIND_SIG_FIRPWR 0x03fc0000126#define AR9170_PHY_FIND_SIG_FIRPWR_S 18127 128#define AR9170_PHY_REG_AGC_CTL1 (AR9170_PHY_REG_BASE + 0x005c)129#define AR9170_PHY_AGC_CTL1_COARSE_LOW 0x00007f80130#define AR9170_PHY_AGC_CTL1_COARSE_LOW_S 7131#define AR9170_PHY_AGC_CTL1_COARSE_HIGH 0x003f8000132#define AR9170_PHY_AGC_CTL1_COARSE_HIGH_S 15133 134#define AR9170_PHY_REG_AGC_CONTROL (AR9170_PHY_REG_BASE + 0x0060)135#define AR9170_PHY_AGC_CONTROL_CAL 0x00000001136#define AR9170_PHY_AGC_CONTROL_NF 0x00000002137#define AR9170_PHY_AGC_CONTROL_ENABLE_NF 0x00008000138#define AR9170_PHY_AGC_CONTROL_FLTR_CAL 0x00010000139#define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000140 141#define AR9170_PHY_REG_CCA (AR9170_PHY_REG_BASE + 0x0064)142#define AR9170_PHY_CCA_MIN_PWR 0x0ff80000143#define AR9170_PHY_CCA_MIN_PWR_S 19144#define AR9170_PHY_CCA_THRESH62 0x0007f000145#define AR9170_PHY_CCA_THRESH62_S 12146 147#define AR9170_PHY_REG_SFCORR (AR9170_PHY_REG_BASE + 0x0068)148#define AR9170_PHY_SFCORR_M2COUNT_THR 0x0000001f149#define AR9170_PHY_SFCORR_M2COUNT_THR_S 0150#define AR9170_PHY_SFCORR_M1_THRESH 0x00fe0000151#define AR9170_PHY_SFCORR_M1_THRESH_S 17152#define AR9170_PHY_SFCORR_M2_THRESH 0x7f000000153#define AR9170_PHY_SFCORR_M2_THRESH_S 24154 155#define AR9170_PHY_REG_SFCORR_LOW (AR9170_PHY_REG_BASE + 0x006c)156#define AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001157#define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003f00158#define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8159#define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001fc000160#define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14161#define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0fe00000162#define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21163 164#define AR9170_PHY_REG_SLEEP_CTR_CONTROL (AR9170_PHY_REG_BASE + 0x0070)165#define AR9170_PHY_REG_SLEEP_CTR_LIMIT (AR9170_PHY_REG_BASE + 0x0074)166#define AR9170_PHY_REG_SLEEP_SCAL (AR9170_PHY_REG_BASE + 0x0078)167 168#define AR9170_PHY_REG_PLL_CTL (AR9170_PHY_REG_BASE + 0x007c)169#define AR9170_PHY_PLL_CTL_40 0xaa170#define AR9170_PHY_PLL_CTL_40_5413 0x04171#define AR9170_PHY_PLL_CTL_44 0xab172#define AR9170_PHY_PLL_CTL_44_2133 0xeb173#define AR9170_PHY_PLL_CTL_40_2133 0xea174 175#define AR9170_PHY_REG_BIN_MASK_1 (AR9170_PHY_REG_BASE + 0x0100)176#define AR9170_PHY_REG_BIN_MASK_2 (AR9170_PHY_REG_BASE + 0x0104)177#define AR9170_PHY_REG_BIN_MASK_3 (AR9170_PHY_REG_BASE + 0x0108)178#define AR9170_PHY_REG_MASK_CTL (AR9170_PHY_REG_BASE + 0x010c)179 180/* analogue power on time (100ns) */181#define AR9170_PHY_REG_RX_DELAY (AR9170_PHY_REG_BASE + 0x0114)182#define AR9170_PHY_REG_SEARCH_START_DELAY (AR9170_PHY_REG_BASE + 0x0118)183#define AR9170_PHY_RX_DELAY_DELAY 0x00003fff184 185#define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + \186 (0x0120 + ((_i) << 12)))187#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01f188#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0189#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7e0190#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5191#define AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800192#define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xf000193#define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12194#define AR9170_PHY_TIMING_CTRL4_DO_IQCAL 0x10000195#define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000196#define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000197#define AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000198#define AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000199 200#define AR9170_PHY_REG_TIMING5 (AR9170_PHY_REG_BASE + 0x0124)201#define AR9170_PHY_TIMING5_CYCPWR_THR1 0x000000fe202#define AR9170_PHY_TIMING5_CYCPWR_THR1_S 1203 204#define AR9170_PHY_REG_POWER_TX_RATE1 (AR9170_PHY_REG_BASE + 0x0134)205#define AR9170_PHY_REG_POWER_TX_RATE2 (AR9170_PHY_REG_BASE + 0x0138)206#define AR9170_PHY_REG_POWER_TX_RATE_MAX (AR9170_PHY_REG_BASE + 0x013c)207#define AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040208 209#define AR9170_PHY_REG_FRAME_CTL (AR9170_PHY_REG_BASE + 0x0144)210#define AR9170_PHY_FRAME_CTL_TX_CLIP 0x00000038211#define AR9170_PHY_FRAME_CTL_TX_CLIP_S 3212 213#define AR9170_PHY_REG_SPUR_REG (AR9170_PHY_REG_BASE + 0x014c)214#define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL (0xff << 18)215#define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S 18216#define AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000217#define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT (0xff << 9)218#define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S 9219#define AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100220#define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7f221#define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0222 223#define AR9170_PHY_REG_RADAR_EXT (AR9170_PHY_REG_BASE + 0x0140)224#define AR9170_PHY_RADAR_EXT_ENA 0x00004000225 226#define AR9170_PHY_REG_RADAR_0 (AR9170_PHY_REG_BASE + 0x0154)227#define AR9170_PHY_RADAR_0_ENA 0x00000001228#define AR9170_PHY_RADAR_0_FFT_ENA 0x80000000229/* inband pulse threshold */230#define AR9170_PHY_RADAR_0_INBAND 0x0000003e231#define AR9170_PHY_RADAR_0_INBAND_S 1232/* pulse RSSI threshold */233#define AR9170_PHY_RADAR_0_PRSSI 0x00000fc0234#define AR9170_PHY_RADAR_0_PRSSI_S 6235/* pulse height threshold */236#define AR9170_PHY_RADAR_0_HEIGHT 0x0003f000237#define AR9170_PHY_RADAR_0_HEIGHT_S 12238/* radar RSSI threshold */239#define AR9170_PHY_RADAR_0_RRSSI 0x00fc0000240#define AR9170_PHY_RADAR_0_RRSSI_S 18241/* radar firepower threshold */242#define AR9170_PHY_RADAR_0_FIRPWR 0x7f000000243#define AR9170_PHY_RADAR_0_FIRPWR_S 24244 245#define AR9170_PHY_REG_RADAR_1 (AR9170_PHY_REG_BASE + 0x0158)246#define AR9170_PHY_RADAR_1_RELPWR_ENA 0x00800000247#define AR9170_PHY_RADAR_1_USE_FIR128 0x00400000248#define AR9170_PHY_RADAR_1_RELPWR_THRESH 0x003f0000249#define AR9170_PHY_RADAR_1_RELPWR_THRESH_S 16250#define AR9170_PHY_RADAR_1_BLOCK_CHECK 0x00008000251#define AR9170_PHY_RADAR_1_MAX_RRSSI 0x00004000252#define AR9170_PHY_RADAR_1_RELSTEP_CHECK 0x00002000253#define AR9170_PHY_RADAR_1_RELSTEP_THRESH 0x00001f00254#define AR9170_PHY_RADAR_1_RELSTEP_THRESH_S 8255#define AR9170_PHY_RADAR_1_MAXLEN 0x000000ff256#define AR9170_PHY_RADAR_1_MAXLEN_S 0257 258#define AR9170_PHY_REG_SWITCH_CHAIN_0 (AR9170_PHY_REG_BASE + 0x0160)259#define AR9170_PHY_REG_SWITCH_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2160)260 261#define AR9170_PHY_REG_SWITCH_COM (AR9170_PHY_REG_BASE + 0x0164)262 263#define AR9170_PHY_REG_CCA_THRESHOLD (AR9170_PHY_REG_BASE + 0x0168)264 265#define AR9170_PHY_REG_SIGMA_DELTA (AR9170_PHY_REG_BASE + 0x016c)266#define AR9170_PHY_SIGMA_DELTA_ADC_SEL 0x00000003267#define AR9170_PHY_SIGMA_DELTA_ADC_SEL_S 0268#define AR9170_PHY_SIGMA_DELTA_FILT2 0x000000f8269#define AR9170_PHY_SIGMA_DELTA_FILT2_S 3270#define AR9170_PHY_SIGMA_DELTA_FILT1 0x00001f00271#define AR9170_PHY_SIGMA_DELTA_FILT1_S 8272#define AR9170_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000273#define AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S 13274 275#define AR9170_PHY_REG_RESTART (AR9170_PHY_REG_BASE + 0x0170)276#define AR9170_PHY_RESTART_DIV_GC 0x001c0000277#define AR9170_PHY_RESTART_DIV_GC_S 18278 279#define AR9170_PHY_REG_RFBUS_REQ (AR9170_PHY_REG_BASE + 0x017c)280#define AR9170_PHY_RFBUS_REQ_EN 0x00000001281 282#define AR9170_PHY_REG_TIMING7 (AR9170_PHY_REG_BASE + 0x0180)283#define AR9170_PHY_REG_TIMING8 (AR9170_PHY_REG_BASE + 0x0184)284#define AR9170_PHY_TIMING8_PILOT_MASK_2 0x000fffff285#define AR9170_PHY_TIMING8_PILOT_MASK_2_S 0286 287#define AR9170_PHY_REG_BIN_MASK2_1 (AR9170_PHY_REG_BASE + 0x0188)288#define AR9170_PHY_REG_BIN_MASK2_2 (AR9170_PHY_REG_BASE + 0x018c)289#define AR9170_PHY_REG_BIN_MASK2_3 (AR9170_PHY_REG_BASE + 0x0190)290#define AR9170_PHY_REG_BIN_MASK2_4 (AR9170_PHY_REG_BASE + 0x0194)291#define AR9170_PHY_BIN_MASK2_4_MASK_4 0x00003fff292#define AR9170_PHY_BIN_MASK2_4_MASK_4_S 0293 294#define AR9170_PHY_REG_TIMING9 (AR9170_PHY_REG_BASE + 0x0198)295#define AR9170_PHY_REG_TIMING10 (AR9170_PHY_REG_BASE + 0x019c)296#define AR9170_PHY_TIMING10_PILOT_MASK_2 0x000fffff297#define AR9170_PHY_TIMING10_PILOT_MASK_2_S 0298 299#define AR9170_PHY_REG_TIMING11 (AR9170_PHY_REG_BASE + 0x01a0)300#define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE 0x000fffff301#define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S 0302#define AR9170_PHY_TIMING11_SPUR_FREQ_SD 0x3ff00000303#define AR9170_PHY_TIMING11_SPUR_FREQ_SD_S 20304#define AR9170_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000305#define AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000306 307#define AR9170_PHY_REG_RX_CHAINMASK (AR9170_PHY_REG_BASE + 0x01a4)308#define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \309 0x01b4 + ((_i) << 12))310#define AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000311#define AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000312 313#define AR9170_PHY_REG_MULTICHAIN_GAIN_CTL (AR9170_PHY_REG_BASE + 0x01ac)314#define AR9170_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000315#define AR9170_PHY_9285_ANT_DIV_CTL 0x01000000316#define AR9170_PHY_9285_ANT_DIV_CTL_S 24317#define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000318#define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S 25319#define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000320#define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27321#define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000322#define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S 29323#define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000324#define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30325#define AR9170_PHY_9285_ANT_DIV_LNA1 2326#define AR9170_PHY_9285_ANT_DIV_LNA2 1327#define AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3328#define AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0329#define AR9170_PHY_9285_ANT_DIV_GAINTB_0 0330#define AR9170_PHY_9285_ANT_DIV_GAINTB_1 1331 332#define AR9170_PHY_REG_EXT_CCA0 (AR9170_PHY_REG_BASE + 0x01b8)333#define AR9170_PHY_REG_EXT_CCA0_THRESH62 0x000000ff334#define AR9170_PHY_REG_EXT_CCA0_THRESH62_S 0335 336#define AR9170_PHY_REG_EXT_CCA (AR9170_PHY_REG_BASE + 0x01bc)337#define AR9170_PHY_EXT_CCA_CYCPWR_THR1 0x0000fe00338#define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S 9339#define AR9170_PHY_EXT_CCA_THRESH62 0x007f0000340#define AR9170_PHY_EXT_CCA_THRESH62_S 16341#define AR9170_PHY_EXT_CCA_MIN_PWR 0xff800000342#define AR9170_PHY_EXT_CCA_MIN_PWR_S 23343 344#define AR9170_PHY_REG_SFCORR_EXT (AR9170_PHY_REG_BASE + 0x01c0)345#define AR9170_PHY_SFCORR_EXT_M1_THRESH 0x0000007f346#define AR9170_PHY_SFCORR_EXT_M1_THRESH_S 0347#define AR9170_PHY_SFCORR_EXT_M2_THRESH 0x00003f80348#define AR9170_PHY_SFCORR_EXT_M2_THRESH_S 7349#define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001fc000350#define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14351#define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0fe00000352#define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21353#define AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28354 355#define AR9170_PHY_REG_HALFGI (AR9170_PHY_REG_BASE + 0x01d0)356#define AR9170_PHY_HALFGI_DSC_MAN 0x0007fff0357#define AR9170_PHY_HALFGI_DSC_MAN_S 4358#define AR9170_PHY_HALFGI_DSC_EXP 0x0000000f359#define AR9170_PHY_HALFGI_DSC_EXP_S 0360 361#define AR9170_PHY_REG_CHANNEL_MASK_01_30 (AR9170_PHY_REG_BASE + 0x01d4)362#define AR9170_PHY_REG_CHANNEL_MASK_31_60 (AR9170_PHY_REG_BASE + 0x01d8)363 364#define AR9170_PHY_REG_CHAN_INFO_MEMORY (AR9170_PHY_REG_BASE + 0x01dc)365#define AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001366 367#define AR9170_PHY_REG_HEAVY_CLIP_ENABLE (AR9170_PHY_REG_BASE + 0x01e0)368#define AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS (AR9170_PHY_REG_BASE + 0x01ec)369#define AR9170_PHY_RIFS_INIT_DELAY 0x03ff0000370 371#define AR9170_PHY_REG_CALMODE (AR9170_PHY_REG_BASE + 0x01f0)372#define AR9170_PHY_CALMODE_IQ 0x00000000373#define AR9170_PHY_CALMODE_ADC_GAIN 0x00000001374#define AR9170_PHY_CALMODE_ADC_DC_PER 0x00000002375#define AR9170_PHY_CALMODE_ADC_DC_INIT 0x00000003376 377#define AR9170_PHY_REG_REFCLKDLY (AR9170_PHY_REG_BASE + 0x01f4)378#define AR9170_PHY_REG_REFCLKPD (AR9170_PHY_REG_BASE + 0x01f8)379 380 381#define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + \382 0x0410 + ((_i) << 12))383#define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + \384 0x0414 \ + ((_i) << 12))385#define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + \386 0x0418 + ((_i) << 12))387#define AR9170_PHY_REG_CAL_MEAS_3(_i) (AR9170_PHY_REG_BASE + \388 0x041c + ((_i) << 12))389 390#define AR9170_PHY_REG_CURRENT_RSSI (AR9170_PHY_REG_BASE + 0x041c)391 392#define AR9170_PHY_REG_RFBUS_GRANT (AR9170_PHY_REG_BASE + 0x0420)393#define AR9170_PHY_RFBUS_GRANT_EN 0x00000001394 395#define AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF (AR9170_PHY_REG_BASE + 0x04f4)396#define AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320397 398#define AR9170_PHY_REG_CHAN_INFO_GAIN (AR9170_PHY_REG_BASE + 0x04fc)399 400#define AR9170_PHY_REG_MODE (AR9170_PHY_REG_BASE + 0x0a00)401#define AR9170_PHY_MODE_ASYNCFIFO 0x80402#define AR9170_PHY_MODE_AR2133 0x08403#define AR9170_PHY_MODE_AR5111 0x00404#define AR9170_PHY_MODE_AR5112 0x08405#define AR9170_PHY_MODE_DYNAMIC 0x04406#define AR9170_PHY_MODE_RF2GHZ 0x02407#define AR9170_PHY_MODE_RF5GHZ 0x00408#define AR9170_PHY_MODE_CCK 0x01409#define AR9170_PHY_MODE_OFDM 0x00410#define AR9170_PHY_MODE_DYN_CCK_DISABLE 0x100411 412#define AR9170_PHY_REG_CCK_TX_CTRL (AR9170_PHY_REG_BASE + 0x0a04)413#define AR9170_PHY_CCK_TX_CTRL_JAPAN 0x00000010414#define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000c415#define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2416 417#define AR9170_PHY_REG_CCK_DETECT (AR9170_PHY_REG_BASE + 0x0a08)418#define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003f419#define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0420/* [12:6] settling time for antenna switch */421#define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001fc0422#define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6423#define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000424#define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13425 426#define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c)427#define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c)428#define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000429#define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18430#define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00431#define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S 10432#define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001f433#define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S 0434#define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003e0000435#define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17436#define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001f000437#define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12438#define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000fc0439#define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S 6440#define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003f441#define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S 0442 443#define AR9170_PHY_REG_CCK_RXCTRL4 (AR9170_PHY_REG_BASE + 0x0a1c)444#define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01f80000445#define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19446 447#define AR9170_PHY_REG_DAG_CTRLCCK (AR9170_PHY_REG_BASE + 0x0a28)448#define AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR 0x00000200449#define AR9170_REG_DAG_CTRLCCK_RSSI_THR 0x0001fc00450#define AR9170_REG_DAG_CTRLCCK_RSSI_THR_S 10451 452#define AR9170_PHY_REG_FORCE_CLKEN_CCK (AR9170_PHY_REG_BASE + 0x0a2c)453#define AR9170_FORCE_CLKEN_CCK_MRC_MUX 0x00000040454 455#define AR9170_PHY_REG_POWER_TX_RATE3 (AR9170_PHY_REG_BASE + 0x0a34)456#define AR9170_PHY_REG_POWER_TX_RATE4 (AR9170_PHY_REG_BASE + 0x0a38)457 458#define AR9170_PHY_REG_SCRM_SEQ_XR (AR9170_PHY_REG_BASE + 0x0a3c)459#define AR9170_PHY_REG_HEADER_DETECT_XR (AR9170_PHY_REG_BASE + 0x0a40)460#define AR9170_PHY_REG_CHIRP_DETECTED_XR (AR9170_PHY_REG_BASE + 0x0a44)461#define AR9170_PHY_REG_BLUETOOTH (AR9170_PHY_REG_BASE + 0x0a54)462 463#define AR9170_PHY_REG_TPCRG1 (AR9170_PHY_REG_BASE + 0x0a58)464#define AR9170_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000465#define AR9170_PHY_TPCRG1_NUM_PD_GAIN_S 14466#define AR9170_PHY_TPCRG1_PD_GAIN_1 0x00030000467#define AR9170_PHY_TPCRG1_PD_GAIN_1_S 16468#define AR9170_PHY_TPCRG1_PD_GAIN_2 0x000c0000469#define AR9170_PHY_TPCRG1_PD_GAIN_2_S 18470#define AR9170_PHY_TPCRG1_PD_GAIN_3 0x00300000471#define AR9170_PHY_TPCRG1_PD_GAIN_3_S 20472#define AR9170_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000473#define AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S 22474 475#define AR9170_PHY_REG_TX_PWRCTRL4 (AR9170_PHY_REG_BASE + 0x0a64)476#define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001477#define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0478#define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001fe479#define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1480 481#define AR9170_PHY_REG_ANALOG_SWAP (AR9170_PHY_REG_BASE + 0x0a68)482#define AR9170_PHY_ANALOG_SWAP_AB 0x0001483#define AR9170_PHY_ANALOG_SWAP_ALT_CHAIN 0x00000040484 485#define AR9170_PHY_REG_TPCRG5 (AR9170_PHY_REG_BASE + 0x0a6c)486#define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000f487#define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0488#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003f0489#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4490#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000fc00491#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10492#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003f0000493#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16494#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0fc00000495#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22496 497#define AR9170_PHY_REG_TX_PWRCTRL6_0 (AR9170_PHY_REG_BASE + 0x0a70)498#define AR9170_PHY_REG_TX_PWRCTRL6_1 (AR9170_PHY_REG_BASE + 0x1a70)499#define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000500#define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24501 502#define AR9170_PHY_REG_TX_PWRCTRL7 (AR9170_PHY_REG_BASE + 0x0a74)503#define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01f80000504#define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19505 506#define AR9170_PHY_REG_TX_PWRCTRL9 (AR9170_PHY_REG_BASE + 0x0a7c)507#define AR9170_PHY_TX_DESIRED_SCALE_CCK 0x00007c00508#define AR9170_PHY_TX_DESIRED_SCALE_CCK_S 10509#define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000510#define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31511 512#define AR9170_PHY_REG_TX_GAIN_TBL1 (AR9170_PHY_REG_BASE + 0x0b00)513#define AR9170_PHY_TX_GAIN 0x0007f000514#define AR9170_PHY_TX_GAIN_S 12515 516/* Carrier leak calibration control, do it after AGC calibration */517#define AR9170_PHY_REG_CL_CAL_CTL (AR9170_PHY_REG_BASE + 0x0b58)518#define AR9170_PHY_CL_CAL_ENABLE 0x00000002519#define AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE 0x00000001520 521#define AR9170_PHY_REG_POWER_TX_RATE5 (AR9170_PHY_REG_BASE + 0x0b8c)522#define AR9170_PHY_REG_POWER_TX_RATE6 (AR9170_PHY_REG_BASE + 0x0b90)523 524#define AR9170_PHY_REG_CH0_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x0b98)525#define AR9170_PHY_REG_CH1_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x1b98)526#define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP 0x0000fc00527#define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S 10528 529#define AR9170_PHY_REG_CAL_CHAINMASK (AR9170_PHY_REG_BASE + 0x0b9c)530#define AR9170_PHY_REG_VIT_MASK2_M_46_61 (AR9170_PHY_REG_BASE + 0x0ba0)531#define AR9170_PHY_REG_MASK2_M_31_45 (AR9170_PHY_REG_BASE + 0x0ba4)532#define AR9170_PHY_REG_MASK2_M_16_30 (AR9170_PHY_REG_BASE + 0x0ba8)533#define AR9170_PHY_REG_MASK2_M_00_15 (AR9170_PHY_REG_BASE + 0x0bac)534#define AR9170_PHY_REG_PILOT_MASK_01_30 (AR9170_PHY_REG_BASE + 0x0bb0)535#define AR9170_PHY_REG_PILOT_MASK_31_60 (AR9170_PHY_REG_BASE + 0x0bb4)536#define AR9170_PHY_REG_MASK2_P_15_01 (AR9170_PHY_REG_BASE + 0x0bb8)537#define AR9170_PHY_REG_MASK2_P_30_16 (AR9170_PHY_REG_BASE + 0x0bbc)538#define AR9170_PHY_REG_MASK2_P_45_31 (AR9170_PHY_REG_BASE + 0x0bc0)539#define AR9170_PHY_REG_MASK2_P_61_45 (AR9170_PHY_REG_BASE + 0x0bc4)540#define AR9170_PHY_REG_POWER_TX_SUB (AR9170_PHY_REG_BASE + 0x0bc8)541#define AR9170_PHY_REG_POWER_TX_RATE7 (AR9170_PHY_REG_BASE + 0x0bcc)542#define AR9170_PHY_REG_POWER_TX_RATE8 (AR9170_PHY_REG_BASE + 0x0bd0)543#define AR9170_PHY_REG_POWER_TX_RATE9 (AR9170_PHY_REG_BASE + 0x0bd4)544#define AR9170_PHY_REG_XPA_CFG (AR9170_PHY_REG_BASE + 0x0bd8)545#define AR9170_PHY_FORCE_XPA_CFG 0x000000001546#define AR9170_PHY_FORCE_XPA_CFG_S 0547 548#define AR9170_PHY_REG_CH1_CCA (AR9170_PHY_REG_BASE + 0x1064)549#define AR9170_PHY_CH1_CCA_MIN_PWR 0x0ff80000550#define AR9170_PHY_CH1_CCA_MIN_PWR_S 19551 552#define AR9170_PHY_REG_CH2_CCA (AR9170_PHY_REG_BASE + 0x2064)553#define AR9170_PHY_CH2_CCA_MIN_PWR 0x0ff80000554#define AR9170_PHY_CH2_CCA_MIN_PWR_S 19555 556#define AR9170_PHY_REG_CH1_EXT_CCA (AR9170_PHY_REG_BASE + 0x11bc)557#define AR9170_PHY_CH1_EXT_CCA_MIN_PWR 0xff800000558#define AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S 23559 560#define AR9170_PHY_REG_CH2_EXT_CCA (AR9170_PHY_REG_BASE + 0x21bc)561#define AR9170_PHY_CH2_EXT_CCA_MIN_PWR 0xff800000562#define AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S 23563 564#endif /* __CARL9170_SHARED_PHY_H */565