40 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef B43_PHY_AC_H_3#define B43_PHY_AC_H_4 5#include "phy_common.h"6 7#define B43_PHY_AC_BBCFG 0x0018#define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */9#define B43_PHY_AC_BANDCTL 0x003 /* Band control */10#define B43_PHY_AC_BANDCTL_5GHZ 0x000111#define B43_PHY_AC_TABLE_ID 0x00d12#define B43_PHY_AC_TABLE_OFFSET 0x00e13#define B43_PHY_AC_TABLE_DATA1 0x00f14#define B43_PHY_AC_TABLE_DATA2 0x01015#define B43_PHY_AC_TABLE_DATA3 0x01116#define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */17#define B43_PHY_AC_CLASSCTL_CCKEN 0x0001 /* CCK enable */18#define B43_PHY_AC_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */19#define B43_PHY_AC_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */20#define B43_PHY_AC_BW1A 0x37121#define B43_PHY_AC_BW2 0x37222#define B43_PHY_AC_BW3 0x37323#define B43_PHY_AC_BW4 0x37424#define B43_PHY_AC_BW5 0x37525#define B43_PHY_AC_BW6 0x37626#define B43_PHY_AC_RFCTL_CMD 0x40827#define B43_PHY_AC_C1_CLIP 0x6d428#define B43_PHY_AC_C1_CLIP_DIS 0x400029#define B43_PHY_AC_C2_CLIP 0x8d430#define B43_PHY_AC_C2_CLIP_DIS 0x400031#define B43_PHY_AC_C3_CLIP 0xad432#define B43_PHY_AC_C3_CLIP_DIS 0x400033 34struct b43_phy_ac {35};36 37extern const struct b43_phy_operations b43_phyops_ac;38 39#endif /* B43_PHY_AC_H_ */40