418 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef B43_XMIT_H_3#define B43_XMIT_H_4 5#include "main.h"6#include <net/mac80211.h>7 8 9#define _b43_declare_plcp_hdr(size) \10 struct b43_plcp_hdr##size { \11 union { \12 __le32 data; \13 __u8 raw[size]; \14 } __packed; \15 } __packed16 17/* struct b43_plcp_hdr4 */18_b43_declare_plcp_hdr(4);19/* struct b43_plcp_hdr6 */20_b43_declare_plcp_hdr(6);21 22#undef _b43_declare_plcp_hdr23 24/* TX header for v4 firmware */25struct b43_txhdr {26 __le32 mac_ctl; /* MAC TX control */27 __le16 mac_frame_ctl; /* Copy of the FrameControl field */28 __le16 tx_fes_time_norm; /* TX FES Time Normal */29 __le16 phy_ctl; /* PHY TX control */30 __le16 phy_ctl1; /* PHY TX control word 1 */31 __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */32 __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */33 __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */34 __u8 phy_rate; /* PHY rate */35 __u8 phy_rate_rts; /* PHY rate for RTS/CTS */36 __u8 extra_ft; /* Extra Frame Types */37 __u8 chan_radio_code; /* Channel Radio Code */38 __u8 iv[16]; /* Encryption IV */39 __u8 tx_receiver[6]; /* TX Frame Receiver address */40 __le16 tx_fes_time_fb; /* TX FES Time Fallback */41 struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */42 __le16 rts_dur_fb; /* RTS fallback duration */43 struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */44 __le16 dur_fb; /* Fallback duration */45 __le16 mimo_modelen; /* MIMO mode length */46 __le16 mimo_ratelen_fb; /* MIMO fallback rate length */47 __le32 timeout; /* Timeout */48 49 union {50 /* Tested with 598.314, 644.1001 and 666.2 */51 struct {52 __le16 mimo_antenna; /* MIMO antenna select */53 __le16 preload_size; /* Preload size */54 PAD_BYTES(2);55 __le16 cookie; /* TX frame cookie */56 __le16 tx_status; /* TX status */57 __le16 max_n_mpdus;58 __le16 max_a_bytes_mrt;59 __le16 max_a_bytes_fbr;60 __le16 min_m_bytes;61 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */62 __u8 rts_frame[16]; /* The RTS frame (if used) */63 PAD_BYTES(2);64 struct b43_plcp_hdr6 plcp; /* Main PLCP header */65 } format_598 __packed;66 67 /* Tested with 410.2160, 478.104 and 508.* */68 struct {69 __le16 mimo_antenna; /* MIMO antenna select */70 __le16 preload_size; /* Preload size */71 PAD_BYTES(2);72 __le16 cookie; /* TX frame cookie */73 __le16 tx_status; /* TX status */74 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */75 __u8 rts_frame[16]; /* The RTS frame (if used) */76 PAD_BYTES(2);77 struct b43_plcp_hdr6 plcp; /* Main PLCP header */78 } format_410 __packed;79 80 /* Tested with 351.126 */81 struct {82 PAD_BYTES(2);83 __le16 cookie; /* TX frame cookie */84 __le16 tx_status; /* TX status */85 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */86 __u8 rts_frame[16]; /* The RTS frame (if used) */87 PAD_BYTES(2);88 struct b43_plcp_hdr6 plcp; /* Main PLCP header */89 } format_351 __packed;90 91 } __packed;92} __packed;93 94struct b43_tx_legacy_rate_phy_ctl_entry {95 u8 bitrate;96 u16 coding_rate;97 u16 modulation;98};99 100/* MAC TX control */101#define B43_TXH_MAC_RTS_FB_SHORTPRMBL 0x80000000 /* RTS fallback preamble */102#define B43_TXH_MAC_RTS_SHORTPRMBL 0x40000000 /* RTS main rate preamble */103#define B43_TXH_MAC_FB_SHORTPRMBL 0x20000000 /* Main fallback preamble */104#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */105#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */106#define B43_TXH_MAC_KEYIDX_SHIFT 20107#define B43_TXH_MAC_ALT_TXPWR 0x00080000 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */108#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */109#define B43_TXH_MAC_KEYALG_SHIFT 16110#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */111#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */112#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */113#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */114#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */115#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */116#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */117#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */118#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */119#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */120#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */121#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */122#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */123#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */124#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */125#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */126#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */127#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */128#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */129 130/* Extra Frame Types */131#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */132#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */133#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */134#define B43_TXH_EFT_FB_HT 0x02 /* HT */135#define B43_TXH_EFT_FB_VHT 0x03 /* VHT */136#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */137#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */138#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */139#define B43_TXH_EFT_RTS_HT 0x08 /* HT */140#define B43_TXH_EFT_RTS_VHT 0x0C /* VHT */141#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */142#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */143#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */144#define B43_TXH_EFT_RTSFB_HT 0x20 /* HT */145#define B43_TXH_EFT_RTSFB_VHT 0x30 /* VHT */146 147/* PHY TX control word */148#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */149#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */150#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */151#define B43_TXH_PHY_ENC_HT 0x0002 /* HT */152#define B43_TXH_PHY_ENC_VHT 0x0003 /* VHT */153#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */154#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */155#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */156#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */157#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */158#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */159#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */160#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */161#define B43_TXH_PHY_TXPWR_SHIFT 10162 163/* PHY TX control word 1 */164#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */165#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */166#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */167#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */168#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */169#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */170#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */171#define B43_TXH_PHY1_MODE 0x0038 /* Mode */172#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */173#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */174#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */175#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */176#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */177#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */178#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */179#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */180#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */181#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */182#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */183#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */184#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */185#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */186#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */187#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */188#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */189 190 191static inline192size_t b43_txhdr_size(struct b43_wldev *dev)193{194 switch (dev->fw.hdr_format) {195 case B43_FW_HDR_598:196 return 112 + sizeof(struct b43_plcp_hdr6);197 case B43_FW_HDR_410:198 return 104 + sizeof(struct b43_plcp_hdr6);199 case B43_FW_HDR_351:200 return 100 + sizeof(struct b43_plcp_hdr6);201 }202 return 0;203}204 205 206int b43_generate_txhdr(struct b43_wldev *dev,207 u8 * txhdr,208 struct sk_buff *skb_frag,209 struct ieee80211_tx_info *txctl, u16 cookie);210 211/* Transmit Status */212struct b43_txstatus {213 u16 cookie; /* The cookie from the txhdr */214 u16 seq; /* Sequence number */215 u8 phy_stat; /* PHY TX status */216 u8 frame_count; /* Frame transmit count */217 u8 rts_count; /* RTS transmit count */218 u8 supp_reason; /* Suppression reason */219 /* flags */220 u8 pm_indicated; /* PM mode indicated to AP */221 u8 intermediate; /* Intermediate status notification (not final) */222 u8 for_ampdu; /* Status is for an AMPDU (afterburner) */223 u8 acked; /* Wireless ACK received */224};225 226/* txstatus supp_reason values */227enum {228 B43_TXST_SUPP_NONE, /* Not suppressed */229 B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */230 B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */231 B43_TXST_SUPP_PREV, /* Previous fragment failed */232 B43_TXST_SUPP_CHAN, /* Channel mismatch */233 B43_TXST_SUPP_LIFE, /* Lifetime expired */234 B43_TXST_SUPP_UNDER, /* Buffer underflow */235 B43_TXST_SUPP_ABNACK, /* Afterburner NACK */236};237 238/* Receive header for v4 firmware. */239struct b43_rxhdr_fw4 {240 __le16 frame_len; /* Frame length */241 PAD_BYTES(2);242 __le16 phy_status0; /* PHY RX Status 0 */243 union {244 /* RSSI for A/B/G-PHYs */245 struct {246 __u8 jssi; /* PHY RX Status 1: JSSI */247 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */248 } __packed;249 250 /* RSSI for N-PHYs */251 struct {252 __s8 power0; /* PHY RX Status 1: Power 0 */253 __s8 power1; /* PHY RX Status 1: Power 1 */254 } __packed;255 } __packed;256 union {257 /* HT-PHY */258 struct {259 PAD_BYTES(1);260 __s8 phy_ht_power0;261 } __packed;262 263 /* RSSI for N-PHYs */264 struct {265 __s8 power2;266 PAD_BYTES(1);267 } __packed;268 269 __le16 phy_status2; /* PHY RX Status 2 */270 } __packed;271 union {272 /* HT-PHY */273 struct {274 __s8 phy_ht_power1;275 __s8 phy_ht_power2;276 } __packed;277 278 __le16 phy_status3; /* PHY RX Status 3 */279 } __packed;280 union {281 /* Tested with 598.314, 644.1001 and 666.2 */282 struct {283 __le16 phy_status4; /* PHY RX Status 4 */284 __le16 phy_status5; /* PHY RX Status 5 */285 __le32 mac_status; /* MAC RX status */286 __le16 mac_time;287 __le16 channel;288 } format_598 __packed;289 290 /* Tested with 351.126, 410.2160, 478.104 and 508.* */291 struct {292 __le32 mac_status; /* MAC RX status */293 __le16 mac_time;294 __le16 channel;295 } format_351 __packed;296 } __packed;297} __packed;298 299/* PHY RX Status 0 */300#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */301#define B43_RX_PHYST0_PLCPHCF 0x0200302#define B43_RX_PHYST0_PLCPFV 0x0100303#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */304#define B43_RX_PHYST0_LCRS 0x0040305#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */306#define B43_RX_PHYST0_UNSRATE 0x0010307#define B43_RX_PHYST0_CLIP 0x000C308#define B43_RX_PHYST0_CLIP_SHIFT 2309#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */310#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */311#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */312#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */313#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */314 315/* PHY RX Status 2 */316#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */317#define B43_RX_PHYST2_LNAG_SHIFT 14318#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */319#define B43_RX_PHYST2_PNAG_SHIFT 10320#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */321 322/* PHY RX Status 3 */323#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */324#define B43_RX_PHYST3_DIGG_SHIFT 11325#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */326 327/* MAC RX Status */328#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */329#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */330#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */331#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */332#define B43_RX_MAC_AGGTYPE_SHIFT 17333#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */334#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */335#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */336#define B43_RX_MAC_KEYIDX_SHIFT 5337#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */338#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */339#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */340#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */341#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */342 343/* RX channel */344#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */345#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */346#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */347#define B43_RX_CHAN_ID_SHIFT 3348#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */349 350 351u8 b43_plcp_get_ratecode_cck(const u8 bitrate);352u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);353 354void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,355 const u16 octets, const u8 bitrate);356 357void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);358 359void b43_handle_txstatus(struct b43_wldev *dev,360 const struct b43_txstatus *status);361bool b43_fill_txstatus_report(struct b43_wldev *dev,362 struct ieee80211_tx_info *report,363 const struct b43_txstatus *status);364 365void b43_tx_suspend(struct b43_wldev *dev);366void b43_tx_resume(struct b43_wldev *dev);367 368 369/* Helper functions for converting the key-table index from "firmware-format"370 * to "raw-format" and back. The firmware API changed for this at some revision.371 * We need to account for that here. */372static inline int b43_new_kidx_api(struct b43_wldev *dev)373{374 /* FIXME: Not sure the change was at rev 351 */375 return (dev->fw.rev >= 351);376}377static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)378{379 u8 firmware_kidx;380 if (b43_new_kidx_api(dev)) {381 firmware_kidx = raw_kidx;382 } else {383 if (raw_kidx >= 4) /* Is per STA key? */384 firmware_kidx = raw_kidx - 4;385 else386 firmware_kidx = raw_kidx; /* TX default key */387 }388 return firmware_kidx;389}390static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)391{392 u8 raw_kidx;393 if (b43_new_kidx_api(dev))394 raw_kidx = firmware_kidx;395 else396 raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */397 return raw_kidx;398}399 400/* struct b43_private_tx_info - TX info private to b43.401 * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data402 *403 * @bouncebuffer: DMA Bouncebuffer (if used)404 */405struct b43_private_tx_info {406 void *bouncebuffer;407};408 409static inline struct b43_private_tx_info *410b43_get_priv_tx_info(struct ieee80211_tx_info *info)411{412 BUILD_BUG_ON(sizeof(struct b43_private_tx_info) >413 sizeof(info->rate_driver_data));414 return (struct b43_private_tx_info *)info->rate_driver_data;415}416 417#endif /* B43_XMIT_H_ */418