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1// SPDX-License-Identifier: ISC2/*3 * Copyright (c) 2010 Broadcom Corporation4 */5 6/*7 * phy_hal.h: functionality exported from the phy to higher layers8 */9 10#ifndef _BRCM_PHY_HAL_H_11#define _BRCM_PHY_HAL_H_12 13#include <brcmu_utils.h>14#include <brcmu_wifi.h>15#include <phy_shim.h>16 17#define IDCODE_VER_MASK 0x0000000f18#define IDCODE_VER_SHIFT 019#define IDCODE_MFG_MASK 0x00000fff20#define IDCODE_MFG_SHIFT 021#define IDCODE_ID_MASK 0x0ffff00022#define IDCODE_ID_SHIFT 1223#define IDCODE_REV_MASK 0xf000000024#define IDCODE_REV_SHIFT 2825 26#define NORADIO_ID 0xe4f527#define NORADIO_IDCODE 0x4e4f524628 29#define BCM2055_ID 0x205530#define BCM2055_IDCODE 0x0205500031#define BCM2055A0_IDCODE 0x1205517f32 33#define BCM2056_ID 0x205634#define BCM2056_IDCODE 0x0205600035#define BCM2056A0_IDCODE 0x1205617f36 37#define BCM2057_ID 0x205738#define BCM2057_IDCODE 0x0205700039#define BCM2057A0_IDCODE 0x1205717f40 41#define BCM2064_ID 0x206442#define BCM2064_IDCODE 0x0206400043#define BCM2064A0_IDCODE 0x0206417f44 45#define PHY_TPC_HW_OFF false46#define PHY_TPC_HW_ON true47 48#define PHY_PERICAL_DRIVERUP 149#define PHY_PERICAL_WATCHDOG 250#define PHY_PERICAL_PHYINIT 351#define PHY_PERICAL_JOIN_BSS 452#define PHY_PERICAL_START_IBSS 553#define PHY_PERICAL_UP_BSS 654#define PHY_PERICAL_CHAN 755#define PHY_FULLCAL 856 57#define PHY_PERICAL_DISABLE 058#define PHY_PERICAL_SPHASE 159#define PHY_PERICAL_MPHASE 260#define PHY_PERICAL_MANUAL 361 62#define PHY_HOLD_FOR_ASSOC 163#define PHY_HOLD_FOR_SCAN 264#define PHY_HOLD_FOR_RM 465#define PHY_HOLD_FOR_PLT 866#define PHY_HOLD_FOR_MUTE 1667#define PHY_HOLD_FOR_NOT_ASSOC 0x2068 69#define PHY_MUTE_FOR_PREISM 170#define PHY_MUTE_ALL 0xffffffff71 72#define PHY_NOISE_FIXED_VAL (-95)73#define PHY_NOISE_FIXED_VAL_NPHY (-92)74#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)75 76#define PHY_MODE_CAL 0x000277#define PHY_MODE_NOISEM 0x000478 79#define BRCMS_TXPWR_DB_FACTOR 480 81/* a large TX Power as an init value to factor out of min() calculations,82 * keep low enough to fit in an s8, units are .25 dBm83 */84#define BRCMS_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */85 86#define BRCMS_NUM_RATES_CCK 487#define BRCMS_NUM_RATES_OFDM 888#define BRCMS_NUM_RATES_MCS_1_STREAM 889#define BRCMS_NUM_RATES_MCS_2_STREAM 890#define BRCMS_NUM_RATES_MCS_3_STREAM 891#define BRCMS_NUM_RATES_MCS_4_STREAM 892 93#define BRCMS_RSSI_INVALID 0 /* invalid RSSI value */94 95struct d11regs;96struct phy_shim_info;97 98struct txpwr_limits {99 u8 cck[BRCMS_NUM_RATES_CCK];100 u8 ofdm[BRCMS_NUM_RATES_OFDM];101 102 u8 ofdm_cdd[BRCMS_NUM_RATES_OFDM];103 104 u8 ofdm_40_siso[BRCMS_NUM_RATES_OFDM];105 u8 ofdm_40_cdd[BRCMS_NUM_RATES_OFDM];106 107 u8 mcs_20_siso[BRCMS_NUM_RATES_MCS_1_STREAM];108 u8 mcs_20_cdd[BRCMS_NUM_RATES_MCS_1_STREAM];109 u8 mcs_20_stbc[BRCMS_NUM_RATES_MCS_1_STREAM];110 u8 mcs_20_mimo[BRCMS_NUM_RATES_MCS_2_STREAM];111 112 u8 mcs_40_siso[BRCMS_NUM_RATES_MCS_1_STREAM];113 u8 mcs_40_cdd[BRCMS_NUM_RATES_MCS_1_STREAM];114 u8 mcs_40_stbc[BRCMS_NUM_RATES_MCS_1_STREAM];115 u8 mcs_40_mimo[BRCMS_NUM_RATES_MCS_2_STREAM];116 u8 mcs32;117};118 119struct tx_power {120 u32 flags;121 u16 chanspec; /* txpwr report for this channel */122 u16 local_chanspec; /* channel on which we are associated */123 u8 local_max; /* local max according to the AP */124 u8 local_constraint; /* local constraint according to the AP */125 s8 antgain[2]; /* Ant gain for each band - from SROM */126 u8 rf_cores; /* count of RF Cores being reported */127 u8 est_Pout[4]; /* Latest tx power out estimate per RF chain */128 u8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain129 * without adjustment */130 u8 est_Pout_cck; /* Latest CCK tx power out estimate */131 u8 tx_power_max[4]; /* Maximum target power among all rates */132 /* Index of the rate with the max target power */133 u8 tx_power_max_rate_ind[4];134 /* User limit */135 u8 user_limit[WL_TX_POWER_RATES];136 /* Regulatory power limit */137 u8 reg_limit[WL_TX_POWER_RATES];138 /* Max power board can support (SROM) */139 u8 board_limit[WL_TX_POWER_RATES];140 /* Latest target power */141 u8 target[WL_TX_POWER_RATES];142};143 144struct brcms_chanvec {145 u8 vec[MAXCHANNEL / NBBY];146};147 148struct shared_phy_params {149 struct si_pub *sih;150 struct phy_shim_info *physhim;151 uint unit;152 uint corerev;153 u16 vid;154 u16 did;155 uint chip;156 uint chiprev;157 uint chippkg;158 uint sromrev;159 uint boardtype;160 uint boardrev;161 u32 boardflags;162 u32 boardflags2;163};164 165 166struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp);167struct brcms_phy_pub *wlc_phy_attach(struct shared_phy *sh,168 struct bcma_device *d11core, int bandtype,169 struct wiphy *wiphy);170void wlc_phy_detach(struct brcms_phy_pub *ppi);171 172bool wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype,173 u16 *phyrev, u16 *radioid, u16 *radiover);174bool wlc_phy_get_encore(struct brcms_phy_pub *pih);175u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih);176 177void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *ppi, bool newstate);178void wlc_phy_hw_state_upd(struct brcms_phy_pub *ppi, bool newstate);179void wlc_phy_init(struct brcms_phy_pub *ppi, u16 chanspec);180void wlc_phy_watchdog(struct brcms_phy_pub *ppi);181int wlc_phy_down(struct brcms_phy_pub *ppi);182u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih);183void wlc_phy_cal_init(struct brcms_phy_pub *ppi);184void wlc_phy_antsel_init(struct brcms_phy_pub *ppi, bool lut_init);185 186void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi, u16 chanspec);187u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi);188void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi, u16 newch);189u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi);190void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw);191 192int wlc_phy_rssi_compute(struct brcms_phy_pub *pih, struct d11rxhdr *rxh);193void wlc_phy_por_inform(struct brcms_phy_pub *ppi);194void wlc_phy_noise_sample_intr(struct brcms_phy_pub *ppi);195bool wlc_phy_bist_check_phy(struct brcms_phy_pub *ppi);196 197void wlc_phy_set_deaf(struct brcms_phy_pub *ppi, bool user_flag);198 199void wlc_phy_switch_radio(struct brcms_phy_pub *ppi, bool on);200void wlc_phy_anacore(struct brcms_phy_pub *ppi, bool on);201 202 203void wlc_phy_BSSinit(struct brcms_phy_pub *ppi, bool bonlyap, int rssi);204 205void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,206 bool wide_filter);207void wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,208 struct brcms_chanvec *channels);209u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi, uint band);210 211void wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint chan, u8 *_min_,212 u8 *_max_, int rate);213void wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi, uint chan,214 u8 *_max_, u8 *_min_);215void wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi, uint band,216 s32 *, s32 *, u32 *);217void wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi, struct txpwr_limits *,218 u16 chanspec);219int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm, bool *override);220int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm, bool override);221void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,222 struct txpwr_limits *);223bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi);224void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi, bool hwpwrctrl);225u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi);226u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi);227bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *pih);228 229void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain);230void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain);231void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih, u8 *txchain, u8 *rxchain);232u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih);233s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih, u16 chanspec);234void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool val);235 236void wlc_phy_cal_perical(struct brcms_phy_pub *ppi, u8 reason);237void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *ppi);238void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih, bool lock);239void wlc_phy_cal_papd_recal(struct brcms_phy_pub *ppi);240 241void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val);242void wlc_phy_clear_tssi(struct brcms_phy_pub *ppi);243void wlc_phy_hold_upd(struct brcms_phy_pub *ppi, u32 id, bool val);244void wlc_phy_mute_upd(struct brcms_phy_pub *ppi, bool val, u32 flags);245 246void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type);247 248void wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi,249 struct tx_power *power, uint channel);250 251void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal);252bool wlc_phy_test_ison(struct brcms_phy_pub *ppi);253void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi, u8 txpwr_percent);254void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war);255void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih, bool bf_preempt);256void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap);257 258void wlc_phy_runbist_config(struct brcms_phy_pub *ppi, bool start_end);259 260void wlc_phy_freqtrack_start(struct brcms_phy_pub *ppi);261void wlc_phy_freqtrack_end(struct brcms_phy_pub *ppi);262 263const u8 *wlc_phy_get_ofdm_rate_lookup(void);264 265s8 wlc_phy_get_tx_power_offset_by_mcs(struct brcms_phy_pub *ppi,266 u8 mcs_offset);267s8 wlc_phy_get_tx_power_offset(struct brcms_phy_pub *ppi, u8 tbl_offset);268#endif /* _BRCM_PHY_HAL_H_ */269