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1/* SPDX-License-Identifier: GPL-2.0-only */2/******************************************************************************3 4 Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.5 6 7 Contact Information:8 Intel Linux Wireless <ilw@linux.intel.com>9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649710 11******************************************************************************/12 13#ifndef __ipw2200_h__14#define __ipw2200_h__15 16#include <linux/module.h>17#include <linux/moduleparam.h>18#include <linux/interrupt.h>19#include <linux/mutex.h>20 21#include <linux/pci.h>22#include <linux/netdevice.h>23#include <linux/ethtool.h>24#include <linux/skbuff.h>25#include <linux/etherdevice.h>26#include <linux/delay.h>27#include <linux/random.h>28#include <linux/dma-mapping.h>29 30#include <linux/firmware.h>31#include <linux/wireless.h>32#include <linux/jiffies.h>33#include <asm/io.h>34 35#include <net/lib80211.h>36#include <net/ieee80211_radiotap.h>37 38#define DRV_NAME "ipw2200"39 40#include <linux/workqueue.h>41 42#include "libipw.h"43 44/* Authentication and Association States */45enum connection_manager_assoc_states {46 CMAS_INIT = 0,47 CMAS_TX_AUTH_SEQ_1,48 CMAS_RX_AUTH_SEQ_2,49 CMAS_AUTH_SEQ_1_PASS,50 CMAS_AUTH_SEQ_1_FAIL,51 CMAS_TX_AUTH_SEQ_3,52 CMAS_RX_AUTH_SEQ_4,53 CMAS_AUTH_SEQ_2_PASS,54 CMAS_AUTH_SEQ_2_FAIL,55 CMAS_AUTHENTICATED,56 CMAS_TX_ASSOC,57 CMAS_RX_ASSOC_RESP,58 CMAS_ASSOCIATED,59 CMAS_LAST60};61 62#define IPW_WAIT (1<<0)63#define IPW_QUIET (1<<1)64#define IPW_ROAMING (1<<2)65 66#define IPW_POWER_MODE_CAM 0x00 //(always on)67#define IPW_POWER_INDEX_1 0x0168#define IPW_POWER_INDEX_2 0x0269#define IPW_POWER_INDEX_3 0x0370#define IPW_POWER_INDEX_4 0x0471#define IPW_POWER_INDEX_5 0x0572#define IPW_POWER_AC 0x0673#define IPW_POWER_BATTERY 0x0774#define IPW_POWER_LIMIT 0x0775#define IPW_POWER_MASK 0x0F76#define IPW_POWER_ENABLED 0x1077#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)78 79#define IPW_CMD_HOST_COMPLETE 280#define IPW_CMD_POWER_DOWN 481#define IPW_CMD_SYSTEM_CONFIG 682#define IPW_CMD_MULTICAST_ADDRESS 783#define IPW_CMD_SSID 884#define IPW_CMD_ADAPTER_ADDRESS 1185#define IPW_CMD_PORT_TYPE 1286#define IPW_CMD_RTS_THRESHOLD 1587#define IPW_CMD_FRAG_THRESHOLD 1688#define IPW_CMD_POWER_MODE 1789#define IPW_CMD_WEP_KEY 1890#define IPW_CMD_TGI_TX_KEY 1991#define IPW_CMD_SCAN_REQUEST 2092#define IPW_CMD_ASSOCIATE 2193#define IPW_CMD_SUPPORTED_RATES 2294#define IPW_CMD_SCAN_ABORT 2395#define IPW_CMD_TX_FLUSH 2496#define IPW_CMD_QOS_PARAMETERS 2597#define IPW_CMD_SCAN_REQUEST_EXT 2698#define IPW_CMD_DINO_CONFIG 3099#define IPW_CMD_RSN_CAPABILITIES 31100#define IPW_CMD_RX_KEY 32101#define IPW_CMD_CARD_DISABLE 33102#define IPW_CMD_SEED_NUMBER 34103#define IPW_CMD_TX_POWER 35104#define IPW_CMD_COUNTRY_INFO 36105#define IPW_CMD_AIRONET_INFO 37106#define IPW_CMD_AP_TX_POWER 38107#define IPW_CMD_CCKM_INFO 39108#define IPW_CMD_CCX_VER_INFO 40109#define IPW_CMD_SET_CALIBRATION 41110#define IPW_CMD_SENSITIVITY_CALIB 42111#define IPW_CMD_RETRY_LIMIT 51112#define IPW_CMD_IPW_PRE_POWER_DOWN 58113#define IPW_CMD_VAP_BEACON_TEMPLATE 60114#define IPW_CMD_VAP_DTIM_PERIOD 61115#define IPW_CMD_EXT_SUPPORTED_RATES 62116#define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63117#define IPW_CMD_VAP_QUIET_INTERVALS 64118#define IPW_CMD_VAP_CHANNEL_SWITCH 65119#define IPW_CMD_VAP_MANDATORY_CHANNELS 66120#define IPW_CMD_VAP_CELL_PWR_LIMIT 67121#define IPW_CMD_VAP_CF_PARAM_SET 68122#define IPW_CMD_VAP_SET_BEACONING_STATE 69123#define IPW_CMD_MEASUREMENT 80124#define IPW_CMD_POWER_CAPABILITY 81125#define IPW_CMD_SUPPORTED_CHANNELS 82126#define IPW_CMD_TPC_REPORT 83127#define IPW_CMD_WME_INFO 84128#define IPW_CMD_PRODUCTION_COMMAND 85129#define IPW_CMD_LINKSYS_EOU_INFO 90130 131#define RFD_SIZE 4132#define NUM_TFD_CHUNKS 6133 134#define TX_QUEUE_SIZE 32135#define RX_QUEUE_SIZE 32136 137#define DINO_CMD_WEP_KEY 0x08138#define DINO_CMD_TX 0x0B139#define DCT_ANTENNA_A 0x01140#define DCT_ANTENNA_B 0x02141 142#define IPW_A_MODE 0143#define IPW_B_MODE 1144#define IPW_G_MODE 2145 146/*147 * TX Queue Flag Definitions148 */149 150/* tx wep key definition */151#define DCT_WEP_KEY_NOT_IMMIDIATE 0x00152#define DCT_WEP_KEY_64Bit 0x40153#define DCT_WEP_KEY_128Bit 0x80154#define DCT_WEP_KEY_128bitIV 0xC0155#define DCT_WEP_KEY_SIZE_MASK 0xC0156 157#define DCT_WEP_KEY_INDEX_MASK 0x0F158#define DCT_WEP_INDEX_USE_IMMEDIATE 0x20159 160/* abort attempt if mgmt frame is rx'd */161#define DCT_FLAG_ABORT_MGMT 0x01162 163/* require CTS */164#define DCT_FLAG_CTS_REQUIRED 0x02165 166/* use short preamble */167#define DCT_FLAG_LONG_PREAMBLE 0x00168#define DCT_FLAG_SHORT_PREAMBLE 0x04169 170/* RTS/CTS first */171#define DCT_FLAG_RTS_REQD 0x08172 173/* dont calculate duration field */174#define DCT_FLAG_DUR_SET 0x10175 176/* even if MAC WEP set (allows pre-encrypt) */177#define DCT_FLAG_NO_WEP 0x20178 179/* overwrite TSF field */180#define DCT_FLAG_TSF_REQD 0x40181 182/* ACK rx is expected to follow */183#define DCT_FLAG_ACK_REQD 0x80184 185/* TX flags extension */186#define DCT_FLAG_EXT_MODE_CCK 0x01187#define DCT_FLAG_EXT_MODE_OFDM 0x00188 189#define DCT_FLAG_EXT_SECURITY_WEP 0x00190#define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP191#define DCT_FLAG_EXT_SECURITY_CKIP 0x04192#define DCT_FLAG_EXT_SECURITY_CCM 0x08193#define DCT_FLAG_EXT_SECURITY_TKIP 0x0C194#define DCT_FLAG_EXT_SECURITY_MASK 0x0C195 196#define DCT_FLAG_EXT_QOS_ENABLED 0x10197 198#define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00199#define DCT_FLAG_EXT_HC_SIFS 0x20200#define DCT_FLAG_EXT_HC_PIFS 0x40201 202#define TX_RX_TYPE_MASK 0xFF203#define TX_FRAME_TYPE 0x00204#define TX_HOST_COMMAND_TYPE 0x01205#define RX_FRAME_TYPE 0x09206#define RX_HOST_NOTIFICATION_TYPE 0x03207#define RX_HOST_CMD_RESPONSE_TYPE 0x04208#define RX_TX_FRAME_RESPONSE_TYPE 0x05209#define TFD_NEED_IRQ_MASK 0x04210 211#define HOST_CMD_DINO_CONFIG 30212 213#define HOST_NOTIFICATION_STATUS_ASSOCIATED 10214#define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11215#define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12216#define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13217#define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14218#define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15219#define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16220#define HOST_NOTIFICATION_STATUS_BEACON_STATE 17221#define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18222#define HOST_NOTIFICATION_TX_STATUS 19223#define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20224#define HOST_NOTIFICATION_MEASUREMENT_STARTED 21225#define HOST_NOTIFICATION_MEASUREMENT_ENDED 22226#define HOST_NOTIFICATION_CHANNEL_SWITCHED 23227#define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24228#define HOST_NOTIFICATION_NOISE_STATS 25229#define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30230#define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31231 232#define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1233#define IPW_MB_SCAN_CANCEL_THRESHOLD 3234#define IPW_MB_ROAMING_THRESHOLD_MIN 1235#define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8236#define IPW_MB_ROAMING_THRESHOLD_MAX 30237#define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 3*IPW_MB_ROAMING_THRESHOLD_DEFAULT238#define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300239 240#define MACADRR_BYTE_LEN 6241 242#define DCR_TYPE_AP 0x01243#define DCR_TYPE_WLAP 0x02244#define DCR_TYPE_MU_ESS 0x03245#define DCR_TYPE_MU_IBSS 0x04246#define DCR_TYPE_MU_PIBSS 0x05247#define DCR_TYPE_SNIFFER 0x06248#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS249 250/* QoS definitions */251 252#define CW_MIN_OFDM 15253#define CW_MAX_OFDM 1023254#define CW_MIN_CCK 31255#define CW_MAX_CCK 1023256 257#define QOS_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)258#define QOS_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)259#define QOS_TX2_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)260#define QOS_TX3_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/4 - 1)261 262#define QOS_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)263#define QOS_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)264#define QOS_TX2_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)265#define QOS_TX3_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/4 - 1)266 267#define QOS_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)268#define QOS_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)269#define QOS_TX2_CW_MAX_OFDM cpu_to_le16(CW_MIN_OFDM)270#define QOS_TX3_CW_MAX_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)271 272#define QOS_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)273#define QOS_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)274#define QOS_TX2_CW_MAX_CCK cpu_to_le16(CW_MIN_CCK)275#define QOS_TX3_CW_MAX_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)276 277#define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)278#define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)279#define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)280#define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)281 282#define QOS_TX0_ACM 0283#define QOS_TX1_ACM 0284#define QOS_TX2_ACM 0285#define QOS_TX3_ACM 0286 287#define QOS_TX0_TXOP_LIMIT_CCK 0288#define QOS_TX1_TXOP_LIMIT_CCK 0289#define QOS_TX2_TXOP_LIMIT_CCK cpu_to_le16(6016)290#define QOS_TX3_TXOP_LIMIT_CCK cpu_to_le16(3264)291 292#define QOS_TX0_TXOP_LIMIT_OFDM 0293#define QOS_TX1_TXOP_LIMIT_OFDM 0294#define QOS_TX2_TXOP_LIMIT_OFDM cpu_to_le16(3008)295#define QOS_TX3_TXOP_LIMIT_OFDM cpu_to_le16(1504)296 297#define DEF_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)298#define DEF_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)299#define DEF_TX2_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)300#define DEF_TX3_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)301 302#define DEF_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)303#define DEF_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)304#define DEF_TX2_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)305#define DEF_TX3_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)306 307#define DEF_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)308#define DEF_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)309#define DEF_TX2_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)310#define DEF_TX3_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)311 312#define DEF_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)313#define DEF_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)314#define DEF_TX2_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)315#define DEF_TX3_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)316 317#define DEF_TX0_AIFS 0318#define DEF_TX1_AIFS 0319#define DEF_TX2_AIFS 0320#define DEF_TX3_AIFS 0321 322#define DEF_TX0_ACM 0323#define DEF_TX1_ACM 0324#define DEF_TX2_ACM 0325#define DEF_TX3_ACM 0326 327#define DEF_TX0_TXOP_LIMIT_CCK 0328#define DEF_TX1_TXOP_LIMIT_CCK 0329#define DEF_TX2_TXOP_LIMIT_CCK 0330#define DEF_TX3_TXOP_LIMIT_CCK 0331 332#define DEF_TX0_TXOP_LIMIT_OFDM 0333#define DEF_TX1_TXOP_LIMIT_OFDM 0334#define DEF_TX2_TXOP_LIMIT_OFDM 0335#define DEF_TX3_TXOP_LIMIT_OFDM 0336 337#define QOS_QOS_SETS 3338#define QOS_PARAM_SET_ACTIVE 0339#define QOS_PARAM_SET_DEF_CCK 1340#define QOS_PARAM_SET_DEF_OFDM 2341 342#define CTRL_QOS_NO_ACK (0x0020)343 344#define IPW_TX_QUEUE_1 1345#define IPW_TX_QUEUE_2 2346#define IPW_TX_QUEUE_3 3347#define IPW_TX_QUEUE_4 4348 349/* QoS sturctures */350struct ipw_qos_info {351 int qos_enable;352 struct libipw_qos_parameters *def_qos_parm_OFDM;353 struct libipw_qos_parameters *def_qos_parm_CCK;354 u32 burst_duration_CCK;355 u32 burst_duration_OFDM;356 u16 qos_no_ack_mask;357 int burst_enable;358};359 360/**************************************************************/361/**362 * Generic queue structure363 *364 * Contains common data for Rx and Tx queues365 */366struct clx2_queue {367 int n_bd; /**< number of BDs in this queue */368 int first_empty; /**< 1-st empty entry (index) */369 int last_used; /**< last used entry (index) */370 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */371 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */372 dma_addr_t dma_addr; /**< physical addr for BD's */373 int low_mark; /**< low watermark, resume queue if free space more than this */374 int high_mark; /**< high watermark, stop queue if free space less than this */375} __packed; /* XXX */376 377struct machdr32 {378 __le16 frame_ctl;379 __le16 duration; // watch out for endians!380 u8 addr1[MACADRR_BYTE_LEN];381 u8 addr2[MACADRR_BYTE_LEN];382 u8 addr3[MACADRR_BYTE_LEN];383 __le16 seq_ctrl; // more endians!384 u8 addr4[MACADRR_BYTE_LEN];385 __le16 qos_ctrl;386} __packed;387 388struct machdr30 {389 __le16 frame_ctl;390 __le16 duration; // watch out for endians!391 u8 addr1[MACADRR_BYTE_LEN];392 u8 addr2[MACADRR_BYTE_LEN];393 u8 addr3[MACADRR_BYTE_LEN];394 __le16 seq_ctrl; // more endians!395 u8 addr4[MACADRR_BYTE_LEN];396} __packed;397 398struct machdr26 {399 __le16 frame_ctl;400 __le16 duration; // watch out for endians!401 u8 addr1[MACADRR_BYTE_LEN];402 u8 addr2[MACADRR_BYTE_LEN];403 u8 addr3[MACADRR_BYTE_LEN];404 __le16 seq_ctrl; // more endians!405 __le16 qos_ctrl;406} __packed;407 408struct machdr24 {409 __le16 frame_ctl;410 __le16 duration; // watch out for endians!411 u8 addr1[MACADRR_BYTE_LEN];412 u8 addr2[MACADRR_BYTE_LEN];413 u8 addr3[MACADRR_BYTE_LEN];414 __le16 seq_ctrl; // more endians!415} __packed;416 417// TX TFD with 32 byte MAC Header418struct tx_tfd_32 {419 struct machdr32 mchdr; // 32420 __le32 uivplaceholder[2]; // 8421} __packed;422 423// TX TFD with 30 byte MAC Header424struct tx_tfd_30 {425 struct machdr30 mchdr; // 30426 u8 reserved[2]; // 2427 __le32 uivplaceholder[2]; // 8428} __packed;429 430// tx tfd with 26 byte mac header431struct tx_tfd_26 {432 struct machdr26 mchdr; // 26433 u8 reserved1[2]; // 2434 __le32 uivplaceholder[2]; // 8435 u8 reserved2[4]; // 4436} __packed;437 438// tx tfd with 24 byte mac header439struct tx_tfd_24 {440 struct machdr24 mchdr; // 24441 __le32 uivplaceholder[2]; // 8442 u8 reserved[8]; // 8443} __packed;444 445#define DCT_WEP_KEY_FIELD_LENGTH 16446 447struct tfd_command {448 u8 index;449 u8 length;450 __le16 reserved;451 u8 payload[];452} __packed;453 454struct tfd_data {455 /* Header */456 __le32 work_area_ptr;457 u8 station_number; /* 0 for BSS */458 u8 reserved1;459 __le16 reserved2;460 461 /* Tx Parameters */462 u8 cmd_id;463 u8 seq_num;464 __le16 len;465 u8 priority;466 u8 tx_flags;467 u8 tx_flags_ext;468 u8 key_index;469 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];470 u8 rate;471 u8 antenna;472 __le16 next_packet_duration;473 __le16 next_frag_len;474 __le16 back_off_counter; //////txop;475 u8 retrylimit;476 __le16 cwcurrent;477 u8 reserved3;478 479 /* 802.11 MAC Header */480 union {481 struct tx_tfd_24 tfd_24;482 struct tx_tfd_26 tfd_26;483 struct tx_tfd_30 tfd_30;484 struct tx_tfd_32 tfd_32;485 } tfd;486 487 /* Payload DMA info */488 __le32 num_chunks;489 __le32 chunk_ptr[NUM_TFD_CHUNKS];490 __le16 chunk_len[NUM_TFD_CHUNKS];491} __packed;492 493struct txrx_control_flags {494 u8 message_type;495 u8 rx_seq_num;496 u8 control_bits;497 u8 reserved;498} __packed;499 500#define TFD_SIZE 128501#define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))502 503struct tfd_frame {504 struct txrx_control_flags control_flags;505 union {506 struct tfd_data data;507 struct tfd_command cmd;508 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];509 } u;510} __packed;511 512typedef void destructor_func(const void *);513 514/**515 * Tx Queue for DMA. Queue consists of circular buffer of516 * BD's and required locking structures.517 */518struct clx2_tx_queue {519 struct clx2_queue q;520 struct tfd_frame *bd;521 struct libipw_txb **txb;522};523 524/*525 * RX related structures and functions526 */527#define RX_FREE_BUFFERS 32528#define RX_LOW_WATERMARK 8529 530#define SUP_RATE_11A_MAX_NUM_CHANNELS 8531#define SUP_RATE_11B_MAX_NUM_CHANNELS 4532#define SUP_RATE_11G_MAX_NUM_CHANNELS 12533 534// Used for passing to driver number of successes and failures per rate535struct rate_histogram {536 union {537 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];538 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];539 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];540 } success;541 union {542 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];543 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];544 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];545 } failed;546} __packed;547 548/* statistics command response */549struct ipw_cmd_stats {550 u8 cmd_id;551 u8 seq_num;552 __le16 good_sfd;553 __le16 bad_plcp;554 __le16 wrong_bssid;555 __le16 valid_mpdu;556 __le16 bad_mac_header;557 __le16 reserved_frame_types;558 __le16 rx_ina;559 __le16 bad_crc32;560 __le16 invalid_cts;561 __le16 invalid_acks;562 __le16 long_distance_ina_fina;563 __le16 dsp_silence_unreachable;564 __le16 accumulated_rssi;565 __le16 rx_ovfl_frame_tossed;566 __le16 rssi_silence_threshold;567 __le16 rx_ovfl_frame_supplied;568 __le16 last_rx_frame_signal;569 __le16 last_rx_frame_noise;570 __le16 rx_autodetec_no_ofdm;571 __le16 rx_autodetec_no_barker;572 __le16 reserved;573} __packed;574 575struct notif_channel_result {576 u8 channel_num;577 struct ipw_cmd_stats stats;578 u8 uReserved;579} __packed;580 581#define SCAN_COMPLETED_STATUS_COMPLETE 1582#define SCAN_COMPLETED_STATUS_ABORTED 2583 584struct notif_scan_complete {585 u8 scan_type;586 u8 num_channels;587 u8 status;588 u8 reserved;589} __packed;590 591struct notif_frag_length {592 __le16 frag_length;593 __le16 reserved;594} __packed;595 596struct notif_beacon_state {597 __le32 state;598 __le32 number;599} __packed;600 601struct notif_tgi_tx_key {602 u8 key_state;603 u8 security_type;604 u8 station_index;605 u8 reserved;606} __packed;607 608#define SILENCE_OVER_THRESH (1)609#define SILENCE_UNDER_THRESH (2)610 611struct notif_link_deterioration {612 struct ipw_cmd_stats stats;613 u8 rate;614 u8 modulation;615 struct rate_histogram histogram;616 u8 silence_notification_type; /* SILENCE_OVER/UNDER_THRESH */617 __le16 silence_count;618} __packed;619 620struct notif_association {621 u8 state;622} __packed;623 624struct notif_authenticate {625 u8 state;626 struct machdr24 addr;627 __le16 status;628} __packed;629 630struct notif_calibration {631 u8 data[104];632} __packed;633 634struct notif_noise {635 __le32 value;636} __packed;637 638struct ipw_rx_notification {639 u8 reserved[8];640 u8 subtype;641 u8 flags;642 __le16 size;643 union {644 struct notif_association assoc;645 struct notif_authenticate auth;646 struct notif_channel_result channel_result;647 struct notif_scan_complete scan_complete;648 struct notif_frag_length frag_len;649 struct notif_beacon_state beacon_state;650 struct notif_tgi_tx_key tgi_tx_key;651 struct notif_link_deterioration link_deterioration;652 struct notif_calibration calibration;653 struct notif_noise noise;654 DECLARE_FLEX_ARRAY(u8, raw);655 } u;656} __packed;657 658struct ipw_rx_frame {659 __le32 reserved1;660 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER661 u8 received_channel; // The channel that this frame was received on.662 // Note that for .11b this does not have to be663 // the same as the channel that it was sent.664 // Filled by LMAC665 u8 frameStatus;666 u8 rate;667 u8 rssi;668 u8 agc;669 u8 rssi_dbm;670 __le16 signal;671 __le16 noise;672 u8 antennaAndPhy;673 u8 control; // control bit should be on in bg674 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate675 // is identical)676 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen677 __le16 length;678 u8 data[];679} __packed;680 681struct ipw_rx_header {682 u8 message_type;683 u8 rx_seq_num;684 u8 control_bits;685 u8 reserved;686} __packed;687 688struct ipw_rx_packet {689 struct ipw_rx_header header;690 union {691 struct ipw_rx_frame frame;692 struct ipw_rx_notification notification;693 } u;694} __packed;695 696#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12697#define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \698 sizeof(struct ipw_rx_frame))699 700struct ipw_rx_mem_buffer {701 dma_addr_t dma_addr;702 struct sk_buff *skb;703 struct list_head list;704}; /* Not transferred over network, so not __packed */705 706struct ipw_rx_queue {707 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];708 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];709 u32 processed; /* Internal index to last handled Rx packet */710 u32 read; /* Shared index to newest available Rx buffer */711 u32 write; /* Shared index to oldest written Rx packet */712 u32 free_count; /* Number of pre-allocated buffers in rx_free */713 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */714 struct list_head rx_free; /* Own an SKBs */715 struct list_head rx_used; /* No SKB allocated */716 spinlock_t lock;717}; /* Not transferred over network, so not __packed */718 719struct alive_command_responce {720 u8 alive_command;721 u8 sequence_number;722 __le16 software_revision;723 u8 device_identifier;724 u8 reserved1[5];725 __le16 reserved2;726 __le16 reserved3;727 __le16 clock_settle_time;728 __le16 powerup_settle_time;729 __le16 reserved4;730 u8 time_stamp[5]; /* month, day, year, hours, minutes */731 u8 ucode_valid;732} __packed;733 734#define IPW_MAX_RATES 12735 736struct ipw_rates {737 u8 num_rates;738 u8 rates[IPW_MAX_RATES];739} __packed;740 741struct command_block {742 unsigned int control;743 u32 source_addr;744 u32 dest_addr;745 unsigned int status;746} __packed;747 748#define CB_NUMBER_OF_ELEMENTS_SMALL 64749struct fw_image_desc {750 unsigned long last_cb_index;751 unsigned long current_cb_index;752 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];753 void *v_addr;754 unsigned long p_addr;755 unsigned long len;756};757 758struct ipw_sys_config {759 u8 bt_coexistence;760 u8 reserved1;761 u8 answer_broadcast_ssid_probe;762 u8 accept_all_data_frames;763 u8 accept_non_directed_frames;764 u8 exclude_unicast_unencrypted;765 u8 disable_unicast_decryption;766 u8 exclude_multicast_unencrypted;767 u8 disable_multicast_decryption;768 u8 antenna_diversity;769 u8 pass_crc_to_host;770 u8 dot11g_auto_detection;771 u8 enable_cts_to_self;772 u8 enable_multicast_filtering;773 u8 bt_coexist_collision_thr;774 u8 silence_threshold;775 u8 accept_all_mgmt_bcpr;776 u8 accept_all_mgmt_frames;777 u8 pass_noise_stats_to_host;778 u8 reserved3;779} __packed;780 781struct ipw_multicast_addr {782 u8 num_of_multicast_addresses;783 u8 reserved[3];784 u8 mac1[6];785 u8 mac2[6];786 u8 mac3[6];787 u8 mac4[6];788} __packed;789 790#define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */791#define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */792 793#define DCW_WEP_KEY_SEC_TYPE_WEP 0x00794#define DCW_WEP_KEY_SEC_TYPE_CCM 0x20795#define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30796 797#define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */798#define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */799#define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */800#define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */801//#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */802 803struct ipw_wep_key {804 u8 cmd_id;805 u8 seq_num;806 u8 key_index;807 u8 key_size;808 u8 key[16];809} __packed;810 811struct ipw_tgi_tx_key {812 u8 key_id;813 u8 security_type;814 u8 station_index;815 u8 flags;816 u8 key[16];817 __le32 tx_counter[2];818} __packed;819 820#define IPW_SCAN_CHANNELS 54821 822struct ipw_scan_request {823 u8 scan_type;824 __le16 dwell_time;825 u8 channels_list[IPW_SCAN_CHANNELS];826 u8 channels_reserved[3];827} __packed;828 829enum {830 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,831 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,832 IPW_SCAN_ACTIVE_DIRECT_SCAN,833 IPW_SCAN_ACTIVE_BROADCAST_SCAN,834 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,835 IPW_SCAN_TYPES836};837 838struct ipw_scan_request_ext {839 __le32 full_scan_index;840 u8 channels_list[IPW_SCAN_CHANNELS];841 u8 scan_type[IPW_SCAN_CHANNELS / 2];842 u8 reserved;843 __le16 dwell_time[IPW_SCAN_TYPES];844} __packed;845 846static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)847{848 if (index % 2)849 return scan->scan_type[index / 2] & 0x0F;850 else851 return (scan->scan_type[index / 2] & 0xF0) >> 4;852}853 854static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,855 u8 index, u8 scan_type)856{857 if (index % 2)858 scan->scan_type[index / 2] =859 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);860 else861 scan->scan_type[index / 2] =862 (scan->scan_type[index / 2] & 0x0F) |863 ((scan_type & 0x0F) << 4);864}865 866struct ipw_associate {867 u8 channel;868#ifdef __LITTLE_ENDIAN_BITFIELD869 u8 auth_type:4, auth_key:4;870#else871 u8 auth_key:4, auth_type:4;872#endif873 u8 assoc_type;874 u8 reserved;875 __le16 policy_support;876 u8 preamble_length;877 u8 ieee_mode;878 u8 bssid[ETH_ALEN];879 __le32 assoc_tsf_msw;880 __le32 assoc_tsf_lsw;881 __le16 capability;882 __le16 listen_interval;883 __le16 beacon_interval;884 u8 dest[ETH_ALEN];885 __le16 atim_window;886 u8 smr;887 u8 reserved1;888 __le16 reserved2;889} __packed;890 891struct ipw_supported_rates {892 u8 ieee_mode;893 u8 num_rates;894 u8 purpose;895 u8 reserved;896 u8 supported_rates[IPW_MAX_RATES];897} __packed;898 899struct ipw_rts_threshold {900 __le16 rts_threshold;901 __le16 reserved;902} __packed;903 904struct ipw_frag_threshold {905 __le16 frag_threshold;906 __le16 reserved;907} __packed;908 909struct ipw_retry_limit {910 u8 short_retry_limit;911 u8 long_retry_limit;912 __le16 reserved;913} __packed;914 915struct ipw_dino_config {916 __le32 dino_config_addr;917 __le16 dino_config_size;918 u8 dino_response;919 u8 reserved;920} __packed;921 922struct ipw_aironet_info {923 u8 id;924 u8 length;925 __le16 reserved;926} __packed;927 928struct ipw_rx_key {929 u8 station_index;930 u8 key_type;931 u8 key_id;932 u8 key_flag;933 u8 key[16];934 u8 station_address[6];935 u8 key_index;936 u8 reserved;937} __packed;938 939struct ipw_country_channel_info {940 u8 first_channel;941 u8 no_channels;942 s8 max_tx_power;943} __packed;944 945struct ipw_country_info {946 u8 id;947 u8 length;948 u8 country_str[IEEE80211_COUNTRY_STRING_LEN];949 struct ipw_country_channel_info groups[7];950} __packed;951 952struct ipw_channel_tx_power {953 u8 channel_number;954 s8 tx_power;955} __packed;956 957#define SCAN_ASSOCIATED_INTERVAL (HZ)958#define SCAN_INTERVAL (HZ / 10)959#define MAX_A_CHANNELS 37960#define MAX_B_CHANNELS 14961 962struct ipw_tx_power {963 u8 num_channels;964 u8 ieee_mode;965 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];966} __packed;967 968struct ipw_rsn_capabilities {969 u8 id;970 u8 length;971 __le16 version;972} __packed;973 974struct ipw_sensitivity_calib {975 __le16 beacon_rssi_raw;976 __le16 reserved;977} __packed;978 979/**980 * Host command structure.981 *982 * On input, the following fields should be filled:983 * - cmd984 * - len985 * - status_len986 * - param (if needed)987 *988 * On output,989 * - \a status contains status;990 * - \a param filled with status parameters.991 */992struct ipw_cmd { /* XXX */993 u32 cmd; /**< Host command */994 u32 status;/**< Status */995 u32 status_len;996 /**< How many 32 bit parameters in the status */997 u32 len; /**< incoming parameters length, bytes */998 /**999 * command parameters.1000 * There should be enough space for incoming and1001 * outcoming parameters.1002 * Incoming parameters listed 1-st, followed by outcoming params.1003 * nParams=(len+3)/4+status_len1004 */1005 u32 param[];1006} __packed;1007 1008#define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */1009 1010#define STATUS_INT_ENABLED (1<<1)1011#define STATUS_RF_KILL_HW (1<<2)1012#define STATUS_RF_KILL_SW (1<<3)1013#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)1014 1015#define STATUS_INIT (1<<5)1016#define STATUS_AUTH (1<<6)1017#define STATUS_ASSOCIATED (1<<7)1018#define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)1019 1020#define STATUS_ASSOCIATING (1<<8)1021#define STATUS_DISASSOCIATING (1<<9)1022#define STATUS_ROAMING (1<<10)1023#define STATUS_EXIT_PENDING (1<<11)1024#define STATUS_DISASSOC_PENDING (1<<12)1025#define STATUS_STATE_PENDING (1<<13)1026 1027#define STATUS_DIRECT_SCAN_PENDING (1<<19)1028#define STATUS_SCAN_PENDING (1<<20)1029#define STATUS_SCANNING (1<<21)1030#define STATUS_SCAN_ABORTING (1<<22)1031#define STATUS_SCAN_FORCED (1<<23)1032 1033#define STATUS_LED_LINK_ON (1<<24)1034#define STATUS_LED_ACT_ON (1<<25)1035 1036#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */1037#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */1038#define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */1039 1040#define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */1041 1042#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */1043#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */1044#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */1045#define CFG_CUSTOM_MAC (1<<3)1046#define CFG_PREAMBLE_LONG (1<<4)1047#define CFG_ADHOC_PERSIST (1<<5)1048#define CFG_ASSOCIATE (1<<6)1049#define CFG_FIXED_RATE (1<<7)1050#define CFG_ADHOC_CREATE (1<<8)1051#define CFG_NO_LED (1<<9)1052#define CFG_BACKGROUND_SCAN (1<<10)1053#define CFG_SPEED_SCAN (1<<11)1054#define CFG_NET_STATS (1<<12)1055 1056#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */1057#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */1058 1059#define MAX_STATIONS 321060#define IPW_INVALID_STATION (0xff)1061 1062struct ipw_station_entry {1063 u8 mac_addr[ETH_ALEN];1064 u8 reserved;1065 u8 support_mode;1066};1067 1068#define AVG_ENTRIES 81069struct average {1070 s16 entries[AVG_ENTRIES];1071 u8 pos;1072 u8 init;1073 s32 sum;1074};1075 1076#define MAX_SPEED_SCAN 1001077#define IPW_IBSS_MAC_HASH_SIZE 311078 1079struct ipw_ibss_seq {1080 u8 mac[ETH_ALEN];1081 u16 seq_num;1082 u16 frag_num;1083 unsigned long packet_time;1084 struct list_head list;1085};1086 1087struct ipw_error_elem { /* XXX */1088 u32 desc;1089 u32 time;1090 u32 blink1;1091 u32 blink2;1092 u32 link1;1093 u32 link2;1094 u32 data;1095};1096 1097struct ipw_event { /* XXX */1098 u32 event;1099 u32 time;1100 u32 data;1101} __packed;1102 1103struct ipw_fw_error { /* XXX */1104 unsigned long jiffies;1105 u32 status;1106 u32 config;1107 u32 elem_len;1108 u32 log_len;1109 struct ipw_event *log;1110 struct ipw_error_elem elem[];1111} __packed;1112 1113#ifdef CONFIG_IPW2200_PROMISCUOUS1114 1115enum ipw_prom_filter {1116 IPW_PROM_CTL_HEADER_ONLY = (1 << 0),1117 IPW_PROM_MGMT_HEADER_ONLY = (1 << 1),1118 IPW_PROM_DATA_HEADER_ONLY = (1 << 2),1119 IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */1120 IPW_PROM_NO_TX = (1 << 4),1121 IPW_PROM_NO_RX = (1 << 5),1122 IPW_PROM_NO_CTL = (1 << 6),1123 IPW_PROM_NO_MGMT = (1 << 7),1124 IPW_PROM_NO_DATA = (1 << 8),1125};1126 1127struct ipw_priv;1128struct ipw_prom_priv {1129 struct ipw_priv *priv;1130 struct libipw_device *ieee;1131 enum ipw_prom_filter filter;1132 int tx_packets;1133 int rx_packets;1134};1135#endif1136 1137#if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS)1138/* Magic struct that slots into the radiotap header -- no reason1139 * to build this manually element by element, we can write it much1140 * more efficiently than we can parse it. ORDER MATTERS HERE1141 *1142 * When sent to us via the simulated Rx interface in sysfs, the entire1143 * structure is provided regardless of any bits unset.1144 */1145struct ipw_rt_hdr {1146 struct ieee80211_radiotap_header_fixed rt_hdr;1147 u64 rt_tsf; /* TSF */ /* XXX */1148 u8 rt_flags; /* radiotap packet flags */1149 u8 rt_rate; /* rate in 500kb/s */1150 __le16 rt_channel; /* channel in mhz */1151 __le16 rt_chbitmask; /* channel bitfield */1152 s8 rt_dbmsignal; /* signal in dbM, kluged to signed */1153 s8 rt_dbmnoise;1154 u8 rt_antenna; /* antenna number */1155 u8 payload[]; /* payload... */1156} __packed;1157#endif1158 1159struct ipw_priv {1160 /* ieee device used by generic ieee processing code */1161 struct libipw_device *ieee;1162 1163 spinlock_t lock;1164 spinlock_t irq_lock;1165 struct mutex mutex;1166 1167 /* basic pci-network driver stuff */1168 struct pci_dev *pci_dev;1169 struct net_device *net_dev;1170 1171#ifdef CONFIG_IPW2200_PROMISCUOUS1172 /* Promiscuous mode */1173 struct ipw_prom_priv *prom_priv;1174 struct net_device *prom_net_dev;1175#endif1176 1177 /* pci hardware address support */1178 void __iomem *hw_base;1179 unsigned long hw_len;1180 1181 struct fw_image_desc sram_desc;1182 1183 /* result of ucode download */1184 struct alive_command_responce dino_alive;1185 1186 wait_queue_head_t wait_command_queue;1187 wait_queue_head_t wait_state;1188 1189 /* Rx and Tx DMA processing queues */1190 struct ipw_rx_queue *rxq;1191 struct clx2_tx_queue txq_cmd;1192 struct clx2_tx_queue txq[4];1193 u32 status;1194 u32 config;1195 u32 capability;1196 1197 struct average average_missed_beacons;1198 s16 exp_avg_rssi;1199 s16 exp_avg_noise;1200 u32 port_type;1201 int rx_bufs_min; /**< minimum number of bufs in Rx queue */1202 int rx_pend_max; /**< maximum pending buffers for one IRQ */1203 u32 hcmd_seq; /**< sequence number for hcmd */1204 u32 disassociate_threshold;1205 u32 roaming_threshold;1206 1207 struct ipw_associate assoc_request;1208 struct libipw_network *assoc_network;1209 1210 unsigned long ts_scan_abort;1211 struct ipw_supported_rates rates;1212 struct ipw_rates phy[3]; /**< PHY restrictions, per band */1213 struct ipw_rates supp; /**< software defined */1214 struct ipw_rates extended; /**< use for corresp. IE, AP only */1215 1216 struct notif_link_deterioration last_link_deterioration; /** for statistics */1217 struct ipw_cmd *hcmd; /**< host command currently executed */1218 1219 wait_queue_head_t hcmd_wq; /**< host command waits for execution */1220 u32 tsf_bcn[2]; /**< TSF from latest beacon */1221 1222 struct notif_calibration calib; /**< last calibration */1223 1224 /* ordinal interface with firmware */1225 u32 table0_addr;1226 u32 table0_len;1227 u32 table1_addr;1228 u32 table1_len;1229 u32 table2_addr;1230 u32 table2_len;1231 1232 /* context information */1233 u8 essid[IW_ESSID_MAX_SIZE];1234 u8 essid_len;1235 u8 nick[IW_ESSID_MAX_SIZE];1236 u16 rates_mask;1237 u8 channel;1238 struct ipw_sys_config sys_config;1239 u32 power_mode;1240 u8 bssid[ETH_ALEN];1241 u16 rts_threshold;1242 u8 mac_addr[ETH_ALEN];1243 u8 num_stations;1244 u8 stations[MAX_STATIONS][ETH_ALEN];1245 u8 short_retry_limit;1246 u8 long_retry_limit;1247 1248 u32 notif_missed_beacons;1249 1250 /* Statistics and counters normalized with each association */1251 u32 last_missed_beacons;1252 u32 last_tx_packets;1253 u32 last_rx_packets;1254 u32 last_tx_failures;1255 u32 last_rx_err;1256 u32 last_rate;1257 1258 u32 missed_adhoc_beacons;1259 u32 missed_beacons;1260 u32 rx_packets;1261 u32 tx_packets;1262 u32 quality;1263 1264 u8 speed_scan[MAX_SPEED_SCAN];1265 u8 speed_scan_pos;1266 1267 u16 last_seq_num;1268 u16 last_frag_num;1269 unsigned long last_packet_time;1270 struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];1271 1272 /* eeprom */1273 u8 eeprom[0x100]; /* 256 bytes of eeprom */1274 u8 country[4];1275 int eeprom_delay;1276 1277 struct iw_statistics wstats;1278 1279 struct iw_public_data wireless_data;1280 1281 int user_requested_scan;1282 u8 direct_scan_ssid[IW_ESSID_MAX_SIZE];1283 u8 direct_scan_ssid_len;1284 1285 struct delayed_work adhoc_check;1286 struct work_struct associate;1287 struct work_struct disassociate;1288 struct work_struct system_config;1289 struct work_struct rx_replenish;1290 struct delayed_work request_scan;1291 struct delayed_work request_direct_scan;1292 struct delayed_work request_passive_scan;1293 struct delayed_work scan_event;1294 struct work_struct adapter_restart;1295 struct delayed_work rf_kill;1296 struct work_struct up;1297 struct work_struct down;1298 struct delayed_work gather_stats;1299 struct work_struct abort_scan;1300 struct work_struct roam;1301 struct delayed_work scan_check;1302 struct work_struct link_up;1303 struct work_struct link_down;1304 1305 struct tasklet_struct irq_tasklet;1306 1307 /* LED related variables and work_struct */1308 u8 nic_type;1309 u32 led_activity_on;1310 u32 led_activity_off;1311 u32 led_association_on;1312 u32 led_association_off;1313 u32 led_ofdm_on;1314 u32 led_ofdm_off;1315 1316 struct delayed_work led_link_on;1317 struct delayed_work led_link_off;1318 struct delayed_work led_act_off;1319 struct work_struct merge_networks;1320 1321 struct ipw_cmd_log *cmdlog;1322 int cmdlog_len;1323 int cmdlog_pos;1324 1325#define IPW_2200BG 11326#define IPW_2915ABG 21327 u8 adapter;1328 1329 s8 tx_power;1330 1331 /* Track time in suspend using CLOCK_BOOTTIME */1332 time64_t suspend_at;1333 time64_t suspend_time;1334 1335#ifdef CONFIG_PM1336 u32 pm_state[16];1337#endif1338 1339 struct ipw_fw_error *error;1340 1341 /* network state */1342 1343 /* Used to pass the current INTA value from ISR to Tasklet */1344 u32 isr_inta;1345 1346 /* QoS */1347 struct ipw_qos_info qos_data;1348 struct work_struct qos_activate;1349 /*********************************/1350 1351 /* debugging info */1352 u32 indirect_dword;1353 u32 direct_dword;1354 u32 indirect_byte;1355}; /*ipw_priv */1356 1357/* debug macros */1358 1359/* Debug and printf string expansion helpers for printing bitfields */1360#define BIT_FMT8 "%c%c%c%c-%c%c%c%c"1361#define BIT_FMT16 BIT_FMT8 ":" BIT_FMT81362#define BIT_FMT32 BIT_FMT16 " " BIT_FMT161363 1364#define BITC(x,y) (((x>>y)&1)?'1':'0')1365#define BIT_ARG8(x) \1366BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\1367BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)1368 1369#define BIT_ARG16(x) \1370BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\1371BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\1372BIT_ARG8(x)1373 1374#define BIT_ARG32(x) \1375BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\1376BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\1377BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\1378BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\1379BIT_ARG16(x)1380 1381 1382#define IPW_DEBUG(level, fmt, args...) \1383do { if (ipw_debug_level & (level)) \1384 printk(KERN_DEBUG DRV_NAME": %s " fmt, __func__ , ## args); } while (0)1385 1386#ifdef CONFIG_IPW2200_DEBUG1387#define IPW_LL_DEBUG(level, fmt, args...) \1388do { if (ipw_debug_level & (level)) \1389 printk(KERN_DEBUG DRV_NAME": %s " fmt, __func__ , ## args); } while (0)1390#else1391#define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)1392#endif /* CONFIG_IPW2200_DEBUG */1393 1394/*1395 * To use the debug system;1396 *1397 * If you are defining a new debug classification, simply add it to the #define1398 * list here in the form of:1399 *1400 * #define IPW_DL_xxxx VALUE1401 *1402 * shifting value to the left one bit from the previous entry. xxxx should be1403 * the name of the classification (for example, WEP)1404 *1405 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your1406 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want1407 * to send output to that classification.1408 *1409 * To add your debug level to the list of levels seen when you perform1410 *1411 * % cat /proc/net/ipw/debug_level1412 *1413 * you simply need to add your entry to the ipw_debug_levels array.1414 *1415 * If you do not see debug_level in /proc/net/ipw then you do not have1416 * CONFIG_IPW2200_DEBUG defined in your kernel configuration1417 *1418 */1419 1420#define IPW_DL_ERROR (1<<0)1421#define IPW_DL_WARNING (1<<1)1422#define IPW_DL_INFO (1<<2)1423#define IPW_DL_WX (1<<3)1424#define IPW_DL_HOST_COMMAND (1<<5)1425#define IPW_DL_STATE (1<<6)1426 1427#define IPW_DL_NOTIF (1<<10)1428#define IPW_DL_SCAN (1<<11)1429#define IPW_DL_ASSOC (1<<12)1430#define IPW_DL_DROP (1<<13)1431#define IPW_DL_IOCTL (1<<14)1432 1433#define IPW_DL_MANAGE (1<<15)1434#define IPW_DL_FW (1<<16)1435#define IPW_DL_RF_KILL (1<<17)1436#define IPW_DL_FW_ERRORS (1<<18)1437 1438#define IPW_DL_LED (1<<19)1439 1440#define IPW_DL_ORD (1<<20)1441 1442#define IPW_DL_FRAG (1<<21)1443#define IPW_DL_WEP (1<<22)1444#define IPW_DL_TX (1<<23)1445#define IPW_DL_RX (1<<24)1446#define IPW_DL_ISR (1<<25)1447#define IPW_DL_FW_INFO (1<<26)1448#define IPW_DL_IO (1<<27)1449#define IPW_DL_TRACE (1<<28)1450 1451#define IPW_DL_STATS (1<<29)1452#define IPW_DL_MERGE (1<<30)1453#define IPW_DL_QOS (1<<31)1454 1455#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)1456#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)1457#define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)1458 1459#define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)1460#define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)1461#define IPW_DEBUG_TRACE(f, a...) IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a)1462#define IPW_DEBUG_RX(f, a...) IPW_LL_DEBUG(IPW_DL_RX, f, ## a)1463#define IPW_DEBUG_TX(f, a...) IPW_LL_DEBUG(IPW_DL_TX, f, ## a)1464#define IPW_DEBUG_ISR(f, a...) IPW_LL_DEBUG(IPW_DL_ISR, f, ## a)1465#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)1466#define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a)1467#define IPW_DEBUG_WEP(f, a...) IPW_LL_DEBUG(IPW_DL_WEP, f, ## a)1468#define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)1469#define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a)1470#define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a)1471#define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)1472#define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)1473#define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a)1474#define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a)1475#define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a)1476#define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)1477#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)1478#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)1479#define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a)1480#define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a)1481#define IPW_DEBUG_QOS(f, a...) IPW_LL_DEBUG(IPW_DL_QOS, f, ## a)1482 1483#include <linux/ctype.h>1484 1485/*1486* Register bit definitions1487*/1488 1489#define IPW_INTA_RW 0x000000081490#define IPW_INTA_MASK_R 0x0000000C1491#define IPW_INDIRECT_ADDR 0x000000101492#define IPW_INDIRECT_DATA 0x000000141493#define IPW_AUTOINC_ADDR 0x000000181494#define IPW_AUTOINC_DATA 0x0000001C1495#define IPW_RESET_REG 0x000000201496#define IPW_GP_CNTRL_RW 0x000000241497 1498#define IPW_READ_INT_REGISTER 0xFF41499 1500#define IPW_GP_CNTRL_BIT_INIT_DONE 0x000000041501 1502#define IPW_REGISTER_DOMAIN1_END 0x000010001503#define IPW_SRAM_READ_INT_REGISTER 0x00000ff41504 1505#define IPW_SHARED_LOWER_BOUND 0x000002001506#define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f801507 1508#define IPW_NIC_SRAM_LOWER_BOUND 0x000000001509#define IPW_NIC_SRAM_UPPER_BOUND 0x000300001510 1511#define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)1512#define IPW_GP_CNTRL_BIT_CLOCK_READY 0x000000011513#define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x000000021514 1515/*1516 * RESET Register Bit Indexes1517 */1518#define CBD_RESET_REG_PRINCETON_RESET (1<<0)1519#define IPW_START_STANDBY (1<<2)1520#define IPW_ACTIVITY_LED (1<<4)1521#define IPW_ASSOCIATED_LED (1<<5)1522#define IPW_OFDM_LED (1<<6)1523#define IPW_RESET_REG_SW_RESET (1<<7)1524#define IPW_RESET_REG_MASTER_DISABLED (1<<8)1525#define IPW_RESET_REG_STOP_MASTER (1<<9)1526#define IPW_GATE_ODMA (1<<25)1527#define IPW_GATE_IDMA (1<<26)1528#define IPW_ARC_KESHET_CONFIG (1<<27)1529#define IPW_GATE_ADMA (1<<29)1530 1531#define IPW_CSR_CIS_UPPER_BOUND 0x000002001532#define IPW_DOMAIN_0_END 0x10001533#define CLX_MEM_BAR_SIZE 0x10001534 1535/* Dino/baseband control registers bits */1536 1537#define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */1538#define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */1539#define DINO_RXFIFO_DATA 0x01 /* 1 = data available */1540#define IPW_BASEBAND_CONTROL_STATUS 0X002000001541#define IPW_BASEBAND_TX_FIFO_WRITE 0X002000041542#define IPW_BASEBAND_RX_FIFO_READ 0X002000041543#define IPW_BASEBAND_CONTROL_STORE 0X002000101544 1545#define IPW_INTERNAL_CMD_EVENT 0X003000041546#define IPW_BASEBAND_POWER_DOWN 0x000000011547 1548#define IPW_MEM_HALT_AND_RESET 0x003000e01549 1550/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */1551#define IPW_BIT_HALT_RESET_ON 0x800000001552#define IPW_BIT_HALT_RESET_OFF 0x000000001553 1554#define CB_LAST_VALID 0x200000001555#define CB_INT_ENABLED 0x400000001556#define CB_VALID 0x800000001557#define CB_SRC_LE 0x080000001558#define CB_DEST_LE 0x040000001559#define CB_SRC_AUTOINC 0x008000001560#define CB_SRC_IO_GATED 0x004000001561#define CB_DEST_AUTOINC 0x000800001562#define CB_SRC_SIZE_LONG 0x002000001563#define CB_DEST_SIZE_LONG 0x000200001564 1565/* DMA DEFINES */1566 1567#define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x005400001568#define DMA_CB_STOP_AND_ABORT 0x00000C001569#define DMA_CB_START 0x000001001570 1571#define IPW_SHARED_SRAM_SIZE 0x000300001572#define IPW_SHARED_SRAM_DMA_CONTROL 0x000270001573#define CB_MAX_LENGTH 0x1FFF1574 1575#define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA181576#define IPW_EEPROM_IMAGE_SIZE 0x1001577 1578/* DMA defs */1579#define IPW_DMA_I_CURRENT_CB 0x003000D01580#define IPW_DMA_O_CURRENT_CB 0x003000D41581#define IPW_DMA_I_DMA_CONTROL 0x003000A41582#define IPW_DMA_I_CB_BASE 0x003000A01583 1584#define IPW_TX_CMD_QUEUE_BD_BASE 0x000002001585#define IPW_TX_CMD_QUEUE_BD_SIZE 0x000002041586#define IPW_TX_QUEUE_0_BD_BASE 0x000002081587#define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)1588#define IPW_TX_QUEUE_1_BD_BASE 0x000002101589#define IPW_TX_QUEUE_1_BD_SIZE 0x000002141590#define IPW_TX_QUEUE_2_BD_BASE 0x000002181591#define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)1592#define IPW_TX_QUEUE_3_BD_BASE 0x000002201593#define IPW_TX_QUEUE_3_BD_SIZE 0x000002241594#define IPW_RX_BD_BASE 0x000002401595#define IPW_RX_BD_SIZE 0x000002441596#define IPW_RFDS_TABLE_LOWER 0x000005001597 1598#define IPW_TX_CMD_QUEUE_READ_INDEX 0x000002801599#define IPW_TX_QUEUE_0_READ_INDEX 0x000002841600#define IPW_TX_QUEUE_1_READ_INDEX 0x000002881601#define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)1602#define IPW_TX_QUEUE_3_READ_INDEX 0x000002901603#define IPW_RX_READ_INDEX (0x000002A0)1604 1605#define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)1606#define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)1607#define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)1608#define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)1609#define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)1610#define IPW_RX_WRITE_INDEX (0x00000FA0)1611 1612/*1613 * EEPROM Related Definitions1614 */1615 1616#define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)1617#define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)1618#define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)1619#define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)1620#define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)1621 1622#define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)1623#define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)1624#define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)1625#define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)1626#define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)1627#define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)1628 1629#define MSB 11630#define LSB 01631#define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))1632 1633#define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \1634 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )1635 1636/* EEPROM access by BYTE */1637#define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */1638#define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */1639#define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */1640#define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */1641#define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */1642#define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */1643#define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */1644#define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */1645#define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */1646#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */1647 1648/* NIC type as found in the one byte EEPROM_NIC_TYPE offset */1649#define EEPROM_NIC_TYPE_0 01650#define EEPROM_NIC_TYPE_1 11651#define EEPROM_NIC_TYPE_2 21652#define EEPROM_NIC_TYPE_3 31653#define EEPROM_NIC_TYPE_4 41654 1655/* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */1656#define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */1657#define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */1658#define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */1659 1660#define FW_MEM_REG_LOWER_BOUND 0x003000001661#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)1662#define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)1663#define EEPROM_BIT_SK (1<<0)1664#define EEPROM_BIT_CS (1<<1)1665#define EEPROM_BIT_DI (1<<2)1666#define EEPROM_BIT_DO (1<<4)1667 1668#define EEPROM_CMD_READ 0x21669 1670/* Interrupts masks */1671#define IPW_INTA_NONE 0x000000001672 1673#define IPW_INTA_BIT_RX_TRANSFER 0x000000021674#define IPW_INTA_BIT_STATUS_CHANGE 0x000000101675#define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x000000201676 1677//Inta Bits for CF1678#define IPW_INTA_BIT_TX_CMD_QUEUE 0x000008001679#define IPW_INTA_BIT_TX_QUEUE_1 0x000010001680#define IPW_INTA_BIT_TX_QUEUE_2 0x000020001681#define IPW_INTA_BIT_TX_QUEUE_3 0x000040001682#define IPW_INTA_BIT_TX_QUEUE_4 0x000080001683 1684#define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x000100001685 1686#define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x001000001687#define IPW_INTA_BIT_POWER_DOWN 0x002000001688 1689#define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x010000001690#define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x020000001691#define IPW_INTA_BIT_RF_KILL_DONE 0x040000001692#define IPW_INTA_BIT_FATAL_ERROR 0x400000001693#define IPW_INTA_BIT_PARITY_ERROR 0x800000001694 1695/* Interrupts enabled at init time. */1696#define IPW_INTA_MASK_ALL \1697 (IPW_INTA_BIT_TX_QUEUE_1 | \1698 IPW_INTA_BIT_TX_QUEUE_2 | \1699 IPW_INTA_BIT_TX_QUEUE_3 | \1700 IPW_INTA_BIT_TX_QUEUE_4 | \1701 IPW_INTA_BIT_TX_CMD_QUEUE | \1702 IPW_INTA_BIT_RX_TRANSFER | \1703 IPW_INTA_BIT_FATAL_ERROR | \1704 IPW_INTA_BIT_PARITY_ERROR | \1705 IPW_INTA_BIT_STATUS_CHANGE | \1706 IPW_INTA_BIT_FW_INITIALIZATION_DONE | \1707 IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \1708 IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \1709 IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \1710 IPW_INTA_BIT_POWER_DOWN | \1711 IPW_INTA_BIT_RF_KILL_DONE )1712 1713/* FW event log definitions */1714#define EVENT_ELEM_SIZE (3 * sizeof(u32))1715#define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))1716 1717/* FW error log definitions */1718#define ERROR_ELEM_SIZE (7 * sizeof(u32))1719#define ERROR_START_OFFSET (1 * sizeof(u32))1720 1721/* TX power level (dbm) */1722#define IPW_TX_POWER_MIN -121723#define IPW_TX_POWER_MAX 201724#define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX1725 1726enum {1727 IPW_FW_ERROR_OK = 0,1728 IPW_FW_ERROR_FAIL,1729 IPW_FW_ERROR_MEMORY_UNDERFLOW,1730 IPW_FW_ERROR_MEMORY_OVERFLOW,1731 IPW_FW_ERROR_BAD_PARAM,1732 IPW_FW_ERROR_BAD_CHECKSUM,1733 IPW_FW_ERROR_NMI_INTERRUPT,1734 IPW_FW_ERROR_BAD_DATABASE,1735 IPW_FW_ERROR_ALLOC_FAIL,1736 IPW_FW_ERROR_DMA_UNDERRUN,1737 IPW_FW_ERROR_DMA_STATUS,1738 IPW_FW_ERROR_DINO_ERROR,1739 IPW_FW_ERROR_EEPROM_ERROR,1740 IPW_FW_ERROR_SYSASSERT,1741 IPW_FW_ERROR_FATAL_ERROR1742};1743 1744#define AUTH_OPEN 01745#define AUTH_SHARED_KEY 11746#define AUTH_LEAP 21747#define AUTH_IGNORE 31748 1749#define HC_ASSOCIATE 01750#define HC_REASSOCIATE 11751#define HC_DISASSOCIATE 21752#define HC_IBSS_START 31753#define HC_IBSS_RECONF 41754#define HC_DISASSOC_QUIET 51755 1756#define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01)1757 1758#define IPW_RATE_CAPABILITIES 11759#define IPW_RATE_CONNECT 01760 1761/*1762 * Rate values and masks1763 */1764#define IPW_TX_RATE_1MB 0x0A1765#define IPW_TX_RATE_2MB 0x141766#define IPW_TX_RATE_5MB 0x371767#define IPW_TX_RATE_6MB 0x0D1768#define IPW_TX_RATE_9MB 0x0F1769#define IPW_TX_RATE_11MB 0x6E1770#define IPW_TX_RATE_12MB 0x051771#define IPW_TX_RATE_18MB 0x071772#define IPW_TX_RATE_24MB 0x091773#define IPW_TX_RATE_36MB 0x0B1774#define IPW_TX_RATE_48MB 0x011775#define IPW_TX_RATE_54MB 0x031776 1777#define IPW_ORD_TABLE_ID_MASK 0x0000FF001778#define IPW_ORD_TABLE_VALUE_MASK 0x000000FF1779 1780#define IPW_ORD_TABLE_0_MASK 0x0000F0001781#define IPW_ORD_TABLE_1_MASK 0x0000F1001782#define IPW_ORD_TABLE_2_MASK 0x0000F2001783#define IPW_ORD_TABLE_3_MASK 0x0000F3001784#define IPW_ORD_TABLE_4_MASK 0x0000F4001785#define IPW_ORD_TABLE_5_MASK 0x0000F5001786#define IPW_ORD_TABLE_6_MASK 0x0000F6001787#define IPW_ORD_TABLE_7_MASK 0x0000F7001788 1789/*1790 * Table 0 Entries (all entries are 32 bits)1791 */1792enum {1793 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,1794 IPW_ORD_STAT_FRAG_TRESHOLD,1795 IPW_ORD_STAT_RTS_THRESHOLD,1796 IPW_ORD_STAT_TX_HOST_REQUESTS,1797 IPW_ORD_STAT_TX_HOST_COMPLETE,1798 IPW_ORD_STAT_TX_DIR_DATA,1799 IPW_ORD_STAT_TX_DIR_DATA_B_1,1800 IPW_ORD_STAT_TX_DIR_DATA_B_2,1801 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,1802 IPW_ORD_STAT_TX_DIR_DATA_B_11,1803 /* Hole */1804 1805 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,1806 IPW_ORD_STAT_TX_DIR_DATA_G_2,1807 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,1808 IPW_ORD_STAT_TX_DIR_DATA_G_6,1809 IPW_ORD_STAT_TX_DIR_DATA_G_9,1810 IPW_ORD_STAT_TX_DIR_DATA_G_11,1811 IPW_ORD_STAT_TX_DIR_DATA_G_12,1812 IPW_ORD_STAT_TX_DIR_DATA_G_18,1813 IPW_ORD_STAT_TX_DIR_DATA_G_24,1814 IPW_ORD_STAT_TX_DIR_DATA_G_36,1815 IPW_ORD_STAT_TX_DIR_DATA_G_48,1816 IPW_ORD_STAT_TX_DIR_DATA_G_54,1817 IPW_ORD_STAT_TX_NON_DIR_DATA,1818 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,1819 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,1820 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,1821 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,1822 /* Hole */1823 1824 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,1825 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,1826 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,1827 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,1828 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,1829 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,1830 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,1831 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,1832 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,1833 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,1834 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,1835 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,1836 IPW_ORD_STAT_TX_RETRY,1837 IPW_ORD_STAT_TX_FAILURE,1838 IPW_ORD_STAT_RX_ERR_CRC,1839 IPW_ORD_STAT_RX_ERR_ICV,1840 IPW_ORD_STAT_RX_NO_BUFFER,1841 IPW_ORD_STAT_FULL_SCANS,1842 IPW_ORD_STAT_PARTIAL_SCANS,1843 IPW_ORD_STAT_TGH_ABORTED_SCANS,1844 IPW_ORD_STAT_TX_TOTAL_BYTES,1845 IPW_ORD_STAT_CURR_RSSI_RAW,1846 IPW_ORD_STAT_RX_BEACON,1847 IPW_ORD_STAT_MISSED_BEACONS,1848 IPW_ORD_TABLE_0_LAST1849};1850 1851#define IPW_RSSI_TO_DBM 1121852 1853/* Table 1 Entries1854 */1855enum {1856 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,1857};1858 1859/*1860 * Table 2 Entries1861 *1862 * FW_VERSION: 16 byte string1863 * FW_DATE: 16 byte string (only 14 bytes used)1864 * UCODE_VERSION: 4 byte version code1865 * UCODE_DATE: 5 bytes code code1866 * ADDAPTER_MAC: 6 byte MAC address1867 * RTC: 4 byte clock1868 */1869enum {1870 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,1871 IPW_ORD_STAT_FW_DATE,1872 IPW_ORD_STAT_UCODE_VERSION,1873 IPW_ORD_STAT_UCODE_DATE,1874 IPW_ORD_STAT_ADAPTER_MAC,1875 IPW_ORD_STAT_RTC,1876 IPW_ORD_TABLE_2_LAST1877};1878 1879/* Table 3 */1880enum {1881 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,1882 IPW_ORD_STAT_TX_PACKET_FAILURE,1883 IPW_ORD_STAT_TX_PACKET_SUCCESS,1884 IPW_ORD_STAT_TX_PACKET_ABORTED,1885 IPW_ORD_TABLE_3_LAST1886};1887 1888/* Table 4 */1889enum {1890 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK1891};1892 1893/* Table 5 */1894enum {1895 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,1896 IPW_ORD_STAT_AP_ASSNS,1897 IPW_ORD_STAT_ROAM,1898 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,1899 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,1900 IPW_ORD_STAT_ROAM_CAUSE_RSSI,1901 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,1902 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,1903 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,1904 IPW_ORD_STAT_LINK_UP,1905 IPW_ORD_STAT_LINK_DOWN,1906 IPW_ORD_ANTENNA_DIVERSITY,1907 IPW_ORD_CURR_FREQ,1908 IPW_ORD_TABLE_5_LAST1909};1910 1911/* Table 6 */1912enum {1913 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,1914 IPW_ORD_CURR_BSSID,1915 IPW_ORD_CURR_SSID,1916 IPW_ORD_TABLE_6_LAST1917};1918 1919/* Table 7 */1920enum {1921 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,1922 IPW_ORD_STAT_PERCENT_TX_RETRIES,1923 IPW_ORD_STAT_PERCENT_LINK_QUALITY,1924 IPW_ORD_STAT_CURR_RSSI_DBM,1925 IPW_ORD_TABLE_7_LAST1926};1927 1928#define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)1929#define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)1930#define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)1931#define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)1932#define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)1933#define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)1934#define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)1935 1936struct ipw_fixed_rate {1937 __le16 tx_rates;1938 __le16 reserved;1939} __packed;1940 1941#define IPW_INDIRECT_ADDR_MASK (~0x3ul)1942 1943struct host_cmd {1944 u8 cmd;1945 u8 len;1946 u16 reserved;1947 const u32 *param;1948} __packed; /* XXX */1949 1950struct cmdlog_host_cmd {1951 u8 cmd;1952 u8 len;1953 __le16 reserved;1954 char param[124];1955} __packed;1956 1957struct ipw_cmd_log {1958 unsigned long jiffies;1959 int retcode;1960 struct cmdlog_host_cmd cmd;1961};1962 1963/* SysConfig command parameters ... */1964/* bt_coexistence param */1965#define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */1966#define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */1967#define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */1968#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */1969#define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */1970 1971/* clear-to-send to self param */1972#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x001973#define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x011974#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN1975 1976/* Antenna diversity param (h/w can select best antenna, based on signal) */1977#define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */1978#define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */1979#define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */1980#define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */1981 1982#define IPW_MAX_CONFIG_RETRIES 101983 1984#endif /* __ipw2200_h__ */1985