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1/* SPDX-License-Identifier: GPL-2.0-only */2/******************************************************************************3 *4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.5 *6 * Contact Information:7 * Intel Linux Wireless <ilw@linux.intel.com>8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-64979 *10 *****************************************************************************/11 12#ifndef __il_3945_h__13#define __il_3945_h__14 15#include <linux/pci.h> /* for struct pci_device_id */16#include <linux/kernel.h>17#include <net/ieee80211_radiotap.h>18 19/* Hardware specific file defines the PCI IDs table for that hardware module */20extern const struct pci_device_id il3945_hw_card_ids[];21 22#include "common.h"23 24extern const struct il_ops il3945_ops;25 26/* Highest firmware API version supported */27#define IL3945_UCODE_API_MAX 228 29/* Lowest firmware API version supported */30#define IL3945_UCODE_API_MIN 131 32#define IL3945_FW_PRE "iwlwifi-3945-"33#define _IL3945_MODULE_FIRMWARE(api) IL3945_FW_PRE #api ".ucode"34#define IL3945_MODULE_FIRMWARE(api) _IL3945_MODULE_FIRMWARE(api)35 36/* Default noise level to report when noise measurement is not available.37 * This may be because we're:38 * 1) Not associated (4965, no beacon stats being sent to driver)39 * 2) Scanning (noise measurement does not apply to associated channel)40 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)41 * Use default noise value of -127 ... this is below the range of measurable42 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.43 * Also, -127 works better than 0 when averaging frames with/without44 * noise info (e.g. averaging might be done in app); measured dBm values are45 * always negative ... using a negative value as the default keeps all46 * averages within an s8's (used in some apps) range of negative values. */47#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)48 49/* Module parameters accessible from iwl-*.c */50extern struct il_mod_params il3945_mod_params;51 52struct il3945_rate_scale_data {53 u64 data;54 s32 success_counter;55 s32 success_ratio;56 s32 counter;57 s32 average_tpt;58 unsigned long stamp;59};60 61struct il3945_rs_sta {62 spinlock_t lock;63 struct il_priv *il;64 s32 *expected_tpt;65 unsigned long last_partial_flush;66 unsigned long last_flush;67 u32 flush_time;68 u32 last_tx_packets;69 u32 tx_packets;70 u8 tgg;71 u8 flush_pending;72 u8 start_rate;73 struct timer_list rate_scale_flush;74 struct il3945_rate_scale_data win[RATE_COUNT_3945];75 76 /* used to be in sta_info */77 int last_txrate_idx;78};79 80/*81 * The common struct MUST be first because it is shared between82 * 3945 and 4965!83 */84struct il3945_sta_priv {85 struct il_station_priv_common common;86 struct il3945_rs_sta rs_sta;87};88 89enum il3945_antenna {90 IL_ANTENNA_DIVERSITY,91 IL_ANTENNA_MAIN,92 IL_ANTENNA_AUX93};94 95/*96 * RTS threshold here is total size [2347] minus 4 FCS bytes97 * Per spec:98 * a value of 0 means RTS on all data/management packets99 * a value > max MSDU size means no RTS100 * else RTS for data/management frames where MPDU is larger101 * than RTS value.102 */103#define DEFAULT_RTS_THRESHOLD 2347U104#define MIN_RTS_THRESHOLD 0U105#define MAX_RTS_THRESHOLD 2347U106#define MAX_MSDU_SIZE 2304U107#define MAX_MPDU_SIZE 2346U108#define DEFAULT_BEACON_INTERVAL 100U109#define DEFAULT_SHORT_RETRY_LIMIT 7U110#define DEFAULT_LONG_RETRY_LIMIT 4U111 112#define IL_TX_FIFO_AC0 0113#define IL_TX_FIFO_AC1 1114#define IL_TX_FIFO_AC2 2115#define IL_TX_FIFO_AC3 3116#define IL_TX_FIFO_HCCA_1 5117#define IL_TX_FIFO_HCCA_2 6118#define IL_TX_FIFO_NONE 7119 120#define IEEE80211_DATA_LEN 2304121#define IEEE80211_4ADDR_LEN 30122#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)123#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)124 125struct il3945_frame {126 union {127 struct ieee80211_hdr frame;128 struct il3945_tx_beacon_cmd beacon;129 u8 raw[IEEE80211_FRAME_LEN];130 u8 cmd[360];131 } u;132 struct list_head list;133};134 135#define SUP_RATE_11A_MAX_NUM_CHANNELS 8136#define SUP_RATE_11B_MAX_NUM_CHANNELS 4137#define SUP_RATE_11G_MAX_NUM_CHANNELS 12138 139#define IL_SUPPORTED_RATES_IE_LEN 8140 141#define SCAN_INTERVAL 100142 143#define MAX_TID_COUNT 9144 145#define IL_INVALID_RATE 0xFF146#define IL_INVALID_VALUE -1147 148#define STA_PS_STATUS_WAKE 0149#define STA_PS_STATUS_SLEEP 1150 151struct il3945_ibss_seq {152 u8 mac[ETH_ALEN];153 u16 seq_num;154 u16 frag_num;155 unsigned long packet_time;156 struct list_head list;157};158 159#define IL_RX_HDR(x) ((struct il3945_rx_frame_hdr *)(\160 container_of(&x->u.rx_frame.stats, \161 struct il3945_rx_frame_stats, \162 hdr)->payload + \163 x->u.rx_frame.stats.phy_count))164#define IL_RX_END(x) ((struct il3945_rx_frame_end *)(\165 IL_RX_HDR(x)->payload + \166 le16_to_cpu(IL_RX_HDR(x)->len)))167#define IL_RX_STATS(x) (&x->u.rx_frame.stats)168#define IL_RX_DATA(x) (IL_RX_HDR(x)->payload)169 170/******************************************************************************171 *172 * Functions implemented in iwl3945-base.c which are forward declared here173 * for use by iwl-*.c174 *175 *****************************************************************************/176int il3945_calc_db_from_ratio(int sig_ratio);177void il3945_rx_replenish(void *data);178void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);179unsigned int il3945_fill_beacon_frame(struct il_priv *il,180 struct ieee80211_hdr *hdr, int left);181int il3945_dump_nic_event_log(struct il_priv *il, bool full_log, char **buf,182 bool display);183void il3945_dump_nic_error_log(struct il_priv *il);184 185/******************************************************************************186 *187 * Functions implemented in iwl-[34]*.c which are forward declared here188 * for use by iwl3945-base.c189 *190 * NOTE: The implementation of these functions are hardware specific191 * which is why they are in the hardware specific files (vs. iwl-base.c)192 *193 * Naming convention --194 * il3945_ <-- Its part of iwlwifi (should be changed to il3945_)195 * il3945_hw_ <-- Hardware specific (implemented in iwl-XXXX.c by all HW)196 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)197 * il3945_bg_ <-- Called from work queue context198 * il3945_mac_ <-- mac80211 callback199 *200 ****************************************************************************/201void il3945_hw_handler_setup(struct il_priv *il);202void il3945_hw_setup_deferred_work(struct il_priv *il);203void il3945_hw_cancel_deferred_work(struct il_priv *il);204int il3945_hw_rxq_stop(struct il_priv *il);205int il3945_hw_set_hw_params(struct il_priv *il);206int il3945_hw_nic_init(struct il_priv *il);207int il3945_hw_nic_stop_master(struct il_priv *il);208void il3945_hw_txq_ctx_free(struct il_priv *il);209void il3945_hw_txq_ctx_stop(struct il_priv *il);210int il3945_hw_nic_reset(struct il_priv *il);211int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,212 dma_addr_t addr, u16 len, u8 reset, u8 pad);213void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);214int il3945_hw_get_temperature(struct il_priv *il);215int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);216unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il,217 struct il3945_frame *frame, u8 rate);218void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,219 struct ieee80211_tx_info *info,220 struct ieee80211_hdr *hdr, int sta_id);221int il3945_hw_reg_send_txpower(struct il_priv *il);222int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power);223void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);224void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);225void il3945_disable_events(struct il_priv *il);226int il4965_get_temperature(const struct il_priv *il);227void il3945_post_associate(struct il_priv *il);228void il3945_config_ap(struct il_priv *il);229 230int il3945_commit_rxon(struct il_priv *il);231 232/**233 * il3945_hw_find_station - Find station id for a given BSSID234 * @bssid: MAC address of station ID to find235 *236 * NOTE: This should not be hardware specific but the code has237 * not yet been merged into a single common layer for managing the238 * station tables.239 */240u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid);241 242__le32 il3945_get_antenna_flags(const struct il_priv *il);243int il3945_init_hw_rate_table(struct il_priv *il);244void il3945_reg_txpower_periodic(struct il_priv *il);245int il3945_txpower_set_from_eeprom(struct il_priv *il);246 247int il3945_rs_next_rate(struct il_priv *il, int rate);248 249/* scanning */250int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif);251void il3945_post_scan(struct il_priv *il);252 253/* rates */254extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945];255 256/* RSSI to dBm */257#define IL39_RSSI_OFFSET 95258 259/*260 * EEPROM related constants, enums, and structures.261 */262#define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)263 264/*265 * Mapping of a Tx power level, at factory calibration temperature,266 * to a radio/DSP gain table idx.267 * One for each of 5 "sample" power levels in each band.268 * v_det is measured at the factory, using the 3945's built-in power amplifier269 * (PA) output voltage detector. This same detector is used during Tx of270 * long packets in normal operation to provide feedback as to proper output271 * level.272 * Data copied from EEPROM.273 * DO NOT ALTER THIS STRUCTURE!!!274 */275struct il3945_eeprom_txpower_sample {276 u8 gain_idx; /* idx into power (gain) setup table ... */277 s8 power; /* ... for this pwr level for this chnl group */278 u16 v_det; /* PA output voltage */279} __packed;280 281/*282 * Mappings of Tx power levels -> nominal radio/DSP gain table idxes.283 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).284 * Tx power setup code interpolates between the 5 "sample" power levels285 * to determine the nominal setup for a requested power level.286 * Data copied from EEPROM.287 * DO NOT ALTER THIS STRUCTURE!!!288 */289struct il3945_eeprom_txpower_group {290 struct il3945_eeprom_txpower_sample samples[5]; /* 5 power levels */291 s32 a, b, c, d, e; /* coefficients for voltage->power292 * formula (signed) */293 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on294 * frequency (signed) */295 s8 saturation_power; /* highest power possible by h/w in this296 * band */297 u8 group_channel; /* "representative" channel # in this band */298 s16 temperature; /* h/w temperature at factory calib this band299 * (signed) */300} __packed;301 302/*303 * Temperature-based Tx-power compensation data, not band-specific.304 * These coefficients are use to modify a/b/c/d/e coeffs based on305 * difference between current temperature and factory calib temperature.306 * Data copied from EEPROM.307 */308struct il3945_eeprom_temperature_corr {309 u32 Ta;310 u32 Tb;311 u32 Tc;312 u32 Td;313 u32 Te;314} __packed;315 316/*317 * EEPROM map318 */319struct il3945_eeprom {320 u8 reserved0[16];321 u16 device_id; /* abs.ofs: 16 */322 u8 reserved1[2];323 u16 pmc; /* abs.ofs: 20 */324 u8 reserved2[20];325 u8 mac_address[6]; /* abs.ofs: 42 */326 u8 reserved3[58];327 u16 board_revision; /* abs.ofs: 106 */328 u8 reserved4[11];329 u8 board_pba_number[9]; /* abs.ofs: 119 */330 u8 reserved5[8];331 u16 version; /* abs.ofs: 136 */332 u8 sku_cap; /* abs.ofs: 138 */333 u8 leds_mode; /* abs.ofs: 139 */334 u16 oem_mode;335 u16 wowlan_mode; /* abs.ofs: 142 */336 u16 leds_time_interval; /* abs.ofs: 144 */337 u8 leds_off_time; /* abs.ofs: 146 */338 u8 leds_on_time; /* abs.ofs: 147 */339 u8 almgor_m_version; /* abs.ofs: 148 */340 u8 antenna_switch_type; /* abs.ofs: 149 */341 u8 reserved6[42];342 u8 sku_id[4]; /* abs.ofs: 192 */343 344/*345 * Per-channel regulatory data.346 *347 * Each channel that *might* be supported by 3945 has a fixed location348 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory349 * txpower (MSB).350 *351 * Entries immediately below are for 20 MHz channel width.352 *353 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14354 */355 u16 band_1_count; /* abs.ofs: 196 */356 struct il_eeprom_channel band_1_channels[14]; /* abs.ofs: 198 */357 358/*359 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,360 * 5.0 GHz channels 7, 8, 11, 12, 16361 * (4915-5080MHz) (none of these is ever supported)362 */363 u16 band_2_count; /* abs.ofs: 226 */364 struct il_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */365 366/*367 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64368 * (5170-5320MHz)369 */370 u16 band_3_count; /* abs.ofs: 254 */371 struct il_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */372 373/*374 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140375 * (5500-5700MHz)376 */377 u16 band_4_count; /* abs.ofs: 280 */378 struct il_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */379 380/*381 * 5.7 GHz channels 145, 149, 153, 157, 161, 165382 * (5725-5825MHz)383 */384 u16 band_5_count; /* abs.ofs: 304 */385 struct il_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */386 387 u8 reserved9[194];388 389/*390 * 3945 Txpower calibration data.391 */392#define IL_NUM_TX_CALIB_GROUPS 5393 struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS];394/* abs.ofs: 512 */395 struct il3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */396 u8 reserved16[172]; /* fill out to full 1024 byte block */397} __packed;398 399#define IL3945_EEPROM_IMG_SIZE 1024400 401/* End of EEPROM */402 403#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */404#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */405 406/* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */407#define IL39_NUM_QUEUES 5408#define IL39_CMD_QUEUE_NUM 4409 410#define IL_DEFAULT_TX_RETRY 15411 412/*********************************************/413 414#define RFD_SIZE 4415#define NUM_TFD_CHUNKS 4416 417#define TFD_CTL_COUNT_SET(n) (n << 24)418#define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7)419#define TFD_CTL_PAD_SET(n) (n << 28)420#define TFD_CTL_PAD_GET(ctl) (ctl >> 28)421 422/* Sizes and addresses for instruction and data memory (SRAM) in423 * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */424#define IL39_RTC_INST_LOWER_BOUND (0x000000)425#define IL39_RTC_INST_UPPER_BOUND (0x014000)426 427#define IL39_RTC_DATA_LOWER_BOUND (0x800000)428#define IL39_RTC_DATA_UPPER_BOUND (0x808000)429 430#define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \431 IL39_RTC_INST_LOWER_BOUND)432#define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \433 IL39_RTC_DATA_LOWER_BOUND)434 435#define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE436#define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE437 438/* Size of uCode instruction memory in bootstrap state machine */439#define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE440 441static inline int442il3945_hw_valid_rtc_data_addr(u32 addr)443{444 return (addr >= IL39_RTC_DATA_LOWER_BOUND &&445 addr < IL39_RTC_DATA_UPPER_BOUND);446}447 448/* Base physical address of il3945_shared is provided to FH39_TSSR_CBB_BASE449 * and &il3945_shared.rx_read_ptr[0] is provided to FH39_RCSR_RPTR_ADDR(0) */450struct il3945_shared {451 __le32 tx_base_ptr[8];452} __packed;453 454/************************************/455/* iwl3945 Flow Handler Definitions */456/************************************/457 458/**459 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())460 * Addresses are offsets from device's PCI hardware base address.461 */462#define FH39_MEM_LOWER_BOUND (0x0800)463#define FH39_MEM_UPPER_BOUND (0x1000)464 465#define FH39_CBCC_TBL (FH39_MEM_LOWER_BOUND + 0x140)466#define FH39_TFDB_TBL (FH39_MEM_LOWER_BOUND + 0x180)467#define FH39_RCSR_TBL (FH39_MEM_LOWER_BOUND + 0x400)468#define FH39_RSSR_TBL (FH39_MEM_LOWER_BOUND + 0x4c0)469#define FH39_TCSR_TBL (FH39_MEM_LOWER_BOUND + 0x500)470#define FH39_TSSR_TBL (FH39_MEM_LOWER_BOUND + 0x680)471 472/* TFDB (Transmit Frame Buffer Descriptor) */473#define FH39_TFDB(_ch, buf) (FH39_TFDB_TBL + \474 ((_ch) * 2 + (buf)) * 0x28)475#define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TBL + 0x50 * (_ch))476 477/* CBCC channel is [0,2] */478#define FH39_CBCC(_ch) (FH39_CBCC_TBL + (_ch) * 0x8)479#define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00)480#define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04)481 482/* RCSR channel is [0,2] */483#define FH39_RCSR(_ch) (FH39_RCSR_TBL + (_ch) * 0x40)484#define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00)485#define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04)486#define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20)487#define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24)488 489#define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0))490 491/* RSSR */492#define FH39_RSSR_CTRL (FH39_RSSR_TBL + 0x000)493#define FH39_RSSR_STATUS (FH39_RSSR_TBL + 0x004)494 495/* TCSR */496#define FH39_TCSR(_ch) (FH39_TCSR_TBL + (_ch) * 0x20)497#define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00)498#define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04)499#define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08)500 501/* TSSR */502#define FH39_TSSR_CBB_BASE (FH39_TSSR_TBL + 0x000)503#define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TBL + 0x008)504#define FH39_TSSR_TX_STATUS (FH39_TSSR_TBL + 0x010)505 506/* DBM */507 508#define FH39_SRVC_CHNL (6)509 510#define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)511#define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)512 513#define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)514 515#define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)516 517#define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)518 519#define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)520 521#define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)522 523#define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)524 525#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)526#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)527 528#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)529#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)530 531#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)532 533#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)534 535#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)536#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)537 538#define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)539 540#define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)541 542#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)543#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)544 545#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)546 547#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)548#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)549 550#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)551#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)552 553#define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24)554#define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16)555 556#define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \557 (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \558 FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))559 560#define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)561 562struct il3945_tfd_tb {563 __le32 addr;564 __le32 len;565} __packed;566 567struct il3945_tfd {568 __le32 control_flags;569 struct il3945_tfd_tb tbs[4];570 u8 __pad[28];571} __packed;572 573#ifdef CONFIG_IWLEGACY_DEBUGFS574extern const struct il_debugfs_ops il3945_debugfs_ops;575#endif576 577#endif578