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1/******************************************************************************2 *3 * This file is provided under a dual BSD/GPLv2 license. When using or4 * redistributing this file, you may do so under either license.5 *6 * GPL LICENSE SUMMARY7 *8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.9 *10 * This program is free software; you can redistribute it and/or modify11 * it under the terms of version 2 of the GNU General Public License as12 * published by the Free Software Foundation.13 *14 * This program is distributed in the hope that it will be useful, but15 * WITHOUT ANY WARRANTY; without even the implied warranty of16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU17 * General Public License for more details.18 *19 * You should have received a copy of the GNU General Public License20 * along with this program; if not, write to the Free Software21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,22 * USA23 *24 * The full GNU General Public License is included in this distribution25 * in the file called LICENSE.GPL.26 *27 * Contact Information:28 * Intel Linux Wireless <ilw@linux.intel.com>29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649730 *31 * BSD LICENSE32 *33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.34 * All rights reserved.35 *36 * Redistribution and use in source and binary forms, with or without37 * modification, are permitted provided that the following conditions38 * are met:39 *40 * * Redistributions of source code must retain the above copyright41 * notice, this list of conditions and the following disclaimer.42 * * Redistributions in binary form must reproduce the above copyright43 * notice, this list of conditions and the following disclaimer in44 * the documentation and/or other materials provided with the45 * distribution.46 * * Neither the name Intel Corporation nor the names of its47 * contributors may be used to endorse or promote products derived48 * from this software without specific prior written permission.49 *50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.61 *****************************************************************************/62 63#ifndef __il_prph_h__64#define __il_prph_h__65 66/*67 * Registers in this file are internal, not PCI bus memory mapped.68 * Driver accesses these via HBUS_TARG_PRPH_* registers.69 */70#define PRPH_BASE (0x00000)71#define PRPH_END (0xFFFFF)72 73/* APMG (power management) constants */74#define APMG_BASE (PRPH_BASE + 0x3000)75#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)76#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)77#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)78#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)79#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)80#define APMG_RFKILL_REG (APMG_BASE + 0x0014)81#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)82#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)83#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)84#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)85 86#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)87#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)88#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)89 90#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)91#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)92#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)93#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)94#define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */95#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)96#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */97#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)98 99#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)100 101/**102 * BSM (Bootstrap State Machine)103 *104 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program105 * in special SRAM that does not power down when the embedded control106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).107 *108 * When powering back up after sleeps (or during initial uCode load), the BSM109 * internally loads the short bootstrap program from the special SRAM into the110 * embedded processor's instruction SRAM, and starts the processor so it runs111 * the bootstrap program.112 *113 * This bootstrap program loads (via PCI busmaster DMA) instructions and data114 * images for a uCode program from host DRAM locations. The host driver115 * indicates DRAM locations and sizes for instruction and data images via the116 * four BSM_DRAM_* registers. Once the bootstrap program loads the new program,117 * the new program starts automatically.118 *119 * The uCode used for open-source drivers includes two programs:120 *121 * 1) Initialization -- performs hardware calibration and sets up some122 * internal data, then notifies host via "initialize alive" notification123 * (struct il_init_alive_resp) that it has completed all of its work.124 * After signal from host, it then loads and starts the runtime program.125 * The initialization program must be used when initially setting up the126 * NIC after loading the driver.127 *128 * 2) Runtime/Protocol -- performs all normal runtime operations. This129 * notifies host via "alive" notification (struct il_alive_resp) that it130 * is ready to be used.131 *132 * When initializing the NIC, the host driver does the following procedure:133 *134 * 1) Load bootstrap program (instructions only, no data image for bootstrap)135 * into bootstrap memory. Use dword writes starting at BSM_SRAM_LOWER_BOUND136 *137 * 2) Point (via BSM_DRAM_*) to the "initialize" uCode data and instruction138 * images in host DRAM.139 *140 * 3) Set up BSM to copy from BSM SRAM into uCode instruction SRAM when asked:141 * BSM_WR_MEM_SRC_REG = 0142 * BSM_WR_MEM_DST_REG = RTC_INST_LOWER_BOUND143 * BSM_WR_MEM_DWCOUNT_REG = # dwords in bootstrap instruction image144 *145 * 4) Load bootstrap into instruction SRAM:146 * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START147 *148 * 5) Wait for load completion:149 * Poll BSM_WR_CTRL_REG for BSM_WR_CTRL_REG_BIT_START = 0150 *151 * 6) Enable future boot loads whenever NIC's power management triggers it:152 * BSM_WR_CTRL_REG = BSM_WR_CTRL_REG_BIT_START_EN153 *154 * 7) Start the NIC by removing all reset bits:155 * CSR_RESET = 0156 *157 * The bootstrap uCode (already in instruction SRAM) loads initialization158 * uCode. Initialization uCode performs data initialization, sends159 * "initialize alive" notification to host, and waits for a signal from160 * host to load runtime code.161 *162 * 4) Point (via BSM_DRAM_*) to the "runtime" uCode data and instruction163 * images in host DRAM. The last register loaded must be the instruction164 * byte count register ("1" in MSbit tells initialization uCode to load165 * the runtime uCode):166 * BSM_DRAM_INST_BYTECOUNT_REG = byte count | BSM_DRAM_INST_LOAD167 *168 * 5) Wait for "alive" notification, then issue normal runtime commands.169 *170 * Data caching during power-downs:171 *172 * Just before the embedded controller powers down (e.g for automatic173 * power-saving modes, or for RFKILL), uCode stores (via PCI busmaster DMA)174 * a current snapshot of the embedded processor's data SRAM into host DRAM.175 * This caches the data while the embedded processor's memory is powered down.176 * Location and size are controlled by BSM_DRAM_DATA_* registers.177 *178 * NOTE: Instruction SRAM does not need to be saved, since that doesn't179 * change during operation; the original image (from uCode distribution180 * file) can be used for reload.181 *182 * When powering back up, the BSM loads the bootstrap program. Bootstrap looks183 * at the BSM_DRAM_* registers, which now point to the runtime instruction184 * image and the cached (modified) runtime data (*not* the initialization185 * uCode). Bootstrap reloads these runtime images into SRAM, and restarts the186 * uCode from where it left off before the power-down.187 *188 * NOTE: Initialization uCode does *not* run as part of the save/restore189 * procedure.190 *191 * This save/restore method is mostly for autonomous power management during192 * normal operation (result of C_POWER_TBL). Platform suspend/resume and193 * RFKILL should use complete restarts (with total re-initialization) of uCode,194 * allowing total shutdown (including BSM memory).195 *196 * Note that, during normal operation, the host DRAM that held the initial197 * startup data for the runtime code is now being used as a backup data cache198 * for modified data! If you need to completely re-initialize the NIC, make199 * sure that you use the runtime data image from the uCode distribution file,200 * not the modified/saved runtime data. You may want to store a separate201 * "clean" runtime data image in DRAM to avoid disk reads of distribution file.202 */203 204/* BSM bit fields */205#define BSM_WR_CTRL_REG_BIT_START (0x80000000) /* start boot load now */206#define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) /* enable boot after pwrup */207#define BSM_DRAM_INST_LOAD (0x80000000) /* start program load now */208 209/* BSM addresses */210#define BSM_BASE (PRPH_BASE + 0x3400)211#define BSM_END (PRPH_BASE + 0x3800)212 213#define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */214#define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */215#define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */216#define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */217#define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */218 219/*220 * Pointers and size regs for bootstrap load and data SRAM save/restore.221 * NOTE: 3945 pointers use bits 31:0 of DRAM address.222 * 4965 pointers use bits 35:4 of DRAM address.223 */224#define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090)225#define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094)226#define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098)227#define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C)228 229/*230 * BSM special memory, stays powered on during power-save sleeps.231 * Read/write, address range from LOWER_BOUND to (LOWER_BOUND + SIZE -1)232 */233#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)234#define BSM_SRAM_SIZE (1024) /* bytes */235 236/* 3945 Tx scheduler registers */237#define ALM_SCD_BASE (PRPH_BASE + 0x2E00)238#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)239#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)240#define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)241#define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)242#define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)243#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)244#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)245 246/**247 * Tx Scheduler248 *249 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs250 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in251 * host DRAM. It steers each frame's Tx command (which contains the frame252 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the253 * device. A queue maps to only one (selectable by driver) Tx DMA channel,254 * but one DMA channel may take input from several queues.255 *256 * Tx DMA FIFOs have dedicated purposes. For 4965, they are used as follows257 * (cf. default_queue_to_tx_fifo in 4965.c):258 *259 * 0 -- EDCA BK (background) frames, lowest priority260 * 1 -- EDCA BE (best effort) frames, normal priority261 * 2 -- EDCA VI (video) frames, higher priority262 * 3 -- EDCA VO (voice) and management frames, highest priority263 * 4 -- Commands (e.g. RXON, etc.)264 * 5 -- unused (HCCA)265 * 6 -- unused (HCCA)266 * 7 -- not used by driver (device-internal only)267 *268 *269 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.270 * In addition, driver can map the remaining queues to Tx DMA/FIFO271 * channels 0-3 to support 11n aggregation via EDCA DMA channels.272 *273 * The driver sets up each queue to work in one of two modes:274 *275 * 1) Scheduler-Ack, in which the scheduler automatically supports a276 * block-ack (BA) win of up to 64 TFDs. In this mode, each queue277 * contains TFDs for a unique combination of Recipient Address (RA)278 * and Traffic Identifier (TID), that is, traffic of a given279 * Quality-Of-Service (QOS) priority, destined for a single station.280 *281 * In scheduler-ack mode, the scheduler keeps track of the Tx status of282 * each frame within the BA win, including whether it's been transmitted,283 * and whether it's been acknowledged by the receiving station. The device284 * automatically processes block-acks received from the receiving STA,285 * and reschedules un-acked frames to be retransmitted (successful286 * Tx completion may end up being out-of-order).287 *288 * The driver must maintain the queue's Byte Count table in host DRAM289 * (struct il4965_sched_queue_byte_cnt_tbl) for this mode.290 * This mode does not support fragmentation.291 *292 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.293 * The device may automatically retry Tx, but will retry only one frame294 * at a time, until receiving ACK from receiving station, or reaching295 * retry limit and giving up.296 *297 * The command queue (#4/#9) must use this mode!298 * This mode does not require use of the Byte Count table in host DRAM.299 *300 * Driver controls scheduler operation via 3 means:301 * 1) Scheduler registers302 * 2) Shared scheduler data base in internal 4956 SRAM303 * 3) Shared data in host DRAM304 *305 * Initialization:306 *307 * When loading, driver should allocate memory for:308 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.309 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory310 * (1024 bytes for each queue).311 *312 * After receiving "Alive" response from uCode, driver must initialize313 * the scheduler (especially for queue #4/#9, the command queue, otherwise314 * the driver can't issue commands!):315 */316 317/**318 * Max Tx win size is the max number of contiguous TFDs that the scheduler319 * can keep track of at one time when creating block-ack chains of frames.320 * Note that "64" matches the number of ack bits in a block-ack packet.321 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize322 * IL49_SCD_CONTEXT_QUEUE_OFFSET(x) values.323 */324#define SCD_WIN_SIZE 64325#define SCD_FRAME_LIMIT 64326 327/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */328#define IL49_SCD_START_OFFSET 0xa02c00329 330/*331 * 4965 tells driver SRAM address for internal scheduler structs via this reg.332 * Value is valid only after "Alive" response from uCode.333 */334#define IL49_SCD_SRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x0)335 336/*337 * Driver may need to update queue-empty bits after changing queue's338 * write and read pointers (idxes) during (re-)initialization (i.e. when339 * scheduler is not tracking what's happening).340 * Bit fields:341 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit342 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty343 * NOTE: This register is not used by Linux driver.344 */345#define IL49_SCD_EMPTY_BITS (IL49_SCD_START_OFFSET + 0x4)346 347/*348 * Physical base address of array of byte count (BC) circular buffers (CBs).349 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.350 * This register points to BC CB for queue 0, must be on 1024-byte boundary.351 * Others are spaced by 1024 bytes.352 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.353 * (Index into a queue's BC CB) = (idx into queue's TFD CB) = (SSN & 0xff).354 * Bit fields:355 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.356 */357#define IL49_SCD_DRAM_BASE_ADDR (IL49_SCD_START_OFFSET + 0x10)358 359/*360 * Enables any/all Tx DMA/FIFO channels.361 * Scheduler generates requests for only the active channels.362 * Set this to 0xff to enable all 8 channels (normal usage).363 * Bit fields:364 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7365 */366#define IL49_SCD_TXFACT (IL49_SCD_START_OFFSET + 0x1c)367/*368 * Queue (x) Write Pointers (idxes, really!), one for each Tx queue.369 * Initialized and updated by driver as new TFDs are added to queue.370 * NOTE: If using Block Ack, idx must correspond to frame's371 * Start Sequence Number; idx = (SSN & 0xff)372 * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?373 */374#define IL49_SCD_QUEUE_WRPTR(x) (IL49_SCD_START_OFFSET + 0x24 + (x) * 4)375 376/*377 * Queue (x) Read Pointers (idxes, really!), one for each Tx queue.378 * For FIFO mode, idx indicates next frame to transmit.379 * For Scheduler-ACK mode, idx indicates first frame in Tx win.380 * Initialized by driver, updated by scheduler.381 */382#define IL49_SCD_QUEUE_RDPTR(x) (IL49_SCD_START_OFFSET + 0x64 + (x) * 4)383 384/*385 * Select which queues work in chain mode (1) vs. not (0).386 * Use chain mode to build chains of aggregated frames.387 * Bit fields:388 * 31-16: Reserved389 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time390 * NOTE: If driver sets up queue for chain mode, it should be also set up391 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).392 */393#define IL49_SCD_QUEUECHAIN_SEL (IL49_SCD_START_OFFSET + 0xd0)394 395/*396 * Select which queues interrupt driver when scheduler increments397 * a queue's read pointer (idx).398 * Bit fields:399 * 31-16: Reserved400 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled401 * NOTE: This functionality is apparently a no-op; driver relies on interrupts402 * from Rx queue to read Tx command responses and update Tx queues.403 */404#define IL49_SCD_INTERRUPT_MASK (IL49_SCD_START_OFFSET + 0xe4)405 406/*407 * Queue search status registers. One for each queue.408 * Sets up queue mode and assigns queue to Tx DMA channel.409 * Bit fields:410 * 19-10: Write mask/enable bits for bits 0-9411 * 9: Driver should init to "0"412 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).413 * Driver should init to "1" for aggregation mode, or "0" otherwise.414 * 7-6: Driver should init to "0"415 * 5: Window Size Left; indicates whether scheduler can request416 * another TFD, based on win size, etc. Driver should init417 * this bit to "1" for aggregation mode, or "0" for non-agg.418 * 4-1: Tx FIFO to use (range 0-7).419 * 0: Queue is active (1), not active (0).420 * Other bits should be written as "0"421 *422 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled423 * via SCD_QUEUECHAIN_SEL.424 */425#define IL49_SCD_QUEUE_STATUS_BITS(x)\426 (IL49_SCD_START_OFFSET + 0x104 + (x) * 4)427 428/* Bit field positions */429#define IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE (0)430#define IL49_SCD_QUEUE_STTS_REG_POS_TXF (1)431#define IL49_SCD_QUEUE_STTS_REG_POS_WSL (5)432#define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)433 434/* Write masks */435#define IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)436#define IL49_SCD_QUEUE_STTS_REG_MSK (0x0007FC00)437 438/**439 * 4965 internal SRAM structures for scheduler, shared with driver ...440 *441 * Driver should clear and initialize the following areas after receiving442 * "Alive" response from 4965 uCode, i.e. after initial443 * uCode load, or after a uCode load done for error recovery:444 *445 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes)446 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)447 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)448 *449 * Driver accesses SRAM via HBUS_TARG_MEM_* registers.450 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.451 * All OFFSET values must be added to this base address.452 */453 454/*455 * Queue context. One 8-byte entry for each of 16 queues.456 *457 * Driver should clear this entire area (size 0x80) to 0 after receiving458 * "Alive" notification from uCode. Additionally, driver should init459 * each queue's entry as follows:460 *461 * LS Dword bit fields:462 * 0-06: Max Tx win size for Scheduler-ACK. Driver should init to 64.463 *464 * MS Dword bit fields:465 * 16-22: Frame limit. Driver should init to 10 (0xa).466 *467 * Driver should init all other bits to 0.468 *469 * Init must be done after driver receives "Alive" response from 4965 uCode,470 * and when setting up queue for aggregation.471 */472#define IL49_SCD_CONTEXT_DATA_OFFSET 0x380473#define IL49_SCD_CONTEXT_QUEUE_OFFSET(x) \474 (IL49_SCD_CONTEXT_DATA_OFFSET + ((x) * 8))475 476#define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)477#define IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)478#define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)479#define IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)480 481/*482 * Tx Status Bitmap483 *484 * Driver should clear this entire area (size 0x100) to 0 after receiving485 * "Alive" notification from uCode. Area is used only by device itself;486 * no other support (besides clearing) is required from driver.487 */488#define IL49_SCD_TX_STTS_BITMAP_OFFSET 0x400489 490/*491 * RAxTID to queue translation mapping.492 *493 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be494 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.495 * one QOS priority level destined for one station (for this wireless link,496 * not final destination). The SCD_TRANSLATE_TBL area provides 16 16-bit497 * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK498 * mode, the device ignores the mapping value.499 *500 * Bit fields, for each 16-bit map:501 * 15-9: Reserved, set to 0502 * 8-4: Index into device's station table for recipient station503 * 3-0: Traffic ID (tid), range 0-15504 *505 * Driver should clear this entire area (size 32 bytes) to 0 after receiving506 * "Alive" notification from uCode. To update a 16-bit map value, driver507 * must read a dword-aligned value from device SRAM, replace the 16-bit map508 * value of interest, and write the dword value back into device SRAM.509 */510#define IL49_SCD_TRANSLATE_TBL_OFFSET 0x500511 512/* Find translation table dword to read/write for given queue */513#define IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \514 ((IL49_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)515 516#define IL_SCD_TXFIFO_POS_TID (0)517#define IL_SCD_TXFIFO_POS_RA (4)518#define IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)519 520/*********************** END TX SCHEDULER *************************************/521 522#endif /* __il_prph_h__ */523