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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * Copyright (C) 2005-2014, 2019-2021, 2023-2024 Intel Corporation4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH5 * Copyright (C) 2016-2017 Intel Deutschland GmbH6 */7#ifndef __iwl_fw_api_txq_h__8#define __iwl_fw_api_txq_h__9 10/*11 * DQA queue numbers12 *13 * @IWL_MVM_DQA_CMD_QUEUE: a queue reserved for sending HCMDs to the FW14 * @IWL_MVM_DQA_AUX_QUEUE: a queue reserved for aux frames15 * @IWL_MVM_DQA_P2P_DEVICE_QUEUE: a queue reserved for P2P device frames16 * @IWL_MVM_DQA_INJECT_MONITOR_QUEUE: a queue reserved for injection using17 * monitor mode. Note this queue is the same as the queue for P2P device18 * but we can't have active monitor mode along with P2P device anyway.19 * @IWL_MVM_DQA_GCAST_QUEUE: a queue reserved for P2P GO/SoftAP GCAST frames20 * @IWL_MVM_DQA_BSS_CLIENT_QUEUE: a queue reserved for BSS activity, to ensure21 * that we are never left without the possibility to connect to an AP.22 * @IWL_MVM_DQA_MIN_MGMT_QUEUE: first TXQ in pool for MGMT and non-QOS frames.23 * Each MGMT queue is mapped to a single STA24 * MGMT frames are frames that return true on ieee80211_is_mgmt()25 * @IWL_MVM_DQA_MAX_MGMT_QUEUE: last TXQ in pool for MGMT frames26 * @IWL_MVM_DQA_AP_PROBE_RESP_QUEUE: a queue reserved for P2P GO/SoftAP probe27 * responses28 * @IWL_MVM_DQA_MIN_DATA_QUEUE: first TXQ in pool for DATA frames.29 * DATA frames are intended for !ieee80211_is_mgmt() frames, but if30 * the MGMT TXQ pool is exhausted, mgmt frames can be sent on DATA queues31 * as well32 * @IWL_MVM_DQA_MAX_DATA_QUEUE: last TXQ in pool for DATA frames33 */34enum iwl_mvm_dqa_txq {35 IWL_MVM_DQA_CMD_QUEUE = 0,36 IWL_MVM_DQA_AUX_QUEUE = 1,37 IWL_MVM_DQA_P2P_DEVICE_QUEUE = 2,38 IWL_MVM_DQA_INJECT_MONITOR_QUEUE = 2,39 IWL_MVM_DQA_GCAST_QUEUE = 3,40 IWL_MVM_DQA_BSS_CLIENT_QUEUE = 4,41 IWL_MVM_DQA_MIN_MGMT_QUEUE = 5,42 IWL_MVM_DQA_MAX_MGMT_QUEUE = 8,43 IWL_MVM_DQA_AP_PROBE_RESP_QUEUE = 9,44 IWL_MVM_DQA_MIN_DATA_QUEUE = 10,45 IWL_MVM_DQA_MAX_DATA_QUEUE = 30,46};47 48enum iwl_mvm_tx_fifo {49 IWL_MVM_TX_FIFO_BK = 0,50 IWL_MVM_TX_FIFO_BE,51 IWL_MVM_TX_FIFO_VI,52 IWL_MVM_TX_FIFO_VO,53 IWL_MVM_TX_FIFO_MCAST = 5,54 IWL_MVM_TX_FIFO_CMD = 7,55};56 57enum iwl_gen2_tx_fifo {58 IWL_GEN2_TX_FIFO_CMD = 0,59 IWL_GEN2_EDCA_TX_FIFO_BK,60 IWL_GEN2_EDCA_TX_FIFO_BE,61 IWL_GEN2_EDCA_TX_FIFO_VI,62 IWL_GEN2_EDCA_TX_FIFO_VO,63 IWL_GEN2_TRIG_TX_FIFO_BK,64 IWL_GEN2_TRIG_TX_FIFO_BE,65 IWL_GEN2_TRIG_TX_FIFO_VI,66 IWL_GEN2_TRIG_TX_FIFO_VO,67};68 69enum iwl_bz_tx_fifo {70 IWL_BZ_EDCA_TX_FIFO_BK,71 IWL_BZ_EDCA_TX_FIFO_BE,72 IWL_BZ_EDCA_TX_FIFO_VI,73 IWL_BZ_EDCA_TX_FIFO_VO,74 IWL_BZ_TRIG_TX_FIFO_BK,75 IWL_BZ_TRIG_TX_FIFO_BE,76 IWL_BZ_TRIG_TX_FIFO_VI,77 IWL_BZ_TRIG_TX_FIFO_VO,78};79/**80 * enum iwl_tx_queue_cfg_actions - TXQ config options81 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue82 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format83 */84enum iwl_tx_queue_cfg_actions {85 TX_QUEUE_CFG_ENABLE_QUEUE = BIT(0),86 TX_QUEUE_CFG_TFD_SHORT_FORMAT = BIT(1),87};88 89#define IWL_DEFAULT_QUEUE_SIZE_EHT (512 * 4)90#define IWL_DEFAULT_QUEUE_SIZE_HE 102491#define IWL_DEFAULT_QUEUE_SIZE 25692#define IWL_MGMT_QUEUE_SIZE 1693#define IWL_CMD_QUEUE_SIZE 3294/**95 * struct iwl_tx_queue_cfg_cmd - txq hw scheduler config command96 * @sta_id: station id97 * @tid: tid of the queue98 * @flags: see &enum iwl_tx_queue_cfg_actions99 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3.100 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs)101 * @byte_cnt_addr: address of byte count table102 * @tfdq_addr: address of TFD circular buffer103 */104struct iwl_tx_queue_cfg_cmd {105 u8 sta_id;106 u8 tid;107 __le16 flags;108 __le32 cb_size;109 __le64 byte_cnt_addr;110 __le64 tfdq_addr;111} __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */112 113/**114 * struct iwl_tx_queue_cfg_rsp - response to txq hw scheduler config115 * @queue_number: queue number assigned to this RA -TID116 * @flags: set on failure117 * @write_pointer: initial value for write pointer118 * @reserved: reserved119 */120struct iwl_tx_queue_cfg_rsp {121 __le16 queue_number;122 __le16 flags;123 __le16 write_pointer;124 __le16 reserved;125} __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */126 127#endif /* __iwl_fw_api_txq_h__ */128