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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH5 * Copyright (C) 2016 Intel Deutschland GmbH6 */7#ifndef __iwl_prph_h__8#define __iwl_prph_h__9#include <linux/bitfield.h>10 11/*12 * Registers in this file are internal, not PCI bus memory mapped.13 * Driver accesses these via HBUS_TARG_PRPH_* registers.14 */15#define PRPH_BASE (0x00000)16#define PRPH_END (0xFFFFF)17 18/* APMG (power management) constants */19#define APMG_BASE (PRPH_BASE + 0x3000)20#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)21#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)22#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)23#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)24#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)25#define APMG_RFKILL_REG (APMG_BASE + 0x0014)26#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)27#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)28#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)29#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)30 31#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)32#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)33#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)34 35#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)36#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)37#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)38#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)39#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)40#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */41#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)42 43#define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)44#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)45#define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000)46 47#define APMG_RTC_INT_STT_RFKILL (0x10000000)48 49/* Device system time */50#define DEVICE_SYSTEM_TIME_REG 0xA0206C51 52/* Device NMI register and value for 8000 family and lower hw's */53#define DEVICE_SET_NMI_REG 0x00a01c3054#define DEVICE_SET_NMI_VAL_DRV BIT(7)55/* Device NMI register and value for 9000 family and above hw's */56#define UREG_NIC_SET_NMI_DRIVER 0x00a05c1057#define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER BIT(24)58#define UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE (BIT(24) | BIT(25))59 60/* Shared registers (0x0..0x3ff, via target indirect or periphery */61#define SHR_BASE 0x00a1000062 63/* Shared GP1 register */64#define SHR_APMG_GP1_REG 0x01dc65#define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG)66#define SHR_APMG_GP1_WF_XTAL_LP_EN 0x0000000467#define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x8000000068 69/* Shared DL_CFG register */70#define SHR_APMG_DL_CFG_REG 0x01c471#define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG)72#define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c073#define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x0000008074#define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x0000010075 76/* Shared APMG_XTAL_CFG register */77#define SHR_APMG_XTAL_CFG_REG 0x1c078#define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x8000000079 80/*81 * Device reset for family 800082 * write to bit 24 in order to reset the CPU83*/84#define RELEASE_CPU_RESET (0x300C)85#define RELEASE_CPU_RESET_BIT BIT(24)86 87/*****************************************************************************88 * 7000/3000 series SHR DTS addresses *89 *****************************************************************************/90 91#define SHR_MISC_WFM_DTS_EN (0x00a10024)92#define DTSC_CFG_MODE (0x00a10604)93#define DTSC_VREF_AVG (0x00a10648)94#define DTSC_VREF5_AVG (0x00a1064c)95#define DTSC_CFG_MODE_PERIODIC (0x2)96#define DTSC_PTAT_AVG (0x00a10650)97 98 99/*100 * Tx Scheduler101 *102 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs103 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in104 * host DRAM. It steers each frame's Tx command (which contains the frame105 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the106 * device. A queue maps to only one (selectable by driver) Tx DMA channel,107 * but one DMA channel may take input from several queues.108 *109 * Tx DMA FIFOs have dedicated purposes.110 *111 * For 5000 series and up, they are used differently112 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):113 *114 * 0 -- EDCA BK (background) frames, lowest priority115 * 1 -- EDCA BE (best effort) frames, normal priority116 * 2 -- EDCA VI (video) frames, higher priority117 * 3 -- EDCA VO (voice) and management frames, highest priority118 * 4 -- unused119 * 5 -- unused120 * 6 -- unused121 * 7 -- Commands122 *123 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.124 * In addition, driver can map the remaining queues to Tx DMA/FIFO125 * channels 0-3 to support 11n aggregation via EDCA DMA channels.126 *127 * The driver sets up each queue to work in one of two modes:128 *129 * 1) Scheduler-Ack, in which the scheduler automatically supports a130 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue131 * contains TFDs for a unique combination of Recipient Address (RA)132 * and Traffic Identifier (TID), that is, traffic of a given133 * Quality-Of-Service (QOS) priority, destined for a single station.134 *135 * In scheduler-ack mode, the scheduler keeps track of the Tx status of136 * each frame within the BA window, including whether it's been transmitted,137 * and whether it's been acknowledged by the receiving station. The device138 * automatically processes block-acks received from the receiving STA,139 * and reschedules un-acked frames to be retransmitted (successful140 * Tx completion may end up being out-of-order).141 *142 * The driver must maintain the queue's Byte Count table in host DRAM143 * for this mode.144 * This mode does not support fragmentation.145 *146 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.147 * The device may automatically retry Tx, but will retry only one frame148 * at a time, until receiving ACK from receiving station, or reaching149 * retry limit and giving up.150 *151 * The command queue (#4/#9) must use this mode!152 * This mode does not require use of the Byte Count table in host DRAM.153 *154 * Driver controls scheduler operation via 3 means:155 * 1) Scheduler registers156 * 2) Shared scheduler data base in internal SRAM157 * 3) Shared data in host DRAM158 *159 * Initialization:160 *161 * When loading, driver should allocate memory for:162 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.163 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory164 * (1024 bytes for each queue).165 *166 * After receiving "Alive" response from uCode, driver must initialize167 * the scheduler (especially for queue #4/#9, the command queue, otherwise168 * the driver can't issue commands!):169 */170#define SCD_MEM_LOWER_BOUND (0x0000)171 172/*173 * Max Tx window size is the max number of contiguous TFDs that the scheduler174 * can keep track of at one time when creating block-ack chains of frames.175 * Note that "64" matches the number of ack bits in a block-ack packet.176 */177#define SCD_WIN_SIZE 64178#define SCD_FRAME_LIMIT 64179 180#define SCD_TXFIFO_POS_TID (0)181#define SCD_TXFIFO_POS_RA (4)182#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)183 184/* agn SCD */185#define SCD_QUEUE_STTS_REG_POS_TXF (0)186#define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)187#define SCD_QUEUE_STTS_REG_POS_WSL (4)188#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)189#define SCD_QUEUE_STTS_REG_MSK (0x017F0000)190 191#define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00)192#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000)193#define SCD_QUEUE_CTX_REG1_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG1_ ## _n, _v)194 195#define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F)196#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000)197#define SCD_QUEUE_CTX_REG2_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG2_ ## _n, _v)198 199#define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0)200#define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18)201 202/* Context Data */203#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)204#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)205 206/* Tx status */207#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)208#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)209 210/* Translation Data */211#define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)212#define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)213 214#define SCD_CONTEXT_QUEUE_OFFSET(x)\215 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))216 217#define SCD_TX_STTS_QUEUE_OFFSET(x)\218 (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))219 220#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \221 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)222 223#define SCD_BASE (PRPH_BASE + 0xa02c00)224 225#define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)226#define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)227#define SCD_AIT (SCD_BASE + 0x0c)228#define SCD_TXFACT (SCD_BASE + 0x10)229#define SCD_ACTIVE (SCD_BASE + 0x14)230#define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)231#define SCD_CHAINEXT_EN (SCD_BASE + 0x244)232#define SCD_AGGR_SEL (SCD_BASE + 0x248)233#define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)234#define SCD_GP_CTRL (SCD_BASE + 0x1a8)235#define SCD_EN_CTRL (SCD_BASE + 0x254)236 237/*********************** END TX SCHEDULER *************************************/238 239/* Oscillator clock */240#define OSC_CLK (0xa04068)241#define OSC_CLK_FORCE_CONTROL (0x8)242 243#define FH_UCODE_LOAD_STATUS (0x1AF0)244 245/*246 * Replacing FH_UCODE_LOAD_STATUS247 * This register is writen by driver and is read by uCode during boot flow.248 * Note this address is cleared after MAC reset.249 */250#define UREG_UCODE_LOAD_STATUS (0xa05c40)251#define UREG_CPU_INIT_RUN (0xa05c44)252 253#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)254#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)255 256#define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)257#define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)258 259#define LMAC2_PRPH_OFFSET (0x100000)260 261/* Rx FIFO */262#define RXF_SIZE_ADDR (0xa00c88)263#define RXF_RD_D_SPACE (0xa00c40)264#define RXF_RD_WR_PTR (0xa00c50)265#define RXF_RD_RD_PTR (0xa00c54)266#define RXF_RD_FENCE_PTR (0xa00c4c)267#define RXF_SET_FENCE_MODE (0xa00c14)268#define RXF_LD_WR2FENCE (0xa00c1c)269#define RXF_FIFO_RD_FENCE_INC (0xa00c68)270#define RXF_SIZE_BYTE_CND_POS (7)271#define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)272#define RXF_DIFF_FROM_PREV (0x200)273#define RXF2C_DIFF_FROM_PREV (0x4e00)274 275#define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)276#define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)277 278/* Tx FIFO */279#define TXF_FIFO_ITEM_CNT (0xa00438)280#define TXF_WR_PTR (0xa00414)281#define TXF_RD_PTR (0xa00410)282#define TXF_FENCE_PTR (0xa00418)283#define TXF_LOCK_FENCE (0xa00424)284#define TXF_LARC_NUM (0xa0043c)285#define TXF_READ_MODIFY_DATA (0xa00448)286#define TXF_READ_MODIFY_ADDR (0xa0044c)287 288/* UMAC Internal Tx Fifo */289#define TXF_CPU2_FIFO_ITEM_CNT (0xA00538)290#define TXF_CPU2_WR_PTR (0xA00514)291#define TXF_CPU2_RD_PTR (0xA00510)292#define TXF_CPU2_FENCE_PTR (0xA00518)293#define TXF_CPU2_LOCK_FENCE (0xA00524)294#define TXF_CPU2_NUM (0xA0053C)295#define TXF_CPU2_READ_MODIFY_DATA (0xA00548)296#define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C)297 298/* Radio registers access */299#define RSP_RADIO_CMD (0xa02804)300#define RSP_RADIO_RDDAT (0xa02814)301#define RADIO_RSP_ADDR_POS (6)302#define RADIO_RSP_RD_CMD (3)303 304/* LTR control (Qu only) */305#define HPM_MAC_LTR_CSR 0xa0348c306#define HPM_MAC_LRT_ENABLE_ALL 0xf307/* also uses CSR_LTR_* for values */308#define HPM_UMAC_LTR 0xa03480309 310/* FW monitor */311#define MON_BUFF_SAMPLE_CTL (0xa03c00)312#define MON_BUFF_BASE_ADDR (0xa03c1c)313#define MON_BUFF_END_ADDR (0xa03c40)314#define MON_BUFF_WRPTR (0xa03c44)315#define MON_BUFF_CYCLE_CNT (0xa03c48)316/* FW monitor family 8000 and on */317#define MON_BUFF_BASE_ADDR_VER2 (0xa03c1c)318#define MON_BUFF_END_ADDR_VER2 (0xa03c20)319#define MON_BUFF_WRPTR_VER2 (0xa03c24)320#define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28)321#define MON_BUFF_SHIFT_VER2 (0x8)322/* FW monitor familiy AX210 and on */323#define DBGC_CUR_DBGBUF_BASE_ADDR_LSB (0xd03c20)324#define DBGC_CUR_DBGBUF_BASE_ADDR_MSB (0xd03c24)325#define DBGC_CUR_DBGBUF_STATUS (0xd03c1c)326#define DBGC_DBGBUF_WRAP_AROUND (0xd03c2c)327#define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK (0x00ffffff)328#define DBGC_CUR_DBGBUF_STATUS_IDX_MSK (0x0f000000)329 330#define MON_DMARB_RD_CTL_ADDR (0xa03c60)331#define MON_DMARB_RD_DATA_ADDR (0xa03c5c)332 333#define DBGC_IN_SAMPLE (0xa03c00)334#define DBGC_OUT_CTRL (0xa03c0c)335 336/* M2S registers */337#define LDBG_M2S_BUF_WPTR (0xa0476c)338#define LDBG_M2S_BUF_WRAP_CNT (0xa04774)339#define LDBG_M2S_BUF_WPTR_VAL_MSK (0x000fffff)340#define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK (0x000fffff)341 342/* enable the ID buf for read */343#define WFPM_PS_CTL_CLR 0xA0300C344#define WFMP_MAC_ADDR_0 0xA03080345#define WFMP_MAC_ADDR_1 0xA03084346#define LMPM_PMG_EN 0xA01CEC347#define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078348#define RFIC_REG_RD 0xAD0470349#define WFPM_CTRL_REG 0xA03030350#define WFPM_OTP_CFG1_ADDR 0x00a03098351#define WFPM_OTP_CFG1_IS_JACKET_BIT BIT(5)352#define WFPM_OTP_CFG1_IS_CDB_BIT BIT(4)353#define WFPM_OTP_BZ_BNJ_JACKET_BIT 5354#define WFPM_OTP_BZ_BNJ_CDB_BIT 4355#define WFPM_OTP_CFG1_IS_JACKET(_val) (((_val) & 0x00000020) >> WFPM_OTP_BZ_BNJ_JACKET_BIT)356#define WFPM_OTP_CFG1_IS_CDB(_val) (((_val) & 0x00000010) >> WFPM_OTP_BZ_BNJ_CDB_BIT)357 358 359#define WFPM_GP2 0xA030B4360 361/* DBGI SRAM Register details */362#define DBGI_SRAM_TARGET_ACCESS_RDATA_LSB 0x00A2E154363#define DBGI_SRAM_TARGET_ACCESS_RDATA_MSB 0x00A2E158364#define DBGI_SRAM_FIFO_POINTERS 0x00A2E148365#define DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK 0x00000FFF366 367enum {368 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000,369};370 371#define CNVI_AUX_MISC_CHIP 0xA200B0372#define CNVI_AUX_MISC_CHIP_MAC_STEP(_val) (((_val) & 0xf000000) >> 24)373#define CNVI_AUX_MISC_CHIP_PROD_TYPE(_val) ((_val) & 0xfff)374#define CNVI_AUX_MISC_CHIP_PROD_TYPE_GL 0x910375#define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U 0x930376#define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_I 0x900377#define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_W 0x901378 379#define CNVR_AUX_MISC_CHIP 0xA2B800380#define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM 0xA29890381#define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938382#define CNVI_SCU_SEQ_DATA_DW9 0xA27488383 384#define CNVI_PMU_STEP_FLOW 0xA2D588385#define CNVI_PMU_STEP_FLOW_FORCE_URM BIT(2)386 387#define PREG_AUX_BUS_WPROT_0 0xA04CC0388 389/* device family 9000 WPROT register */390#define PREG_PRPH_WPROT_9000 0xA04CE0391/* device family 22000 WPROT register */392#define PREG_PRPH_WPROT_22000 0xA04D00393 394#define SB_MODIFY_CFG_FLAG 0xA03088395#define SB_CFG_RESIDES_IN_ROM 0x80396#define SB_CPU_1_STATUS 0xA01E30397#define SB_CPU_2_STATUS 0xA01E34398#define UMAG_SB_CPU_1_STATUS 0xA038C0399#define UMAG_SB_CPU_2_STATUS 0xA038C4400#define UMAG_GEN_HW_STATUS 0xA038C8401#define UREG_UMAC_CURRENT_PC 0xa05c18402#define UREG_LMAC1_CURRENT_PC 0xa05c1c403#define UREG_LMAC2_CURRENT_PC 0xa05c20404 405#define WFPM_LMAC1_PD_NOTIFICATION 0xa0338c406#define WFPM_ARC1_PD_NOTIFICATION 0xa03044407#define HPM_SECONDARY_DEVICE_STATE 0xa03404408#define WFPM_MAC_OTP_CFG7_ADDR 0xa03338409#define WFPM_MAC_OTP_CFG7_DATA 0xa0333c410 411 412/* For UMAG_GEN_HW_STATUS reg check */413enum {414 UMAG_GEN_HW_IS_FPGA = BIT(1),415};416 417/* FW chicken bits */418#define LMPM_CHICK 0xA01FF8419enum {420 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0),421};422 423/* FW chicken bits */424#define LMPM_PAGE_PASS_NOTIF 0xA03824425enum {426 LMPM_PAGE_PASS_NOTIF_POS = BIT(20),427};428 429/*430 * CRF ID register431 *432 * type: bits 0-11433 * reserved: bits 12-18434 * slave_exist: bit 19435 * dash: bits 20-23436 * step: bits 24-27437 * flavor: bits 28-31438 */439#define REG_CRF_ID_TYPE(val) (((val) & 0x00000FFF) >> 0)440#define REG_CRF_ID_SLAVE(val) (((val) & 0x00080000) >> 19)441#define REG_CRF_ID_DASH(val) (((val) & 0x00F00000) >> 20)442#define REG_CRF_ID_STEP(val) (((val) & 0x0F000000) >> 24)443#define REG_CRF_ID_FLAVOR(val) (((val) & 0xF0000000) >> 28)444 445#define UREG_CHICK (0xA05C00)446#define UREG_CHICK_MSI_ENABLE BIT(24)447#define UREG_CHICK_MSIX_ENABLE BIT(25)448 449#define SD_REG_VER 0xa29600450#define SD_REG_VER_GEN2 0x00a2b800451 452#define REG_CRF_ID_TYPE_JF_1 0x201453#define REG_CRF_ID_TYPE_JF_2 0x202454#define REG_CRF_ID_TYPE_HR_CDB 0x503455#define REG_CRF_ID_TYPE_HR_NONE_CDB 0x504456#define REG_CRF_ID_TYPE_HR_NONE_CDB_1X1 0x501457#define REG_CRF_ID_TYPE_HR_NONE_CDB_CCP 0x532458#define REG_CRF_ID_TYPE_GF 0x410459#define REG_CRF_ID_TYPE_FM 0x910460#define REG_CRF_ID_TYPE_WHP 0xA10461 462#define HPM_DEBUG 0xA03440463#define PERSISTENCE_BIT BIT(12)464#define PREG_WFPM_ACCESS BIT(12)465 466#define HPM_HIPM_GEN_CFG 0xA03458467#define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0)468#define HPM_HIPM_GEN_CFG_CR_SLP_EN BIT(1)469#define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE BIT(10)470 471#define UREG_DOORBELL_TO_ISR6 0xA05C04472#define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0)473#define UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE (BIT(0) | BIT(1))474#define UREG_DOORBELL_TO_ISR6_SUSPEND BIT(18)475#define UREG_DOORBELL_TO_ISR6_RESUME BIT(19)476#define UREG_DOORBELL_TO_ISR6_PNVM BIT(20)477 478/*479 * From BZ family driver triggers this bit for suspend and resume480 * The driver should update CSR_IPC_SLEEP_CONTROL before triggering481 * this interrupt with suspend/resume value482 */483#define UREG_DOORBELL_TO_ISR6_SLEEP_CTRL BIT(31)484 485#define CNVI_MBOX_C 0xA3400C486 487#define FSEQ_ERROR_CODE 0xA340C8488#define FSEQ_TOP_INIT_VERSION 0xA34038489#define FSEQ_CNVIO_INIT_VERSION 0xA3403C490#define FSEQ_OTP_VERSION 0xA340FC491#define FSEQ_TOP_CONTENT_VERSION 0xA340F4492#define FSEQ_ALIVE_TOKEN 0xA340F0493#define FSEQ_CNVI_ID 0xA3408C494#define FSEQ_CNVR_ID 0xA34090495#define FSEQ_PREV_CNVIO_INIT_VERSION 0xA34084496#define FSEQ_WIFI_FSEQ_VERSION 0xA34040497#define FSEQ_BT_FSEQ_VERSION 0xA34044498#define FSEQ_CLASS_TP_VERSION 0xA34078499 500#define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3501#define IWL_D3_SLEEP_STATUS_RESUME 0xD0502 503#define WMAL_INDRCT_RD_CMD1_OPMOD_POS 28504#define WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK 0xFFFFF505#define WMAL_CMD_READ_BURST_ACCESS 2506#define WMAL_MRSPF_1 0xADFC20507#define WMAL_INDRCT_RD_CMD1 0xADFD44508#define WMAL_INDRCT_CMD1 0xADFC14509#define WMAL_INDRCT_CMD(addr) \510 ((WMAL_CMD_READ_BURST_ACCESS << WMAL_INDRCT_RD_CMD1_OPMOD_POS) | \511 ((addr) & WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK))512 513#define WFPM_LMAC1_PS_CTL_RW 0xA03380514#define WFPM_LMAC2_PS_CTL_RW 0xA033C0515#define WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK 0x0000000F516#define WFPM_PHYRF_STATE_ON 5517#define HBUS_TIMEOUT 0xA5A5A5A1518#define WFPM_DPHY_OFF 0xDF10FF519 520#define REG_OTP_MINOR 0xA0333C521 522#define WFPM_LMAC2_PD_NOTIFICATION 0xA033CC523#define WFPM_LMAC2_PD_RE_READ BIT(31)524 525#define DPHYIP_INDIRECT 0xA2D800526#define DPHYIP_INDIRECT_RD_MSK 0xFF000000527#define DPHYIP_INDIRECT_RD_SHIFT 24528 529#endif /* __iwl_prph_h__ */530