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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH5 * Copyright (C) 2016-2017 Intel Deutschland GmbH6 */7#ifndef __iwl_trans_h__8#define __iwl_trans_h__9 10#include <linux/ieee80211.h>11#include <linux/mm.h> /* for page_address */12#include <linux/lockdep.h>13#include <linux/kernel.h>14 15#include "iwl-debug.h"16#include "iwl-config.h"17#include "fw/img.h"18#include "iwl-op-mode.h"19#include <linux/firmware.h>20#include "fw/api/cmdhdr.h"21#include "fw/api/txq.h"22#include "fw/api/dbg-tlv.h"23#include "iwl-dbg-tlv.h"24 25/**26 * DOC: Transport layer - what is it ?27 *28 * The transport layer is the layer that deals with the HW directly. It provides29 * the PCIe access to the underlying hardwarwe. The transport layer doesn't30 * provide any policy, algorithm or anything of this kind, but only mechanisms31 * to make the HW do something. It is not completely stateless but close to it.32 */33 34/**35 * DOC: Life cycle of the transport layer36 *37 * The transport layer has a very precise life cycle.38 *39 * 1) A helper function is called during the module initialization and40 * registers the bus driver's ops with the transport's alloc function.41 * 2) Bus's probe calls to the transport layer's allocation functions.42 * Of course this function is bus specific.43 * 3) This allocation functions will spawn the upper layer which will44 * register mac80211.45 *46 * 4) At some point (i.e. mac80211's start call), the op_mode will call47 * the following sequence:48 * start_hw49 * start_fw50 *51 * 5) Then when finished (or reset):52 * stop_device53 *54 * 6) Eventually, the free function will be called.55 */56 57/* default preset 0 (start from bit 16)*/58#define IWL_FW_DBG_DOMAIN_POS 1659#define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS)60 61#define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON62 63#define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */64#define FH_RSCSR_FRAME_INVALID 0x5555000065#define FH_RSCSR_FRAME_ALIGN 0x4066#define FH_RSCSR_RPA_EN BIT(25)67#define FH_RSCSR_RADA_EN BIT(26)68#define FH_RSCSR_RXQ_POS 1669#define FH_RSCSR_RXQ_MASK 0x3F000070 71struct iwl_rx_packet {72 /*73 * The first 4 bytes of the RX frame header contain both the RX frame74 * size and some flags.75 * Bit fields:76 * 31: flag flush RB request77 * 30: flag ignore TC (terminal counter) request78 * 29: flag fast IRQ request79 * 28-27: Reserved80 * 26: RADA enabled81 * 25: Offload enabled82 * 24: RPF enabled83 * 23: RSS enabled84 * 22: Checksum enabled85 * 21-16: RX queue86 * 15-14: Reserved87 * 13-00: RX frame size88 */89 __le32 len_n_flags;90 struct iwl_cmd_header hdr;91 u8 data[];92} __packed;93 94static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt)95{96 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;97}98 99static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt)100{101 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr);102}103 104/**105 * enum CMD_MODE - how to send the host commands ?106 *107 * @CMD_ASYNC: Return right away and don't wait for the response108 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of109 * the response. The caller needs to call iwl_free_resp when done.110 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill.111 * @CMD_BLOCK_TXQS: Block TXQs while the comment is executing.112 * @CMD_SEND_IN_D3: Allow the command to be sent in D3 mode, relevant to113 * SUSPEND and RESUME commands. We are in D3 mode when we set114 * trans->system_pm_mode to IWL_PLAT_PM_MODE_D3.115 */116enum CMD_MODE {117 CMD_ASYNC = BIT(0),118 CMD_WANT_SKB = BIT(1),119 CMD_SEND_IN_RFKILL = BIT(2),120 CMD_BLOCK_TXQS = BIT(3),121 CMD_SEND_IN_D3 = BIT(4),122};123#define CMD_MODE_BITS 5124 125#define DEF_CMD_PAYLOAD_SIZE 320126 127/**128 * struct iwl_device_cmd129 *130 * For allocation of the command and tx queues, this establishes the overall131 * size of the largest command we send to uCode, except for commands that132 * aren't fully copied and use other TFD space.133 *134 * @hdr: command header135 * @payload: payload for the command136 * @hdr_wide: wide command header137 * @payload_wide: payload for the wide command138 */139struct iwl_device_cmd {140 union {141 struct {142 struct iwl_cmd_header hdr; /* uCode API */143 u8 payload[DEF_CMD_PAYLOAD_SIZE];144 };145 struct {146 struct iwl_cmd_header_wide hdr_wide;147 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE -148 sizeof(struct iwl_cmd_header_wide) +149 sizeof(struct iwl_cmd_header)];150 };151 };152} __packed;153 154/**155 * struct iwl_device_tx_cmd - buffer for TX command156 * @hdr: the header157 * @payload: the payload placeholder158 *159 * The actual structure is sized dynamically according to need.160 */161struct iwl_device_tx_cmd {162 struct iwl_cmd_header hdr;163 u8 payload[];164} __packed;165 166#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))167 168/*169 * number of transfer buffers (fragments) per transmit frame descriptor;170 * this is just the driver's idea, the hardware supports 20171 */172#define IWL_MAX_CMD_TBS_PER_TFD 2173 174/**175 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command176 *177 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's178 * ring. The transport layer doesn't map the command's buffer to DMA, but179 * rather copies it to a previously allocated DMA buffer. This flag tells180 * the transport layer not to copy the command, but to map the existing181 * buffer (that is passed in) instead. This saves the memcpy and allows182 * commands that are bigger than the fixed buffer to be submitted.183 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one.184 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this185 * chunk internally and free it again after the command completes. This186 * can (currently) be used only once per command.187 * Note that a TFD entry after a DUP one cannot be a normal copied one.188 */189enum iwl_hcmd_dataflag {190 IWL_HCMD_DFL_NOCOPY = BIT(0),191 IWL_HCMD_DFL_DUP = BIT(1),192};193 194enum iwl_error_event_table_status {195 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0),196 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1),197 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2),198 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3),199 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4),200 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5),201 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6),202};203 204/**205 * struct iwl_host_cmd - Host command to the uCode206 *207 * @data: array of chunks that composes the data of the host command208 * @resp_pkt: response packet, if %CMD_WANT_SKB was set209 * @_rx_page_order: (internally used to free response packet)210 * @_rx_page_addr: (internally used to free response packet)211 * @flags: can be CMD_*212 * @len: array of the lengths of the chunks in data213 * @dataflags: IWL_HCMD_DFL_*214 * @id: command id of the host command, for wide commands encoding the215 * version and group as well216 */217struct iwl_host_cmd {218 const void *data[IWL_MAX_CMD_TBS_PER_TFD];219 struct iwl_rx_packet *resp_pkt;220 unsigned long _rx_page_addr;221 u32 _rx_page_order;222 223 u32 flags;224 u32 id;225 u16 len[IWL_MAX_CMD_TBS_PER_TFD];226 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD];227};228 229static inline void iwl_free_resp(struct iwl_host_cmd *cmd)230{231 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order);232}233 234struct iwl_rx_cmd_buffer {235 struct page *_page;236 int _offset;237 bool _page_stolen;238 u32 _rx_page_order;239 unsigned int truesize;240};241 242static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r)243{244 return (void *)((unsigned long)page_address(r->_page) + r->_offset);245}246 247static inline int rxb_offset(struct iwl_rx_cmd_buffer *r)248{249 return r->_offset;250}251 252static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r)253{254 r->_page_stolen = true;255 get_page(r->_page);256 return r->_page;257}258 259static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r)260{261 __free_pages(r->_page, r->_rx_page_order);262}263 264#define MAX_NO_RECLAIM_CMDS 6265 266#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))267 268/*269 * Maximum number of HW queues the transport layer270 * currently supports271 */272#define IWL_MAX_HW_QUEUES 32273#define IWL_MAX_TVQM_QUEUES 512274 275#define IWL_MAX_TID_COUNT 8276#define IWL_MGMT_TID 15277#define IWL_FRAME_LIMIT 64278#define IWL_MAX_RX_HW_QUEUES 16279#define IWL_9000_MAX_RX_HW_QUEUES 1280 281/**282 * enum iwl_d3_status - WoWLAN image/device status283 * @IWL_D3_STATUS_ALIVE: firmware is still running after resume284 * @IWL_D3_STATUS_RESET: device was reset while suspended285 */286enum iwl_d3_status {287 IWL_D3_STATUS_ALIVE,288 IWL_D3_STATUS_RESET,289};290 291/**292 * enum iwl_trans_status: transport status flags293 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed294 * @STATUS_DEVICE_ENABLED: APM is enabled295 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up)296 * @STATUS_INT_ENABLED: interrupts are enabled297 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch298 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode299 * @STATUS_FW_ERROR: the fw is in error state300 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation301 * @STATUS_SUPPRESS_CMD_ERROR_ONCE: suppress "FW error in SYNC CMD" once,302 * e.g. for testing303 */304enum iwl_trans_status {305 STATUS_SYNC_HCMD_ACTIVE,306 STATUS_DEVICE_ENABLED,307 STATUS_TPOWER_PMI,308 STATUS_INT_ENABLED,309 STATUS_RFKILL_HW,310 STATUS_RFKILL_OPMODE,311 STATUS_FW_ERROR,312 STATUS_TRANS_DEAD,313 STATUS_SUPPRESS_CMD_ERROR_ONCE,314};315 316static inline int317iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size)318{319 switch (rb_size) {320 case IWL_AMSDU_2K:321 return get_order(2 * 1024);322 case IWL_AMSDU_4K:323 return get_order(4 * 1024);324 case IWL_AMSDU_8K:325 return get_order(8 * 1024);326 case IWL_AMSDU_12K:327 return get_order(16 * 1024);328 default:329 WARN_ON(1);330 return -1;331 }332}333 334static inline int335iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size)336{337 switch (rb_size) {338 case IWL_AMSDU_2K:339 return 2 * 1024;340 case IWL_AMSDU_4K:341 return 4 * 1024;342 case IWL_AMSDU_8K:343 return 8 * 1024;344 case IWL_AMSDU_12K:345 return 16 * 1024;346 default:347 WARN_ON(1);348 return 0;349 }350}351 352struct iwl_hcmd_names {353 u8 cmd_id;354 const char *const cmd_name;355};356 357#define HCMD_NAME(x) \358 { .cmd_id = x, .cmd_name = #x }359 360struct iwl_hcmd_arr {361 const struct iwl_hcmd_names *arr;362 int size;363};364 365#define HCMD_ARR(x) \366 { .arr = x, .size = ARRAY_SIZE(x) }367 368/**369 * struct iwl_dump_sanitize_ops - dump sanitization operations370 * @frob_txf: Scrub the TX FIFO data371 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header372 * but that might be short or long (&struct iwl_cmd_header or373 * &struct iwl_cmd_header_wide)374 * @frob_mem: Scrub memory data375 */376struct iwl_dump_sanitize_ops {377 void (*frob_txf)(void *ctx, void *buf, size_t buflen);378 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen);379 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen);380};381 382/**383 * struct iwl_trans_config - transport configuration384 *385 * @op_mode: pointer to the upper layer.386 * @cmd_queue: the index of the command queue.387 * Must be set before start_fw.388 * @cmd_fifo: the fifo for host commands389 * @no_reclaim_cmds: Some devices erroneously don't set the390 * SEQ_RX_FRAME bit on some notifications, this is the391 * list of such notifications to filter. Max length is392 * %MAX_NO_RECLAIM_CMDS.393 * @n_no_reclaim_cmds: # of commands in list394 * @rx_buf_size: RX buffer size needed for A-MSDUs395 * if unset 4k will be the RX buffer size396 * @bc_table_dword: set to true if the BC table expects the byte count to be397 * in DWORD (as opposed to bytes)398 * @scd_set_active: should the transport configure the SCD for HCMD queue399 * @command_groups: array of command groups, each member is an array of the400 * commands in the group; for debugging only401 * @command_groups_size: number of command groups, to avoid illegal access402 * @cb_data_offs: offset inside skb->cb to store transport data at, must have403 * space for at least two pointers404 * @fw_reset_handshake: firmware supports reset flow handshake405 * @queue_alloc_cmd_ver: queue allocation command version, set to 0406 * for using the older SCD_QUEUE_CFG, set to the version of407 * SCD_QUEUE_CONFIG_CMD otherwise.408 */409struct iwl_trans_config {410 struct iwl_op_mode *op_mode;411 412 u8 cmd_queue;413 u8 cmd_fifo;414 const u8 *no_reclaim_cmds;415 unsigned int n_no_reclaim_cmds;416 417 enum iwl_amsdu_size rx_buf_size;418 bool bc_table_dword;419 bool scd_set_active;420 const struct iwl_hcmd_arr *command_groups;421 int command_groups_size;422 423 u8 cb_data_offs;424 bool fw_reset_handshake;425 u8 queue_alloc_cmd_ver;426};427 428struct iwl_trans_dump_data {429 u32 len;430 u8 data[];431};432 433struct iwl_trans;434 435struct iwl_trans_txq_scd_cfg {436 u8 fifo;437 u8 sta_id;438 u8 tid;439 bool aggregate;440 int frame_limit;441};442 443/**444 * struct iwl_trans_rxq_dma_data - RX queue DMA data445 * @fr_bd_cb: DMA address of free BD cyclic buffer446 * @fr_bd_wid: Initial write index of the free BD cyclic buffer447 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr448 * @ur_bd_cb: DMA address of used BD cyclic buffer449 */450struct iwl_trans_rxq_dma_data {451 u64 fr_bd_cb;452 u32 fr_bd_wid;453 u64 urbd_stts_wrptr;454 u64 ur_bd_cb;455};456 457/* maximal number of DRAM MAP entries supported by FW */458#define IPC_DRAM_MAP_ENTRY_NUM_MAX 64459 460/**461 * struct iwl_pnvm_image - contains info about the parsed pnvm image462 * @chunks: array of pointers to pnvm payloads and their sizes463 * @n_chunks: the number of the pnvm payloads.464 * @version: the version of the loaded PNVM image465 */466struct iwl_pnvm_image {467 struct {468 const void *data;469 u32 len;470 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX];471 u32 n_chunks;472 u32 version;473};474 475/**476 * enum iwl_trans_state - state of the transport layer477 *478 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed479 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet480 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response481 */482enum iwl_trans_state {483 IWL_TRANS_NO_FW,484 IWL_TRANS_FW_STARTED,485 IWL_TRANS_FW_ALIVE,486};487 488/**489 * DOC: Platform power management490 *491 * In system-wide power management the entire platform goes into a low492 * power state (e.g. idle or suspend to RAM) at the same time and the493 * device is configured as a wakeup source for the entire platform.494 * This is usually triggered by userspace activity (e.g. the user495 * presses the suspend button or a power management daemon decides to496 * put the platform in low power mode). The device's behavior in this497 * mode is dictated by the wake-on-WLAN configuration.498 *499 * The terms used for the device's behavior are as follows:500 *501 * - D0: the device is fully powered and the host is awake;502 * - D3: the device is in low power mode and only reacts to503 * specific events (e.g. magic-packet received or scan504 * results found);505 *506 * These terms reflect the power modes in the firmware and are not to507 * be confused with the physical device power state.508 */509 510/**511 * enum iwl_plat_pm_mode - platform power management mode512 *513 * This enumeration describes the device's platform power management514 * behavior when in system-wide suspend (i.e WoWLAN).515 *516 * @IWL_PLAT_PM_MODE_DISABLED: power management is disabled for this517 * device. In system-wide suspend mode, it means that the all518 * connections will be closed automatically by mac80211 before519 * the platform is suspended.520 * @IWL_PLAT_PM_MODE_D3: the device goes into D3 mode (i.e. WoWLAN).521 */522enum iwl_plat_pm_mode {523 IWL_PLAT_PM_MODE_DISABLED,524 IWL_PLAT_PM_MODE_D3,525};526 527/**528 * enum iwl_ini_cfg_state529 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given530 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded531 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs532 * are corrupted. The rest of the debug TLVs will still be used533 */534enum iwl_ini_cfg_state {535 IWL_INI_CFG_STATE_NOT_LOADED,536 IWL_INI_CFG_STATE_LOADED,537 IWL_INI_CFG_STATE_CORRUPTED,538};539 540/* Max time to wait for nmi interrupt */541#define IWL_TRANS_NMI_TIMEOUT (HZ / 4)542 543/**544 * struct iwl_dram_data545 * @physical: page phy pointer546 * @block: pointer to the allocated block/page547 * @size: size of the block/page548 */549struct iwl_dram_data {550 dma_addr_t physical;551 void *block;552 int size;553};554 555/**556 * struct iwl_dram_regions - DRAM regions container structure557 * @drams: array of several DRAM areas that contains the pnvm and power558 * reduction table payloads.559 * @n_regions: number of DRAM regions that were allocated560 * @prph_scratch_mem_desc: points to a structure allocated in dram,561 * designed to show FW where all the payloads are.562 */563struct iwl_dram_regions {564 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX];565 struct iwl_dram_data prph_scratch_mem_desc;566 u8 n_regions;567};568 569/**570 * struct iwl_fw_mon - fw monitor per allocation id571 * @num_frags: number of fragments572 * @frags: an array of DRAM buffer fragments573 */574struct iwl_fw_mon {575 u32 num_frags;576 struct iwl_dram_data *frags;577};578 579/**580 * struct iwl_self_init_dram - dram data used by self init process581 * @fw: lmac and umac dram data582 * @fw_cnt: total number of items in array583 * @paging: paging dram data584 * @paging_cnt: total number of items in array585 */586struct iwl_self_init_dram {587 struct iwl_dram_data *fw;588 int fw_cnt;589 struct iwl_dram_data *paging;590 int paging_cnt;591};592 593/**594 * struct iwl_imr_data - imr dram data used during debug process595 * @imr_enable: imr enable status received from fw596 * @imr_size: imr dram size received from fw597 * @sram_addr: sram address from debug tlv598 * @sram_size: sram size from debug tlv599 * @imr2sram_remainbyte: size remained after each dma transfer600 * @imr_curr_addr: current dst address used during dma transfer601 * @imr_base_addr: imr address received from fw602 */603struct iwl_imr_data {604 u32 imr_enable;605 u32 imr_size;606 u32 sram_addr;607 u32 sram_size;608 u32 imr2sram_remainbyte;609 u64 imr_curr_addr;610 __le64 imr_base_addr;611};612 613#define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32614 615/**616 * struct iwl_pc_data - program counter details617 * @pc_name: cpu name618 * @pc_address: cpu program counter619 */620struct iwl_pc_data {621 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES];622 u32 pc_address;623};624 625/**626 * struct iwl_trans_debug - transport debug related data627 *628 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv629 * @rec_on: true iff there is a fw debug recording currently active630 * @dest_tlv: points to the destination TLV for debug631 * @conf_tlv: array of pointers to configuration TLVs for debug632 * @trigger_tlv: array of pointers to triggers TLVs for debug633 * @lmac_error_event_table: addrs of lmacs error tables634 * @umac_error_event_table: addr of umac error table635 * @tcm_error_event_table: address(es) of TCM error table(s)636 * @rcm_error_event_table: address(es) of RCM error table(s)637 * @error_event_table_tlv_status: bitmap that indicates what error table638 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status639 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state640 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state641 * @fw_mon_cfg: debug buffer allocation configuration642 * @fw_mon_ini: DRAM buffer fragments per allocation id643 * @fw_mon: DRAM buffer for firmware monitor644 * @hw_error: equals true if hw error interrupt was received from the FW645 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location646 * @unsupported_region_msk: unsupported regions out of active_regions647 * @active_regions: active regions648 * @debug_info_tlv_list: list of debug info TLVs649 * @time_point: array of debug time points650 * @periodic_trig_list: periodic triggers list651 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON652 * @ucode_preset: preset based on ucode653 * @restart_required: indicates debug restart is required654 * @last_tp_resetfw: last handling of reset during debug timepoint655 * @imr_data: IMR debug data allocation656 * @dump_file_name_ext: dump file name extension657 * @dump_file_name_ext_valid: dump file name extension if valid or not658 * @num_pc: number of program counter for cpu659 * @pc_data: details of the program counter660 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded661 */662struct iwl_trans_debug {663 u8 n_dest_reg;664 bool rec_on;665 666 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;667 const struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];668 struct iwl_fw_dbg_trigger_tlv * const *trigger_tlv;669 670 u32 lmac_error_event_table[2];671 u32 umac_error_event_table;672 u32 tcm_error_event_table[2];673 u32 rcm_error_event_table[2];674 unsigned int error_event_table_tlv_status;675 676 enum iwl_ini_cfg_state internal_ini_cfg;677 enum iwl_ini_cfg_state external_ini_cfg;678 679 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM];680 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM];681 682 struct iwl_dram_data fw_mon;683 684 bool hw_error;685 enum iwl_fw_ini_buffer_location ini_dest;686 687 u64 unsupported_region_msk;688 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID];689 struct list_head debug_info_tlv_list;690 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM];691 struct list_head periodic_trig_list;692 693 u32 domains_bitmap;694 u32 ucode_preset;695 bool restart_required;696 u32 last_tp_resetfw;697 struct iwl_imr_data imr_data;698 u8 dump_file_name_ext[IWL_FW_INI_MAX_NAME];699 bool dump_file_name_ext_valid;700 u32 num_pc;701 struct iwl_pc_data *pc_data;702 bool yoyo_bin_loaded;703};704 705struct iwl_dma_ptr {706 dma_addr_t dma;707 void *addr;708 size_t size;709};710 711struct iwl_cmd_meta {712 /* only for SYNC commands, iff the reply skb is wanted */713 struct iwl_host_cmd *source;714 u32 flags: CMD_MODE_BITS;715 /* sg_offset is valid if it is non-zero */716 u32 sg_offset: PAGE_SHIFT;717 u32 tbs;718};719 720/*721 * The FH will write back to the first TB only, so we need to copy some data722 * into the buffer regardless of whether it should be mapped or not.723 * This indicates how big the first TB must be to include the scratch buffer724 * and the assigned PN.725 * Since PN location is 8 bytes at offset 12, it's 20 now.726 * If we make it bigger then allocations will be bigger and copy slower, so727 * that's probably not useful.728 */729#define IWL_FIRST_TB_SIZE 20730#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64)731 732struct iwl_pcie_txq_entry {733 void *cmd;734 struct sk_buff *skb;735 /* buffer to free after command completes */736 const void *free_buf;737 struct iwl_cmd_meta meta;738};739 740struct iwl_pcie_first_tb_buf {741 u8 buf[IWL_FIRST_TB_SIZE_ALIGN];742};743 744/**745 * struct iwl_txq - Tx Queue for DMA746 * @tfds: transmit frame descriptors (DMA memory)747 * @first_tb_bufs: start of command headers, including scratch buffers, for748 * the writeback -- this is DMA memory and an array holding one buffer749 * for each command on the queue750 * @first_tb_dma: DMA address for the first_tb_bufs start751 * @entries: transmit entries (driver state)752 * @lock: queue lock753 * @reclaim_lock: reclaim lock754 * @stuck_timer: timer that fires if queue gets stuck755 * @trans: pointer back to transport (for timer)756 * @need_update: indicates need to update read/write index757 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID758 * @wd_timeout: queue watchdog timeout (jiffies) - per queue759 * @frozen: tx stuck queue timer is frozen760 * @frozen_expiry_remainder: remember how long until the timer fires761 * @block: queue is blocked762 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport)763 * @write_ptr: 1-st empty entry (index) host_w764 * @read_ptr: last used entry (index) host_r765 * @dma_addr: physical addr for BD's766 * @n_window: safe queue window767 * @id: queue id768 * @low_mark: low watermark, resume queue if free space more than this769 * @high_mark: high watermark, stop queue if free space less than this770 * @overflow_q: overflow queue for handling frames that didn't fit on HW queue771 * @overflow_tx: need to transmit from overflow772 *773 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame774 * descriptors) and required locking structures.775 *776 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware777 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless778 * there might be HW changes in the future). For the normal TX779 * queues, n_window, which is the size of the software queue data780 * is also 256; however, for the command queue, n_window is only781 * 32 since we don't need so many commands pending. Since the HW782 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256.783 * This means that we end up with the following:784 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |785 * SW entries: | 0 | ... | 31 |786 * where N is a number between 0 and 7. This means that the SW787 * data is a window overlayed over the HW queue.788 */789struct iwl_txq {790 void *tfds;791 struct iwl_pcie_first_tb_buf *first_tb_bufs;792 dma_addr_t first_tb_dma;793 struct iwl_pcie_txq_entry *entries;794 /* lock for syncing changes on the queue */795 spinlock_t lock;796 /* lock to prevent concurrent reclaim */797 spinlock_t reclaim_lock;798 unsigned long frozen_expiry_remainder;799 struct timer_list stuck_timer;800 struct iwl_trans *trans;801 bool need_update;802 bool frozen;803 bool ampdu;804 int block;805 unsigned long wd_timeout;806 struct sk_buff_head overflow_q;807 struct iwl_dma_ptr bc_tbl;808 809 int write_ptr;810 int read_ptr;811 dma_addr_t dma_addr;812 int n_window;813 u32 id;814 int low_mark;815 int high_mark;816 817 bool overflow_tx;818};819 820/**821 * struct iwl_trans - transport common data822 *823 * @csme_own: true if we couldn't get ownership on the device824 * @op_mode: pointer to the op_mode825 * @trans_cfg: the trans-specific configuration part826 * @cfg: pointer to the configuration827 * @drv: pointer to iwl_drv828 * @state: current device state829 * @status: a bit-mask of transport status flags830 * @dev: pointer to struct device * that represents the device831 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted.832 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported.833 * @hw_rf_id: a u32 with the device RF ID834 * @hw_cnv_id: a u32 with the device CNV ID835 * @hw_crf_id: a u32 with the device CRF ID836 * @hw_wfpm_id: a u32 with the device wfpm ID837 * @hw_id: a u32 with the ID of the device / sub-device.838 * Set during transport allocation.839 * @hw_id_str: a string with info about HW ID. Set during transport allocation.840 * @sku_id: the SKU identifier (for PNVM matching)841 * @pnvm_loaded: indicates PNVM was loaded842 * @hw_rev: the revision data of the HW843 * @hw_rev_step: The mac step of the HW844 * @pm_support: set to true in start_hw if link pm is supported845 * @ltr_enabled: set to true if the LTR is enabled846 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed847 * @reduce_power_loaded: indicates reduced power section was loaded848 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed849 * @command_groups: pointer to command group name list array850 * @command_groups_size: array size of @command_groups851 * @wide_cmd_header: true when ucode supports wide command header format852 * @wait_command_queue: wait queue for sync commands853 * @num_rx_queues: number of RX queues allocated by the transport;854 * the transport must set this before calling iwl_drv_start()855 * @iml_len: the length of the image loader856 * @iml: a pointer to the image loader itself857 * @dev_cmd_pool: pool for Tx cmd allocation - for internal use only.858 * The user should use iwl_trans_{alloc,free}_tx_cmd.859 * @dev_cmd_pool_name: name for the TX command allocation pool860 * @dbgfs_dir: iwlwifi debugfs base dir for this device861 * @sync_cmd_lockdep_map: lockdep map for checking sync commands862 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before863 * starting the firmware, used for tracing864 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the865 * start of the 802.11 header in the @rx_mpdu_cmd866 * @dbg: additional debug data, see &struct iwl_trans_debug867 * @init_dram: FW initialization DMA data868 * @system_pm_mode: the system-wide power management mode in use.869 * This mode is set dynamically, depending on the WoWLAN values870 * configured from the userspace at runtime.871 * @name: the device name872 * @mbx_addr_0_step: step address data 0873 * @mbx_addr_1_step: step address data 1874 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*),875 * only valid for discrete (not integrated) NICs876 * @invalid_tx_cmd: invalid TX command buffer877 * @reduced_cap_sku: reduced capability supported SKU878 * @no_160: device not supporting 160 MHz879 * @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz880 * @trans_specific: data for the specific transport this is allocated for/with881 */882struct iwl_trans {883 bool csme_own;884 struct iwl_op_mode *op_mode;885 const struct iwl_cfg_trans_params *trans_cfg;886 const struct iwl_cfg *cfg;887 struct iwl_drv *drv;888 enum iwl_trans_state state;889 unsigned long status;890 891 struct device *dev;892 u32 max_skb_frags;893 u32 hw_rev;894 u32 hw_rev_step;895 u32 hw_rf_id;896 u32 hw_crf_id;897 u32 hw_cnv_id;898 u32 hw_wfpm_id;899 u32 hw_id;900 char hw_id_str[52];901 u32 sku_id[3];902 bool reduced_cap_sku;903 u8 no_160:1, step_urm:1;904 905 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;906 907 bool pm_support;908 bool ltr_enabled;909 u8 pnvm_loaded:1;910 u8 fail_to_parse_pnvm_image:1;911 u8 reduce_power_loaded:1;912 u8 failed_to_load_reduce_power_image:1;913 914 const struct iwl_hcmd_arr *command_groups;915 int command_groups_size;916 bool wide_cmd_header;917 918 wait_queue_head_t wait_command_queue;919 u8 num_rx_queues;920 921 size_t iml_len;922 u8 *iml;923 924 /* The following fields are internal only */925 struct kmem_cache *dev_cmd_pool;926 char dev_cmd_pool_name[50];927 928 struct dentry *dbgfs_dir;929 930#ifdef CONFIG_LOCKDEP931 struct lockdep_map sync_cmd_lockdep_map;932#endif933 934 struct iwl_trans_debug dbg;935 struct iwl_self_init_dram init_dram;936 937 enum iwl_plat_pm_mode system_pm_mode;938 939 const char *name;940 u32 mbx_addr_0_step;941 u32 mbx_addr_1_step;942 943 u8 pcie_link_speed;944 945 struct iwl_dma_ptr invalid_tx_cmd;946 947 /* pointer to trans specific struct */948 /*Ensure that this pointer will always be aligned to sizeof pointer */949 char trans_specific[] __aligned(sizeof(void *));950};951 952const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id);953int iwl_cmd_groups_verify_sorted(const struct iwl_trans_config *trans);954 955void iwl_trans_configure(struct iwl_trans *trans,956 const struct iwl_trans_config *trans_cfg);957 958int iwl_trans_start_hw(struct iwl_trans *trans);959 960void iwl_trans_op_mode_leave(struct iwl_trans *trans);961 962void iwl_trans_fw_alive(struct iwl_trans *trans, u32 scd_addr);963 964int iwl_trans_start_fw(struct iwl_trans *trans, const struct fw_img *fw,965 bool run_in_rfkill);966 967void iwl_trans_stop_device(struct iwl_trans *trans);968 969int iwl_trans_d3_suspend(struct iwl_trans *trans, bool test, bool reset);970 971int iwl_trans_d3_resume(struct iwl_trans *trans, enum iwl_d3_status *status,972 bool test, bool reset);973 974struct iwl_trans_dump_data *975iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask,976 const struct iwl_dump_sanitize_ops *sanitize_ops,977 void *sanitize_ctx);978 979static inline struct iwl_device_tx_cmd *980iwl_trans_alloc_tx_cmd(struct iwl_trans *trans)981{982 return kmem_cache_zalloc(trans->dev_cmd_pool, GFP_ATOMIC);983}984 985int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);986 987static inline void iwl_trans_free_tx_cmd(struct iwl_trans *trans,988 struct iwl_device_tx_cmd *dev_cmd)989{990 kmem_cache_free(trans->dev_cmd_pool, dev_cmd);991}992 993int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,994 struct iwl_device_tx_cmd *dev_cmd, int queue);995 996void iwl_trans_reclaim(struct iwl_trans *trans, int queue, int ssn,997 struct sk_buff_head *skbs, bool is_flush);998 999void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, int ptr);1000 1001void iwl_trans_txq_disable(struct iwl_trans *trans, int queue,1002 bool configure_scd);1003 1004bool iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn,1005 const struct iwl_trans_txq_scd_cfg *cfg,1006 unsigned int queue_wdg_timeout);1007 1008int iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue,1009 struct iwl_trans_rxq_dma_data *data);1010 1011void iwl_trans_txq_free(struct iwl_trans *trans, int queue);1012 1013int iwl_trans_txq_alloc(struct iwl_trans *trans, u32 flags, u32 sta_mask,1014 u8 tid, int size, unsigned int wdg_timeout);1015 1016void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans,1017 int txq_id, bool shared_mode);1018 1019static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue,1020 int fifo, int sta_id, int tid,1021 int frame_limit, u16 ssn,1022 unsigned int queue_wdg_timeout)1023{1024 struct iwl_trans_txq_scd_cfg cfg = {1025 .fifo = fifo,1026 .sta_id = sta_id,1027 .tid = tid,1028 .frame_limit = frame_limit,1029 .aggregate = sta_id >= 0,1030 };1031 1032 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout);1033}1034 1035static inline1036void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo,1037 unsigned int queue_wdg_timeout)1038{1039 struct iwl_trans_txq_scd_cfg cfg = {1040 .fifo = fifo,1041 .sta_id = -1,1042 .tid = IWL_MAX_TID_COUNT,1043 .frame_limit = IWL_FRAME_LIMIT,1044 .aggregate = false,1045 };1046 1047 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout);1048}1049 1050void iwl_trans_freeze_txq_timer(struct iwl_trans *trans,1051 unsigned long txqs, bool freeze);1052 1053int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs);1054 1055int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue);1056 1057void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val);1058 1059void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val);1060 1061u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs);1062 1063u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs);1064 1065void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val);1066 1067int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,1068 void *buf, int dwords);1069 1070int iwl_trans_read_config32(struct iwl_trans *trans, u32 ofs,1071 u32 *val);1072 1073#ifdef CONFIG_IWLWIFI_DEBUGFS1074void iwl_trans_debugfs_cleanup(struct iwl_trans *trans);1075#endif1076 1077#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \1078 do { \1079 if (__builtin_constant_p(bufsize)) \1080 BUILD_BUG_ON((bufsize) % sizeof(u32)); \1081 iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\1082 } while (0)1083 1084int iwl_trans_write_imr_mem(struct iwl_trans *trans, u32 dst_addr,1085 u64 src_addr, u32 byte_cnt);1086 1087static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)1088{1089 u32 value;1090 1091 if (iwl_trans_read_mem(trans, addr, &value, 1))1092 return 0xa5a5a5a5;1093 1094 return value;1095}1096 1097int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,1098 const void *buf, int dwords);1099 1100static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,1101 u32 val)1102{1103 return iwl_trans_write_mem(trans, addr, &val, 1);1104}1105 1106void iwl_trans_set_pmi(struct iwl_trans *trans, bool state);1107 1108int iwl_trans_sw_reset(struct iwl_trans *trans, bool retake_ownership);1109 1110void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg,1111 u32 mask, u32 value);1112 1113bool _iwl_trans_grab_nic_access(struct iwl_trans *trans);1114 1115#define iwl_trans_grab_nic_access(trans) \1116 __cond_lock(nic_access, \1117 likely(_iwl_trans_grab_nic_access(trans)))1118 1119void __releases(nic_access)1120iwl_trans_release_nic_access(struct iwl_trans *trans);1121 1122static inline void iwl_trans_fw_error(struct iwl_trans *trans, bool sync)1123{1124 if (WARN_ON_ONCE(!trans->op_mode))1125 return;1126 1127 /* prevent double restarts due to the same erroneous FW */1128 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) {1129 trans->state = IWL_TRANS_NO_FW;1130 iwl_op_mode_nic_error(trans->op_mode, sync);1131 }1132}1133 1134static inline bool iwl_trans_fw_running(struct iwl_trans *trans)1135{1136 return trans->state == IWL_TRANS_FW_ALIVE;1137}1138 1139void iwl_trans_sync_nmi(struct iwl_trans *trans);1140 1141void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,1142 u32 sw_err_bit);1143 1144int iwl_trans_load_pnvm(struct iwl_trans *trans,1145 const struct iwl_pnvm_image *pnvm_data,1146 const struct iwl_ucode_capabilities *capa);1147 1148void iwl_trans_set_pnvm(struct iwl_trans *trans,1149 const struct iwl_ucode_capabilities *capa);1150 1151int iwl_trans_load_reduce_power(struct iwl_trans *trans,1152 const struct iwl_pnvm_image *payloads,1153 const struct iwl_ucode_capabilities *capa);1154 1155void iwl_trans_set_reduce_power(struct iwl_trans *trans,1156 const struct iwl_ucode_capabilities *capa);1157 1158static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans)1159{1160 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED ||1161 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED;1162}1163 1164void iwl_trans_interrupts(struct iwl_trans *trans, bool enable);1165 1166/*****************************************************1167 * transport helper functions1168 *****************************************************/1169struct iwl_trans *iwl_trans_alloc(unsigned int priv_size,1170 struct device *dev,1171 const struct iwl_cfg_trans_params *cfg_trans);1172int iwl_trans_init(struct iwl_trans *trans);1173void iwl_trans_free(struct iwl_trans *trans);1174 1175static inline bool iwl_trans_is_hw_error_value(u32 val)1176{1177 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50);1178}1179 1180/*****************************************************1181 * PCIe handling1182 *****************************************************/1183int __must_check iwl_pci_register_driver(void);1184void iwl_pci_unregister_driver(void);1185void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan);1186 1187int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans,1188 struct iwl_host_cmd *cmd);1189 1190#endif /* __iwl_trans_h__ */1191