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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause2/*3 * Copyright (C) 2017 Intel Deutschland GmbH4 * Copyright (C) 2018-2024 Intel Corporation5 */6#include "iwl-trans.h"7#include "iwl-prph.h"8#include "iwl-context-info.h"9#include "iwl-context-info-gen3.h"10#include "internal.h"11#include "fw/dbg.h"12 13#define FW_RESET_TIMEOUT (HZ / 5)14 15/*16 * Start up NIC's basic functionality after it has been reset17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())18 * NOTE: This does not load uCode nor start the embedded processor19 */20int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)21{22 int ret = 0;23 24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");25 26 /*27 * Use "set_bit" below rather than "write", to preserve any hardware28 * bits already set by default after reset.29 */30 31 /*32 * Disable L0s without affecting L1;33 * don't wait for ICH L0s (ICH bug W/A)34 */35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);37 38 /* Set FH wait threshold to maximum (HW error during stress W/A) */39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);40 41 /*42 * Enable HAP INTA (interrupt from management bus) to43 * wake device's PCI Express link L1a -> L0s44 */45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);47 48 iwl_pcie_apm_config(trans);49 50 ret = iwl_finish_nic_init(trans);51 if (ret)52 return ret;53 54 set_bit(STATUS_DEVICE_ENABLED, &trans->status);55 56 return 0;57}58 59static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)60{61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");62 63 if (op_mode_leave) {64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))65 iwl_pcie_gen2_apm_init(trans);66 67 /* inform ME that we are leaving */68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,69 CSR_RESET_LINK_PWR_MGMT_DISABLED);70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,71 CSR_HW_IF_CONFIG_REG_PREPARE |72 CSR_HW_IF_CONFIG_REG_ENABLE_PME);73 mdelay(1);74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,75 CSR_RESET_LINK_PWR_MGMT_DISABLED);76 mdelay(5);77 }78 79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);80 81 /* Stop device's DMA activity */82 iwl_pcie_apm_stop_master(trans);83 84 iwl_trans_sw_reset(trans, false);85 86 /*87 * Clear "initialization complete" bit to move adapter from88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.89 */90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)91 iwl_clear_bit(trans, CSR_GP_CNTRL,92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);93 else94 iwl_clear_bit(trans, CSR_GP_CNTRL,95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);96}97 98static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)99{100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);101 int ret;102 103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;104 105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);108 else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);111 else112 iwl_write32(trans, CSR_DOORBELL_VECTOR,113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);114 115 /* wait 200ms */116 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,117 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,118 FW_RESET_TIMEOUT);119 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {120 u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);121 122 IWL_ERR(trans,123 "timeout waiting for FW reset ACK (inta_hw=0x%x)\n",124 inta_hw);125 126 if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE))127 iwl_trans_fw_error(trans, true);128 }129 130 trans_pcie->fw_reset_state = FW_RESET_IDLE;131}132 133void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)134{135 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);136 137 lockdep_assert_held(&trans_pcie->mutex);138 139 if (trans_pcie->is_down)140 return;141 142 if (trans->state >= IWL_TRANS_FW_STARTED)143 if (trans_pcie->fw_reset_handshake)144 iwl_trans_pcie_fw_reset_handshake(trans);145 146 trans_pcie->is_down = true;147 148 /* tell the device to stop sending interrupts */149 iwl_disable_interrupts(trans);150 151 /* device going down, Stop using ICT table */152 iwl_pcie_disable_ict(trans);153 154 /*155 * If a HW restart happens during firmware loading,156 * then the firmware loading might call this function157 * and later it might be called again due to the158 * restart. So don't process again if the device is159 * already dead.160 */161 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {162 IWL_DEBUG_INFO(trans,163 "DEVICE_ENABLED bit was set and is now cleared\n");164 iwl_pcie_synchronize_irqs(trans);165 iwl_pcie_rx_napi_sync(trans);166 iwl_txq_gen2_tx_free(trans);167 iwl_pcie_rx_stop(trans);168 }169 170 iwl_pcie_ctxt_info_free_paging(trans);171 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)172 iwl_pcie_ctxt_info_gen3_free(trans, false);173 else174 iwl_pcie_ctxt_info_free(trans);175 176 /* Stop the device, and put it in low power state */177 iwl_pcie_gen2_apm_stop(trans, false);178 179 /* re-take ownership to prevent other users from stealing the device */180 iwl_trans_sw_reset(trans, true);181 182 /*183 * Upon stop, the IVAR table gets erased, so msi-x won't184 * work. This causes a bug in RF-KILL flows, since the interrupt185 * that enables radio won't fire on the correct irq, and the186 * driver won't be able to handle the interrupt.187 * Configure the IVAR table again after reset.188 */189 iwl_pcie_conf_msix_hw(trans_pcie);190 191 /*192 * Upon stop, the APM issues an interrupt if HW RF kill is set.193 * This is a bug in certain verions of the hardware.194 * Certain devices also keep sending HW RF kill interrupt all195 * the time, unless the interrupt is ACKed even if the interrupt196 * should be masked. Re-ACK all the interrupts here.197 */198 iwl_disable_interrupts(trans);199 200 /* clear all status bits */201 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);202 clear_bit(STATUS_INT_ENABLED, &trans->status);203 clear_bit(STATUS_TPOWER_PMI, &trans->status);204 205 /*206 * Even if we stop the HW, we still want the RF kill207 * interrupt208 */209 iwl_enable_rfkill_int(trans);210}211 212void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)213{214 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);215 bool was_in_rfkill;216 217 iwl_op_mode_time_point(trans->op_mode,218 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,219 NULL);220 221 mutex_lock(&trans_pcie->mutex);222 trans_pcie->opmode_down = true;223 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);224 _iwl_trans_pcie_gen2_stop_device(trans);225 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);226 mutex_unlock(&trans_pcie->mutex);227}228 229static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)230{231 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);232 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,233 trans->cfg->min_txq_size);234 int ret;235 236 /* TODO: most of the logic can be removed in A0 - but not in Z0 */237 spin_lock_bh(&trans_pcie->irq_lock);238 ret = iwl_pcie_gen2_apm_init(trans);239 spin_unlock_bh(&trans_pcie->irq_lock);240 if (ret)241 return ret;242 243 iwl_op_mode_nic_config(trans->op_mode);244 245 /* Allocate the RX queue, or reset if it is already allocated */246 if (iwl_pcie_gen2_rx_init(trans))247 return -ENOMEM;248 249 /* Allocate or reset and init all Tx and Command queues */250 if (iwl_txq_gen2_init(trans, trans_pcie->txqs.cmd.q_id, queue_size))251 return -ENOMEM;252 253 /* enable shadow regs in HW */254 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);255 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");256 257 return 0;258}259 260static void iwl_pcie_get_rf_name(struct iwl_trans *trans)261{262 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);263 char *buf = trans_pcie->rf_name;264 size_t buflen = sizeof(trans_pcie->rf_name);265 size_t pos;266 u32 version;267 268 if (buf[0])269 return;270 271 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {272 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):273 pos = scnprintf(buf, buflen, "JF");274 break;275 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):276 pos = scnprintf(buf, buflen, "GF");277 break;278 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):279 pos = scnprintf(buf, buflen, "GF4");280 break;281 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):282 pos = scnprintf(buf, buflen, "HR");283 break;284 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):285 pos = scnprintf(buf, buflen, "HR1");286 break;287 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):288 pos = scnprintf(buf, buflen, "HRCDB");289 break;290 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_MS):291 pos = scnprintf(buf, buflen, "MS");292 break;293 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_FM):294 pos = scnprintf(buf, buflen, "FM");295 break;296 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_WP):297 if (SILICON_Z_STEP ==298 CSR_HW_RFID_STEP(trans->hw_rf_id))299 pos = scnprintf(buf, buflen, "WHTC");300 else301 pos = scnprintf(buf, buflen, "WH");302 break;303 default:304 return;305 }306 307 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {308 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):309 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):310 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):311 version = iwl_read_prph(trans, CNVI_MBOX_C);312 switch (version) {313 case 0x20000:314 pos += scnprintf(buf + pos, buflen - pos, " B3");315 break;316 case 0x120000:317 pos += scnprintf(buf + pos, buflen - pos, " B5");318 break;319 default:320 pos += scnprintf(buf + pos, buflen - pos,321 " (0x%x)", version);322 break;323 }324 break;325 default:326 break;327 }328 329 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",330 trans->hw_rf_id);331 332 IWL_INFO(trans, "Detected RF %s\n", buf);333 334 /*335 * also add a \n for debugfs - need to do it after printing336 * since our IWL_INFO machinery wants to see a static \n at337 * the end of the string338 */339 pos += scnprintf(buf + pos, buflen - pos, "\n");340}341 342void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)343{344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);345 346 iwl_pcie_reset_ict(trans);347 348 /* make sure all queue are not stopped/used */349 memset(trans_pcie->txqs.queue_stopped, 0,350 sizeof(trans_pcie->txqs.queue_stopped));351 memset(trans_pcie->txqs.queue_used, 0,352 sizeof(trans_pcie->txqs.queue_used));353 354 /* now that we got alive we can free the fw image & the context info.355 * paging memory cannot be freed included since FW will still use it356 */357 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)358 iwl_pcie_ctxt_info_gen3_free(trans, true);359 else360 iwl_pcie_ctxt_info_free(trans);361 362 /*363 * Re-enable all the interrupts, including the RF-Kill one, now that364 * the firmware is alive.365 */366 iwl_enable_interrupts(trans);367 mutex_lock(&trans_pcie->mutex);368 iwl_pcie_check_hw_rf_kill(trans);369 370 iwl_pcie_get_rf_name(trans);371 mutex_unlock(&trans_pcie->mutex);372}373 374static bool iwl_pcie_set_ltr(struct iwl_trans *trans)375{376 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |377 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,378 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |379 u32_encode_bits(250,380 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |381 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |382 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,383 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |384 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);385 386 /*387 * To workaround hardware latency issues during the boot process,388 * initialize the LTR to ~250 usec (see ltr_val above).389 * The firmware initializes this again later (to a smaller value).390 */391 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||392 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&393 !trans->trans_cfg->integrated) {394 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);395 return true;396 }397 398 if (trans->trans_cfg->integrated &&399 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {400 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);401 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);402 return true;403 }404 405 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {406 /* First clear the interrupt, just in case */407 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,408 MSIX_HW_INT_CAUSES_REG_IML);409 /* In this case, unfortunately the same ROM bug exists in the410 * device (not setting LTR correctly), but we don't have control411 * over the settings from the host due to some hardware security412 * features. The only workaround we've been able to come up with413 * so far is to try to keep the CPU and device busy by polling414 * it and the IML (image loader) completed interrupt.415 */416 return false;417 }418 419 /* nothing needs to be done on other devices */420 return true;421}422 423static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)424{425/* in practice, this seems to complete in around 20-30ms at most, wait 100 */426#define IML_WAIT_TIMEOUT (HZ / 10)427 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);428 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;429 u32 value, loops = 0;430 bool irq = false;431 432 if (WARN_ON(!trans_pcie->iml))433 return;434 435 value = iwl_read32(trans, CSR_LTR_LAST_MSG);436 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",437 value);438 439 while (time_before(jiffies, end_time)) {440 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &441 MSIX_HW_INT_CAUSES_REG_IML) {442 irq = true;443 break;444 }445 /* Keep the CPU and device busy. */446 value = iwl_read32(trans, CSR_LTR_LAST_MSG);447 loops++;448 }449 450 IWL_DEBUG_INFO(trans,451 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",452 irq, loops, value);453 454 /* We don't fail here even if we timed out - maybe we get lucky and the455 * interrupt comes in later (and we get alive from firmware) and then456 * we're all happy - but if not we'll fail on alive timeout or get some457 * other error out.458 */459}460 461int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,462 const struct fw_img *fw, bool run_in_rfkill)463{464 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);465 bool hw_rfkill, keep_ram_busy;466 int ret;467 468 /* This may fail if AMT took ownership of the device */469 if (iwl_pcie_prepare_card_hw(trans)) {470 IWL_WARN(trans, "Exit HW not ready\n");471 return -EIO;472 }473 474 iwl_enable_rfkill_int(trans);475 476 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);477 478 /*479 * We enabled the RF-Kill interrupt and the handler may very480 * well be running. Disable the interrupts to make sure no other481 * interrupt can be fired.482 */483 iwl_disable_interrupts(trans);484 485 /* Make sure it finished running */486 iwl_pcie_synchronize_irqs(trans);487 488 mutex_lock(&trans_pcie->mutex);489 490 /* If platform's RF_KILL switch is NOT set to KILL */491 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);492 if (hw_rfkill && !run_in_rfkill) {493 ret = -ERFKILL;494 goto out;495 }496 497 /* Someone called stop_device, don't try to start_fw */498 if (trans_pcie->is_down) {499 IWL_WARN(trans,500 "Can't start_fw since the HW hasn't been started\n");501 ret = -EIO;502 goto out;503 }504 505 /* make sure rfkill handshake bits are cleared */506 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);507 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,508 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);509 510 /* clear (again), then enable host interrupts */511 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);512 513 ret = iwl_pcie_gen2_nic_init(trans);514 if (ret) {515 IWL_ERR(trans, "Unable to init nic\n");516 goto out;517 }518 519 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)520 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);521 else522 ret = iwl_pcie_ctxt_info_init(trans, fw);523 if (ret)524 goto out;525 526 keep_ram_busy = !iwl_pcie_set_ltr(trans);527 528 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {529 IWL_DEBUG_POWER(trans, "function scratch register value is 0x%08x\n",530 iwl_read32(trans, CSR_FUNC_SCRATCH));531 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);532 iwl_set_bit(trans, CSR_GP_CNTRL,533 CSR_GP_CNTRL_REG_FLAG_ROM_START);534 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {535 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);536 } else {537 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);538 }539 540 if (keep_ram_busy)541 iwl_pcie_spin_for_iml(trans);542 543 /* re-check RF-Kill state since we may have missed the interrupt */544 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);545 if (hw_rfkill && !run_in_rfkill)546 ret = -ERFKILL;547 548out:549 mutex_unlock(&trans_pcie->mutex);550 return ret;551}552