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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause2/*3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH5 * Copyright (C) 2016-2017 Intel Deutschland GmbH6 */7#include <linux/pci.h>8#include <linux/interrupt.h>9#include <linux/debugfs.h>10#include <linux/sched.h>11#include <linux/bitops.h>12#include <linux/gfp.h>13#include <linux/vmalloc.h>14#include <linux/module.h>15#include <linux/wait.h>16#include <linux/seq_file.h>17 18#include "iwl-drv.h"19#include "iwl-trans.h"20#include "iwl-csr.h"21#include "iwl-prph.h"22#include "iwl-scd.h"23#include "iwl-agn-hw.h"24#include "fw/error-dump.h"25#include "fw/dbg.h"26#include "fw/api/tx.h"27#include "mei/iwl-mei.h"28#include "internal.h"29#include "iwl-fh.h"30#include "iwl-context-info-gen3.h"31 32/* extended range in FW SRAM */33#define IWL_FW_MEM_EXTENDED_START 0x4000034#define IWL_FW_MEM_EXTENDED_END 0x57FFF35 36void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)37{38#define PCI_DUMP_SIZE 35239#define PCI_MEM_DUMP_SIZE 6440#define PCI_PARENT_DUMP_SIZE 52441#define PREFIX_LEN 3242 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);43 struct pci_dev *pdev = trans_pcie->pci_dev;44 u32 i, pos, alloc_size, *ptr, *buf;45 char *prefix;46 47 if (trans_pcie->pcie_dbg_dumped_once)48 return;49 50 /* Should be a multiple of 4 */51 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);52 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);53 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);54 55 /* Alloc a max size buffer */56 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN;57 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);58 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);59 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);60 61 buf = kmalloc(alloc_size, GFP_ATOMIC);62 if (!buf)63 return;64 prefix = (char *)buf + alloc_size - PREFIX_LEN;65 66 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");67 68 /* Print wifi device registers */69 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));70 IWL_ERR(trans, "iwlwifi device config registers:\n");71 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)72 if (pci_read_config_dword(pdev, i, ptr))73 goto err_read;74 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);75 76 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");77 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)78 *ptr = iwl_read32(trans, i);79 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);80 81 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);82 if (pos) {83 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");84 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)85 if (pci_read_config_dword(pdev, pos + i, ptr))86 goto err_read;87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,88 32, 4, buf, i, 0);89 }90 91 /* Print parent device registers next */92 if (!pdev->bus->self)93 goto out;94 95 pdev = pdev->bus->self;96 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));97 98 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",99 pci_name(pdev));100 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)101 if (pci_read_config_dword(pdev, i, ptr))102 goto err_read;103 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);104 105 /* Print root port AER registers */106 pos = 0;107 pdev = pcie_find_root_port(pdev);108 if (pdev)109 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);110 if (pos) {111 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",112 pci_name(pdev));113 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));114 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)115 if (pci_read_config_dword(pdev, pos + i, ptr))116 goto err_read;117 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,118 4, buf, i, 0);119 }120 goto out;121 122err_read:123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);124 IWL_ERR(trans, "Read failed at 0x%X\n", i);125out:126 trans_pcie->pcie_dbg_dumped_once = 1;127 kfree(buf);128}129 130int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership)131{132 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */133 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {134 iwl_set_bit(trans, CSR_GP_CNTRL,135 CSR_GP_CNTRL_REG_FLAG_SW_RESET);136 usleep_range(10000, 20000);137 } else {138 iwl_set_bit(trans, CSR_RESET,139 CSR_RESET_REG_FLAG_SW_RESET);140 usleep_range(5000, 6000);141 }142 143 if (retake_ownership)144 return iwl_pcie_prepare_card_hw(trans);145 146 return 0;147}148 149static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)150{151 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;152 153 if (!fw_mon->size)154 return;155 156 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,157 fw_mon->physical);158 159 fw_mon->block = NULL;160 fw_mon->physical = 0;161 fw_mon->size = 0;162}163 164static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,165 u8 max_power)166{167 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;168 void *block = NULL;169 dma_addr_t physical = 0;170 u32 size = 0;171 u8 power;172 173 if (fw_mon->size) {174 memset(fw_mon->block, 0, fw_mon->size);175 return;176 }177 178 /* need at least 2 KiB, so stop at 11 */179 for (power = max_power; power >= 11; power--) {180 size = BIT(power);181 block = dma_alloc_coherent(trans->dev, size, &physical,182 GFP_KERNEL | __GFP_NOWARN);183 if (!block)184 continue;185 186 IWL_INFO(trans,187 "Allocated 0x%08x bytes for firmware monitor.\n",188 size);189 break;190 }191 192 if (WARN_ON_ONCE(!block))193 return;194 195 if (power != max_power)196 IWL_ERR(trans,197 "Sorry - debug buffer is only %luK while you requested %luK\n",198 (unsigned long)BIT(power - 10),199 (unsigned long)BIT(max_power - 10));200 201 fw_mon->block = block;202 fw_mon->physical = physical;203 fw_mon->size = size;204}205 206void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)207{208 if (!max_power) {209 /* default max_power is maximum */210 max_power = 26;211 } else {212 max_power += 11;213 }214 215 if (WARN(max_power > 26,216 "External buffer size for monitor is too big %d, check the FW TLV\n",217 max_power))218 return;219 220 iwl_pcie_alloc_fw_monitor_block(trans, max_power);221}222 223static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)224{225 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,226 ((reg & 0x0000ffff) | (2 << 28)));227 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);228}229 230static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)231{232 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);233 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,234 ((reg & 0x0000ffff) | (3 << 28)));235}236 237static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)238{239 if (trans->cfg->apmg_not_supported)240 return;241 242 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))243 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,244 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,245 ~APMG_PS_CTRL_MSK_PWR_SRC);246 else247 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,248 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,249 ~APMG_PS_CTRL_MSK_PWR_SRC);250}251 252/* PCI registers */253#define PCI_CFG_RETRY_TIMEOUT 0x041254 255void iwl_pcie_apm_config(struct iwl_trans *trans)256{257 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);258 u16 lctl;259 u16 cap;260 261 /*262 * L0S states have been found to be unstable with our devices263 * and in newer hardware they are not officially supported at264 * all, so we must always set the L0S_DISABLED bit.265 */266 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);267 268 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);269 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);270 271 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);272 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;273 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",274 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",275 trans->ltr_enabled ? "En" : "Dis");276}277 278/*279 * Start up NIC's basic functionality after it has been reset280 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())281 * NOTE: This does not load uCode nor start the embedded processor282 */283static int iwl_pcie_apm_init(struct iwl_trans *trans)284{285 int ret;286 287 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");288 289 /*290 * Use "set_bit" below rather than "write", to preserve any hardware291 * bits already set by default after reset.292 */293 294 /* Disable L0S exit timer (platform NMI Work/Around) */295 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)296 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,297 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);298 299 /*300 * Disable L0s without affecting L1;301 * don't wait for ICH L0s (ICH bug W/A)302 */303 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,304 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);305 306 /* Set FH wait threshold to maximum (HW error during stress W/A) */307 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);308 309 /*310 * Enable HAP INTA (interrupt from management bus) to311 * wake device's PCI Express link L1a -> L0s312 */313 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,314 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);315 316 iwl_pcie_apm_config(trans);317 318 /* Configure analog phase-lock-loop before activating to D0A */319 if (trans->trans_cfg->base_params->pll_cfg)320 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);321 322 ret = iwl_finish_nic_init(trans);323 if (ret)324 return ret;325 326 if (trans->cfg->host_interrupt_operation_mode) {327 /*328 * This is a bit of an abuse - This is needed for 7260 / 3160329 * only check host_interrupt_operation_mode even if this is330 * not related to host_interrupt_operation_mode.331 *332 * Enable the oscillator to count wake up time for L1 exit. This333 * consumes slightly more power (100uA) - but allows to be sure334 * that we wake up from L1 on time.335 *336 * This looks weird: read twice the same register, discard the337 * value, set a bit, and yet again, read that same register338 * just to discard the value. But that's the way the hardware339 * seems to like it.340 */341 iwl_read_prph(trans, OSC_CLK);342 iwl_read_prph(trans, OSC_CLK);343 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);344 iwl_read_prph(trans, OSC_CLK);345 iwl_read_prph(trans, OSC_CLK);346 }347 348 /*349 * Enable DMA clock and wait for it to stabilize.350 *351 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"352 * bits do not disable clocks. This preserves any hardware353 * bits already set by default in "CLK_CTRL_REG" after reset.354 */355 if (!trans->cfg->apmg_not_supported) {356 iwl_write_prph(trans, APMG_CLK_EN_REG,357 APMG_CLK_VAL_DMA_CLK_RQT);358 udelay(20);359 360 /* Disable L1-Active */361 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,362 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);363 364 /* Clear the interrupt in APMG if the NIC is in RFKILL */365 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,366 APMG_RTC_INT_STT_RFKILL);367 }368 369 set_bit(STATUS_DEVICE_ENABLED, &trans->status);370 371 return 0;372}373 374/*375 * Enable LP XTAL to avoid HW bug where device may consume much power if376 * FW is not loaded after device reset. LP XTAL is disabled by default377 * after device HW reset. Do it only if XTAL is fed by internal source.378 * Configure device's "persistence" mode to avoid resetting XTAL again when379 * SHRD_HW_RST occurs in S3.380 */381static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)382{383 int ret;384 u32 apmg_gp1_reg;385 u32 apmg_xtal_cfg_reg;386 u32 dl_cfg_reg;387 388 /* Force XTAL ON */389 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,390 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);391 392 ret = iwl_trans_pcie_sw_reset(trans, true);393 394 if (!ret)395 ret = iwl_finish_nic_init(trans);396 397 if (WARN_ON(ret)) {398 /* Release XTAL ON request */399 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,400 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);401 return;402 }403 404 /*405 * Clear "disable persistence" to avoid LP XTAL resetting when406 * SHRD_HW_RST is applied in S3.407 */408 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,409 APMG_PCIDEV_STT_VAL_PERSIST_DIS);410 411 /*412 * Force APMG XTAL to be active to prevent its disabling by HW413 * caused by APMG idle state.414 */415 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,416 SHR_APMG_XTAL_CFG_REG);417 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,418 apmg_xtal_cfg_reg |419 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);420 421 ret = iwl_trans_pcie_sw_reset(trans, true);422 if (ret)423 IWL_ERR(trans,424 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n");425 426 /* Enable LP XTAL by indirect access through CSR */427 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);428 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |429 SHR_APMG_GP1_WF_XTAL_LP_EN |430 SHR_APMG_GP1_CHICKEN_BIT_SELECT);431 432 /* Clear delay line clock power up */433 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);434 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &435 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);436 437 /*438 * Enable persistence mode to avoid LP XTAL resetting when439 * SHRD_HW_RST is applied in S3.440 */441 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,442 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);443 444 /*445 * Clear "initialization complete" bit to move adapter from446 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.447 */448 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);449 450 /* Activates XTAL resources monitor */451 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,452 CSR_MONITOR_XTAL_RESOURCES);453 454 /* Release XTAL ON request */455 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,456 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);457 udelay(10);458 459 /* Release APMG XTAL */460 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,461 apmg_xtal_cfg_reg &462 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);463}464 465void iwl_pcie_apm_stop_master(struct iwl_trans *trans)466{467 int ret;468 469 /* stop device's busmaster DMA activity */470 471 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {472 iwl_set_bit(trans, CSR_GP_CNTRL,473 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);474 475 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,476 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,477 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,478 100);479 usleep_range(10000, 20000);480 } else {481 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);482 483 ret = iwl_poll_bit(trans, CSR_RESET,484 CSR_RESET_REG_FLAG_MASTER_DISABLED,485 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);486 }487 488 if (ret < 0)489 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");490 491 IWL_DEBUG_INFO(trans, "stop master\n");492}493 494static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)495{496 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");497 498 if (op_mode_leave) {499 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))500 iwl_pcie_apm_init(trans);501 502 /* inform ME that we are leaving */503 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)504 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,505 APMG_PCIDEV_STT_VAL_WAKE_ME);506 else if (trans->trans_cfg->device_family >=507 IWL_DEVICE_FAMILY_8000) {508 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,509 CSR_RESET_LINK_PWR_MGMT_DISABLED);510 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,511 CSR_HW_IF_CONFIG_REG_PREPARE |512 CSR_HW_IF_CONFIG_REG_ENABLE_PME);513 mdelay(1);514 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,515 CSR_RESET_LINK_PWR_MGMT_DISABLED);516 }517 mdelay(5);518 }519 520 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);521 522 /* Stop device's DMA activity */523 iwl_pcie_apm_stop_master(trans);524 525 if (trans->cfg->lp_xtal_workaround) {526 iwl_pcie_apm_lp_xtal_enable(trans);527 return;528 }529 530 iwl_trans_pcie_sw_reset(trans, false);531 532 /*533 * Clear "initialization complete" bit to move adapter from534 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.535 */536 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);537}538 539static int iwl_pcie_nic_init(struct iwl_trans *trans)540{541 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);542 int ret;543 544 /* nic_init */545 spin_lock_bh(&trans_pcie->irq_lock);546 ret = iwl_pcie_apm_init(trans);547 spin_unlock_bh(&trans_pcie->irq_lock);548 549 if (ret)550 return ret;551 552 iwl_pcie_set_pwr(trans, false);553 554 iwl_op_mode_nic_config(trans->op_mode);555 556 /* Allocate the RX queue, or reset if it is already allocated */557 ret = iwl_pcie_rx_init(trans);558 if (ret)559 return ret;560 561 /* Allocate or reset and init all Tx and Command queues */562 if (iwl_pcie_tx_init(trans)) {563 iwl_pcie_rx_free(trans);564 return -ENOMEM;565 }566 567 if (trans->trans_cfg->base_params->shadow_reg_enable) {568 /* enable shadow regs in HW */569 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);570 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");571 }572 573 return 0;574}575 576#define HW_READY_TIMEOUT (50)577 578/* Note: returns poll_bit return value, which is >= 0 if success */579static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)580{581 int ret;582 583 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,584 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);585 586 /* See if we got it */587 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,588 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,589 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,590 HW_READY_TIMEOUT);591 592 if (ret >= 0)593 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);594 595 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");596 return ret;597}598 599/* Note: returns standard 0/-ERROR code */600int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)601{602 int ret;603 int iter;604 605 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");606 607 ret = iwl_pcie_set_hw_ready(trans);608 /* If the card is ready, exit 0 */609 if (ret >= 0) {610 trans->csme_own = false;611 return 0;612 }613 614 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,615 CSR_RESET_LINK_PWR_MGMT_DISABLED);616 usleep_range(1000, 2000);617 618 for (iter = 0; iter < 10; iter++) {619 int t = 0;620 621 /* If HW is not ready, prepare the conditions to check again */622 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,623 CSR_HW_IF_CONFIG_REG_PREPARE);624 625 do {626 ret = iwl_pcie_set_hw_ready(trans);627 if (ret >= 0) {628 trans->csme_own = false;629 return 0;630 }631 632 if (iwl_mei_is_connected()) {633 IWL_DEBUG_INFO(trans,634 "Couldn't prepare the card but SAP is connected\n");635 trans->csme_own = true;636 if (trans->trans_cfg->device_family !=637 IWL_DEVICE_FAMILY_9000)638 IWL_ERR(trans,639 "SAP not supported for this NIC family\n");640 641 return -EBUSY;642 }643 644 usleep_range(200, 1000);645 t += 200;646 } while (t < 150000);647 msleep(25);648 }649 650 IWL_ERR(trans, "Couldn't prepare the card\n");651 652 return ret;653}654 655/*656 * ucode657 */658static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,659 u32 dst_addr, dma_addr_t phy_addr,660 u32 byte_cnt)661{662 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),663 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);664 665 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),666 dst_addr);667 668 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),669 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);670 671 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),672 (iwl_get_dma_hi_addr(phy_addr)673 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);674 675 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),676 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |677 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |678 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);679 680 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),681 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |682 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |683 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);684}685 686static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,687 u32 dst_addr, dma_addr_t phy_addr,688 u32 byte_cnt)689{690 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);691 int ret;692 693 trans_pcie->ucode_write_complete = false;694 695 if (!iwl_trans_grab_nic_access(trans))696 return -EIO;697 698 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,699 byte_cnt);700 iwl_trans_release_nic_access(trans);701 702 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,703 trans_pcie->ucode_write_complete, 5 * HZ);704 if (!ret) {705 IWL_ERR(trans, "Failed to load firmware chunk!\n");706 iwl_trans_pcie_dump_regs(trans);707 return -ETIMEDOUT;708 }709 710 return 0;711}712 713static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,714 const struct fw_desc *section)715{716 u8 *v_addr;717 dma_addr_t p_addr;718 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);719 int ret = 0;720 721 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",722 section_num);723 724 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,725 GFP_KERNEL | __GFP_NOWARN);726 if (!v_addr) {727 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");728 chunk_sz = PAGE_SIZE;729 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,730 &p_addr, GFP_KERNEL);731 if (!v_addr)732 return -ENOMEM;733 }734 735 for (offset = 0; offset < section->len; offset += chunk_sz) {736 u32 copy_size, dst_addr;737 bool extended_addr = false;738 739 copy_size = min_t(u32, chunk_sz, section->len - offset);740 dst_addr = section->offset + offset;741 742 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&743 dst_addr <= IWL_FW_MEM_EXTENDED_END)744 extended_addr = true;745 746 if (extended_addr)747 iwl_set_bits_prph(trans, LMPM_CHICK,748 LMPM_CHICK_EXTENDED_ADDR_SPACE);749 750 memcpy(v_addr, (const u8 *)section->data + offset, copy_size);751 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,752 copy_size);753 754 if (extended_addr)755 iwl_clear_bits_prph(trans, LMPM_CHICK,756 LMPM_CHICK_EXTENDED_ADDR_SPACE);757 758 if (ret) {759 IWL_ERR(trans,760 "Could not load the [%d] uCode section\n",761 section_num);762 break;763 }764 }765 766 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);767 return ret;768}769 770static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,771 const struct fw_img *image,772 int cpu,773 int *first_ucode_section)774{775 int shift_param;776 int i, ret = 0, sec_num = 0x1;777 u32 val, last_read_idx = 0;778 779 if (cpu == 1) {780 shift_param = 0;781 *first_ucode_section = 0;782 } else {783 shift_param = 16;784 (*first_ucode_section)++;785 }786 787 for (i = *first_ucode_section; i < image->num_sec; i++) {788 last_read_idx = i;789 790 /*791 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between792 * CPU1 to CPU2.793 * PAGING_SEPARATOR_SECTION delimiter - separate between794 * CPU2 non paged to CPU2 paging sec.795 */796 if (!image->sec[i].data ||797 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||798 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {799 IWL_DEBUG_FW(trans,800 "Break since Data not valid or Empty section, sec = %d\n",801 i);802 break;803 }804 805 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);806 if (ret)807 return ret;808 809 /* Notify ucode of loaded section number and status */810 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);811 val = val | (sec_num << shift_param);812 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);813 814 sec_num = (sec_num << 1) | 0x1;815 }816 817 *first_ucode_section = last_read_idx;818 819 iwl_enable_interrupts(trans);820 821 if (trans->trans_cfg->gen2) {822 if (cpu == 1)823 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,824 0xFFFF);825 else826 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,827 0xFFFFFFFF);828 } else {829 if (cpu == 1)830 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,831 0xFFFF);832 else833 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,834 0xFFFFFFFF);835 }836 837 return 0;838}839 840static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,841 const struct fw_img *image,842 int cpu,843 int *first_ucode_section)844{845 int i, ret = 0;846 u32 last_read_idx = 0;847 848 if (cpu == 1)849 *first_ucode_section = 0;850 else851 (*first_ucode_section)++;852 853 for (i = *first_ucode_section; i < image->num_sec; i++) {854 last_read_idx = i;855 856 /*857 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between858 * CPU1 to CPU2.859 * PAGING_SEPARATOR_SECTION delimiter - separate between860 * CPU2 non paged to CPU2 paging sec.861 */862 if (!image->sec[i].data ||863 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||864 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {865 IWL_DEBUG_FW(trans,866 "Break since Data not valid or Empty section, sec = %d\n",867 i);868 break;869 }870 871 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);872 if (ret)873 return ret;874 }875 876 *first_ucode_section = last_read_idx;877 878 return 0;879}880 881static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)882{883 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;884 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =885 &trans->dbg.fw_mon_cfg[alloc_id];886 struct iwl_dram_data *frag;887 888 if (!iwl_trans_dbg_ini_valid(trans))889 return;890 891 if (le32_to_cpu(fw_mon_cfg->buf_location) ==892 IWL_FW_INI_LOCATION_SRAM_PATH) {893 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");894 /* set sram monitor by enabling bit 7 */895 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,896 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);897 898 return;899 }900 901 if (le32_to_cpu(fw_mon_cfg->buf_location) !=902 IWL_FW_INI_LOCATION_DRAM_PATH ||903 !trans->dbg.fw_mon_ini[alloc_id].num_frags)904 return;905 906 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];907 908 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",909 alloc_id);910 911 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,912 frag->physical >> MON_BUFF_SHIFT_VER2);913 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,914 (frag->physical + frag->size - 256) >>915 MON_BUFF_SHIFT_VER2);916}917 918void iwl_pcie_apply_destination(struct iwl_trans *trans)919{920 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;921 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;922 int i;923 924 if (iwl_trans_dbg_ini_valid(trans)) {925 iwl_pcie_apply_destination_ini(trans);926 return;927 }928 929 IWL_INFO(trans, "Applying debug destination %s\n",930 get_fw_dbg_mode_string(dest->monitor_mode));931 932 if (dest->monitor_mode == EXTERNAL_MODE)933 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);934 else935 IWL_WARN(trans, "PCI should have external buffer debug\n");936 937 for (i = 0; i < trans->dbg.n_dest_reg; i++) {938 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);939 u32 val = le32_to_cpu(dest->reg_ops[i].val);940 941 switch (dest->reg_ops[i].op) {942 case CSR_ASSIGN:943 iwl_write32(trans, addr, val);944 break;945 case CSR_SETBIT:946 iwl_set_bit(trans, addr, BIT(val));947 break;948 case CSR_CLEARBIT:949 iwl_clear_bit(trans, addr, BIT(val));950 break;951 case PRPH_ASSIGN:952 iwl_write_prph(trans, addr, val);953 break;954 case PRPH_SETBIT:955 iwl_set_bits_prph(trans, addr, BIT(val));956 break;957 case PRPH_CLEARBIT:958 iwl_clear_bits_prph(trans, addr, BIT(val));959 break;960 case PRPH_BLOCKBIT:961 if (iwl_read_prph(trans, addr) & BIT(val)) {962 IWL_ERR(trans,963 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",964 val, addr);965 goto monitor;966 }967 break;968 default:969 IWL_ERR(trans, "FW debug - unknown OP %d\n",970 dest->reg_ops[i].op);971 break;972 }973 }974 975monitor:976 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {977 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),978 fw_mon->physical >> dest->base_shift);979 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)980 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),981 (fw_mon->physical + fw_mon->size -982 256) >> dest->end_shift);983 else984 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),985 (fw_mon->physical + fw_mon->size) >>986 dest->end_shift);987 }988}989 990static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,991 const struct fw_img *image)992{993 int ret = 0;994 int first_ucode_section;995 996 IWL_DEBUG_FW(trans, "working with %s CPU\n",997 image->is_dual_cpus ? "Dual" : "Single");998 999 /* load to FW the binary non secured sections of CPU1 */1000 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);1001 if (ret)1002 return ret;1003 1004 if (image->is_dual_cpus) {1005 /* set CPU2 header address */1006 iwl_write_prph(trans,1007 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,1008 LMPM_SECURE_CPU2_HDR_MEM_SPACE);1009 1010 /* load to FW the binary sections of CPU2 */1011 ret = iwl_pcie_load_cpu_sections(trans, image, 2,1012 &first_ucode_section);1013 if (ret)1014 return ret;1015 }1016 1017 if (iwl_pcie_dbg_on(trans))1018 iwl_pcie_apply_destination(trans);1019 1020 iwl_enable_interrupts(trans);1021 1022 /* release CPU reset */1023 iwl_write32(trans, CSR_RESET, 0);1024 1025 return 0;1026}1027 1028static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,1029 const struct fw_img *image)1030{1031 int ret = 0;1032 int first_ucode_section;1033 1034 IWL_DEBUG_FW(trans, "working with %s CPU\n",1035 image->is_dual_cpus ? "Dual" : "Single");1036 1037 if (iwl_pcie_dbg_on(trans))1038 iwl_pcie_apply_destination(trans);1039 1040 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",1041 iwl_read_prph(trans, WFPM_GP2));1042 1043 /*1044 * Set default value. On resume reading the values that were1045 * zeored can provide debug data on the resume flow.1046 * This is for debugging only and has no functional impact.1047 */1048 iwl_write_prph(trans, WFPM_GP2, 0x01010101);1049 1050 /* configure the ucode to be ready to get the secured image */1051 /* release CPU reset */1052 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);1053 1054 /* load to FW the binary Secured sections of CPU1 */1055 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,1056 &first_ucode_section);1057 if (ret)1058 return ret;1059 1060 /* load to FW the binary sections of CPU2 */1061 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,1062 &first_ucode_section);1063}1064 1065bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)1066{1067 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1068 bool hw_rfkill = iwl_is_rfkill_set(trans);1069 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);1070 bool report;1071 1072 if (hw_rfkill) {1073 set_bit(STATUS_RFKILL_HW, &trans->status);1074 set_bit(STATUS_RFKILL_OPMODE, &trans->status);1075 } else {1076 clear_bit(STATUS_RFKILL_HW, &trans->status);1077 if (trans_pcie->opmode_down)1078 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);1079 }1080 1081 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);1082 1083 if (prev != report)1084 iwl_trans_pcie_rf_kill(trans, report, false);1085 1086 return hw_rfkill;1087}1088 1089struct iwl_causes_list {1090 u16 mask_reg;1091 u8 bit;1092 u8 addr;1093};1094 1095#define IWL_CAUSE(reg, mask) \1096 { \1097 .mask_reg = reg, \1098 .bit = ilog2(mask), \1099 .addr = ilog2(mask) + \1100 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \1101 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \1102 0xffff), /* causes overflow warning */ \1103 }1104 1105static const struct iwl_causes_list causes_list_common[] = {1106 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM),1107 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM),1108 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D),1109 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR),1110 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE),1111 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP),1112 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE),1113 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR),1114 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL),1115 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL),1116 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC),1117 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD),1118 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX),1119 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR),1120 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP),1121};1122 1123static const struct iwl_causes_list causes_list_pre_bz[] = {1124 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR),1125};1126 1127static const struct iwl_causes_list causes_list_bz[] = {1128 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ),1129};1130 1131static void iwl_pcie_map_list(struct iwl_trans *trans,1132 const struct iwl_causes_list *causes,1133 int arr_size, int val)1134{1135 int i;1136 1137 for (i = 0; i < arr_size; i++) {1138 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);1139 iwl_clear_bit(trans, causes[i].mask_reg,1140 BIT(causes[i].bit));1141 }1142}1143 1144static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)1145{1146 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1147 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;1148 /*1149 * Access all non RX causes and map them to the default irq.1150 * In case we are missing at least one interrupt vector,1151 * the first interrupt vector will serve non-RX and FBQ causes.1152 */1153 iwl_pcie_map_list(trans, causes_list_common,1154 ARRAY_SIZE(causes_list_common), val);1155 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)1156 iwl_pcie_map_list(trans, causes_list_bz,1157 ARRAY_SIZE(causes_list_bz), val);1158 else1159 iwl_pcie_map_list(trans, causes_list_pre_bz,1160 ARRAY_SIZE(causes_list_pre_bz), val);1161}1162 1163static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)1164{1165 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1166 u32 offset =1167 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;1168 u32 val, idx;1169 1170 /*1171 * The first RX queue - fallback queue, which is designated for1172 * management frame, command responses etc, is always mapped to the1173 * first interrupt vector. The other RX queues are mapped to1174 * the other (N - 2) interrupt vectors.1175 */1176 val = BIT(MSIX_FH_INT_CAUSES_Q(0));1177 for (idx = 1; idx < trans->num_rx_queues; idx++) {1178 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),1179 MSIX_FH_INT_CAUSES_Q(idx - offset));1180 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));1181 }1182 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);1183 1184 val = MSIX_FH_INT_CAUSES_Q(0);1185 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)1186 val |= MSIX_NON_AUTO_CLEAR_CAUSE;1187 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);1188 1189 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)1190 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);1191}1192 1193void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)1194{1195 struct iwl_trans *trans = trans_pcie->trans;1196 1197 if (!trans_pcie->msix_enabled) {1198 if (trans->trans_cfg->mq_rx_supported &&1199 test_bit(STATUS_DEVICE_ENABLED, &trans->status))1200 iwl_write_umac_prph(trans, UREG_CHICK,1201 UREG_CHICK_MSI_ENABLE);1202 return;1203 }1204 /*1205 * The IVAR table needs to be configured again after reset,1206 * but if the device is disabled, we can't write to1207 * prph.1208 */1209 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))1210 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);1211 1212 /*1213 * Each cause from the causes list above and the RX causes is1214 * represented as a byte in the IVAR table. The first nibble1215 * represents the bound interrupt vector of the cause, the second1216 * represents no auto clear for this cause. This will be set if its1217 * interrupt vector is bound to serve other causes.1218 */1219 iwl_pcie_map_rx_causes(trans);1220 1221 iwl_pcie_map_non_rx_causes(trans);1222}1223 1224static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)1225{1226 struct iwl_trans *trans = trans_pcie->trans;1227 1228 iwl_pcie_conf_msix_hw(trans_pcie);1229 1230 if (!trans_pcie->msix_enabled)1231 return;1232 1233 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);1234 trans_pcie->fh_mask = trans_pcie->fh_init_mask;1235 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);1236 trans_pcie->hw_mask = trans_pcie->hw_init_mask;1237}1238 1239static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq)1240{1241 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1242 1243 lockdep_assert_held(&trans_pcie->mutex);1244 1245 if (trans_pcie->is_down)1246 return;1247 1248 trans_pcie->is_down = true;1249 1250 /* tell the device to stop sending interrupts */1251 iwl_disable_interrupts(trans);1252 1253 /* device going down, Stop using ICT table */1254 iwl_pcie_disable_ict(trans);1255 1256 /*1257 * If a HW restart happens during firmware loading,1258 * then the firmware loading might call this function1259 * and later it might be called again due to the1260 * restart. So don't process again if the device is1261 * already dead.1262 */1263 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {1264 IWL_DEBUG_INFO(trans,1265 "DEVICE_ENABLED bit was set and is now cleared\n");1266 if (!from_irq)1267 iwl_pcie_synchronize_irqs(trans);1268 iwl_pcie_rx_napi_sync(trans);1269 iwl_pcie_tx_stop(trans);1270 iwl_pcie_rx_stop(trans);1271 1272 /* Power-down device's busmaster DMA clocks */1273 if (!trans->cfg->apmg_not_supported) {1274 iwl_write_prph(trans, APMG_CLK_DIS_REG,1275 APMG_CLK_VAL_DMA_CLK_RQT);1276 udelay(5);1277 }1278 }1279 1280 /* Make sure (redundant) we've released our request to stay awake */1281 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)1282 iwl_clear_bit(trans, CSR_GP_CNTRL,1283 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);1284 else1285 iwl_clear_bit(trans, CSR_GP_CNTRL,1286 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);1287 1288 /* Stop the device, and put it in low power state */1289 iwl_pcie_apm_stop(trans, false);1290 1291 /* re-take ownership to prevent other users from stealing the device */1292 iwl_trans_pcie_sw_reset(trans, true);1293 1294 /*1295 * Upon stop, the IVAR table gets erased, so msi-x won't1296 * work. This causes a bug in RF-KILL flows, since the interrupt1297 * that enables radio won't fire on the correct irq, and the1298 * driver won't be able to handle the interrupt.1299 * Configure the IVAR table again after reset.1300 */1301 iwl_pcie_conf_msix_hw(trans_pcie);1302 1303 /*1304 * Upon stop, the APM issues an interrupt if HW RF kill is set.1305 * This is a bug in certain verions of the hardware.1306 * Certain devices also keep sending HW RF kill interrupt all1307 * the time, unless the interrupt is ACKed even if the interrupt1308 * should be masked. Re-ACK all the interrupts here.1309 */1310 iwl_disable_interrupts(trans);1311 1312 /* clear all status bits */1313 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);1314 clear_bit(STATUS_INT_ENABLED, &trans->status);1315 clear_bit(STATUS_TPOWER_PMI, &trans->status);1316 1317 /*1318 * Even if we stop the HW, we still want the RF kill1319 * interrupt1320 */1321 iwl_enable_rfkill_int(trans);1322}1323 1324void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)1325{1326 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1327 1328 if (trans_pcie->msix_enabled) {1329 int i;1330 1331 for (i = 0; i < trans_pcie->alloc_vecs; i++)1332 synchronize_irq(trans_pcie->msix_entries[i].vector);1333 } else {1334 synchronize_irq(trans_pcie->pci_dev->irq);1335 }1336}1337 1338int iwl_trans_pcie_start_fw(struct iwl_trans *trans,1339 const struct fw_img *fw, bool run_in_rfkill)1340{1341 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1342 bool hw_rfkill;1343 int ret;1344 1345 /* This may fail if AMT took ownership of the device */1346 if (iwl_pcie_prepare_card_hw(trans)) {1347 IWL_WARN(trans, "Exit HW not ready\n");1348 return -EIO;1349 }1350 1351 iwl_enable_rfkill_int(trans);1352 1353 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);1354 1355 /*1356 * We enabled the RF-Kill interrupt and the handler may very1357 * well be running. Disable the interrupts to make sure no other1358 * interrupt can be fired.1359 */1360 iwl_disable_interrupts(trans);1361 1362 /* Make sure it finished running */1363 iwl_pcie_synchronize_irqs(trans);1364 1365 mutex_lock(&trans_pcie->mutex);1366 1367 /* If platform's RF_KILL switch is NOT set to KILL */1368 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);1369 if (hw_rfkill && !run_in_rfkill) {1370 ret = -ERFKILL;1371 goto out;1372 }1373 1374 /* Someone called stop_device, don't try to start_fw */1375 if (trans_pcie->is_down) {1376 IWL_WARN(trans,1377 "Can't start_fw since the HW hasn't been started\n");1378 ret = -EIO;1379 goto out;1380 }1381 1382 /* make sure rfkill handshake bits are cleared */1383 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);1384 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,1385 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);1386 1387 /* clear (again), then enable host interrupts */1388 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);1389 1390 ret = iwl_pcie_nic_init(trans);1391 if (ret) {1392 IWL_ERR(trans, "Unable to init nic\n");1393 goto out;1394 }1395 1396 /*1397 * Now, we load the firmware and don't want to be interrupted, even1398 * by the RF-Kill interrupt (hence mask all the interrupt besides the1399 * FH_TX interrupt which is needed to load the firmware). If the1400 * RF-Kill switch is toggled, we will find out after having loaded1401 * the firmware and return the proper value to the caller.1402 */1403 iwl_enable_fw_load_int(trans);1404 1405 /* really make sure rfkill handshake bits are cleared */1406 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);1407 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);1408 1409 /* Load the given image to the HW */1410 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)1411 ret = iwl_pcie_load_given_ucode_8000(trans, fw);1412 else1413 ret = iwl_pcie_load_given_ucode(trans, fw);1414 1415 /* re-check RF-Kill state since we may have missed the interrupt */1416 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);1417 if (hw_rfkill && !run_in_rfkill)1418 ret = -ERFKILL;1419 1420out:1421 mutex_unlock(&trans_pcie->mutex);1422 return ret;1423}1424 1425void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)1426{1427 iwl_pcie_reset_ict(trans);1428 iwl_pcie_tx_start(trans, scd_addr);1429}1430 1431void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,1432 bool was_in_rfkill)1433{1434 bool hw_rfkill;1435 1436 /*1437 * Check again since the RF kill state may have changed while1438 * all the interrupts were disabled, in this case we couldn't1439 * receive the RF kill interrupt and update the state in the1440 * op_mode.1441 * Don't call the op_mode if the rkfill state hasn't changed.1442 * This allows the op_mode to call stop_device from the rfkill1443 * notification without endless recursion. Under very rare1444 * circumstances, we might have a small recursion if the rfkill1445 * state changed exactly now while we were called from stop_device.1446 * This is very unlikely but can happen and is supported.1447 */1448 hw_rfkill = iwl_is_rfkill_set(trans);1449 if (hw_rfkill) {1450 set_bit(STATUS_RFKILL_HW, &trans->status);1451 set_bit(STATUS_RFKILL_OPMODE, &trans->status);1452 } else {1453 clear_bit(STATUS_RFKILL_HW, &trans->status);1454 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);1455 }1456 if (hw_rfkill != was_in_rfkill)1457 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false);1458}1459 1460void iwl_trans_pcie_stop_device(struct iwl_trans *trans)1461{1462 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1463 bool was_in_rfkill;1464 1465 iwl_op_mode_time_point(trans->op_mode,1466 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,1467 NULL);1468 1469 mutex_lock(&trans_pcie->mutex);1470 trans_pcie->opmode_down = true;1471 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);1472 _iwl_trans_pcie_stop_device(trans, false);1473 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);1474 mutex_unlock(&trans_pcie->mutex);1475}1476 1477void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq)1478{1479 struct iwl_trans_pcie __maybe_unused *trans_pcie =1480 IWL_TRANS_GET_PCIE_TRANS(trans);1481 1482 lockdep_assert_held(&trans_pcie->mutex);1483 1484 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",1485 state ? "disabled" : "enabled");1486 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) &&1487 !WARN_ON(trans->trans_cfg->gen2))1488 _iwl_trans_pcie_stop_device(trans, from_irq);1489}1490 1491void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,1492 bool test, bool reset)1493{1494 iwl_disable_interrupts(trans);1495 1496 /*1497 * in testing mode, the host stays awake and the1498 * hardware won't be reset (not even partially)1499 */1500 if (test)1501 return;1502 1503 iwl_pcie_disable_ict(trans);1504 1505 iwl_pcie_synchronize_irqs(trans);1506 1507 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {1508 iwl_clear_bit(trans, CSR_GP_CNTRL,1509 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);1510 iwl_clear_bit(trans, CSR_GP_CNTRL,1511 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);1512 } else {1513 iwl_clear_bit(trans, CSR_GP_CNTRL,1514 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);1515 iwl_clear_bit(trans, CSR_GP_CNTRL,1516 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);1517 }1518 1519 if (reset) {1520 /*1521 * reset TX queues -- some of their registers reset during S31522 * so if we don't reset everything here the D3 image would try1523 * to execute some invalid memory upon resume1524 */1525 iwl_trans_pcie_tx_reset(trans);1526 }1527 1528 iwl_pcie_set_pwr(trans, true);1529}1530 1531static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)1532{1533 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1534 int ret;1535 1536 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)1537 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,1538 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :1539 UREG_DOORBELL_TO_ISR6_RESUME);1540 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)1541 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,1542 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :1543 CSR_IPC_SLEEP_CONTROL_RESUME);1544 else1545 return 0;1546 1547 ret = wait_event_timeout(trans_pcie->sx_waitq,1548 trans_pcie->sx_complete, 2 * HZ);1549 1550 /* Invalidate it toward next suspend or resume */1551 trans_pcie->sx_complete = false;1552 1553 if (!ret) {1554 IWL_ERR(trans, "Timeout %s D3\n",1555 suspend ? "entering" : "exiting");1556 return -ETIMEDOUT;1557 }1558 1559 return 0;1560}1561 1562int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset)1563{1564 int ret;1565 1566 if (!reset)1567 /* Enable persistence mode to avoid reset */1568 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,1569 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);1570 1571 ret = iwl_pcie_d3_handshake(trans, true);1572 if (ret)1573 return ret;1574 1575 iwl_pcie_d3_complete_suspend(trans, test, reset);1576 1577 return 0;1578}1579 1580int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,1581 enum iwl_d3_status *status,1582 bool test, bool reset)1583{1584 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1585 u32 val;1586 int ret;1587 1588 if (test) {1589 iwl_enable_interrupts(trans);1590 *status = IWL_D3_STATUS_ALIVE;1591 ret = 0;1592 goto out;1593 }1594 1595 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)1596 iwl_set_bit(trans, CSR_GP_CNTRL,1597 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);1598 else1599 iwl_set_bit(trans, CSR_GP_CNTRL,1600 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);1601 1602 ret = iwl_finish_nic_init(trans);1603 if (ret)1604 return ret;1605 1606 /*1607 * Reconfigure IVAR table in case of MSIX or reset ict table in1608 * MSI mode since HW reset erased it.1609 * Also enables interrupts - none will happen as1610 * the device doesn't know we're waking it up, only when1611 * the opmode actually tells it after this call.1612 */1613 iwl_pcie_conf_msix_hw(trans_pcie);1614 if (!trans_pcie->msix_enabled)1615 iwl_pcie_reset_ict(trans);1616 iwl_enable_interrupts(trans);1617 1618 iwl_pcie_set_pwr(trans, false);1619 1620 if (!reset) {1621 iwl_clear_bit(trans, CSR_GP_CNTRL,1622 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);1623 } else {1624 iwl_trans_pcie_tx_reset(trans);1625 1626 ret = iwl_pcie_rx_init(trans);1627 if (ret) {1628 IWL_ERR(trans,1629 "Failed to resume the device (RX reset)\n");1630 return ret;1631 }1632 }1633 1634 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",1635 iwl_read_umac_prph(trans, WFPM_GP2));1636 1637 val = iwl_read32(trans, CSR_RESET);1638 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)1639 *status = IWL_D3_STATUS_RESET;1640 else1641 *status = IWL_D3_STATUS_ALIVE;1642 1643out:1644 if (*status == IWL_D3_STATUS_ALIVE)1645 ret = iwl_pcie_d3_handshake(trans, false);1646 1647 return ret;1648}1649 1650static void1651iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,1652 struct iwl_trans *trans,1653 const struct iwl_cfg_trans_params *cfg_trans)1654{1655 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1656 int max_irqs, num_irqs, i, ret;1657 u16 pci_cmd;1658 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;1659 1660 if (!cfg_trans->mq_rx_supported)1661 goto enable_msi;1662 1663 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)1664 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;1665 1666 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);1667 for (i = 0; i < max_irqs; i++)1668 trans_pcie->msix_entries[i].entry = i;1669 1670 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,1671 MSIX_MIN_INTERRUPT_VECTORS,1672 max_irqs);1673 if (num_irqs < 0) {1674 IWL_DEBUG_INFO(trans,1675 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",1676 num_irqs);1677 goto enable_msi;1678 }1679 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;1680 1681 IWL_DEBUG_INFO(trans,1682 "MSI-X enabled. %d interrupt vectors were allocated\n",1683 num_irqs);1684 1685 /*1686 * In case the OS provides fewer interrupts than requested, different1687 * causes will share the same interrupt vector as follows:1688 * One interrupt less: non rx causes shared with FBQ.1689 * Two interrupts less: non rx causes shared with FBQ and RSS.1690 * More than two interrupts: we will use fewer RSS queues.1691 */1692 if (num_irqs <= max_irqs - 2) {1693 trans_pcie->trans->num_rx_queues = num_irqs + 1;1694 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |1695 IWL_SHARED_IRQ_FIRST_RSS;1696 } else if (num_irqs == max_irqs - 1) {1697 trans_pcie->trans->num_rx_queues = num_irqs;1698 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;1699 } else {1700 trans_pcie->trans->num_rx_queues = num_irqs - 1;1701 }1702 1703 IWL_DEBUG_INFO(trans,1704 "MSI-X enabled with rx queues %d, vec mask 0x%x\n",1705 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);1706 1707 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);1708 1709 trans_pcie->alloc_vecs = num_irqs;1710 trans_pcie->msix_enabled = true;1711 return;1712 1713enable_msi:1714 ret = pci_enable_msi(pdev);1715 if (ret) {1716 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);1717 /* enable rfkill interrupt: hw bug w/a */1718 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);1719 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {1720 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;1721 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);1722 }1723 }1724}1725 1726static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)1727{1728#if defined(CONFIG_SMP)1729 int iter_rx_q, i, ret, cpu, offset;1730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1731 1732 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;1733 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;1734 offset = 1 + i;1735 for (; i < iter_rx_q ; i++) {1736 /*1737 * Get the cpu prior to the place to search1738 * (i.e. return will be > i - 1).1739 */1740 cpu = cpumask_next(i - offset, cpu_online_mask);1741 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);1742 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,1743 &trans_pcie->affinity_mask[i]);1744 if (ret)1745 IWL_ERR(trans_pcie->trans,1746 "Failed to set affinity mask for IRQ %d\n",1747 trans_pcie->msix_entries[i].vector);1748 }1749#endif1750}1751 1752static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,1753 struct iwl_trans_pcie *trans_pcie)1754{1755 int i;1756 1757 for (i = 0; i < trans_pcie->alloc_vecs; i++) {1758 int ret;1759 struct msix_entry *msix_entry;1760 const char *qname = queue_name(&pdev->dev, trans_pcie, i);1761 1762 if (!qname)1763 return -ENOMEM;1764 1765 msix_entry = &trans_pcie->msix_entries[i];1766 ret = devm_request_threaded_irq(&pdev->dev,1767 msix_entry->vector,1768 iwl_pcie_msix_isr,1769 (i == trans_pcie->def_irq) ?1770 iwl_pcie_irq_msix_handler :1771 iwl_pcie_irq_rx_msix_handler,1772 IRQF_SHARED,1773 qname,1774 msix_entry);1775 if (ret) {1776 IWL_ERR(trans_pcie->trans,1777 "Error allocating IRQ %d\n", i);1778 1779 return ret;1780 }1781 }1782 iwl_pcie_irq_set_affinity(trans_pcie->trans);1783 1784 return 0;1785}1786 1787static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)1788{1789 u32 hpm, wprot;1790 1791 switch (trans->trans_cfg->device_family) {1792 case IWL_DEVICE_FAMILY_9000:1793 wprot = PREG_PRPH_WPROT_9000;1794 break;1795 case IWL_DEVICE_FAMILY_22000:1796 wprot = PREG_PRPH_WPROT_22000;1797 break;1798 default:1799 return 0;1800 }1801 1802 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);1803 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {1804 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);1805 1806 if (wprot_val & PREG_WFPM_ACCESS) {1807 IWL_ERR(trans,1808 "Error, can not clear persistence bit\n");1809 return -EPERM;1810 }1811 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,1812 hpm & ~PERSISTENCE_BIT);1813 }1814 1815 return 0;1816}1817 1818static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)1819{1820 int ret;1821 1822 ret = iwl_finish_nic_init(trans);1823 if (ret < 0)1824 return ret;1825 1826 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,1827 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);1828 udelay(20);1829 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,1830 HPM_HIPM_GEN_CFG_CR_PG_EN |1831 HPM_HIPM_GEN_CFG_CR_SLP_EN);1832 udelay(20);1833 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,1834 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);1835 1836 return iwl_trans_pcie_sw_reset(trans, true);1837}1838 1839static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)1840{1841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1842 int err;1843 1844 lockdep_assert_held(&trans_pcie->mutex);1845 1846 err = iwl_pcie_prepare_card_hw(trans);1847 if (err) {1848 IWL_ERR(trans, "Error while preparing HW: %d\n", err);1849 return err;1850 }1851 1852 err = iwl_trans_pcie_clear_persistence_bit(trans);1853 if (err)1854 return err;1855 1856 err = iwl_trans_pcie_sw_reset(trans, true);1857 if (err)1858 return err;1859 1860 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&1861 trans->trans_cfg->integrated) {1862 err = iwl_pcie_gen2_force_power_gating(trans);1863 if (err)1864 return err;1865 }1866 1867 err = iwl_pcie_apm_init(trans);1868 if (err)1869 return err;1870 1871 iwl_pcie_init_msix(trans_pcie);1872 1873 /* From now on, the op_mode will be kept updated about RF kill state */1874 iwl_enable_rfkill_int(trans);1875 1876 trans_pcie->opmode_down = false;1877 1878 /* Set is_down to false here so that...*/1879 trans_pcie->is_down = false;1880 1881 /* ...rfkill can call stop_device and set it false if needed */1882 iwl_pcie_check_hw_rf_kill(trans);1883 1884 return 0;1885}1886 1887int iwl_trans_pcie_start_hw(struct iwl_trans *trans)1888{1889 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1890 int ret;1891 1892 mutex_lock(&trans_pcie->mutex);1893 ret = _iwl_trans_pcie_start_hw(trans);1894 mutex_unlock(&trans_pcie->mutex);1895 1896 return ret;1897}1898 1899void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)1900{1901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1902 1903 mutex_lock(&trans_pcie->mutex);1904 1905 /* disable interrupts - don't enable HW RF kill interrupt */1906 iwl_disable_interrupts(trans);1907 1908 iwl_pcie_apm_stop(trans, true);1909 1910 iwl_disable_interrupts(trans);1911 1912 iwl_pcie_disable_ict(trans);1913 1914 mutex_unlock(&trans_pcie->mutex);1915 1916 iwl_pcie_synchronize_irqs(trans);1917}1918 1919void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)1920{1921 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);1922}1923 1924void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)1925{1926 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);1927}1928 1929u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)1930{1931 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);1932}1933 1934static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)1935{1936 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)1937 return 0x00FFFFFF;1938 else1939 return 0x000FFFFF;1940}1941 1942u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)1943{1944 u32 mask = iwl_trans_pcie_prph_msk(trans);1945 1946 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,1947 ((reg & mask) | (3 << 24)));1948 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);1949}1950 1951void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val)1952{1953 u32 mask = iwl_trans_pcie_prph_msk(trans);1954 1955 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,1956 ((addr & mask) | (3 << 24)));1957 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);1958}1959 1960void iwl_trans_pcie_configure(struct iwl_trans *trans,1961 const struct iwl_trans_config *trans_cfg)1962{1963 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);1964 1965 /* free all first - we might be reconfigured for a different size */1966 iwl_pcie_free_rbs_pool(trans);1967 1968 trans_pcie->txqs.cmd.q_id = trans_cfg->cmd_queue;1969 trans_pcie->txqs.cmd.fifo = trans_cfg->cmd_fifo;1970 trans_pcie->txqs.page_offs = trans_cfg->cb_data_offs;1971 trans_pcie->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);1972 trans_pcie->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver;1973 1974 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))1975 trans_pcie->n_no_reclaim_cmds = 0;1976 else1977 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;1978 if (trans_pcie->n_no_reclaim_cmds)1979 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,1980 trans_pcie->n_no_reclaim_cmds * sizeof(u8));1981 1982 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;1983 trans_pcie->rx_page_order =1984 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);1985 trans_pcie->rx_buf_bytes =1986 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);1987 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);1988 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)1989 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);1990 1991 trans_pcie->txqs.bc_table_dword = trans_cfg->bc_table_dword;1992 trans_pcie->scd_set_active = trans_cfg->scd_set_active;1993 1994 trans->command_groups = trans_cfg->command_groups;1995 trans->command_groups_size = trans_cfg->command_groups_size;1996 1997 1998 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;1999}2000 2001void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,2002 struct device *dev)2003{2004 u8 i;2005 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;2006 2007 /* free DRAM payloads */2008 for (i = 0; i < dram_regions->n_regions; i++) {2009 dma_free_coherent(dev, dram_regions->drams[i].size,2010 dram_regions->drams[i].block,2011 dram_regions->drams[i].physical);2012 }2013 dram_regions->n_regions = 0;2014 2015 /* free DRAM addresses array */2016 if (desc_dram->block) {2017 dma_free_coherent(dev, desc_dram->size,2018 desc_dram->block,2019 desc_dram->physical);2020 }2021 memset(desc_dram, 0, sizeof(*desc_dram));2022}2023 2024static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans)2025{2026 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd);2027}2028 2029static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans)2030{2031 struct iwl_cmd_header_wide bad_cmd = {2032 .cmd = INVALID_WR_PTR_CMD,2033 .group_id = DEBUG_GROUP,2034 .sequence = cpu_to_le16(0xffff),2035 .length = cpu_to_le16(0),2036 .version = 0,2037 };2038 int ret;2039 2040 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd,2041 sizeof(bad_cmd));2042 if (ret)2043 return ret;2044 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd));2045 return 0;2046}2047 2048void iwl_trans_pcie_free(struct iwl_trans *trans)2049{2050 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2051 int i;2052 2053 iwl_pcie_synchronize_irqs(trans);2054 2055 if (trans->trans_cfg->gen2)2056 iwl_txq_gen2_tx_free(trans);2057 else2058 iwl_pcie_tx_free(trans);2059 iwl_pcie_rx_free(trans);2060 2061 if (trans_pcie->rba.alloc_wq) {2062 destroy_workqueue(trans_pcie->rba.alloc_wq);2063 trans_pcie->rba.alloc_wq = NULL;2064 }2065 2066 if (trans_pcie->msix_enabled) {2067 for (i = 0; i < trans_pcie->alloc_vecs; i++) {2068 irq_set_affinity_hint(2069 trans_pcie->msix_entries[i].vector,2070 NULL);2071 }2072 2073 trans_pcie->msix_enabled = false;2074 } else {2075 iwl_pcie_free_ict(trans);2076 }2077 2078 free_netdev(trans_pcie->napi_dev);2079 2080 iwl_pcie_free_invalid_tx_cmd(trans);2081 2082 iwl_pcie_free_fw_monitor(trans);2083 2084 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data,2085 trans->dev);2086 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data,2087 trans->dev);2088 2089 mutex_destroy(&trans_pcie->mutex);2090 2091 if (trans_pcie->txqs.tso_hdr_page) {2092 for_each_possible_cpu(i) {2093 struct iwl_tso_hdr_page *p =2094 per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i);2095 2096 if (p && p->page)2097 __free_page(p->page);2098 }2099 2100 free_percpu(trans_pcie->txqs.tso_hdr_page);2101 }2102 2103 iwl_trans_free(trans);2104}2105 2106struct iwl_trans_pcie_removal {2107 struct pci_dev *pdev;2108 struct work_struct work;2109 bool rescan;2110};2111 2112static void iwl_trans_pcie_removal_wk(struct work_struct *wk)2113{2114 struct iwl_trans_pcie_removal *removal =2115 container_of(wk, struct iwl_trans_pcie_removal, work);2116 struct pci_dev *pdev = removal->pdev;2117 static char *prop[] = {"EVENT=INACCESSIBLE", NULL};2118 struct pci_bus *bus;2119 2120 pci_lock_rescan_remove();2121 2122 bus = pdev->bus;2123 /* in this case, something else already removed the device */2124 if (!bus)2125 goto out;2126 2127 dev_err(&pdev->dev, "Device gone - attempting removal\n");2128 2129 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);2130 2131 pci_stop_and_remove_bus_device(pdev);2132 pci_dev_put(pdev);2133 2134 if (removal->rescan) {2135 if (bus->parent)2136 bus = bus->parent;2137 pci_rescan_bus(bus);2138 }2139 2140out:2141 pci_unlock_rescan_remove();2142 2143 kfree(removal);2144 module_put(THIS_MODULE);2145}2146 2147void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan)2148{2149 struct iwl_trans_pcie_removal *removal;2150 2151 if (test_bit(STATUS_TRANS_DEAD, &trans->status))2152 return;2153 2154 IWL_ERR(trans, "Device gone - scheduling removal!\n");2155 iwl_pcie_dump_csr(trans);2156 2157 /*2158 * get a module reference to avoid doing this2159 * while unloading anyway and to avoid2160 * scheduling a work with code that's being2161 * removed.2162 */2163 if (!try_module_get(THIS_MODULE)) {2164 IWL_ERR(trans,2165 "Module is being unloaded - abort\n");2166 return;2167 }2168 2169 removal = kzalloc(sizeof(*removal), GFP_ATOMIC);2170 if (!removal) {2171 module_put(THIS_MODULE);2172 return;2173 }2174 /*2175 * we don't need to clear this flag, because2176 * the trans will be freed and reallocated.2177 */2178 set_bit(STATUS_TRANS_DEAD, &trans->status);2179 2180 removal->pdev = to_pci_dev(trans->dev);2181 removal->rescan = rescan;2182 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);2183 pci_dev_get(removal->pdev);2184 schedule_work(&removal->work);2185}2186EXPORT_SYMBOL(iwl_trans_pcie_remove);2187 2188/*2189 * This version doesn't disable BHs but rather assumes they're2190 * already disabled.2191 */2192bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)2193{2194 int ret;2195 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2196 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;2197 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |2198 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;2199 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;2200 2201 if (test_bit(STATUS_TRANS_DEAD, &trans->status))2202 return false;2203 2204 spin_lock(&trans_pcie->reg_lock);2205 2206 if (trans_pcie->cmd_hold_nic_awake)2207 goto out;2208 2209 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {2210 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;2211 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;2212 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;2213 }2214 2215 /* this bit wakes up the NIC */2216 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);2217 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)2218 udelay(2);2219 2220 /*2221 * These bits say the device is running, and should keep running for2222 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),2223 * but they do not indicate that embedded SRAM is restored yet;2224 * HW with volatile SRAM must save/restore contents to/from2225 * host DRAM when sleeping/waking for power-saving.2226 * Each direction takes approximately 1/4 millisecond; with this2227 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a2228 * series of register accesses are expected (e.g. reading Event Log),2229 * to keep device from sleeping.2230 *2231 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that2232 * SRAM is okay/restored. We don't check that here because this call2233 * is just for hardware register access; but GP1 MAC_SLEEP2234 * check is a good idea before accessing the SRAM of HW with2235 * volatile SRAM (e.g. reading Event Log).2236 *2237 * 5000 series and later (including 1000 series) have non-volatile SRAM,2238 * and do not save/restore SRAM when power cycling.2239 */2240 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);2241 if (unlikely(ret < 0)) {2242 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);2243 2244 WARN_ONCE(1,2245 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",2246 cntrl);2247 2248 iwl_trans_pcie_dump_regs(trans);2249 2250 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U)2251 iwl_trans_pcie_remove(trans, false);2252 else2253 iwl_write32(trans, CSR_RESET,2254 CSR_RESET_REG_FLAG_FORCE_NMI);2255 2256 spin_unlock(&trans_pcie->reg_lock);2257 return false;2258 }2259 2260out:2261 /*2262 * Fool sparse by faking we release the lock - sparse will2263 * track nic_access anyway.2264 */2265 __release(&trans_pcie->reg_lock);2266 return true;2267}2268 2269bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)2270{2271 bool ret;2272 2273 local_bh_disable();2274 ret = __iwl_trans_pcie_grab_nic_access(trans);2275 if (ret) {2276 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */2277 return ret;2278 }2279 local_bh_enable();2280 return false;2281}2282 2283void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)2284{2285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2286 2287 lockdep_assert_held(&trans_pcie->reg_lock);2288 2289 /*2290 * Fool sparse by faking we acquiring the lock - sparse will2291 * track nic_access anyway.2292 */2293 __acquire(&trans_pcie->reg_lock);2294 2295 if (trans_pcie->cmd_hold_nic_awake)2296 goto out;2297 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)2298 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,2299 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);2300 else2301 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,2302 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);2303 /*2304 * Above we read the CSR_GP_CNTRL register, which will flush2305 * any previous writes, but we need the write that clears the2306 * MAC_ACCESS_REQ bit to be performed before any other writes2307 * scheduled on different CPUs (after we drop reg_lock).2308 */2309out:2310 spin_unlock_bh(&trans_pcie->reg_lock);2311}2312 2313int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,2314 void *buf, int dwords)2315{2316#define IWL_MAX_HW_ERRS 52317 unsigned int num_consec_hw_errors = 0;2318 int offs = 0;2319 u32 *vals = buf;2320 2321 while (offs < dwords) {2322 /* limit the time we spin here under lock to 1/2s */2323 unsigned long end = jiffies + HZ / 2;2324 bool resched = false;2325 2326 if (iwl_trans_grab_nic_access(trans)) {2327 iwl_write32(trans, HBUS_TARG_MEM_RADDR,2328 addr + 4 * offs);2329 2330 while (offs < dwords) {2331 vals[offs] = iwl_read32(trans,2332 HBUS_TARG_MEM_RDAT);2333 2334 if (iwl_trans_is_hw_error_value(vals[offs]))2335 num_consec_hw_errors++;2336 else2337 num_consec_hw_errors = 0;2338 2339 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) {2340 iwl_trans_release_nic_access(trans);2341 return -EIO;2342 }2343 2344 offs++;2345 2346 if (time_after(jiffies, end)) {2347 resched = true;2348 break;2349 }2350 }2351 iwl_trans_release_nic_access(trans);2352 2353 if (resched)2354 cond_resched();2355 } else {2356 return -EBUSY;2357 }2358 }2359 2360 return 0;2361}2362 2363int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,2364 const void *buf, int dwords)2365{2366 int offs, ret = 0;2367 const u32 *vals = buf;2368 2369 if (iwl_trans_grab_nic_access(trans)) {2370 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);2371 for (offs = 0; offs < dwords; offs++)2372 iwl_write32(trans, HBUS_TARG_MEM_WDAT,2373 vals ? vals[offs] : 0);2374 iwl_trans_release_nic_access(trans);2375 } else {2376 ret = -EBUSY;2377 }2378 return ret;2379}2380 2381int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,2382 u32 *val)2383{2384 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,2385 ofs, val);2386}2387 2388#define IWL_FLUSH_WAIT_MS 20002389 2390int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,2391 struct iwl_trans_rxq_dma_data *data)2392{2393 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2394 2395 if (queue >= trans->num_rx_queues || !trans_pcie->rxq)2396 return -EINVAL;2397 2398 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;2399 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;2400 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;2401 data->fr_bd_wid = 0;2402 2403 return 0;2404}2405 2406int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)2407{2408 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2409 struct iwl_txq *txq;2410 unsigned long now = jiffies;2411 bool overflow_tx;2412 u8 wr_ptr;2413 2414 /* Make sure the NIC is still alive in the bus */2415 if (test_bit(STATUS_TRANS_DEAD, &trans->status))2416 return -ENODEV;2417 2418 if (!test_bit(txq_idx, trans_pcie->txqs.queue_used))2419 return -EINVAL;2420 2421 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);2422 txq = trans_pcie->txqs.txq[txq_idx];2423 2424 spin_lock_bh(&txq->lock);2425 overflow_tx = txq->overflow_tx ||2426 !skb_queue_empty(&txq->overflow_q);2427 spin_unlock_bh(&txq->lock);2428 2429 wr_ptr = READ_ONCE(txq->write_ptr);2430 2431 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||2432 overflow_tx) &&2433 !time_after(jiffies,2434 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {2435 u8 write_ptr = READ_ONCE(txq->write_ptr);2436 2437 /*2438 * If write pointer moved during the wait, warn only2439 * if the TX came from op mode. In case TX came from2440 * trans layer (overflow TX) don't warn.2441 */2442 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,2443 "WR pointer moved while flushing %d -> %d\n",2444 wr_ptr, write_ptr))2445 return -ETIMEDOUT;2446 wr_ptr = write_ptr;2447 2448 usleep_range(1000, 2000);2449 2450 spin_lock_bh(&txq->lock);2451 overflow_tx = txq->overflow_tx ||2452 !skb_queue_empty(&txq->overflow_q);2453 spin_unlock_bh(&txq->lock);2454 }2455 2456 if (txq->read_ptr != txq->write_ptr) {2457 IWL_ERR(trans,2458 "fail to flush all tx fifo queues Q %d\n", txq_idx);2459 iwl_txq_log_scd_error(trans, txq);2460 return -ETIMEDOUT;2461 }2462 2463 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);2464 2465 return 0;2466}2467 2468int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)2469{2470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2471 int cnt;2472 int ret = 0;2473 2474 /* waiting for all the tx frames complete might take a while */2475 for (cnt = 0;2476 cnt < trans->trans_cfg->base_params->num_of_queues;2477 cnt++) {2478 2479 if (cnt == trans_pcie->txqs.cmd.q_id)2480 continue;2481 if (!test_bit(cnt, trans_pcie->txqs.queue_used))2482 continue;2483 if (!(BIT(cnt) & txq_bm))2484 continue;2485 2486 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);2487 if (ret)2488 break;2489 }2490 2491 return ret;2492}2493 2494void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,2495 u32 mask, u32 value)2496{2497 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2498 2499 spin_lock_bh(&trans_pcie->reg_lock);2500 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);2501 spin_unlock_bh(&trans_pcie->reg_lock);2502}2503 2504static const char *get_csr_string(int cmd)2505{2506#define IWL_CMD(x) case x: return #x2507 switch (cmd) {2508 IWL_CMD(CSR_HW_IF_CONFIG_REG);2509 IWL_CMD(CSR_INT_COALESCING);2510 IWL_CMD(CSR_INT);2511 IWL_CMD(CSR_INT_MASK);2512 IWL_CMD(CSR_FH_INT_STATUS);2513 IWL_CMD(CSR_GPIO_IN);2514 IWL_CMD(CSR_RESET);2515 IWL_CMD(CSR_GP_CNTRL);2516 IWL_CMD(CSR_HW_REV);2517 IWL_CMD(CSR_EEPROM_REG);2518 IWL_CMD(CSR_EEPROM_GP);2519 IWL_CMD(CSR_OTP_GP_REG);2520 IWL_CMD(CSR_GIO_REG);2521 IWL_CMD(CSR_GP_UCODE_REG);2522 IWL_CMD(CSR_GP_DRIVER_REG);2523 IWL_CMD(CSR_UCODE_DRV_GP1);2524 IWL_CMD(CSR_UCODE_DRV_GP2);2525 IWL_CMD(CSR_LED_REG);2526 IWL_CMD(CSR_DRAM_INT_TBL_REG);2527 IWL_CMD(CSR_GIO_CHICKEN_BITS);2528 IWL_CMD(CSR_ANA_PLL_CFG);2529 IWL_CMD(CSR_HW_REV_WA_REG);2530 IWL_CMD(CSR_MONITOR_STATUS_REG);2531 IWL_CMD(CSR_DBG_HPET_MEM_REG);2532 default:2533 return "UNKNOWN";2534 }2535#undef IWL_CMD2536}2537 2538void iwl_pcie_dump_csr(struct iwl_trans *trans)2539{2540 int i;2541 static const u32 csr_tbl[] = {2542 CSR_HW_IF_CONFIG_REG,2543 CSR_INT_COALESCING,2544 CSR_INT,2545 CSR_INT_MASK,2546 CSR_FH_INT_STATUS,2547 CSR_GPIO_IN,2548 CSR_RESET,2549 CSR_GP_CNTRL,2550 CSR_HW_REV,2551 CSR_EEPROM_REG,2552 CSR_EEPROM_GP,2553 CSR_OTP_GP_REG,2554 CSR_GIO_REG,2555 CSR_GP_UCODE_REG,2556 CSR_GP_DRIVER_REG,2557 CSR_UCODE_DRV_GP1,2558 CSR_UCODE_DRV_GP2,2559 CSR_LED_REG,2560 CSR_DRAM_INT_TBL_REG,2561 CSR_GIO_CHICKEN_BITS,2562 CSR_ANA_PLL_CFG,2563 CSR_MONITOR_STATUS_REG,2564 CSR_HW_REV_WA_REG,2565 CSR_DBG_HPET_MEM_REG2566 };2567 IWL_ERR(trans, "CSR values:\n");2568 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "2569 "CSR_INT_PERIODIC_REG)\n");2570 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {2571 IWL_ERR(trans, " %25s: 0X%08x\n",2572 get_csr_string(csr_tbl[i]),2573 iwl_read32(trans, csr_tbl[i]));2574 }2575}2576 2577#ifdef CONFIG_IWLWIFI_DEBUGFS2578/* create and remove of files */2579#define DEBUGFS_ADD_FILE(name, parent, mode) do { \2580 debugfs_create_file(#name, mode, parent, trans, \2581 &iwl_dbgfs_##name##_ops); \2582} while (0)2583 2584/* file operation */2585#define DEBUGFS_READ_FILE_OPS(name) \2586static const struct file_operations iwl_dbgfs_##name##_ops = { \2587 .read = iwl_dbgfs_##name##_read, \2588 .open = simple_open, \2589 .llseek = generic_file_llseek, \2590};2591 2592#define DEBUGFS_WRITE_FILE_OPS(name) \2593static const struct file_operations iwl_dbgfs_##name##_ops = { \2594 .write = iwl_dbgfs_##name##_write, \2595 .open = simple_open, \2596 .llseek = generic_file_llseek, \2597};2598 2599#define DEBUGFS_READ_WRITE_FILE_OPS(name) \2600static const struct file_operations iwl_dbgfs_##name##_ops = { \2601 .write = iwl_dbgfs_##name##_write, \2602 .read = iwl_dbgfs_##name##_read, \2603 .open = simple_open, \2604 .llseek = generic_file_llseek, \2605};2606 2607struct iwl_dbgfs_tx_queue_priv {2608 struct iwl_trans *trans;2609};2610 2611struct iwl_dbgfs_tx_queue_state {2612 loff_t pos;2613};2614 2615static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)2616{2617 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;2618 struct iwl_dbgfs_tx_queue_state *state;2619 2620 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)2621 return NULL;2622 2623 state = kmalloc(sizeof(*state), GFP_KERNEL);2624 if (!state)2625 return NULL;2626 state->pos = *pos;2627 return state;2628}2629 2630static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,2631 void *v, loff_t *pos)2632{2633 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;2634 struct iwl_dbgfs_tx_queue_state *state = v;2635 2636 *pos = ++state->pos;2637 2638 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)2639 return NULL;2640 2641 return state;2642}2643 2644static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)2645{2646 kfree(v);2647}2648 2649static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)2650{2651 struct iwl_dbgfs_tx_queue_priv *priv = seq->private;2652 struct iwl_dbgfs_tx_queue_state *state = v;2653 struct iwl_trans *trans = priv->trans;2654 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2655 struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos];2656 2657 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",2658 (unsigned int)state->pos,2659 !!test_bit(state->pos, trans_pcie->txqs.queue_used),2660 !!test_bit(state->pos, trans_pcie->txqs.queue_stopped));2661 if (txq)2662 seq_printf(seq,2663 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",2664 txq->read_ptr, txq->write_ptr,2665 txq->need_update, txq->frozen,2666 txq->n_window, txq->ampdu);2667 else2668 seq_puts(seq, "(unallocated)");2669 2670 if (state->pos == trans_pcie->txqs.cmd.q_id)2671 seq_puts(seq, " (HCMD)");2672 seq_puts(seq, "\n");2673 2674 return 0;2675}2676 2677static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {2678 .start = iwl_dbgfs_tx_queue_seq_start,2679 .next = iwl_dbgfs_tx_queue_seq_next,2680 .stop = iwl_dbgfs_tx_queue_seq_stop,2681 .show = iwl_dbgfs_tx_queue_seq_show,2682};2683 2684static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)2685{2686 struct iwl_dbgfs_tx_queue_priv *priv;2687 2688 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,2689 sizeof(*priv));2690 2691 if (!priv)2692 return -ENOMEM;2693 2694 priv->trans = inode->i_private;2695 return 0;2696}2697 2698static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,2699 char __user *user_buf,2700 size_t count, loff_t *ppos)2701{2702 struct iwl_trans *trans = file->private_data;2703 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2704 char *buf;2705 int pos = 0, i, ret;2706 size_t bufsz;2707 2708 bufsz = sizeof(char) * 121 * trans->num_rx_queues;2709 2710 if (!trans_pcie->rxq)2711 return -EAGAIN;2712 2713 buf = kzalloc(bufsz, GFP_KERNEL);2714 if (!buf)2715 return -ENOMEM;2716 2717 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {2718 struct iwl_rxq *rxq = &trans_pcie->rxq[i];2719 2720 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",2721 i);2722 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",2723 rxq->read);2724 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",2725 rxq->write);2726 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",2727 rxq->write_actual);2728 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",2729 rxq->need_update);2730 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",2731 rxq->free_count);2732 if (rxq->rb_stts) {2733 u32 r = iwl_get_closed_rb_stts(trans, rxq);2734 pos += scnprintf(buf + pos, bufsz - pos,2735 "\tclosed_rb_num: %u\n", r);2736 } else {2737 pos += scnprintf(buf + pos, bufsz - pos,2738 "\tclosed_rb_num: Not Allocated\n");2739 }2740 }2741 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);2742 kfree(buf);2743 2744 return ret;2745}2746 2747static ssize_t iwl_dbgfs_interrupt_read(struct file *file,2748 char __user *user_buf,2749 size_t count, loff_t *ppos)2750{2751 struct iwl_trans *trans = file->private_data;2752 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2753 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;2754 2755 int pos = 0;2756 char *buf;2757 int bufsz = 24 * 64; /* 24 items * 64 char per item */2758 ssize_t ret;2759 2760 buf = kzalloc(bufsz, GFP_KERNEL);2761 if (!buf)2762 return -ENOMEM;2763 2764 pos += scnprintf(buf + pos, bufsz - pos,2765 "Interrupt Statistics Report:\n");2766 2767 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",2768 isr_stats->hw);2769 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",2770 isr_stats->sw);2771 if (isr_stats->sw || isr_stats->hw) {2772 pos += scnprintf(buf + pos, bufsz - pos,2773 "\tLast Restarting Code: 0x%X\n",2774 isr_stats->err_code);2775 }2776#ifdef CONFIG_IWLWIFI_DEBUG2777 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",2778 isr_stats->sch);2779 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",2780 isr_stats->alive);2781#endif2782 pos += scnprintf(buf + pos, bufsz - pos,2783 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);2784 2785 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",2786 isr_stats->ctkill);2787 2788 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",2789 isr_stats->wakeup);2790 2791 pos += scnprintf(buf + pos, bufsz - pos,2792 "Rx command responses:\t\t %u\n", isr_stats->rx);2793 2794 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",2795 isr_stats->tx);2796 2797 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",2798 isr_stats->unhandled);2799 2800 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);2801 kfree(buf);2802 return ret;2803}2804 2805static ssize_t iwl_dbgfs_interrupt_write(struct file *file,2806 const char __user *user_buf,2807 size_t count, loff_t *ppos)2808{2809 struct iwl_trans *trans = file->private_data;2810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2811 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;2812 u32 reset_flag;2813 int ret;2814 2815 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);2816 if (ret)2817 return ret;2818 if (reset_flag == 0)2819 memset(isr_stats, 0, sizeof(*isr_stats));2820 2821 return count;2822}2823 2824static ssize_t iwl_dbgfs_csr_write(struct file *file,2825 const char __user *user_buf,2826 size_t count, loff_t *ppos)2827{2828 struct iwl_trans *trans = file->private_data;2829 2830 iwl_pcie_dump_csr(trans);2831 2832 return count;2833}2834 2835static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,2836 char __user *user_buf,2837 size_t count, loff_t *ppos)2838{2839 struct iwl_trans *trans = file->private_data;2840 char *buf = NULL;2841 ssize_t ret;2842 2843 ret = iwl_dump_fh(trans, &buf);2844 if (ret < 0)2845 return ret;2846 if (!buf)2847 return -EINVAL;2848 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);2849 kfree(buf);2850 return ret;2851}2852 2853static ssize_t iwl_dbgfs_rfkill_read(struct file *file,2854 char __user *user_buf,2855 size_t count, loff_t *ppos)2856{2857 struct iwl_trans *trans = file->private_data;2858 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2859 char buf[100];2860 int pos;2861 2862 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",2863 trans_pcie->debug_rfkill,2864 !(iwl_read32(trans, CSR_GP_CNTRL) &2865 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));2866 2867 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);2868}2869 2870static ssize_t iwl_dbgfs_rfkill_write(struct file *file,2871 const char __user *user_buf,2872 size_t count, loff_t *ppos)2873{2874 struct iwl_trans *trans = file->private_data;2875 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2876 bool new_value;2877 int ret;2878 2879 ret = kstrtobool_from_user(user_buf, count, &new_value);2880 if (ret)2881 return ret;2882 if (new_value == trans_pcie->debug_rfkill)2883 return count;2884 IWL_WARN(trans, "changing debug rfkill %d->%d\n",2885 trans_pcie->debug_rfkill, new_value);2886 trans_pcie->debug_rfkill = new_value;2887 iwl_pcie_handle_rfkill_irq(trans, false);2888 2889 return count;2890}2891 2892static int iwl_dbgfs_monitor_data_open(struct inode *inode,2893 struct file *file)2894{2895 struct iwl_trans *trans = inode->i_private;2896 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2897 2898 if (!trans->dbg.dest_tlv ||2899 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {2900 IWL_ERR(trans, "Debug destination is not set to DRAM\n");2901 return -ENOENT;2902 }2903 2904 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)2905 return -EBUSY;2906 2907 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;2908 return simple_open(inode, file);2909}2910 2911static int iwl_dbgfs_monitor_data_release(struct inode *inode,2912 struct file *file)2913{2914 struct iwl_trans_pcie *trans_pcie =2915 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);2916 2917 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)2918 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;2919 return 0;2920}2921 2922static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,2923 void *buf, ssize_t *size,2924 ssize_t *bytes_copied)2925{2926 ssize_t buf_size_left = count - *bytes_copied;2927 2928 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));2929 if (*size > buf_size_left)2930 *size = buf_size_left;2931 2932 *size -= copy_to_user(user_buf, buf, *size);2933 *bytes_copied += *size;2934 2935 if (buf_size_left == *size)2936 return true;2937 return false;2938}2939 2940static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,2941 char __user *user_buf,2942 size_t count, loff_t *ppos)2943{2944 struct iwl_trans *trans = file->private_data;2945 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);2946 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;2947 struct cont_rec *data = &trans_pcie->fw_mon_data;2948 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;2949 ssize_t size, bytes_copied = 0;2950 bool b_full;2951 2952 if (trans->dbg.dest_tlv) {2953 write_ptr_addr =2954 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);2955 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);2956 } else {2957 write_ptr_addr = MON_BUFF_WRPTR;2958 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;2959 }2960 2961 if (unlikely(!trans->dbg.rec_on))2962 return 0;2963 2964 mutex_lock(&data->mutex);2965 if (data->state ==2966 IWL_FW_MON_DBGFS_STATE_DISABLED) {2967 mutex_unlock(&data->mutex);2968 return 0;2969 }2970 2971 /* write_ptr position in bytes rather then DW */2972 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);2973 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);2974 2975 if (data->prev_wrap_cnt == wrap_cnt) {2976 size = write_ptr - data->prev_wr_ptr;2977 curr_buf = cpu_addr + data->prev_wr_ptr;2978 b_full = iwl_write_to_user_buf(user_buf, count,2979 curr_buf, &size,2980 &bytes_copied);2981 data->prev_wr_ptr += size;2982 2983 } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&2984 write_ptr < data->prev_wr_ptr) {2985 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;2986 curr_buf = cpu_addr + data->prev_wr_ptr;2987 b_full = iwl_write_to_user_buf(user_buf, count,2988 curr_buf, &size,2989 &bytes_copied);2990 data->prev_wr_ptr += size;2991 2992 if (!b_full) {2993 size = write_ptr;2994 b_full = iwl_write_to_user_buf(user_buf, count,2995 cpu_addr, &size,2996 &bytes_copied);2997 data->prev_wr_ptr = size;2998 data->prev_wrap_cnt++;2999 }3000 } else {3001 if (data->prev_wrap_cnt == wrap_cnt - 1 &&3002 write_ptr > data->prev_wr_ptr)3003 IWL_WARN(trans,3004 "write pointer passed previous write pointer, start copying from the beginning\n");3005 else if (!unlikely(data->prev_wrap_cnt == 0 &&3006 data->prev_wr_ptr == 0))3007 IWL_WARN(trans,3008 "monitor data is out of sync, start copying from the beginning\n");3009 3010 size = write_ptr;3011 b_full = iwl_write_to_user_buf(user_buf, count,3012 cpu_addr, &size,3013 &bytes_copied);3014 data->prev_wr_ptr = size;3015 data->prev_wrap_cnt = wrap_cnt;3016 }3017 3018 mutex_unlock(&data->mutex);3019 3020 return bytes_copied;3021}3022 3023static ssize_t iwl_dbgfs_rf_read(struct file *file,3024 char __user *user_buf,3025 size_t count, loff_t *ppos)3026{3027 struct iwl_trans *trans = file->private_data;3028 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3029 3030 if (!trans_pcie->rf_name[0])3031 return -ENODEV;3032 3033 return simple_read_from_buffer(user_buf, count, ppos,3034 trans_pcie->rf_name,3035 strlen(trans_pcie->rf_name));3036}3037 3038DEBUGFS_READ_WRITE_FILE_OPS(interrupt);3039DEBUGFS_READ_FILE_OPS(fh_reg);3040DEBUGFS_READ_FILE_OPS(rx_queue);3041DEBUGFS_WRITE_FILE_OPS(csr);3042DEBUGFS_READ_WRITE_FILE_OPS(rfkill);3043DEBUGFS_READ_FILE_OPS(rf);3044 3045static const struct file_operations iwl_dbgfs_tx_queue_ops = {3046 .owner = THIS_MODULE,3047 .open = iwl_dbgfs_tx_queue_open,3048 .read = seq_read,3049 .llseek = seq_lseek,3050 .release = seq_release_private,3051};3052 3053static const struct file_operations iwl_dbgfs_monitor_data_ops = {3054 .read = iwl_dbgfs_monitor_data_read,3055 .open = iwl_dbgfs_monitor_data_open,3056 .release = iwl_dbgfs_monitor_data_release,3057};3058 3059/* Create the debugfs files and directories */3060void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)3061{3062 struct dentry *dir = trans->dbgfs_dir;3063 3064 DEBUGFS_ADD_FILE(rx_queue, dir, 0400);3065 DEBUGFS_ADD_FILE(tx_queue, dir, 0400);3066 DEBUGFS_ADD_FILE(interrupt, dir, 0600);3067 DEBUGFS_ADD_FILE(csr, dir, 0200);3068 DEBUGFS_ADD_FILE(fh_reg, dir, 0400);3069 DEBUGFS_ADD_FILE(rfkill, dir, 0600);3070 DEBUGFS_ADD_FILE(monitor_data, dir, 0400);3071 DEBUGFS_ADD_FILE(rf, dir, 0400);3072}3073 3074void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)3075{3076 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3077 struct cont_rec *data = &trans_pcie->fw_mon_data;3078 3079 mutex_lock(&data->mutex);3080 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;3081 mutex_unlock(&data->mutex);3082}3083#endif /*CONFIG_IWLWIFI_DEBUGFS */3084 3085static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)3086{3087 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3088 u32 cmdlen = 0;3089 int i;3090 3091 for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++)3092 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);3093 3094 return cmdlen;3095}3096 3097static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,3098 struct iwl_fw_error_dump_data **data,3099 int allocated_rb_nums)3100{3101 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3102 int max_len = trans_pcie->rx_buf_bytes;3103 /* Dump RBs is supported only for pre-9000 devices (1 queue) */3104 struct iwl_rxq *rxq = &trans_pcie->rxq[0];3105 u32 i, r, j, rb_len = 0;3106 3107 spin_lock_bh(&rxq->lock);3108 3109 r = iwl_get_closed_rb_stts(trans, rxq);3110 3111 for (i = rxq->read, j = 0;3112 i != r && j < allocated_rb_nums;3113 i = (i + 1) & RX_QUEUE_MASK, j++) {3114 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];3115 struct iwl_fw_error_dump_rb *rb;3116 3117 dma_sync_single_for_cpu(trans->dev, rxb->page_dma,3118 max_len, DMA_FROM_DEVICE);3119 3120 rb_len += sizeof(**data) + sizeof(*rb) + max_len;3121 3122 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);3123 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);3124 rb = (void *)(*data)->data;3125 rb->index = cpu_to_le32(i);3126 memcpy(rb->data, page_address(rxb->page), max_len);3127 3128 *data = iwl_fw_error_next_data(*data);3129 }3130 3131 spin_unlock_bh(&rxq->lock);3132 3133 return rb_len;3134}3135#define IWL_CSR_TO_DUMP (0x250)3136 3137static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,3138 struct iwl_fw_error_dump_data **data)3139{3140 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;3141 __le32 *val;3142 int i;3143 3144 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);3145 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);3146 val = (void *)(*data)->data;3147 3148 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)3149 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));3150 3151 *data = iwl_fw_error_next_data(*data);3152 3153 return csr_len;3154}3155 3156static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,3157 struct iwl_fw_error_dump_data **data)3158{3159 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;3160 __le32 *val;3161 int i;3162 3163 if (!iwl_trans_grab_nic_access(trans))3164 return 0;3165 3166 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);3167 (*data)->len = cpu_to_le32(fh_regs_len);3168 val = (void *)(*data)->data;3169 3170 if (!trans->trans_cfg->gen2)3171 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;3172 i += sizeof(u32))3173 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));3174 else3175 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);3176 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);3177 i += sizeof(u32))3178 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,3179 i));3180 3181 iwl_trans_release_nic_access(trans);3182 3183 *data = iwl_fw_error_next_data(*data);3184 3185 return sizeof(**data) + fh_regs_len;3186}3187 3188static u323189iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,3190 struct iwl_fw_error_dump_fw_mon *fw_mon_data,3191 u32 monitor_len)3192{3193 u32 buf_size_in_dwords = (monitor_len >> 2);3194 u32 *buffer = (u32 *)fw_mon_data->data;3195 u32 i;3196 3197 if (!iwl_trans_grab_nic_access(trans))3198 return 0;3199 3200 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);3201 for (i = 0; i < buf_size_in_dwords; i++)3202 buffer[i] = iwl_read_umac_prph_no_grab(trans,3203 MON_DMARB_RD_DATA_ADDR);3204 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);3205 3206 iwl_trans_release_nic_access(trans);3207 3208 return monitor_len;3209}3210 3211static void3212iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,3213 struct iwl_fw_error_dump_fw_mon *fw_mon_data)3214{3215 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;3216 3217 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {3218 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;3219 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;3220 write_ptr = DBGC_CUR_DBGBUF_STATUS;3221 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;3222 } else if (trans->dbg.dest_tlv) {3223 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);3224 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);3225 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);3226 } else {3227 base = MON_BUFF_BASE_ADDR;3228 write_ptr = MON_BUFF_WRPTR;3229 wrap_cnt = MON_BUFF_CYCLE_CNT;3230 }3231 3232 write_ptr_val = iwl_read_prph(trans, write_ptr);3233 fw_mon_data->fw_mon_cycle_cnt =3234 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));3235 fw_mon_data->fw_mon_base_ptr =3236 cpu_to_le32(iwl_read_prph(trans, base));3237 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {3238 fw_mon_data->fw_mon_base_high_ptr =3239 cpu_to_le32(iwl_read_prph(trans, base_high));3240 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;3241 /* convert wrtPtr to DWs, to align with all HWs */3242 write_ptr_val >>= 2;3243 }3244 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);3245}3246 3247static u323248iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,3249 struct iwl_fw_error_dump_data **data,3250 u32 monitor_len)3251{3252 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;3253 u32 len = 0;3254 3255 if (trans->dbg.dest_tlv ||3256 (fw_mon->size &&3257 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||3258 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {3259 struct iwl_fw_error_dump_fw_mon *fw_mon_data;3260 3261 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);3262 fw_mon_data = (void *)(*data)->data;3263 3264 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);3265 3266 len += sizeof(**data) + sizeof(*fw_mon_data);3267 if (fw_mon->size) {3268 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);3269 monitor_len = fw_mon->size;3270 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {3271 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);3272 /*3273 * Update pointers to reflect actual values after3274 * shifting3275 */3276 if (trans->dbg.dest_tlv->version) {3277 base = (iwl_read_prph(trans, base) &3278 IWL_LDBG_M2S_BUF_BA_MSK) <<3279 trans->dbg.dest_tlv->base_shift;3280 base *= IWL_M2S_UNIT_SIZE;3281 base += trans->cfg->smem_offset;3282 } else {3283 base = iwl_read_prph(trans, base) <<3284 trans->dbg.dest_tlv->base_shift;3285 }3286 3287 iwl_trans_read_mem(trans, base, fw_mon_data->data,3288 monitor_len / sizeof(u32));3289 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {3290 monitor_len =3291 iwl_trans_pci_dump_marbh_monitor(trans,3292 fw_mon_data,3293 monitor_len);3294 } else {3295 /* Didn't match anything - output no monitor data */3296 monitor_len = 0;3297 }3298 3299 len += monitor_len;3300 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));3301 }3302 3303 return len;3304}3305 3306static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)3307{3308 if (trans->dbg.fw_mon.size) {3309 *len += sizeof(struct iwl_fw_error_dump_data) +3310 sizeof(struct iwl_fw_error_dump_fw_mon) +3311 trans->dbg.fw_mon.size;3312 return trans->dbg.fw_mon.size;3313 } else if (trans->dbg.dest_tlv) {3314 u32 base, end, cfg_reg, monitor_len;3315 3316 if (trans->dbg.dest_tlv->version == 1) {3317 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);3318 cfg_reg = iwl_read_prph(trans, cfg_reg);3319 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<3320 trans->dbg.dest_tlv->base_shift;3321 base *= IWL_M2S_UNIT_SIZE;3322 base += trans->cfg->smem_offset;3323 3324 monitor_len =3325 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>3326 trans->dbg.dest_tlv->end_shift;3327 monitor_len *= IWL_M2S_UNIT_SIZE;3328 } else {3329 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);3330 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);3331 3332 base = iwl_read_prph(trans, base) <<3333 trans->dbg.dest_tlv->base_shift;3334 end = iwl_read_prph(trans, end) <<3335 trans->dbg.dest_tlv->end_shift;3336 3337 /* Make "end" point to the actual end */3338 if (trans->trans_cfg->device_family >=3339 IWL_DEVICE_FAMILY_8000 ||3340 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)3341 end += (1 << trans->dbg.dest_tlv->end_shift);3342 monitor_len = end - base;3343 }3344 *len += sizeof(struct iwl_fw_error_dump_data) +3345 sizeof(struct iwl_fw_error_dump_fw_mon) +3346 monitor_len;3347 return monitor_len;3348 }3349 return 0;3350}3351 3352struct iwl_trans_dump_data *3353iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,3354 const struct iwl_dump_sanitize_ops *sanitize_ops,3355 void *sanitize_ctx)3356{3357 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3358 struct iwl_fw_error_dump_data *data;3359 struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id];3360 struct iwl_fw_error_dump_txcmd *txcmd;3361 struct iwl_trans_dump_data *dump_data;3362 u32 len, num_rbs = 0, monitor_len = 0;3363 int i, ptr;3364 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&3365 !trans->trans_cfg->mq_rx_supported &&3366 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);3367 3368 if (!dump_mask)3369 return NULL;3370 3371 /* transport dump header */3372 len = sizeof(*dump_data);3373 3374 /* host commands */3375 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)3376 len += sizeof(*data) +3377 cmdq->n_window * (sizeof(*txcmd) +3378 TFD_MAX_PAYLOAD_SIZE);3379 3380 /* FW monitor */3381 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))3382 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);3383 3384 /* CSR registers */3385 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))3386 len += sizeof(*data) + IWL_CSR_TO_DUMP;3387 3388 /* FH registers */3389 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {3390 if (trans->trans_cfg->gen2)3391 len += sizeof(*data) +3392 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -3393 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));3394 else3395 len += sizeof(*data) +3396 (FH_MEM_UPPER_BOUND -3397 FH_MEM_LOWER_BOUND);3398 }3399 3400 if (dump_rbs) {3401 /* Dump RBs is supported only for pre-9000 devices (1 queue) */3402 struct iwl_rxq *rxq = &trans_pcie->rxq[0];3403 /* RBs */3404 num_rbs = iwl_get_closed_rb_stts(trans, rxq);3405 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;3406 len += num_rbs * (sizeof(*data) +3407 sizeof(struct iwl_fw_error_dump_rb) +3408 (PAGE_SIZE << trans_pcie->rx_page_order));3409 }3410 3411 /* Paged memory for gen2 HW */3412 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))3413 for (i = 0; i < trans->init_dram.paging_cnt; i++)3414 len += sizeof(*data) +3415 sizeof(struct iwl_fw_error_dump_paging) +3416 trans->init_dram.paging[i].size;3417 3418 dump_data = vzalloc(len);3419 if (!dump_data)3420 return NULL;3421 3422 len = 0;3423 data = (void *)dump_data->data;3424 3425 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {3426 u16 tfd_size = trans_pcie->txqs.tfd.size;3427 3428 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);3429 txcmd = (void *)data->data;3430 spin_lock_bh(&cmdq->lock);3431 ptr = cmdq->write_ptr;3432 for (i = 0; i < cmdq->n_window; i++) {3433 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);3434 u8 tfdidx;3435 u32 caplen, cmdlen;3436 3437 if (trans->trans_cfg->gen2)3438 tfdidx = idx;3439 else3440 tfdidx = ptr;3441 3442 cmdlen = iwl_trans_pcie_get_cmdlen(trans,3443 (u8 *)cmdq->tfds +3444 tfd_size * tfdidx);3445 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);3446 3447 if (cmdlen) {3448 len += sizeof(*txcmd) + caplen;3449 txcmd->cmdlen = cpu_to_le32(cmdlen);3450 txcmd->caplen = cpu_to_le32(caplen);3451 memcpy(txcmd->data, cmdq->entries[idx].cmd,3452 caplen);3453 if (sanitize_ops && sanitize_ops->frob_hcmd)3454 sanitize_ops->frob_hcmd(sanitize_ctx,3455 txcmd->data,3456 caplen);3457 txcmd = (void *)((u8 *)txcmd->data + caplen);3458 }3459 3460 ptr = iwl_txq_dec_wrap(trans, ptr);3461 }3462 spin_unlock_bh(&cmdq->lock);3463 3464 data->len = cpu_to_le32(len);3465 len += sizeof(*data);3466 data = iwl_fw_error_next_data(data);3467 }3468 3469 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))3470 len += iwl_trans_pcie_dump_csr(trans, &data);3471 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))3472 len += iwl_trans_pcie_fh_regs_dump(trans, &data);3473 if (dump_rbs)3474 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);3475 3476 /* Paged memory for gen2 HW */3477 if (trans->trans_cfg->gen2 &&3478 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {3479 for (i = 0; i < trans->init_dram.paging_cnt; i++) {3480 struct iwl_fw_error_dump_paging *paging;3481 u32 page_len = trans->init_dram.paging[i].size;3482 3483 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);3484 data->len = cpu_to_le32(sizeof(*paging) + page_len);3485 paging = (void *)data->data;3486 paging->index = cpu_to_le32(i);3487 memcpy(paging->data,3488 trans->init_dram.paging[i].block, page_len);3489 data = iwl_fw_error_next_data(data);3490 3491 len += sizeof(*data) + sizeof(*paging) + page_len;3492 }3493 }3494 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))3495 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);3496 3497 dump_data->len = len;3498 3499 return dump_data;3500}3501 3502void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)3503{3504 if (enable)3505 iwl_enable_interrupts(trans);3506 else3507 iwl_disable_interrupts(trans);3508}3509 3510void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)3511{3512 u32 inta_addr, sw_err_bit;3513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3514 3515 if (trans_pcie->msix_enabled) {3516 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;3517 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)3518 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;3519 else3520 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;3521 } else {3522 inta_addr = CSR_INT;3523 sw_err_bit = CSR_INT_BIT_SW_ERR;3524 }3525 3526 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);3527}3528 3529struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,3530 const struct pci_device_id *ent,3531 const struct iwl_cfg_trans_params *cfg_trans)3532{3533 struct iwl_trans_pcie *trans_pcie, **priv;3534 struct iwl_trans *trans;3535 int ret, addr_size;3536 void __iomem * const *table;3537 u32 bar0;3538 3539 /* reassign our BAR 0 if invalid due to possible runtime PM races */3540 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0);3541 if (bar0 == PCI_BASE_ADDRESS_MEM_TYPE_64) {3542 ret = pci_assign_resource(pdev, 0);3543 if (ret)3544 return ERR_PTR(ret);3545 }3546 3547 ret = pcim_enable_device(pdev);3548 if (ret)3549 return ERR_PTR(ret);3550 3551 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev,3552 cfg_trans);3553 if (!trans)3554 return ERR_PTR(-ENOMEM);3555 3556 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3557 3558 if (trans->trans_cfg->gen2) {3559 trans_pcie->txqs.tfd.addr_size = 64;3560 trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS;3561 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd);3562 } else {3563 trans_pcie->txqs.tfd.addr_size = 36;3564 trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS;3565 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd);3566 }3567 trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie);3568 3569 /* Set a short watchdog for the command queue */3570 trans_pcie->txqs.cmd.wdg_timeout = IWL_DEF_WD_TIMEOUT;3571 3572 trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);3573 if (!trans_pcie->txqs.tso_hdr_page) {3574 ret = -ENOMEM;3575 goto out_free_trans;3576 }3577 3578 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)3579 trans_pcie->txqs.bc_tbl_size =3580 sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_BZ;3581 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)3582 trans_pcie->txqs.bc_tbl_size =3583 sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_AX210;3584 else3585 trans_pcie->txqs.bc_tbl_size = sizeof(struct iwlagn_scd_bc_tbl);3586 /*3587 * For gen2 devices, we use a single allocation for each byte-count3588 * table, but they're pretty small (1k) so use a DMA pool that we3589 * allocate here.3590 */3591 if (trans->trans_cfg->gen2) {3592 trans_pcie->txqs.bc_pool =3593 dmam_pool_create("iwlwifi:bc", trans->dev,3594 trans_pcie->txqs.bc_tbl_size,3595 256, 0);3596 if (!trans_pcie->txqs.bc_pool) {3597 ret = -ENOMEM;3598 goto out_free_tso;3599 }3600 }3601 3602 /* Some things must not change even if the config does */3603 WARN_ON(trans_pcie->txqs.tfd.addr_size !=3604 (trans->trans_cfg->gen2 ? 64 : 36));3605 3606 /* Initialize NAPI here - it should be before registering to mac802113607 * in the opmode but after the HW struct is allocated.3608 */3609 trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *));3610 if (!trans_pcie->napi_dev) {3611 ret = -ENOMEM;3612 goto out_free_tso;3613 }3614 /* The private struct in netdev is a pointer to struct iwl_trans_pcie */3615 priv = netdev_priv(trans_pcie->napi_dev);3616 *priv = trans_pcie;3617 3618 trans_pcie->trans = trans;3619 trans_pcie->opmode_down = true;3620 spin_lock_init(&trans_pcie->irq_lock);3621 spin_lock_init(&trans_pcie->reg_lock);3622 spin_lock_init(&trans_pcie->alloc_page_lock);3623 mutex_init(&trans_pcie->mutex);3624 init_waitqueue_head(&trans_pcie->ucode_write_waitq);3625 init_waitqueue_head(&trans_pcie->fw_reset_waitq);3626 init_waitqueue_head(&trans_pcie->imr_waitq);3627 3628 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",3629 WQ_HIGHPRI | WQ_UNBOUND, 0);3630 if (!trans_pcie->rba.alloc_wq) {3631 ret = -ENOMEM;3632 goto out_free_ndev;3633 }3634 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);3635 3636 trans_pcie->debug_rfkill = -1;3637 3638 if (!cfg_trans->base_params->pcie_l1_allowed) {3639 /*3640 * W/A - seems to solve weird behavior. We need to remove this3641 * if we don't want to stay in L1 all the time. This wastes a3642 * lot of power.3643 */3644 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |3645 PCIE_LINK_STATE_L1 |3646 PCIE_LINK_STATE_CLKPM);3647 }3648 3649 pci_set_master(pdev);3650 3651 addr_size = trans_pcie->txqs.tfd.addr_size;3652 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));3653 if (ret) {3654 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));3655 /* both attempts failed: */3656 if (ret) {3657 dev_err(&pdev->dev, "No suitable DMA available\n");3658 goto out_no_pci;3659 }3660 }3661 3662 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);3663 if (ret) {3664 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");3665 goto out_no_pci;3666 }3667 3668 table = pcim_iomap_table(pdev);3669 if (!table) {3670 dev_err(&pdev->dev, "pcim_iomap_table failed\n");3671 ret = -ENOMEM;3672 goto out_no_pci;3673 }3674 3675 trans_pcie->hw_base = table[0];3676 if (!trans_pcie->hw_base) {3677 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");3678 ret = -ENODEV;3679 goto out_no_pci;3680 }3681 3682 /* We disable the RETRY_TIMEOUT register (0x41) to keep3683 * PCI Tx retries from interfering with C3 CPU state */3684 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);3685 3686 trans_pcie->pci_dev = pdev;3687 iwl_disable_interrupts(trans);3688 3689 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);3690 if (trans->hw_rev == 0xffffffff) {3691 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");3692 ret = -EIO;3693 goto out_no_pci;3694 }3695 3696 /*3697 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have3698 * changed, and now the revision step also includes bit 0-1 (no more3699 * "dash" value). To keep hw_rev backwards compatible - we'll store it3700 * in the old format.3701 */3702 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)3703 trans->hw_rev_step = trans->hw_rev & 0xF;3704 else3705 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2;3706 3707 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);3708 3709 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);3710 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;3711 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),3712 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);3713 3714 init_waitqueue_head(&trans_pcie->sx_waitq);3715 3716 ret = iwl_pcie_alloc_invalid_tx_cmd(trans);3717 if (ret)3718 goto out_no_pci;3719 3720 if (trans_pcie->msix_enabled) {3721 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);3722 if (ret)3723 goto out_no_pci;3724 } else {3725 ret = iwl_pcie_alloc_ict(trans);3726 if (ret)3727 goto out_no_pci;3728 3729 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,3730 iwl_pcie_isr,3731 iwl_pcie_irq_handler,3732 IRQF_SHARED, DRV_NAME, trans);3733 if (ret) {3734 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);3735 goto out_free_ict;3736 }3737 }3738 3739#ifdef CONFIG_IWLWIFI_DEBUGFS3740 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;3741 mutex_init(&trans_pcie->fw_mon_data.mutex);3742#endif3743 3744 iwl_dbg_tlv_init(trans);3745 3746 return trans;3747 3748out_free_ict:3749 iwl_pcie_free_ict(trans);3750out_no_pci:3751 destroy_workqueue(trans_pcie->rba.alloc_wq);3752out_free_ndev:3753 free_netdev(trans_pcie->napi_dev);3754out_free_tso:3755 free_percpu(trans_pcie->txqs.tso_hdr_page);3756out_free_trans:3757 iwl_trans_free(trans);3758 return ERR_PTR(ret);3759}3760 3761void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,3762 u32 dst_addr, u64 src_addr, u32 byte_cnt)3763{3764 iwl_write_prph(trans, IMR_UREG_CHICK,3765 iwl_read_prph(trans, IMR_UREG_CHICK) |3766 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);3767 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);3768 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,3769 (u32)(src_addr & 0xFFFFFFFF));3770 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,3771 iwl_get_dma_hi_addr(src_addr));3772 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);3773 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,3774 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |3775 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |3776 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);3777}3778 3779int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,3780 u32 dst_addr, u64 src_addr, u32 byte_cnt)3781{3782 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);3783 int ret = -1;3784 3785 trans_pcie->imr_status = IMR_D2S_REQUESTED;3786 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt);3787 ret = wait_event_timeout(trans_pcie->imr_waitq,3788 trans_pcie->imr_status !=3789 IMR_D2S_REQUESTED, 5 * HZ);3790 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) {3791 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n");3792 iwl_trans_pcie_dump_regs(trans);3793 return -ETIMEDOUT;3794 }3795 trans_pcie->imr_status = IMR_D2S_IDLE;3796 return 0;3797}3798