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1/* SPDX-License-Identifier: ISC */2/*3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>4 */5 6#ifndef __MT76_H7#define __MT76_H8 9#include <linux/kernel.h>10#include <linux/io.h>11#include <linux/spinlock.h>12#include <linux/skbuff.h>13#include <linux/leds.h>14#include <linux/usb.h>15#include <linux/average.h>16#include <linux/soc/mediatek/mtk_wed.h>17#include <net/mac80211.h>18#include <net/page_pool/helpers.h>19#include "util.h"20#include "testmode.h"21 22#define MT_MCU_RING_SIZE 3223#define MT_RX_BUF_SIZE 204824#define MT_SKB_HEAD_LEN 25625 26#define MT_MAX_NON_AQL_PKT 1627#define MT_TXQ_FREE_THR 3228 29#define MT76_TOKEN_FREE_THR 6430 31#define MT_QFLAG_WED_RING GENMASK(1, 0)32#define MT_QFLAG_WED_TYPE GENMASK(4, 2)33#define MT_QFLAG_WED BIT(5)34#define MT_QFLAG_WED_RRO BIT(6)35#define MT_QFLAG_WED_RRO_EN BIT(7)36 37#define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \38 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \39 FIELD_PREP(MT_QFLAG_WED_RING, _n))40#define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n))41 42#define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)43#define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)44#define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)45#define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n)46#define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n)47#define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0)48 49struct mt76_dev;50struct mt76_phy;51struct mt76_wcid;52struct mt76s_intr;53 54struct mt76_reg_pair {55 u32 reg;56 u32 value;57};58 59enum mt76_bus_type {60 MT76_BUS_MMIO,61 MT76_BUS_USB,62 MT76_BUS_SDIO,63};64 65enum mt76_wed_type {66 MT76_WED_Q_TX,67 MT76_WED_Q_TXFREE,68 MT76_WED_Q_RX,69 MT76_WED_RRO_Q_DATA,70 MT76_WED_RRO_Q_MSDU_PG,71 MT76_WED_RRO_Q_IND,72};73 74struct mt76_bus_ops {75 u32 (*rr)(struct mt76_dev *dev, u32 offset);76 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);77 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);78 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,79 int len);80 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,81 int len);82 int (*wr_rp)(struct mt76_dev *dev, u32 base,83 const struct mt76_reg_pair *rp, int len);84 int (*rd_rp)(struct mt76_dev *dev, u32 base,85 struct mt76_reg_pair *rp, int len);86 enum mt76_bus_type type;87};88 89#define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)90#define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)91#define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)92 93enum mt76_txq_id {94 MT_TXQ_VO = IEEE80211_AC_VO,95 MT_TXQ_VI = IEEE80211_AC_VI,96 MT_TXQ_BE = IEEE80211_AC_BE,97 MT_TXQ_BK = IEEE80211_AC_BK,98 MT_TXQ_PSD,99 MT_TXQ_BEACON,100 MT_TXQ_CAB,101 __MT_TXQ_MAX102};103 104enum mt76_mcuq_id {105 MT_MCUQ_WM,106 MT_MCUQ_WA,107 MT_MCUQ_FWDL,108 __MT_MCUQ_MAX109};110 111enum mt76_rxq_id {112 MT_RXQ_MAIN,113 MT_RXQ_MCU,114 MT_RXQ_MCU_WA,115 MT_RXQ_BAND1,116 MT_RXQ_BAND1_WA,117 MT_RXQ_MAIN_WA,118 MT_RXQ_BAND2,119 MT_RXQ_BAND2_WA,120 MT_RXQ_RRO_BAND0,121 MT_RXQ_RRO_BAND1,122 MT_RXQ_RRO_BAND2,123 MT_RXQ_MSDU_PAGE_BAND0,124 MT_RXQ_MSDU_PAGE_BAND1,125 MT_RXQ_MSDU_PAGE_BAND2,126 MT_RXQ_TXFREE_BAND0,127 MT_RXQ_TXFREE_BAND1,128 MT_RXQ_TXFREE_BAND2,129 MT_RXQ_RRO_IND,130 __MT_RXQ_MAX131};132 133enum mt76_band_id {134 MT_BAND0,135 MT_BAND1,136 MT_BAND2,137 __MT_MAX_BAND138};139 140enum mt76_cipher_type {141 MT_CIPHER_NONE,142 MT_CIPHER_WEP40,143 MT_CIPHER_TKIP,144 MT_CIPHER_TKIP_NO_MIC,145 MT_CIPHER_AES_CCMP,146 MT_CIPHER_WEP104,147 MT_CIPHER_BIP_CMAC_128,148 MT_CIPHER_WEP128,149 MT_CIPHER_WAPI,150 MT_CIPHER_CCMP_CCX,151 MT_CIPHER_CCMP_256,152 MT_CIPHER_GCMP,153 MT_CIPHER_GCMP_256,154};155 156enum mt76_dfs_state {157 MT_DFS_STATE_UNKNOWN,158 MT_DFS_STATE_DISABLED,159 MT_DFS_STATE_CAC,160 MT_DFS_STATE_ACTIVE,161};162 163struct mt76_queue_buf {164 dma_addr_t addr;165 u16 len:15,166 skip_unmap:1;167};168 169struct mt76_tx_info {170 struct mt76_queue_buf buf[32];171 struct sk_buff *skb;172 int nbuf;173 u32 info;174};175 176struct mt76_queue_entry {177 union {178 void *buf;179 struct sk_buff *skb;180 };181 union {182 struct mt76_txwi_cache *txwi;183 struct urb *urb;184 int buf_sz;185 };186 dma_addr_t dma_addr[2];187 u16 dma_len[2];188 u16 wcid;189 bool skip_buf0:1;190 bool skip_buf1:1;191 bool done:1;192};193 194struct mt76_queue_regs {195 u32 desc_base;196 u32 ring_size;197 u32 cpu_idx;198 u32 dma_idx;199} __packed __aligned(4);200 201struct mt76_queue {202 struct mt76_queue_regs __iomem *regs;203 204 spinlock_t lock;205 spinlock_t cleanup_lock;206 struct mt76_queue_entry *entry;207 struct mt76_rro_desc *rro_desc;208 struct mt76_desc *desc;209 210 u16 first;211 u16 head;212 u16 tail;213 u8 hw_idx;214 u8 ep;215 int ndesc;216 int queued;217 int buf_size;218 bool stopped;219 bool blocked;220 221 u8 buf_offset;222 u16 flags;223 224 struct mtk_wed_device *wed;225 u32 wed_regs;226 227 dma_addr_t desc_dma;228 struct sk_buff *rx_head;229 struct page_pool *page_pool;230};231 232struct mt76_mcu_ops {233 unsigned int max_retry;234 u32 headroom;235 u32 tailroom;236 237 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,238 int len, bool wait_resp);239 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb,240 int cmd, int *seq);241 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,242 int cmd, int *seq);243 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,244 struct sk_buff *skb, int seq);245 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);246 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);247 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,248 const struct mt76_reg_pair *rp, int len);249 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,250 struct mt76_reg_pair *rp, int len);251 int (*mcu_restart)(struct mt76_dev *dev);252};253 254struct mt76_queue_ops {255 int (*init)(struct mt76_dev *dev,256 int (*poll)(struct napi_struct *napi, int budget));257 258 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,259 int idx, int n_desc, int bufsize,260 u32 ring_base);261 262 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q,263 enum mt76_txq_id qid, struct sk_buff *skb,264 struct mt76_wcid *wcid, struct ieee80211_sta *sta);265 266 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,267 struct sk_buff *skb, u32 tx_info);268 269 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,270 int *len, u32 *info, bool *more);271 272 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);273 274 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,275 bool flush);276 277 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q);278 279 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);280 281 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q);282};283 284enum mt76_phy_type {285 MT_PHY_TYPE_CCK,286 MT_PHY_TYPE_OFDM,287 MT_PHY_TYPE_HT,288 MT_PHY_TYPE_HT_GF,289 MT_PHY_TYPE_VHT,290 MT_PHY_TYPE_HE_SU = 8,291 MT_PHY_TYPE_HE_EXT_SU,292 MT_PHY_TYPE_HE_TB,293 MT_PHY_TYPE_HE_MU,294 MT_PHY_TYPE_EHT_SU = 13,295 MT_PHY_TYPE_EHT_TRIG,296 MT_PHY_TYPE_EHT_MU,297 __MT_PHY_TYPE_MAX,298};299 300struct mt76_sta_stats {301 u64 tx_mode[__MT_PHY_TYPE_MAX];302 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */303 u64 tx_nss[4]; /* 1, 2, 3, 4 */304 u64 tx_mcs[16]; /* mcs idx */305 u64 tx_bytes;306 /* WED TX */307 u32 tx_packets; /* unit: MSDU */308 u32 tx_retries;309 u32 tx_failed;310 /* WED RX */311 u64 rx_bytes;312 u32 rx_packets;313 u32 rx_errors;314 u32 rx_drops;315};316 317enum mt76_wcid_flags {318 MT_WCID_FLAG_CHECK_PS,319 MT_WCID_FLAG_PS,320 MT_WCID_FLAG_4ADDR,321 MT_WCID_FLAG_HDR_TRANS,322};323 324#define MT76_N_WCIDS 1088325 326/* stored in ieee80211_tx_info::hw_queue */327#define MT_TX_HW_QUEUE_PHY GENMASK(3, 2)328 329DECLARE_EWMA(signal, 10, 8);330 331#define MT_WCID_TX_INFO_RATE GENMASK(15, 0)332#define MT_WCID_TX_INFO_NSS GENMASK(17, 16)333#define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)334#define MT_WCID_TX_INFO_SET BIT(31)335 336struct mt76_wcid {337 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];338 339 atomic_t non_aql_packets;340 unsigned long flags;341 342 struct ewma_signal rssi;343 int inactive_count;344 345 struct rate_info rate;346 unsigned long ampdu_state;347 348 u16 idx;349 u8 hw_key_idx;350 u8 hw_key_idx2;351 352 u8 sta:1;353 u8 sta_disabled:1;354 u8 amsdu:1;355 u8 phy_idx:2;356 u8 link_id:4;357 bool link_valid;358 359 u8 rx_check_pn;360 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6];361 u16 cipher;362 363 u32 tx_info;364 bool sw_iv;365 366 struct list_head tx_list;367 struct sk_buff_head tx_pending;368 struct sk_buff_head tx_offchannel;369 370 struct list_head list;371 struct idr pktid;372 373 struct mt76_sta_stats stats;374 375 struct list_head poll_list;376 377 struct mt76_wcid *def_wcid;378};379 380struct mt76_txq {381 u16 wcid;382 383 u16 agg_ssn;384 bool send_bar;385 bool aggr;386};387 388struct mt76_wed_rro_ind {389 u32 se_id : 12;390 u32 rsv : 4;391 u32 start_sn : 12;392 u32 ind_reason : 4;393 u32 ind_cnt : 13;394 u32 win_sz : 3;395 u32 rsv2 : 13;396 u32 magic_cnt : 3;397};398 399struct mt76_txwi_cache {400 struct list_head list;401 dma_addr_t dma_addr;402 403 union {404 struct sk_buff *skb;405 void *ptr;406 };407};408 409struct mt76_rx_tid {410 struct rcu_head rcu_head;411 412 struct mt76_dev *dev;413 414 spinlock_t lock;415 struct delayed_work reorder_work;416 417 u16 id;418 u16 head;419 u16 size;420 u16 nframes;421 422 u8 num;423 424 u8 started:1, stopped:1, timer_pending:1;425 426 struct sk_buff *reorder_buf[] __counted_by(size);427};428 429#define MT_TX_CB_DMA_DONE BIT(0)430#define MT_TX_CB_TXS_DONE BIT(1)431#define MT_TX_CB_TXS_FAILED BIT(2)432 433#define MT_PACKET_ID_MASK GENMASK(6, 0)434#define MT_PACKET_ID_NO_ACK 0435#define MT_PACKET_ID_NO_SKB 1436#define MT_PACKET_ID_WED 2437#define MT_PACKET_ID_FIRST 3438#define MT_PACKET_ID_HAS_RATE BIT(7)439/* This is timer for when to give up when waiting for TXS callback,440 * with starting time being the time at which the DMA_DONE callback441 * was seen (so, we know packet was processed then, it should not take442 * long after that for firmware to send the TXS callback if it is going443 * to do so.)444 */445#define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4)446 447struct mt76_tx_cb {448 unsigned long jiffies;449 u16 wcid;450 u8 pktid;451 u8 flags;452};453 454enum {455 MT76_STATE_INITIALIZED,456 MT76_STATE_REGISTERED,457 MT76_STATE_RUNNING,458 MT76_STATE_MCU_RUNNING,459 MT76_SCANNING,460 MT76_HW_SCANNING,461 MT76_HW_SCHED_SCANNING,462 MT76_RESTART,463 MT76_RESET,464 MT76_MCU_RESET,465 MT76_REMOVED,466 MT76_READING_STATS,467 MT76_STATE_POWER_OFF,468 MT76_STATE_SUSPEND,469 MT76_STATE_ROC,470 MT76_STATE_PM,471 MT76_STATE_WED_RESET,472};473 474enum mt76_sta_event {475 MT76_STA_EVENT_ASSOC,476 MT76_STA_EVENT_AUTHORIZE,477 MT76_STA_EVENT_DISASSOC,478};479 480struct mt76_hw_cap {481 bool has_2ghz;482 bool has_5ghz;483 bool has_6ghz;484};485 486#define MT_DRV_TXWI_NO_FREE BIT(0)487#define MT_DRV_TX_ALIGNED4_SKBS BIT(1)488#define MT_DRV_SW_RX_AIRTIME BIT(2)489#define MT_DRV_RX_DMA_HDR BIT(3)490#define MT_DRV_HW_MGMT_TXQ BIT(4)491#define MT_DRV_AMSDU_OFFLOAD BIT(5)492 493struct mt76_driver_ops {494 u32 drv_flags;495 u32 survey_flags;496 u16 txwi_size;497 u16 token_size;498 u8 mcs_rates;499 500 void (*update_survey)(struct mt76_phy *phy);501 int (*set_channel)(struct mt76_phy *phy);502 503 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,504 enum mt76_txq_id qid, struct mt76_wcid *wcid,505 struct ieee80211_sta *sta,506 struct mt76_tx_info *tx_info);507 508 void (*tx_complete_skb)(struct mt76_dev *dev,509 struct mt76_queue_entry *e);510 511 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);512 513 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);514 515 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,516 struct sk_buff *skb, u32 *info);517 518 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);519 520 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,521 bool ps);522 523 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,524 struct ieee80211_sta *sta);525 526 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif,527 struct ieee80211_sta *sta, enum mt76_sta_event ev);528 529 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,530 struct ieee80211_sta *sta);531};532 533struct mt76_channel_state {534 u64 cc_active;535 u64 cc_busy;536 u64 cc_rx;537 u64 cc_bss_rx;538 u64 cc_tx;539 540 s8 noise;541};542 543struct mt76_sband {544 struct ieee80211_supported_band sband;545 struct mt76_channel_state *chan;546};547 548/* addr req mask */549#define MT_VEND_TYPE_EEPROM BIT(31)550#define MT_VEND_TYPE_CFG BIT(30)551#define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)552 553#define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))554enum mt_vendor_req {555 MT_VEND_DEV_MODE = 0x1,556 MT_VEND_WRITE = 0x2,557 MT_VEND_POWER_ON = 0x4,558 MT_VEND_MULTI_WRITE = 0x6,559 MT_VEND_MULTI_READ = 0x7,560 MT_VEND_READ_EEPROM = 0x9,561 MT_VEND_WRITE_FCE = 0x42,562 MT_VEND_WRITE_CFG = 0x46,563 MT_VEND_READ_CFG = 0x47,564 MT_VEND_READ_EXT = 0x63,565 MT_VEND_WRITE_EXT = 0x66,566 MT_VEND_FEATURE_SET = 0x91,567};568 569enum mt76u_in_ep {570 MT_EP_IN_PKT_RX,571 MT_EP_IN_CMD_RESP,572 __MT_EP_IN_MAX,573};574 575enum mt76u_out_ep {576 MT_EP_OUT_INBAND_CMD,577 MT_EP_OUT_AC_BE,578 MT_EP_OUT_AC_BK,579 MT_EP_OUT_AC_VI,580 MT_EP_OUT_AC_VO,581 MT_EP_OUT_HCCA,582 __MT_EP_OUT_MAX,583};584 585struct mt76_mcu {586 struct mutex mutex;587 u32 msg_seq;588 int timeout;589 590 struct sk_buff_head res_q;591 wait_queue_head_t wait;592};593 594#define MT_TX_SG_MAX_SIZE 8595#define MT_RX_SG_MAX_SIZE 4596#define MT_NUM_TX_ENTRIES 256597#define MT_NUM_RX_ENTRIES 128598#define MCU_RESP_URB_SIZE 1024599struct mt76_usb {600 struct mutex usb_ctrl_mtx;601 u8 *data;602 u16 data_len;603 604 struct mt76_worker status_worker;605 struct mt76_worker rx_worker;606 607 struct work_struct stat_work;608 609 u8 out_ep[__MT_EP_OUT_MAX];610 u8 in_ep[__MT_EP_IN_MAX];611 bool sg_en;612 613 struct mt76u_mcu {614 u8 *data;615 /* multiple reads */616 struct mt76_reg_pair *rp;617 int rp_len;618 u32 base;619 } mcu;620};621 622#define MT76S_XMIT_BUF_SZ 0x3fe00623#define MT76S_NUM_TX_ENTRIES 256624#define MT76S_NUM_RX_ENTRIES 512625struct mt76_sdio {626 struct mt76_worker txrx_worker;627 struct mt76_worker status_worker;628 struct mt76_worker net_worker;629 struct mt76_worker stat_worker;630 631 u8 *xmit_buf;632 u32 xmit_buf_sz;633 634 struct sdio_func *func;635 void *intr_data;636 u8 hw_ver;637 wait_queue_head_t wait;638 639 struct {640 int pse_data_quota;641 int ple_data_quota;642 int pse_mcu_quota;643 int pse_page_size;644 int deficit;645 } sched;646 647 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr);648};649 650struct mt76_mmio {651 void __iomem *regs;652 spinlock_t irq_lock;653 u32 irqmask;654 655 struct mtk_wed_device wed;656 struct mtk_wed_device wed_hif2;657 struct completion wed_reset;658 struct completion wed_reset_complete;659};660 661struct mt76_rx_status {662 union {663 struct mt76_wcid *wcid;664 u16 wcid_idx;665 };666 667 u32 reorder_time;668 669 u32 ampdu_ref;670 u32 timestamp;671 672 u8 iv[6];673 674 u8 phy_idx:2;675 u8 aggr:1;676 u8 qos_ctl;677 u16 seqno;678 679 u16 freq;680 u32 flag;681 u8 enc_flags;682 u8 encoding:3, bw:4;683 union {684 struct {685 u8 he_ru:3;686 u8 he_gi:2;687 u8 he_dcm:1;688 };689 struct {690 u8 ru:4;691 u8 gi:2;692 } eht;693 };694 695 u8 amsdu:1, first_amsdu:1, last_amsdu:1;696 u8 rate_idx;697 u8 nss:5, band:3;698 s8 signal;699 u8 chains;700 s8 chain_signal[IEEE80211_MAX_CHAINS];701};702 703struct mt76_freq_range_power {704 const struct cfg80211_sar_freq_ranges *range;705 s8 power;706};707 708struct mt76_testmode_ops {709 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);710 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,711 enum mt76_testmode_state new_state);712 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);713};714 715struct mt76_testmode_data {716 enum mt76_testmode_state state;717 718 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];719 struct sk_buff *tx_skb;720 721 u32 tx_count;722 u16 tx_mpdu_len;723 724 u8 tx_rate_mode;725 u8 tx_rate_idx;726 u8 tx_rate_nss;727 u8 tx_rate_sgi;728 u8 tx_rate_ldpc;729 u8 tx_rate_stbc;730 u8 tx_ltf;731 732 u8 tx_antenna_mask;733 u8 tx_spe_idx;734 735 u8 tx_duty_cycle;736 u32 tx_time;737 u32 tx_ipg;738 739 u32 freq_offset;740 741 u8 tx_power[4];742 u8 tx_power_control;743 744 u8 addr[3][ETH_ALEN];745 746 u32 tx_pending;747 u32 tx_queued;748 u16 tx_queued_limit;749 u32 tx_done;750 struct {751 u64 packets[__MT_RXQ_MAX];752 u64 fcs_error[__MT_RXQ_MAX];753 } rx_stats;754};755 756struct mt76_vif {757 u8 idx;758 u8 omac_idx;759 u8 band_idx;760 u8 wmm_idx;761 u8 scan_seq_num;762 u8 cipher;763 u8 basic_rates_idx;764 u8 mcast_rates_idx;765 u8 beacon_rates_idx;766 struct ieee80211_chanctx_conf *ctx;767};768 769struct mt76_phy {770 struct ieee80211_hw *hw;771 struct mt76_dev *dev;772 void *priv;773 774 unsigned long state;775 u8 band_idx;776 777 spinlock_t tx_lock;778 struct list_head tx_list;779 struct mt76_queue *q_tx[__MT_TXQ_MAX];780 781 struct cfg80211_chan_def chandef;782 struct ieee80211_channel *main_chan;783 bool offchannel;784 785 struct mt76_channel_state *chan_state;786 enum mt76_dfs_state dfs_state;787 ktime_t survey_time;788 789 u32 aggr_stats[32];790 791 struct mt76_hw_cap cap;792 struct mt76_sband sband_2g;793 struct mt76_sband sband_5g;794 struct mt76_sband sband_6g;795 796 u8 macaddr[ETH_ALEN];797 798 int txpower_cur;799 u8 antenna_mask;800 u16 chainmask;801 802#ifdef CONFIG_NL80211_TESTMODE803 struct mt76_testmode_data test;804#endif805 806 struct delayed_work mac_work;807 u8 mac_work_count;808 809 struct {810 struct sk_buff *head;811 struct sk_buff **tail;812 u16 seqno;813 } rx_amsdu[__MT_RXQ_MAX];814 815 struct mt76_freq_range_power *frp;816 817 struct {818 struct led_classdev cdev;819 char name[32];820 bool al;821 u8 pin;822 } leds;823};824 825struct mt76_dev {826 struct mt76_phy phy; /* must be first */827 struct mt76_phy *phys[__MT_MAX_BAND];828 829 struct ieee80211_hw *hw;830 831 spinlock_t wed_lock;832 spinlock_t lock;833 spinlock_t cc_lock;834 835 u32 cur_cc_bss_rx;836 837 struct mt76_rx_status rx_ampdu_status;838 u32 rx_ampdu_len;839 u32 rx_ampdu_ref;840 841 struct mutex mutex;842 843 const struct mt76_bus_ops *bus;844 const struct mt76_driver_ops *drv;845 const struct mt76_mcu_ops *mcu_ops;846 struct device *dev;847 struct device *dma_dev;848 849 struct mt76_mcu mcu;850 851 struct net_device *napi_dev;852 struct net_device *tx_napi_dev;853 spinlock_t rx_lock;854 struct napi_struct napi[__MT_RXQ_MAX];855 struct sk_buff_head rx_skb[__MT_RXQ_MAX];856 struct tasklet_struct irq_tasklet;857 858 struct list_head txwi_cache;859 struct list_head rxwi_cache;860 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];861 struct mt76_queue q_rx[__MT_RXQ_MAX];862 const struct mt76_queue_ops *queue_ops;863 int tx_dma_idx[4];864 865 struct mt76_worker tx_worker;866 struct napi_struct tx_napi;867 868 spinlock_t token_lock;869 struct idr token;870 u16 wed_token_count;871 u16 token_count;872 u16 token_size;873 874 spinlock_t rx_token_lock;875 struct idr rx_token;876 u16 rx_token_size;877 878 wait_queue_head_t tx_wait;879 /* spinclock used to protect wcid pktid linked list */880 spinlock_t status_lock;881 882 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];883 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];884 885 u64 vif_mask;886 887 struct mt76_wcid global_wcid;888 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];889 struct list_head wcid_list;890 891 struct list_head sta_poll_list;892 spinlock_t sta_poll_lock;893 894 u32 rev;895 896 struct tasklet_struct pre_tbtt_tasklet;897 int beacon_int;898 u8 beacon_mask;899 900 struct debugfs_blob_wrapper eeprom;901 struct debugfs_blob_wrapper otp;902 903 char alpha2[3];904 enum nl80211_dfs_regions region;905 906 u32 debugfs_reg;907 908 u8 csa_complete;909 910 u32 rxfilter;911 912#ifdef CONFIG_NL80211_TESTMODE913 const struct mt76_testmode_ops *test_ops;914 struct {915 const char *name;916 u32 offset;917 } test_mtd;918#endif919 struct workqueue_struct *wq;920 921 union {922 struct mt76_mmio mmio;923 struct mt76_usb usb;924 struct mt76_sdio sdio;925 };926};927 928/* per-phy stats. */929struct mt76_mib_stats {930 u32 ack_fail_cnt;931 u32 fcs_err_cnt;932 u32 rts_cnt;933 u32 rts_retries_cnt;934 u32 ba_miss_cnt;935 u32 tx_bf_cnt;936 u32 tx_mu_bf_cnt;937 u32 tx_mu_mpdu_cnt;938 u32 tx_mu_acked_mpdu_cnt;939 u32 tx_su_acked_mpdu_cnt;940 u32 tx_bf_ibf_ppdu_cnt;941 u32 tx_bf_ebf_ppdu_cnt;942 943 u32 tx_bf_rx_fb_all_cnt;944 u32 tx_bf_rx_fb_eht_cnt;945 u32 tx_bf_rx_fb_he_cnt;946 u32 tx_bf_rx_fb_vht_cnt;947 u32 tx_bf_rx_fb_ht_cnt;948 949 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */950 u32 tx_bf_rx_fb_nc_cnt;951 u32 tx_bf_rx_fb_nr_cnt;952 u32 tx_bf_fb_cpl_cnt;953 u32 tx_bf_fb_trig_cnt;954 955 u32 tx_ampdu_cnt;956 u32 tx_stop_q_empty_cnt;957 u32 tx_mpdu_attempts_cnt;958 u32 tx_mpdu_success_cnt;959 u32 tx_pkt_ebf_cnt;960 u32 tx_pkt_ibf_cnt;961 962 u32 tx_rwp_fail_cnt;963 u32 tx_rwp_need_cnt;964 965 /* rx stats */966 u32 rx_fifo_full_cnt;967 u32 channel_idle_cnt;968 u32 primary_cca_busy_time;969 u32 secondary_cca_busy_time;970 u32 primary_energy_detect_time;971 u32 cck_mdrdy_time;972 u32 ofdm_mdrdy_time;973 u32 green_mdrdy_time;974 u32 rx_vector_mismatch_cnt;975 u32 rx_delimiter_fail_cnt;976 u32 rx_mrdy_cnt;977 u32 rx_len_mismatch_cnt;978 u32 rx_mpdu_cnt;979 u32 rx_ampdu_cnt;980 u32 rx_ampdu_bytes_cnt;981 u32 rx_ampdu_valid_subframe_cnt;982 u32 rx_ampdu_valid_subframe_bytes_cnt;983 u32 rx_pfdrop_cnt;984 u32 rx_vec_queue_overflow_drop_cnt;985 u32 rx_ba_cnt;986 987 u32 tx_amsdu[8];988 u32 tx_amsdu_cnt;989 990 /* mcu_muru_stats */991 u32 dl_cck_cnt;992 u32 dl_ofdm_cnt;993 u32 dl_htmix_cnt;994 u32 dl_htgf_cnt;995 u32 dl_vht_su_cnt;996 u32 dl_vht_2mu_cnt;997 u32 dl_vht_3mu_cnt;998 u32 dl_vht_4mu_cnt;999 u32 dl_he_su_cnt;1000 u32 dl_he_ext_su_cnt;1001 u32 dl_he_2ru_cnt;1002 u32 dl_he_2mu_cnt;1003 u32 dl_he_3ru_cnt;1004 u32 dl_he_3mu_cnt;1005 u32 dl_he_4ru_cnt;1006 u32 dl_he_4mu_cnt;1007 u32 dl_he_5to8ru_cnt;1008 u32 dl_he_9to16ru_cnt;1009 u32 dl_he_gtr16ru_cnt;1010 1011 u32 ul_hetrig_su_cnt;1012 u32 ul_hetrig_2ru_cnt;1013 u32 ul_hetrig_3ru_cnt;1014 u32 ul_hetrig_4ru_cnt;1015 u32 ul_hetrig_5to8ru_cnt;1016 u32 ul_hetrig_9to16ru_cnt;1017 u32 ul_hetrig_gtr16ru_cnt;1018 u32 ul_hetrig_2mu_cnt;1019 u32 ul_hetrig_3mu_cnt;1020 u32 ul_hetrig_4mu_cnt;1021};1022 1023struct mt76_power_limits {1024 s8 cck[4];1025 s8 ofdm[8];1026 s8 mcs[4][10];1027 s8 ru[7][12];1028 s8 eht[16][16];1029};1030 1031struct mt76_ethtool_worker_info {1032 u64 *data;1033 int idx;1034 int initial_stat_idx;1035 int worker_stat_count;1036 int sta_count;1037};1038 1039#define CCK_RATE(_idx, _rate) { \1040 .bitrate = _rate, \1041 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \1042 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \1043 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \1044}1045 1046#define OFDM_RATE(_idx, _rate) { \1047 .bitrate = _rate, \1048 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \1049 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \1050}1051 1052extern struct ieee80211_rate mt76_rates[12];1053 1054#define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)1055#define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)1056#define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)1057#define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)1058#define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)1059 1060#define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)1061#define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)1062 1063#define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)1064#define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)1065#define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)1066#define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)1067#define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)1068#define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)1069#define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)1070 1071 1072#define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))1073 1074#define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)1075#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)1076 1077#define mt76_get_field(_dev, _reg, _field) \1078 FIELD_GET(_field, mt76_rr(dev, _reg))1079 1080#define mt76_rmw_field(_dev, _reg, _field, _val) \1081 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))1082 1083#define __mt76_rmw_field(_dev, _reg, _field, _val) \1084 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))1085 1086#define mt76_hw(dev) (dev)->mphy.hw1087 1088bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,1089 int timeout);1090 1091#define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)1092 1093bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,1094 int timeout, int kick);1095#define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10)1096#define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10)1097#define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)1098 1099void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);1100void mt76_pci_disable_aspm(struct pci_dev *pdev);1101bool mt76_pci_aspm_supported(struct pci_dev *pdev);1102 1103static inline u16 mt76_chip(struct mt76_dev *dev)1104{1105 return dev->rev >> 16;1106}1107 1108static inline u16 mt76_rev(struct mt76_dev *dev)1109{1110 return dev->rev & 0xffff;1111}1112 1113void mt76_wed_release_rx_buf(struct mtk_wed_device *wed);1114void mt76_wed_offload_disable(struct mtk_wed_device *wed);1115void mt76_wed_reset_complete(struct mtk_wed_device *wed);1116void mt76_wed_dma_reset(struct mt76_dev *dev);1117int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif,1118 struct net_device *netdev, enum tc_setup_type type,1119 void *type_data);1120#ifdef CONFIG_NET_MEDIATEK_SOC_WED1121u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size);1122int mt76_wed_offload_enable(struct mtk_wed_device *wed);1123int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset);1124#else1125static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size)1126{1127 return 0;1128}1129 1130static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed)1131{1132 return 0;1133}1134 1135static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q,1136 bool reset)1137{1138 return 0;1139}1140#endif /* CONFIG_NET_MEDIATEK_SOC_WED */1141 1142#define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))1143#define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))1144 1145#define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)1146#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)1147#define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)1148#define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__)1149#define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)1150#define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)1151#define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__)1152#define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)1153#define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__)1154 1155#define mt76_for_each_q_rx(dev, i) \1156 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \1157 if ((dev)->q_rx[i].ndesc)1158 1159struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,1160 const struct ieee80211_ops *ops,1161 const struct mt76_driver_ops *drv_ops);1162int mt76_register_device(struct mt76_dev *dev, bool vht,1163 struct ieee80211_rate *rates, int n_rates);1164void mt76_unregister_device(struct mt76_dev *dev);1165void mt76_free_device(struct mt76_dev *dev);1166void mt76_unregister_phy(struct mt76_phy *phy);1167 1168struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,1169 const struct ieee80211_ops *ops,1170 u8 band_idx);1171int mt76_register_phy(struct mt76_phy *phy, bool vht,1172 struct ieee80211_rate *rates, int n_rates);1173 1174struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy,1175 const struct file_operations *ops);1176static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev)1177{1178 return mt76_register_debugfs_fops(&dev->phy, NULL);1179}1180 1181int mt76_queues_read(struct seq_file *s, void *data);1182void mt76_seq_puts_array(struct seq_file *file, const char *str,1183 s8 *val, int len);1184 1185int mt76_eeprom_init(struct mt76_dev *dev, int len);1186void mt76_eeprom_override(struct mt76_phy *phy);1187int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len);1188int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep,1189 const char *cell_name, int len);1190 1191struct mt76_queue *1192mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,1193 int ring_base, void *wed, u32 flags);1194u16 mt76_calculate_default_rate(struct mt76_phy *phy,1195 struct ieee80211_vif *vif, int rateidx);1196static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,1197 int n_desc, int ring_base, void *wed,1198 u32 flags)1199{1200 struct mt76_queue *q;1201 1202 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags);1203 if (IS_ERR(q))1204 return PTR_ERR(q);1205 1206 phy->q_tx[qid] = q;1207 1208 return 0;1209}1210 1211static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,1212 int n_desc, int ring_base)1213{1214 struct mt76_queue *q;1215 1216 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0);1217 if (IS_ERR(q))1218 return PTR_ERR(q);1219 1220 dev->q_mcu[qid] = q;1221 1222 return 0;1223}1224 1225static inline struct mt76_phy *1226mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx)1227{1228 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) ||1229 (phy_idx == MT_BAND2 && dev->phys[phy_idx]))1230 return dev->phys[phy_idx];1231 1232 return &dev->phy;1233}1234 1235static inline struct ieee80211_hw *1236mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx)1237{1238 return mt76_dev_phy(dev, phy_idx)->hw;1239}1240 1241static inline u8 *1242mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)1243{1244 return (u8 *)t - dev->drv->txwi_size;1245}1246 1247/* increment with wrap-around */1248static inline int mt76_incr(int val, int size)1249{1250 return (val + 1) & (size - 1);1251}1252 1253/* decrement with wrap-around */1254static inline int mt76_decr(int val, int size)1255{1256 return (val - 1) & (size - 1);1257}1258 1259u8 mt76_ac_to_hwq(u8 ac);1260 1261static inline struct ieee80211_txq *1262mtxq_to_txq(struct mt76_txq *mtxq)1263{1264 void *ptr = mtxq;1265 1266 return container_of(ptr, struct ieee80211_txq, drv_priv);1267}1268 1269static inline struct ieee80211_sta *1270wcid_to_sta(struct mt76_wcid *wcid)1271{1272 void *ptr = wcid;1273 1274 if (!wcid || !wcid->sta)1275 return NULL;1276 1277 if (wcid->def_wcid)1278 ptr = wcid->def_wcid;1279 1280 return container_of(ptr, struct ieee80211_sta, drv_priv);1281}1282 1283static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)1284{1285 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >1286 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));1287 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);1288}1289 1290static inline void *mt76_skb_get_hdr(struct sk_buff *skb)1291{1292 struct mt76_rx_status mstat;1293 u8 *data = skb->data;1294 1295 /* Alignment concerns */1296 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);1297 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);1298 1299 mstat = *((struct mt76_rx_status *)skb->cb);1300 1301 if (mstat.flag & RX_FLAG_RADIOTAP_HE)1302 data += sizeof(struct ieee80211_radiotap_he);1303 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)1304 data += sizeof(struct ieee80211_radiotap_he_mu);1305 1306 return data;1307}1308 1309static inline void mt76_insert_hdr_pad(struct sk_buff *skb)1310{1311 int len = ieee80211_get_hdrlen_from_skb(skb);1312 1313 if (len % 4 == 0)1314 return;1315 1316 skb_push(skb, 2);1317 memmove(skb->data, skb->data + 2, len);1318 1319 skb->data[len] = 0;1320 skb->data[len + 1] = 0;1321}1322 1323static inline bool mt76_is_skb_pktid(u8 pktid)1324{1325 if (pktid & MT_PACKET_ID_HAS_RATE)1326 return false;1327 1328 return pktid >= MT_PACKET_ID_FIRST;1329}1330 1331static inline u8 mt76_tx_power_nss_delta(u8 nss)1332{1333 static const u8 nss_delta[4] = { 0, 6, 9, 12 };1334 u8 idx = nss - 1;1335 1336 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0;1337}1338 1339static inline bool mt76_testmode_enabled(struct mt76_phy *phy)1340{1341#ifdef CONFIG_NL80211_TESTMODE1342 return phy->test.state != MT76_TM_STATE_OFF;1343#else1344 return false;1345#endif1346}1347 1348static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,1349 struct sk_buff *skb,1350 struct ieee80211_hw **hw)1351{1352#ifdef CONFIG_NL80211_TESTMODE1353 int i;1354 1355 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {1356 struct mt76_phy *phy = dev->phys[i];1357 1358 if (phy && skb == phy->test.tx_skb) {1359 *hw = dev->phys[i]->hw;1360 return true;1361 }1362 }1363 return false;1364#else1365 return false;1366#endif1367}1368 1369void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);1370void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,1371 struct mt76_wcid *wcid, struct sk_buff *skb);1372void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);1373void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,1374 bool send_bar);1375void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);1376void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);1377void mt76_txq_schedule_all(struct mt76_phy *phy);1378void mt76_tx_worker_run(struct mt76_dev *dev);1379void mt76_tx_worker(struct mt76_worker *w);1380void mt76_release_buffered_frames(struct ieee80211_hw *hw,1381 struct ieee80211_sta *sta,1382 u16 tids, int nframes,1383 enum ieee80211_frame_release_type reason,1384 bool more_data);1385bool mt76_has_tx_pending(struct mt76_phy *phy);1386int mt76_update_channel(struct mt76_phy *phy);1387void mt76_update_survey(struct mt76_phy *phy);1388void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);1389int mt76_get_survey(struct ieee80211_hw *hw, int idx,1390 struct survey_info *survey);1391int mt76_rx_signal(u8 chain_mask, s8 *chain_signal);1392void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);1393 1394int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,1395 u16 ssn, u16 size);1396void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);1397 1398void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,1399 struct ieee80211_key_conf *key);1400 1401void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)1402 __acquires(&dev->status_lock);1403void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)1404 __releases(&dev->status_lock);1405 1406int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,1407 struct sk_buff *skb);1408struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,1409 struct mt76_wcid *wcid, int pktid,1410 struct sk_buff_head *list);1411void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,1412 struct sk_buff_head *list);1413void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb,1414 struct list_head *free_list);1415static inline void1416mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb)1417{1418 __mt76_tx_complete_skb(dev, wcid, skb, NULL);1419}1420 1421void mt76_tx_status_check(struct mt76_dev *dev, bool flush);1422int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,1423 struct ieee80211_sta *sta,1424 enum ieee80211_sta_state old_state,1425 enum ieee80211_sta_state new_state);1426void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif,1427 struct ieee80211_sta *sta);1428void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,1429 struct ieee80211_sta *sta);1430 1431int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy);1432 1433int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,1434 int *dbm);1435int mt76_init_sar_power(struct ieee80211_hw *hw,1436 const struct cfg80211_sar_specs *sar);1437int mt76_get_sar_power(struct mt76_phy *phy,1438 struct ieee80211_channel *chan,1439 int power);1440 1441void mt76_csa_check(struct mt76_dev *dev);1442void mt76_csa_finish(struct mt76_dev *dev);1443 1444int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);1445int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);1446void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);1447int mt76_get_rate(struct mt76_dev *dev,1448 struct ieee80211_supported_band *sband,1449 int idx, bool cck);1450void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,1451 const u8 *mac);1452void mt76_sw_scan_complete(struct ieee80211_hw *hw,1453 struct ieee80211_vif *vif);1454enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy);1455int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,1456 void *data, int len);1457int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,1458 struct netlink_callback *cb, void *data, int len);1459int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);1460int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);1461 1462static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)1463{1464#ifdef CONFIG_NL80211_TESTMODE1465 enum mt76_testmode_state state = MT76_TM_STATE_IDLE;1466 1467 if (disable || phy->test.state == MT76_TM_STATE_OFF)1468 state = MT76_TM_STATE_OFF;1469 1470 mt76_testmode_set_state(phy, state);1471#endif1472}1473 1474 1475/* internal */1476static inline struct ieee80211_hw *1477mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)1478{1479 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);1480 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;1481 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx);1482 1483 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY;1484 1485 return hw;1486}1487 1488void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);1489void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);1490struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);1491void mt76_free_pending_rxwi(struct mt76_dev *dev);1492void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,1493 struct napi_struct *napi);1494void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,1495 struct napi_struct *napi);1496void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);1497void mt76_testmode_tx_pending(struct mt76_phy *phy);1498void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,1499 struct mt76_queue_entry *e);1500int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef,1501 bool offchannel);1502 1503/* usb */1504static inline bool mt76u_urb_error(struct urb *urb)1505{1506 return urb->status &&1507 urb->status != -ECONNRESET &&1508 urb->status != -ESHUTDOWN &&1509 urb->status != -ENOENT;1510}1511 1512static inline int1513mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,1514 int timeout, int ep)1515{1516 struct usb_interface *uintf = to_usb_interface(dev->dev);1517 struct usb_device *udev = interface_to_usbdev(uintf);1518 struct mt76_usb *usb = &dev->usb;1519 unsigned int pipe;1520 1521 if (actual_len)1522 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);1523 else1524 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);1525 1526 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);1527}1528 1529void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index);1530void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi,1531 struct mt76_sta_stats *stats, bool eht);1532int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);1533int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type,1534 u16 val, u16 offset, void *buf, size_t len);1535int mt76u_vendor_request(struct mt76_dev *dev, u8 req,1536 u8 req_type, u16 val, u16 offset,1537 void *buf, size_t len);1538void mt76u_single_wr(struct mt76_dev *dev, const u8 req,1539 const u16 offset, const u32 val);1540void mt76u_read_copy(struct mt76_dev *dev, u32 offset,1541 void *data, int len);1542u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr);1543void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type,1544 u32 addr, u32 val);1545int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,1546 struct mt76_bus_ops *ops);1547int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);1548int mt76u_alloc_mcu_queue(struct mt76_dev *dev);1549int mt76u_alloc_queues(struct mt76_dev *dev);1550void mt76u_stop_tx(struct mt76_dev *dev);1551void mt76u_stop_rx(struct mt76_dev *dev);1552int mt76u_resume_rx(struct mt76_dev *dev);1553void mt76u_queues_deinit(struct mt76_dev *dev);1554 1555int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,1556 const struct mt76_bus_ops *bus_ops);1557int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid);1558int mt76s_alloc_tx(struct mt76_dev *dev);1559void mt76s_deinit(struct mt76_dev *dev);1560void mt76s_sdio_irq(struct sdio_func *func);1561void mt76s_txrx_worker(struct mt76_sdio *sdio);1562bool mt76s_txqs_empty(struct mt76_dev *dev);1563int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func,1564 int hw_ver);1565u32 mt76s_rr(struct mt76_dev *dev, u32 offset);1566void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val);1567u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);1568u32 mt76s_read_pcr(struct mt76_dev *dev);1569void mt76s_write_copy(struct mt76_dev *dev, u32 offset,1570 const void *data, int len);1571void mt76s_read_copy(struct mt76_dev *dev, u32 offset,1572 void *data, int len);1573int mt76s_wr_rp(struct mt76_dev *dev, u32 base,1574 const struct mt76_reg_pair *data,1575 int len);1576int mt76s_rd_rp(struct mt76_dev *dev, u32 base,1577 struct mt76_reg_pair *data, int len);1578 1579struct sk_buff *1580__mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,1581 int len, int data_len, gfp_t gfp);1582static inline struct sk_buff *1583mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,1584 int data_len)1585{1586 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL);1587}1588 1589void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);1590struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,1591 unsigned long expires);1592int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,1593 int len, bool wait_resp, struct sk_buff **ret);1594int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,1595 int cmd, bool wait_resp, struct sk_buff **ret);1596int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,1597 int len, int max_len);1598static inline int1599mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,1600 int len)1601{1602 int max_len = 4096 - dev->mcu_ops->headroom;1603 1604 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len);1605}1606 1607static inline int1608mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,1609 bool wait_resp)1610{1611 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);1612}1613 1614static inline int1615mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,1616 bool wait_resp)1617{1618 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);1619}1620 1621void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);1622 1623struct device_node *1624mt76_find_power_limits_node(struct mt76_dev *dev);1625struct device_node *1626mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan);1627 1628s8 mt76_get_rate_power_limits(struct mt76_phy *phy,1629 struct ieee80211_channel *chan,1630 struct mt76_power_limits *dest,1631 s8 target_power);1632 1633static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q)1634{1635 int i;1636 1637 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) {1638 if (q == &dev->q_rx[i])1639 return true;1640 }1641 1642 return false;1643}1644 1645static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q)1646{1647 return (q->flags & MT_QFLAG_WED) &&1648 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE;1649}1650 1651static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q)1652{1653 return q->flags & MT_QFLAG_WED_RRO;1654}1655 1656static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q)1657{1658 return mt76_queue_is_wed_rro(q) &&1659 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND;1660}1661 1662static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q)1663{1664 return mt76_queue_is_wed_rro(q) &&1665 (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA ||1666 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG);1667}1668 1669static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q)1670{1671 if (!(q->flags & MT_QFLAG_WED))1672 return false;1673 1674 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX ||1675 mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q);1676 1677}1678 1679struct mt76_txwi_cache *1680mt76_token_release(struct mt76_dev *dev, int token, bool *wake);1681int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);1682void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);1683struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token);1684int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,1685 struct mt76_txwi_cache *r, dma_addr_t phys);1686int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q);1687static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct)1688{1689 struct page *page = virt_to_head_page(buf);1690 1691 page_pool_put_full_page(page->pp, page, allow_direct);1692}1693 1694static inline void *1695mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size)1696{1697 struct page *page;1698 1699 page = page_pool_dev_alloc_frag(q->page_pool, offset, size);1700 if (!page)1701 return NULL;1702 1703 return page_address(page) + *offset;1704}1705 1706static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)1707{1708 spin_lock_bh(&dev->token_lock);1709 __mt76_set_tx_blocked(dev, blocked);1710 spin_unlock_bh(&dev->token_lock);1711}1712 1713static inline int1714mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)1715{1716 int token;1717 1718 spin_lock_bh(&dev->token_lock);1719 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC);1720 spin_unlock_bh(&dev->token_lock);1721 1722 return token;1723}1724 1725static inline struct mt76_txwi_cache *1726mt76_token_put(struct mt76_dev *dev, int token)1727{1728 struct mt76_txwi_cache *txwi;1729 1730 spin_lock_bh(&dev->token_lock);1731 txwi = idr_remove(&dev->token, token);1732 spin_unlock_bh(&dev->token_lock);1733 1734 return txwi;1735}1736 1737void mt76_wcid_init(struct mt76_wcid *wcid);1738void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid);1739 1740#endif1741