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1/* SPDX-License-Identifier: ISC */2 3#ifndef __MT7603_REGS_H4#define __MT7603_REGS_H5 6#define MT_HW_REV 0x10007#define MT_HW_CHIPID 0x10088#define MT_TOP_MISC2 0x11349 10#define MT_MCU_BASE 0x200011#define MT_MCU(ofs) (MT_MCU_BASE + (ofs))12 13#define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)14#define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)15#define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)16 17#define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)18#define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)19#define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)20 21#define MT_HIF_BASE 0x400022#define MT_HIF(ofs) (MT_HIF_BASE + (ofs))23 24#define MT_INT_SOURCE_CSR MT_HIF(0x200)25#define MT_INT_MASK_CSR MT_HIF(0x204)26#define MT_DELAY_INT_CFG MT_HIF(0x210)27 28#define MT_INT_RX_DONE(_n) BIT(_n)29#define MT_INT_RX_DONE_ALL GENMASK(1, 0)30#define MT_INT_TX_DONE_ALL GENMASK(19, 4)31#define MT_INT_TX_DONE(_n) BIT((_n) + 4)32 33#define MT_INT_RX_COHERENT BIT(20)34#define MT_INT_TX_COHERENT BIT(21)35#define MT_INT_MAC_IRQ3 BIT(27)36 37#define MT_INT_MCU_CMD BIT(30)38 39#define MT_WPDMA_GLO_CFG MT_HIF(0x208)40#define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)41#define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)42#define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)43#define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)44#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)45#define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)46#define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)47#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)48#define MT_WPDMA_GLO_CFG_SW_RESET BIT(24)49#define MT_WPDMA_GLO_CFG_FORCE_TX_EOF BIT(25)50#define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)51#define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)52 53#define MT_WPDMA_RST_IDX MT_HIF(0x20c)54 55#define MT_WPDMA_DEBUG MT_HIF(0x244)56#define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)57#define MT_WPDMA_DEBUG_SEL BIT(27)58#define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)59 60#define MT_TX_RING_BASE MT_HIF(0x300)61#define MT_RX_RING_BASE MT_HIF(0x400)62 63#define MT_TXTIME_THRESH_BASE MT_HIF(0x500)64#define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4))65 66#define MT_PAGE_COUNT_BASE MT_HIF(0x540)67#define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4))68 69#define MT_SCH_1 MT_HIF(0x588)70#define MT_SCH_2 MT_HIF(0x58c)71#define MT_SCH_3 MT_HIF(0x590)72 73#define MT_SCH_4 MT_HIF(0x594)74#define MT_SCH_4_FORCE_QID GENMASK(4, 0)75#define MT_SCH_4_BYPASS BIT(5)76#define MT_SCH_4_RESET BIT(8)77 78#define MT_GROUP_THRESH_BASE MT_HIF(0x598)79#define MT_GROUP_THRESH(n) (MT_GROUP_THRESH_BASE + ((n) * 4))80 81#define MT_QUEUE_PRIORITY_1 MT_HIF(0x580)82#define MT_QUEUE_PRIORITY_2 MT_HIF(0x584)83 84#define MT_BMAP_0 MT_HIF(0x5b0)85#define MT_BMAP_1 MT_HIF(0x5b4)86#define MT_BMAP_2 MT_HIF(0x5b8)87 88#define MT_HIGH_PRIORITY_1 MT_HIF(0x5bc)89#define MT_HIGH_PRIORITY_2 MT_HIF(0x5c0)90 91#define MT_PRIORITY_MASK MT_HIF(0x5c4)92 93#define MT_RSV_MAX_THRESH MT_HIF(0x5c8)94 95#define MT_PSE_BASE 0x800096#define MT_PSE(ofs) (MT_PSE_BASE + (ofs))97 98#define MT_MCU_DEBUG_RESET MT_PSE(0x16c)99#define MT_MCU_DEBUG_RESET_PSE BIT(0)100#define MT_MCU_DEBUG_RESET_PSE_S BIT(1)101#define MT_MCU_DEBUG_RESET_QUEUES GENMASK(6, 2)102 103#define MT_PSE_FC_P0 MT_PSE(0x120)104#define MT_PSE_FC_P0_MIN_RESERVE GENMASK(11, 0)105#define MT_PSE_FC_P0_MAX_QUOTA GENMASK(27, 16)106 107#define MT_PSE_FRP MT_PSE(0x138)108#define MT_PSE_FRP_P0 GENMASK(2, 0)109#define MT_PSE_FRP_P1 GENMASK(5, 3)110#define MT_PSE_FRP_P2_RQ0 GENMASK(8, 6)111#define MT_PSE_FRP_P2_RQ1 GENMASK(11, 9)112#define MT_PSE_FRP_P2_RQ2 GENMASK(14, 12)113 114#define MT_FC_RSV_COUNT_0 MT_PSE(0x13c)115#define MT_FC_RSV_COUNT_0_P0 GENMASK(11, 0)116#define MT_FC_RSV_COUNT_0_P1 GENMASK(27, 16)117 118#define MT_FC_SP2_Q0Q1 MT_PSE(0x14c)119#define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0 GENMASK(11, 0)120#define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1 GENMASK(27, 16)121 122#define MT_PSE_FW_SHARED MT_PSE(0x17c)123 124#define MT_PSE_RTA MT_PSE(0x194)125#define MT_PSE_RTA_QUEUE_ID GENMASK(4, 0)126#define MT_PSE_RTA_PORT_ID GENMASK(6, 5)127#define MT_PSE_RTA_REDIRECT_EN BIT(7)128#define MT_PSE_RTA_TAG_ID GENMASK(15, 8)129#define MT_PSE_RTA_WRITE BIT(16)130#define MT_PSE_RTA_BUSY BIT(31)131 132#define MT_WF_PHY_BASE 0x10000133#define MT_WF_PHY_OFFSET 0x1000134#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))135 136#define MT_AGC_BASE MT_WF_PHY(0x500)137#define MT_AGC(n) (MT_AGC_BASE + ((n) * 4))138 139#define MT_AGC1_BASE MT_WF_PHY(0x1500)140#define MT_AGC1(n) (MT_AGC1_BASE + ((n) * 4))141 142#define MT_AGC_41_RSSI_0 GENMASK(23, 16)143#define MT_AGC_41_RSSI_1 GENMASK(7, 0)144 145#define MT_RXTD_BASE MT_WF_PHY(0x600)146#define MT_RXTD(n) (MT_RXTD_BASE + ((n) * 4))147 148#define MT_RXTD_6_ACI_TH GENMASK(4, 0)149#define MT_RXTD_6_CCAED_TH GENMASK(14, 8)150 151#define MT_RXTD_8_LOWER_SIGNAL GENMASK(5, 0)152 153#define MT_RXTD_13_ACI_TH_EN BIT(0)154 155#define MT_WF_PHY_CR_TSSI_BASE MT_WF_PHY(0xd00)156#define MT_WF_PHY_CR_TSSI(phy, n) (MT_WF_PHY_CR_TSSI_BASE + \157 ((phy) * MT_WF_PHY_OFFSET) + \158 ((n) * 4))159 160#define MT_PHYCTRL_BASE MT_WF_PHY(0x4100)161#define MT_PHYCTRL(n) (MT_PHYCTRL_BASE + ((n) * 4))162 163#define MT_PHYCTRL_2_STATUS_RESET BIT(6)164#define MT_PHYCTRL_2_STATUS_EN BIT(7)165 166#define MT_PHYCTRL_STAT_PD MT_PHYCTRL(3)167#define MT_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16)168#define MT_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)169 170#define MT_PHYCTRL_STAT_MDRDY MT_PHYCTRL(8)171#define MT_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16)172#define MT_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)173 174#define MT_WF_AGG_BASE 0x21200175#define MT_WF_AGG(ofs) (MT_WF_AGG_BASE + (ofs))176 177#define MT_AGG_ARCR MT_WF_AGG(0x010)178#define MT_AGG_ARCR_INIT_RATE1 BIT(0)179#define MT_AGG_ARCR_FB_SGI_DISABLE BIT(1)180#define MT_AGG_ARCR_RATE8_DOWN_WRAP BIT(2)181#define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)182#define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16)183#define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19)184#define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20)185#define MT_AGG_ARCR_SPE_DIS_TH GENMASK(27, 24)186 187#define MT_AGG_ARUCR MT_WF_AGG(0x014)188#define MT_AGG_ARDCR MT_WF_AGG(0x018)189#define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * (_n))190#define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \191 MT_AGG_ARxCR_LIMIT_SHIFT(_n), \192 MT_AGG_ARxCR_LIMIT_SHIFT(_n))193 194#define MT_AGG_LIMIT MT_WF_AGG(0x040)195#define MT_AGG_LIMIT_1 MT_WF_AGG(0x044)196#define MT_AGG_LIMIT_AC(_n) GENMASK(((_n) + 1) * 8 - 1, (_n) * 8)197 198#define MT_AGG_BA_SIZE_LIMIT_0 MT_WF_AGG(0x048)199#define MT_AGG_BA_SIZE_LIMIT_1 MT_WF_AGG(0x04c)200#define MT_AGG_BA_SIZE_LIMIT_SHIFT 8201 202#define MT_AGG_PCR MT_WF_AGG(0x050)203#define MT_AGG_PCR_MM BIT(16)204#define MT_AGG_PCR_GF BIT(17)205#define MT_AGG_PCR_BW40 BIT(18)206#define MT_AGG_PCR_RIFS BIT(19)207#define MT_AGG_PCR_BW80 BIT(20)208#define MT_AGG_PCR_BW160 BIT(21)209#define MT_AGG_PCR_ERP BIT(22)210 211#define MT_AGG_PCR_RTS MT_WF_AGG(0x054)212#define MT_AGG_PCR_RTS_THR GENMASK(19, 0)213#define MT_AGG_PCR_RTS_PKT_THR GENMASK(31, 25)214 215#define MT_AGG_ASRCR MT_WF_AGG(0x060)216#define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))217 218#define MT_AGG_CONTROL MT_WF_AGG(0x070)219#define MT_AGG_CONTROL_NO_BA_RULE BIT(0)220#define MT_AGG_CONTROL_NO_BA_AR_RULE BIT(1)221#define MT_AGG_CONTROL_CFEND_SPE_EN BIT(3)222#define MT_AGG_CONTROL_CFEND_RATE GENMASK(15, 4)223#define MT_AGG_CONTROL_BAR_SPE_EN BIT(19)224#define MT_AGG_CONTROL_BAR_RATE GENMASK(31, 20)225 226#define MT_AGG_TMP MT_WF_AGG(0x0d8)227 228#define MT_AGG_BWCR MT_WF_AGG(0x0ec)229#define MT_AGG_BWCR_BW GENMASK(3, 2)230 231#define MT_AGG_RETRY_CONTROL MT_WF_AGG(0x0f4)232#define MT_AGG_RETRY_CONTROL_RTS_LIMIT GENMASK(11, 7)233#define MT_AGG_RETRY_CONTROL_BAR_LIMIT GENMASK(15, 12)234 235#define MT_WF_DMA_BASE 0x21c00236#define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs))237 238#define MT_DMA_DCR0 MT_WF_DMA(0x000)239#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 0)240#define MT_DMA_DCR0_DAMSDU BIT(16)241#define MT_DMA_DCR0_RX_VEC_DROP BIT(17)242 243#define MT_DMA_DCR1 MT_WF_DMA(0x004)244 245#define MT_DMA_FQCR0 MT_WF_DMA(0x008)246#define MT_DMA_FQCR0_TARGET_WCID GENMASK(7, 0)247#define MT_DMA_FQCR0_TARGET_BSS GENMASK(13, 8)248#define MT_DMA_FQCR0_TARGET_QID GENMASK(20, 16)249#define MT_DMA_FQCR0_DEST_PORT_ID GENMASK(23, 22)250#define MT_DMA_FQCR0_DEST_QUEUE_ID GENMASK(28, 24)251#define MT_DMA_FQCR0_MODE BIT(29)252#define MT_DMA_FQCR0_STATUS BIT(30)253#define MT_DMA_FQCR0_BUSY BIT(31)254 255#define MT_DMA_RCFR0 MT_WF_DMA(0x070)256#define MT_DMA_VCFR0 MT_WF_DMA(0x07c)257 258#define MT_DMA_TCFR0 MT_WF_DMA(0x080)259#define MT_DMA_TCFR1 MT_WF_DMA(0x084)260#define MT_DMA_TCFR_TXS_AGGR_TIMEOUT GENMASK(27, 16)261#define MT_DMA_TCFR_TXS_QUEUE BIT(14)262#define MT_DMA_TCFR_TXS_AGGR_COUNT GENMASK(12, 8)263#define MT_DMA_TCFR_TXS_BIT_MAP GENMASK(6, 0)264 265#define MT_DMA_TMCFR0 MT_WF_DMA(0x088)266 267#define MT_WF_ARB_BASE 0x21400268#define MT_WF_ARB(ofs) (MT_WF_ARB_BASE + (ofs))269 270#define MT_WMM_AIFSN MT_WF_ARB(0x020)271#define MT_WMM_AIFSN_MASK GENMASK(3, 0)272#define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4)273 274#define MT_WMM_CWMAX_BASE MT_WF_ARB(0x028)275#define MT_WMM_CWMAX(_n) (MT_WMM_CWMAX_BASE + (((_n) / 2) << 2))276#define MT_WMM_CWMAX_SHIFT(_n) (((_n) & 1) * 16)277#define MT_WMM_CWMAX_MASK GENMASK(15, 0)278 279#define MT_WMM_CWMIN MT_WF_ARB(0x040)280#define MT_WMM_CWMIN_MASK GENMASK(7, 0)281#define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 8)282 283#define MT_WF_ARB_RQCR MT_WF_ARB(0x070)284#define MT_WF_ARB_RQCR_RX_START BIT(0)285#define MT_WF_ARB_RQCR_RXV_START BIT(4)286#define MT_WF_ARB_RQCR_RXV_R_EN BIT(7)287#define MT_WF_ARB_RQCR_RXV_T_EN BIT(8)288 289#define MT_ARB_SCR MT_WF_ARB(0x080)290#define MT_ARB_SCR_BCNQ_OPMODE_MASK GENMASK(1, 0)291#define MT_ARB_SCR_BCNQ_OPMODE_SHIFT(n) ((n) * 2)292#define MT_ARB_SCR_TX_DISABLE BIT(8)293#define MT_ARB_SCR_RX_DISABLE BIT(9)294#define MT_ARB_SCR_BCNQ_EMPTY_SKIP BIT(28)295#define MT_ARB_SCR_TTTT_BTIM_PRIO BIT(29)296#define MT_ARB_SCR_TBTT_BCN_PRIO BIT(30)297#define MT_ARB_SCR_TBTT_BCAST_PRIO BIT(31)298 299enum {300 MT_BCNQ_OPMODE_STA = 0,301 MT_BCNQ_OPMODE_AP = 1,302 MT_BCNQ_OPMODE_ADHOC = 2,303};304 305#define MT_WF_ARB_TX_START_0 MT_WF_ARB(0x100)306#define MT_WF_ARB_TX_START_1 MT_WF_ARB(0x104)307#define MT_WF_ARB_TX_FLUSH_0 MT_WF_ARB(0x108)308#define MT_WF_ARB_TX_FLUSH_1 MT_WF_ARB(0x10c)309#define MT_WF_ARB_TX_STOP_0 MT_WF_ARB(0x110)310#define MT_WF_ARB_TX_STOP_1 MT_WF_ARB(0x114)311 312#define MT_WF_ARB_TX_FLUSH_AC0 BIT(0)313#define MT_WF_ARB_TX_FLUSH_AC1 BIT(5)314#define MT_WF_ARB_TX_FLUSH_AC2 BIT(10)315#define MT_WF_ARB_TX_FLUSH_AC3 BIT(16)316#define MT_WF_ARB_TX_FLUSH_AC4 BIT(21)317#define MT_WF_ARB_TX_FLUSH_AC5 BIT(26)318 319#define MT_WF_ARB_BCN_START MT_WF_ARB(0x118)320#define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n))321#define MT_WF_ARB_BCN_START_T_PRE_TTTT BIT(10)322#define MT_WF_ARB_BCN_START_T_TTTT BIT(11)323#define MT_WF_ARB_BCN_START_T_PRE_TBTT BIT(12)324#define MT_WF_ARB_BCN_START_T_TBTT BIT(13)325#define MT_WF_ARB_BCN_START_T_SLOT_IDLE BIT(14)326#define MT_WF_ARB_BCN_START_T_TX_START BIT(15)327#define MT_WF_ARB_BCN_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)328 329#define MT_WF_ARB_BCN_FLUSH MT_WF_ARB(0x11c)330#define MT_WF_ARB_BCN_FLUSH_BSSn(n) BIT(0 + (n))331#define MT_WF_ARB_BCN_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)332 333#define MT_WF_ARB_CAB_START MT_WF_ARB(0x120)334#define MT_WF_ARB_CAB_START_BSSn(n) BIT(0 + (n))335#define MT_WF_ARB_CAB_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)336 337#define MT_WF_ARB_CAB_FLUSH MT_WF_ARB(0x124)338#define MT_WF_ARB_CAB_FLUSH_BSSn(n) BIT(0 + (n))339#define MT_WF_ARB_CAB_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)340 341#define MT_WF_ARB_CAB_COUNT(n) MT_WF_ARB(0x128 + (n) * 4)342#define MT_WF_ARB_CAB_COUNT_SHIFT 4343#define MT_WF_ARB_CAB_COUNT_MASK GENMASK(3, 0)344#define MT_WF_ARB_CAB_COUNT_B0_REG(n) MT_WF_ARB_CAB_COUNT(((n) > 12 ? 2 : \345 ((n) > 4 ? 1 : 0)))346#define MT_WF_ARB_CAB_COUNT_B0_SHIFT(n) (((n) > 12 ? (n) - 12 : \347 ((n) > 4 ? (n) - 4 : \348 (n) ? (n) + 3 : 0)) * 4)349 350#define MT_TX_ABORT MT_WF_ARB(0x134)351#define MT_TX_ABORT_EN BIT(0)352#define MT_TX_ABORT_WCID GENMASK(15, 8)353 354#define MT_WF_TMAC_BASE 0x21600355#define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs))356 357#define MT_TMAC_TCR MT_WF_TMAC(0x000)358#define MT_TMAC_TCR_BLINK_SEL GENMASK(7, 6)359#define MT_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8)360#define MT_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12)361#define MT_TMAC_TCR_RTS_SIGTA BIT(14)362#define MT_TMAC_TCR_LDPC_OFS BIT(15)363#define MT_TMAC_TCR_TX_STREAMS GENMASK(17, 16)364#define MT_TMAC_TCR_SCH_IDLE_SEL GENMASK(19, 18)365#define MT_TMAC_TCR_SCH_DET_PER_IOD BIT(20)366#define MT_TMAC_TCR_DCH_DET_DISABLE BIT(21)367#define MT_TMAC_TCR_TX_RIFS BIT(22)368#define MT_TMAC_TCR_RX_RIFS_MODE BIT(23)369#define MT_TMAC_TCR_TXOP_TBTT_CTL BIT(24)370#define MT_TMAC_TCR_TBTT_TX_STOP_CTL BIT(25)371#define MT_TMAC_TCR_TXOP_BURST_STOP BIT(26)372#define MT_TMAC_TCR_RDG_RA_MODE BIT(27)373#define MT_TMAC_TCR_RDG_RESP BIT(29)374#define MT_TMAC_TCR_RDG_NO_PENDING BIT(30)375#define MT_TMAC_TCR_SMOOTHING BIT(31)376 377#define MT_WMM_TXOP_BASE MT_WF_TMAC(0x010)378#define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + \379 ((((_n) / 2) ^ 0x1) << 2))380#define MT_WMM_TXOP_SHIFT(_n) (((_n) & 1) * 16)381#define MT_WMM_TXOP_MASK GENMASK(15, 0)382 383#define MT_TIMEOUT_CCK MT_WF_TMAC(0x090)384#define MT_TIMEOUT_OFDM MT_WF_TMAC(0x094)385#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)386#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)387 388#define MT_TXREQ MT_WF_TMAC(0x09c)389#define MT_TXREQ_CCA_SRC_SEL GENMASK(31, 30)390 391#define MT_RXREQ MT_WF_TMAC(0x0a0)392#define MT_RXREQ_DELAY GENMASK(8, 0)393 394#define MT_IFS MT_WF_TMAC(0x0a4)395#define MT_IFS_EIFS GENMASK(8, 0)396#define MT_IFS_RIFS GENMASK(14, 10)397#define MT_IFS_SIFS GENMASK(22, 16)398#define MT_IFS_SLOT GENMASK(30, 24)399 400#define MT_TMAC_PCR MT_WF_TMAC(0x0b4)401#define MT_TMAC_PCR_RATE GENMASK(8, 0)402#define MT_TMAC_PCR_RATE_FIXED BIT(15)403#define MT_TMAC_PCR_ANT_ID GENMASK(21, 16)404#define MT_TMAC_PCR_ANT_ID_SEL BIT(22)405#define MT_TMAC_PCR_SPE_EN BIT(23)406#define MT_TMAC_PCR_ANT_PRI GENMASK(26, 24)407#define MT_TMAC_PCR_ANT_PRI_SEL GENMASK(27)408 409#define MT_WF_RMAC_BASE 0x21800410#define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs))411 412#define MT_WF_RFCR MT_WF_RMAC(0x000)413#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)414#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)415#define MT_WF_RFCR_DROP_VERSION BIT(3)416#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)417#define MT_WF_RFCR_DROP_MCAST BIT(5)418#define MT_WF_RFCR_DROP_BCAST BIT(6)419#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)420#define MT_WF_RFCR_DROP_A3_MAC BIT(8)421#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)422#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)423#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)424#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)425#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)426#define MT_WF_RFCR_DROP_CTS BIT(14)427#define MT_WF_RFCR_DROP_RTS BIT(15)428#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)429#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)430#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)431#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)432#define MT_WF_RFCR_DROP_NDPA BIT(20)433#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)434 435#define MT_BSSID0(idx) MT_WF_RMAC(0x004 + (idx) * 8)436#define MT_BSSID1(idx) MT_WF_RMAC(0x008 + (idx) * 8)437#define MT_BSSID1_VALID BIT(16)438 439#define MT_MAC_ADDR0(idx) MT_WF_RMAC(0x024 + (idx) * 8)440#define MT_MAC_ADDR1(idx) MT_WF_RMAC(0x028 + (idx) * 8)441#define MT_MAC_ADDR1_ADDR GENMASK(15, 0)442#define MT_MAC_ADDR1_VALID BIT(16)443 444#define MT_BA_CONTROL_0 MT_WF_RMAC(0x068)445#define MT_BA_CONTROL_1 MT_WF_RMAC(0x06c)446#define MT_BA_CONTROL_1_ADDR GENMASK(15, 0)447#define MT_BA_CONTROL_1_TID GENMASK(19, 16)448#define MT_BA_CONTROL_1_IGNORE_TID BIT(20)449#define MT_BA_CONTROL_1_IGNORE_ALL BIT(21)450#define MT_BA_CONTROL_1_RESET BIT(22)451 452#define MT_WF_RMACDR MT_WF_RMAC(0x078)453#define MT_WF_RMACDR_TSF_PROBERSP_DIS BIT(0)454#define MT_WF_RMACDR_TSF_TIM BIT(4)455#define MT_WF_RMACDR_MBSSID_MASK GENMASK(25, 24)456#define MT_WF_RMACDR_CHECK_HTC_BY_RATE BIT(26)457#define MT_WF_RMACDR_MAXLEN_20BIT BIT(30)458 459#define MT_WF_RMAC_RMCR MT_WF_RMAC(0x080)460#define MT_WF_RMAC_RMCR_SMPS_MODE GENMASK(21, 20)461#define MT_WF_RMAC_RMCR_RX_STREAMS GENMASK(24, 22)462#define MT_WF_RMAC_RMCR_SMPS_RTS BIT(25)463 464#define MT_WF_RMAC_CH_FREQ MT_WF_RMAC(0x090)465#define MT_WF_RMAC_MAXMINLEN MT_WF_RMAC(0x098)466#define MT_WF_RFCR1 MT_WF_RMAC(0x0a4)467#define MT_WF_RMAC_TMR_PA MT_WF_RMAC(0x0e0)468 469#define MT_WF_SEC_BASE 0x21a00470#define MT_WF_SEC(ofs) (MT_WF_SEC_BASE + (ofs))471 472#define MT_WF_CFG_OFF_BASE 0x21e00473#define MT_WF_CFG_OFF(ofs) (MT_WF_CFG_OFF_BASE + (ofs))474#define MT_WF_CFG_OFF_WOCCR MT_WF_CFG_OFF(0x004)475#define MT_WF_CFG_OFF_WOCCR_TMAC_GC_DIS BIT(4)476 477#define MT_SEC_SCR MT_WF_SEC(0x004)478#define MT_SEC_SCR_MASK_ORDER GENMASK(1, 0)479 480#define MT_WTBL_OFF_BASE 0x23000481#define MT_WTBL_OFF(n) (MT_WTBL_OFF_BASE + (n))482 483#define MT_WTBL_UPDATE MT_WTBL_OFF(0x000)484#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)485#define MT_WTBL_UPDATE_WTBL2 BIT(11)486#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)487#define MT_WTBL_UPDATE_RATE_UPDATE BIT(13)488#define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14)489#define MT_WTBL_UPDATE_RX_COUNT_CLEAR BIT(15)490#define MT_WTBL_UPDATE_BUSY BIT(16)491 492#define MT_WTBL_RMVTCR MT_WTBL_OFF(0x008)493#define MT_WTBL_RMVTCR_RX_MV_MODE BIT(23)494 495#define MT_LPON_BASE 0x24000496#define MT_LPON(n) (MT_LPON_BASE + (n))497 498#define MT_LPON_T0CR MT_LPON(0x010)499#define MT_LPON_T0CR_MODE GENMASK(1, 0)500 501#define MT_LPON_UTTR0 MT_LPON(0x018)502#define MT_LPON_UTTR1 MT_LPON(0x01c)503 504#define MT_LPON_BTEIR MT_LPON(0x020)505#define MT_LPON_BTEIR_MBSS_MODE GENMASK(31, 29)506 507#define MT_PRE_TBTT MT_LPON(0x030)508#define MT_PRE_TBTT_MASK GENMASK(7, 0)509#define MT_PRE_TBTT_SHIFT 8510 511#define MT_TBTT MT_LPON(0x034)512#define MT_TBTT_PERIOD GENMASK(15, 0)513#define MT_TBTT_DTIM_PERIOD GENMASK(23, 16)514#define MT_TBTT_TBTT_WAKE_PERIOD GENMASK(27, 24)515#define MT_TBTT_DTIM_WAKE_PERIOD GENMASK(30, 28)516#define MT_TBTT_CAL_ENABLE BIT(31)517 518#define MT_TBTT_TIMER_CFG MT_LPON(0x05c)519 520#define MT_LPON_SBTOR(n) MT_LPON(0x0a0)521#define MT_LPON_SBTOR_SUB_BSS_EN BIT(29)522#define MT_LPON_SBTOR_TIME_OFFSET GENMASK(19, 0)523 524#define MT_INT_WAKEUP_BASE 0x24400525#define MT_INT_WAKEUP(n) (MT_INT_WAKEUP_BASE + (n))526 527#define MT_HW_INT_STATUS(n) MT_INT_WAKEUP(0x3c + (n) * 8)528#define MT_HW_INT_MASK(n) MT_INT_WAKEUP(0x40 + (n) * 8)529 530#define MT_HW_INT3_TBTT0 BIT(15)531#define MT_HW_INT3_PRE_TBTT0 BIT(31)532 533#define MT_WTBL1_BASE 0x28000534 535#define MT_WTBL_ON_BASE (MT_WTBL1_BASE + 0x2000)536#define MT_WTBL_ON(_n) (MT_WTBL_ON_BASE + (_n))537 538#define MT_WTBL_RIUCR0 MT_WTBL_ON(0x200)539 540#define MT_WTBL_RIUCR1 MT_WTBL_ON(0x204)541#define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)542#define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)543#define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24)544 545#define MT_WTBL_RIUCR2 MT_WTBL_ON(0x208)546#define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)547#define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4)548#define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16)549#define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28)550 551#define MT_WTBL_RIUCR3 MT_WTBL_ON(0x20c)552#define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)553#define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)554#define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20)555 556#define MT_MIB_BASE 0x2c000557#define MT_MIB(_n) (MT_MIB_BASE + (_n))558 559#define MT_MIB_CTL MT_MIB(0x00)560#define MT_MIB_CTL_PSCCA_TIME GENMASK(13, 11)561#define MT_MIB_CTL_CCA_NAV_TX GENMASK(16, 14)562#define MT_MIB_CTL_ED_TIME GENMASK(30, 28)563#define MT_MIB_CTL_READ_CLR_DIS BIT(31)564 565#define MT_MIB_STAT(_n) MT_MIB(0x08 + (_n) * 4)566 567#define MT_MIB_STAT_CCA MT_MIB_STAT(9)568#define MT_MIB_STAT_CCA_MASK GENMASK(23, 0)569 570#define MT_MIB_STAT_PSCCA MT_MIB_STAT(16)571#define MT_MIB_STAT_PSCCA_MASK GENMASK(23, 0)572 573#define MT_TX_AGG_CNT(n) MT_MIB(0xa8 + ((n) << 2))574 575#define MT_MIB_STAT_ED MT_MIB_STAT(18)576#define MT_MIB_STAT_ED_MASK GENMASK(23, 0)577 578#define MT_PCIE_REMAP_BASE_1 0x40000579#define MT_PCIE_REMAP_BASE_2 0x80000580 581#define MT_TX_HW_QUEUE_MGMT 4582#define MT_TX_HW_QUEUE_MCU 5583#define MT_TX_HW_QUEUE_BCN 7584#define MT_TX_HW_QUEUE_BMC 8585 586#define MT_LED_BASE_PHYS 0x80024000587#define MT_LED_PHYS(_n) (MT_LED_BASE_PHYS + (_n))588 589#define MT_LED_CTRL MT_LED_PHYS(0x00)590 591#define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))592#define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n)))593#define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n)))594#define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n)))595#define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n)))596#define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n)))597 598#define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8))599#define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8))600#define MT_LED_STATUS_OFF GENMASK(31, 24)601#define MT_LED_STATUS_ON GENMASK(23, 16)602#define MT_LED_STATUS_DURATION GENMASK(15, 0)603 604#define MT_CLIENT_BASE_PHYS_ADDR 0x800c0000605 606#define MT_CLIENT_TMAC_INFO_TEMPLATE 0x040607 608#define MT_CLIENT_STATUS 0x06c609 610#define MT_CLIENT_RESET_TX 0x070611#define MT_CLIENT_RESET_TX_R_E_1 BIT(16)612#define MT_CLIENT_RESET_TX_R_E_2 BIT(17)613#define MT_CLIENT_RESET_TX_R_E_1_S BIT(20)614#define MT_CLIENT_RESET_TX_R_E_2_S BIT(21)615 616#define MT_EFUSE_BASE 0x81070000617 618#define MT_EFUSE_BASE_CTRL 0x000619#define MT_EFUSE_BASE_CTRL_EMPTY BIT(30)620 621#define MT_EFUSE_CTRL 0x008622#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)623#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)624#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)625#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)626#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)627#define MT_EFUSE_CTRL_VALID BIT(29)628#define MT_EFUSE_CTRL_KICK BIT(30)629#define MT_EFUSE_CTRL_SEL BIT(31)630 631#define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4))632#define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4))633 634#define MT_CLIENT_RXINF 0x068635#define MT_CLIENT_RXINF_RXSH_GROUPS GENMASK(2, 0)636 637#define MT_PSE_BASE_PHYS_ADDR 0xa0000000638 639#define MT_PSE_WTBL_2_PHYS_ADDR 0xa5000000640 641#define MT_WTBL1_SIZE (8 * 4)642#define MT_WTBL2_SIZE (16 * 4)643#define MT_WTBL3_OFFSET (MT7603_WTBL_SIZE * MT_WTBL2_SIZE)644#define MT_WTBL3_SIZE (16 * 4)645#define MT_WTBL4_OFFSET (MT7603_WTBL_SIZE * MT_WTBL3_SIZE + \646 MT_WTBL3_OFFSET)647#define MT_WTBL4_SIZE (8 * 4)648 649#define MT_WTBL1_W0_ADDR_HI GENMASK(15, 0)650#define MT_WTBL1_W0_MUAR_IDX GENMASK(21, 16)651#define MT_WTBL1_W0_RX_CHECK_A1 BIT(22)652#define MT_WTBL1_W0_KEY_IDX GENMASK(24, 23)653#define MT_WTBL1_W0_RX_CHECK_KEY_IDX BIT(25)654#define MT_WTBL1_W0_RX_KEY_VALID BIT(26)655#define MT_WTBL1_W0_RX_IK_VALID BIT(27)656#define MT_WTBL1_W0_RX_VALID BIT(28)657#define MT_WTBL1_W0_RX_CHECK_A2 BIT(29)658#define MT_WTBL1_W0_RX_DATA_VALID BIT(30)659#define MT_WTBL1_W0_WRITE_BURST BIT(31)660 661#define MT_WTBL1_W1_ADDR_LO GENMASK(31, 0)662 663#define MT_WTBL1_W2_MPDU_DENSITY GENMASK(2, 0)664#define MT_WTBL1_W2_KEY_TYPE GENMASK(6, 3)665#define MT_WTBL1_W2_EVEN_PN BIT(7)666#define MT_WTBL1_W2_TO_DS BIT(8)667#define MT_WTBL1_W2_FROM_DS BIT(9)668#define MT_WTBL1_W2_HEADER_TRANS BIT(10)669#define MT_WTBL1_W2_AMPDU_FACTOR GENMASK(13, 11)670#define MT_WTBL1_W2_PWR_MGMT BIT(14)671#define MT_WTBL1_W2_RDG BIT(15)672#define MT_WTBL1_W2_RTS BIT(16)673#define MT_WTBL1_W2_CFACK BIT(17)674#define MT_WTBL1_W2_RDG_BA BIT(18)675#define MT_WTBL1_W2_SMPS BIT(19)676#define MT_WTBL1_W2_TXS_BAF_REPORT BIT(20)677#define MT_WTBL1_W2_DYN_BW BIT(21)678#define MT_WTBL1_W2_LDPC BIT(22)679#define MT_WTBL1_W2_ITXBF BIT(23)680#define MT_WTBL1_W2_ETXBF BIT(24)681#define MT_WTBL1_W2_TXOP_PS BIT(25)682#define MT_WTBL1_W2_MESH BIT(26)683#define MT_WTBL1_W2_QOS BIT(27)684#define MT_WTBL1_W2_HT BIT(28)685#define MT_WTBL1_W2_VHT BIT(29)686#define MT_WTBL1_W2_ADMISSION_CONTROL BIT(30)687#define MT_WTBL1_W2_GROUP_ID BIT(31)688 689#define MT_WTBL1_W3_WTBL2_FRAME_ID GENMASK(10, 0)690#define MT_WTBL1_W3_WTBL2_ENTRY_ID GENMASK(15, 11)691#define MT_WTBL1_W3_WTBL4_FRAME_ID GENMASK(26, 16)692#define MT_WTBL1_W3_CHECK_PER BIT(27)693#define MT_WTBL1_W3_KEEP_I_PSM BIT(28)694#define MT_WTBL1_W3_I_PSM BIT(29)695#define MT_WTBL1_W3_POWER_SAVE BIT(30)696#define MT_WTBL1_W3_SKIP_TX BIT(31)697 698#define MT_WTBL1_W4_WTBL3_FRAME_ID GENMASK(10, 0)699#define MT_WTBL1_W4_WTBL3_ENTRY_ID GENMASK(16, 11)700#define MT_WTBL1_W4_WTBL4_ENTRY_ID GENMASK(22, 17)701#define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23)702 703#define MT_WTBL2_W0_PN_LO GENMASK(31, 0)704 705#define MT_WTBL2_W1_PN_HI GENMASK(15, 0)706#define MT_WTBL2_W1_NON_QOS_SEQNO GENMASK(27, 16)707 708#define MT_WTBL2_W2_TID0_SN GENMASK(11, 0)709#define MT_WTBL2_W2_TID1_SN GENMASK(23, 12)710#define MT_WTBL2_W2_TID2_SN_LO GENMASK(31, 24)711 712#define MT_WTBL2_W3_TID2_SN_HI GENMASK(3, 0)713#define MT_WTBL2_W3_TID3_SN GENMASK(15, 4)714#define MT_WTBL2_W3_TID4_SN GENMASK(27, 16)715#define MT_WTBL2_W3_TID5_SN_LO GENMASK(31, 28)716 717#define MT_WTBL2_W4_TID5_SN_HI GENMASK(7, 0)718#define MT_WTBL2_W4_TID6_SN GENMASK(19, 8)719#define MT_WTBL2_W4_TID7_SN GENMASK(31, 20)720 721#define MT_WTBL2_W5_TX_COUNT_RATE1 GENMASK(15, 0)722#define MT_WTBL2_W5_FAIL_COUNT_RATE1 GENAMSK(31, 16)723 724#define MT_WTBL2_W6_TX_COUNT_RATE2 GENMASK(7, 0)725#define MT_WTBL2_W6_TX_COUNT_RATE3 GENMASK(15, 8)726#define MT_WTBL2_W6_TX_COUNT_RATE4 GENMASK(23, 16)727#define MT_WTBL2_W6_TX_COUNT_RATE5 GENMASK(31, 24)728 729#define MT_WTBL2_W7_TX_COUNT_CUR_BW GENMASK(15, 0)730#define MT_WTBL2_W7_FAIL_COUNT_CUR_BW GENMASK(31, 16)731 732#define MT_WTBL2_W8_TX_COUNT_OTHER_BW GENMASK(15, 0)733#define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW GENMASK(31, 16)734 735#define MT_WTBL2_W9_POWER_OFFSET GENMASK(4, 0)736#define MT_WTBL2_W9_SPATIAL_EXT BIT(5)737#define MT_WTBL2_W9_ANT_PRIORITY GENMASK(8, 6)738#define MT_WTBL2_W9_CC_BW_SEL GENMASK(10, 9)739#define MT_WTBL2_W9_CHANGE_BW_RATE GENMASK(13, 11)740#define MT_WTBL2_W9_BW_CAP GENMASK(15, 14)741#define MT_WTBL2_W9_SHORT_GI_20 BIT(16)742#define MT_WTBL2_W9_SHORT_GI_40 BIT(17)743#define MT_WTBL2_W9_SHORT_GI_80 BIT(18)744#define MT_WTBL2_W9_SHORT_GI_160 BIT(19)745#define MT_WTBL2_W9_MPDU_FAIL_COUNT GENMASK(25, 23)746#define MT_WTBL2_W9_MPDU_OK_COUNT GENMASK(28, 26)747#define MT_WTBL2_W9_RATE_IDX GENMASK(31, 29)748 749#define MT_WTBL2_W10_RATE1 GENMASK(11, 0)750#define MT_WTBL2_W10_RATE2 GENMASK(23, 12)751#define MT_WTBL2_W10_RATE3_LO GENMASK(31, 24)752 753#define MT_WTBL2_W11_RATE3_HI GENMASK(3, 0)754#define MT_WTBL2_W11_RATE4 GENMASK(15, 4)755#define MT_WTBL2_W11_RATE5 GENMASK(27, 16)756#define MT_WTBL2_W11_RATE6_LO GENMASK(31, 28)757 758#define MT_WTBL2_W12_RATE6_HI GENMASK(7, 0)759#define MT_WTBL2_W12_RATE7 GENMASK(19, 8)760#define MT_WTBL2_W12_RATE8 GENMASK(31, 20)761 762#define MT_WTBL2_W13_AVG_RCPI0 GENMASK(7, 0)763#define MT_WTBL2_W13_AVG_RCPI1 GENMASK(15, 8)764#define MT_WTBL2_W13_AVG_RCPI2 GENAMSK(23, 16)765 766#define MT_WTBL2_W14_CC_NOISE_1S GENMASK(6, 0)767#define MT_WTBL2_W14_CC_NOISE_2S GENMASK(13, 7)768#define MT_WTBL2_W14_CC_NOISE_3S GENMASK(20, 14)769#define MT_WTBL2_W14_CHAN_EST_RMS GENMASK(24, 21)770#define MT_WTBL2_W14_CC_NOISE_SEL BIT(15)771#define MT_WTBL2_W14_ANT_SEL GENMASK(31, 26)772 773#define MT_WTBL2_W15_BA_WIN_SIZE GENMASK(2, 0)774#define MT_WTBL2_W15_BA_WIN_SIZE_SHIFT 3775#define MT_WTBL2_W15_BA_EN_TIDS GENMASK(31, 24)776 777#define MT_WTBL1_OR (MT_WTBL1_BASE + 0x2300)778#define MT_WTBL1_OR_PSM_WRITE BIT(31)779 780#endif781