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1// SPDX-License-Identifier: ISC2/* Copyright (C) 2019 MediaTek Inc.3 *4 * Author: Ryder Lee <ryder.lee@mediatek.com>5 * Roy Luo <royluo@google.com>6 * Lorenzo Bianconi <lorenzo@kernel.org>7 * Felix Fietkau <nbd@nbd.name>8 */9 10#include "mt7615.h"11#include "../dma.h"12#include "mac.h"13 14static int15mt7622_init_tx_queues_multi(struct mt7615_dev *dev)16{17 static const u8 wmm_queue_map[] = {18 [IEEE80211_AC_BK] = MT7622_TXQ_AC0,19 [IEEE80211_AC_BE] = MT7622_TXQ_AC1,20 [IEEE80211_AC_VI] = MT7622_TXQ_AC2,21 [IEEE80211_AC_VO] = MT7622_TXQ_AC3,22 };23 int ret;24 int i;25 26 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],28 MT7615_TX_RING_SIZE / 2,29 MT_TX_RING_BASE, NULL, 0);30 if (ret)31 return ret;32 }33 34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT,35 MT7615_TX_MGMT_RING_SIZE,36 MT_TX_RING_BASE, NULL, 0);37 if (ret)38 return ret;39 40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU,41 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);42}43 44static int45mt7615_init_tx_queues(struct mt7615_dev *dev)46{47 int ret;48 49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL,50 MT7615_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);51 if (ret)52 return ret;53 54 if (!is_mt7615(&dev->mt76))55 return mt7622_init_tx_queues_multi(dev);56 57 ret = mt76_connac_init_tx_queues(&dev->mphy, 0, MT7615_TX_RING_SIZE,58 MT_TX_RING_BASE, NULL, 0);59 if (ret)60 return ret;61 62 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU,63 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);64}65 66static int mt7615_poll_tx(struct napi_struct *napi, int budget)67{68 struct mt7615_dev *dev;69 70 dev = mt76_priv(napi->dev);71 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {72 napi_complete(napi);73 queue_work(dev->mt76.wq, &dev->pm.wake_work);74 return 0;75 }76 77 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);78 if (napi_complete(napi))79 mt76_connac_irq_enable(&dev->mt76,80 mt7615_tx_mcu_int_mask(dev));81 82 mt76_connac_pm_unref(&dev->mphy, &dev->pm);83 84 return 0;85}86 87static int mt7615_poll_rx(struct napi_struct *napi, int budget)88{89 struct mt7615_dev *dev;90 int done;91 92 dev = mt76_priv(napi->dev);93 94 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {95 napi_complete(napi);96 queue_work(dev->mt76.wq, &dev->pm.wake_work);97 return 0;98 }99 done = mt76_dma_rx_poll(napi, budget);100 mt76_connac_pm_unref(&dev->mphy, &dev->pm);101 102 return done;103}104 105int mt7615_wait_pdma_busy(struct mt7615_dev *dev)106{107 struct mt76_dev *mdev = &dev->mt76;108 109 if (!is_mt7663(mdev)) {110 u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY;111 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY);112 113 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {114 dev_err(mdev->dev, "PDMA engine busy\n");115 return -EIO;116 }117 118 return 0;119 }120 121 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,122 MT_PDMA_TX_IDX_BUSY, 0, 1000)) {123 dev_err(mdev->dev, "PDMA engine tx busy\n");124 return -EIO;125 }126 127 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,128 MT_PSE_SRC_CNT, 0, 1000)) {129 dev_err(mdev->dev, "PSE engine busy\n");130 return -EIO;131 }132 133 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,134 MT_PDMA_BUSY_IDX, 0, 1000)) {135 dev_err(mdev->dev, "PDMA engine busy\n");136 return -EIO;137 }138 139 return 0;140}141 142static void mt7622_dma_sched_init(struct mt7615_dev *dev)143{144 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);145 int i;146 147 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,148 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,149 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |150 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));151 152 for (i = 0; i <= 5; i++)153 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),154 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |155 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));156 157 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);158 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);159 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);160 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);161 162 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);163 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);164}165 166static void mt7663_dma_sched_init(struct mt7615_dev *dev)167{168 int i;169 170 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),171 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,172 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |173 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));174 175 /* enable refill control group 0, 1, 2, 4, 5 */176 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);177 /* enable group 0, 1, 2, 4, 5, 15 */178 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);179 180 /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */181 for (i = 0; i < 5; i++)182 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),183 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |184 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));185 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),186 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |187 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));188 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),189 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |190 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));191 192 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);193 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);194 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);195 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);196 /* ALTX0 and ALTX1 QID mapping to group 5 */197 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);198 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);199}200 201void mt7615_dma_start(struct mt7615_dev *dev)202{203 /* start dma engine */204 mt76_set(dev, MT_WPDMA_GLO_CFG,205 MT_WPDMA_GLO_CFG_TX_DMA_EN |206 MT_WPDMA_GLO_CFG_RX_DMA_EN |207 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);208 209 if (is_mt7622(&dev->mt76))210 mt7622_dma_sched_init(dev);211 212 if (is_mt7663(&dev->mt76)) {213 mt7663_dma_sched_init(dev);214 215 mt76_wr(dev, MT_MCU2HOST_INT_ENABLE, MT7663_MCU_CMD_ERROR_MASK);216 }217 218}219 220int mt7615_dma_init(struct mt7615_dev *dev)221{222 int rx_ring_size = MT7615_RX_RING_SIZE;223 u32 mask;224 int ret;225 226 mt76_dma_attach(&dev->mt76);227 228 mt76_wr(dev, MT_WPDMA_GLO_CFG,229 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |230 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |231 MT_WPDMA_GLO_CFG_OMIT_TX_INFO);232 233 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,234 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);235 236 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,237 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);238 239 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,240 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);241 242 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,243 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);244 245 if (is_mt7615(&dev->mt76)) {246 mt76_set(dev, MT_WPDMA_GLO_CFG,247 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);248 249 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);250 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);251 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);252 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);253 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);254 mt76_set(dev, 0x7158, BIT(16));255 mt76_clear(dev, 0x7000, BIT(23));256 }257 258 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);259 260 ret = mt7615_init_tx_queues(dev);261 if (ret)262 return ret;263 264 /* init rx queues */265 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,266 MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE,267 MT_RX_RING_BASE);268 if (ret)269 return ret;270 271 if (!is_mt7615(&dev->mt76))272 rx_ring_size /= 2;273 274 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,275 rx_ring_size, MT_RX_BUF_SIZE, MT_RX_RING_BASE);276 if (ret)277 return ret;278 279 mt76_wr(dev, MT_DELAY_INT_CFG, 0);280 281 ret = mt76_init_queues(dev, mt7615_poll_rx);282 if (ret < 0)283 return ret;284 285 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,286 mt7615_poll_tx);287 napi_enable(&dev->mt76.tx_napi);288 289 mt76_poll(dev, MT_WPDMA_GLO_CFG,290 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |291 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);292 293 /* enable interrupts for TX/RX rings */294 295 mask = MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev);296 if (is_mt7663(&dev->mt76))297 mask |= MT7663_INT_MCU_CMD;298 else299 mask |= MT_INT_MCU_CMD;300 301 mt76_connac_irq_enable(&dev->mt76, mask);302 303 mt7615_dma_start(dev);304 305 return 0;306}307 308void mt7615_dma_cleanup(struct mt7615_dev *dev)309{310 mt76_clear(dev, MT_WPDMA_GLO_CFG,311 MT_WPDMA_GLO_CFG_TX_DMA_EN |312 MT_WPDMA_GLO_CFG_RX_DMA_EN);313 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);314 315 mt76_dma_cleanup(&dev->mt76);316}317