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1/* SPDX-License-Identifier: ISC */2/* Copyright (C) 2019 MediaTek Inc. */3 4#ifndef __MT7615_MAC_H5#define __MT7615_MAC_H6 7#define MT_CT_PARSE_LEN 728#define MT_CT_DMA_BUF_NUM 29 10#define MT_RXD0_LENGTH GENMASK(15, 0)11#define MT_RXD0_PKT_FLAG GENMASK(19, 16)12#define MT_RXD0_PKT_TYPE GENMASK(31, 29)13 14#define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)15#define MT_RXD0_NORMAL_IP_SUM BIT(23)16#define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)17#define MT_RXD0_NORMAL_GROUP_1 BIT(25)18#define MT_RXD0_NORMAL_GROUP_2 BIT(26)19#define MT_RXD0_NORMAL_GROUP_3 BIT(27)20#define MT_RXD0_NORMAL_GROUP_4 BIT(28)21 22#define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)23#define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)24#define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)25#define MT_RXD1_MID_AMSDU_FRAME BIT(1)26#define MT_RXD1_LAST_AMSDU_FRAME BIT(0)27#define MT_RXD1_NORMAL_HDR_TRANS BIT(23)28#define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)29#define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)30#define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)31#define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)32#define MT_RXD1_NORMAL_BEACON_UC BIT(5)33#define MT_RXD1_NORMAL_BEACON_MC BIT(4)34#define MT_RXD1_NORMAL_BF_REPORT BIT(3)35#define MT_RXD1_NORMAL_ADDR_TYPE GENMASK(2, 1)36#define MT_RXD1_NORMAL_BCAST GENMASK(2, 1)37#define MT_RXD1_NORMAL_MCAST BIT(2)38#define MT_RXD1_NORMAL_U2M BIT(1)39#define MT_RXD1_NORMAL_HTC_VLD BIT(0)40 41#define MT_RXD2_NORMAL_NON_AMPDU BIT(31)42#define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30)43#define MT_RXD2_NORMAL_NDATA BIT(29)44#define MT_RXD2_NORMAL_NULL_FRAME BIT(28)45#define MT_RXD2_NORMAL_FRAG BIT(27)46#define MT_RXD2_NORMAL_INT_FRAME BIT(26)47#define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)48#define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)49#define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)50#define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22)51#define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)52#define MT_RXD2_NORMAL_ICV_ERR BIT(20)53#define MT_RXD2_NORMAL_CLM BIT(19)54#define MT_RXD2_NORMAL_CM BIT(18)55#define MT_RXD2_NORMAL_FCS_ERR BIT(17)56#define MT_RXD2_NORMAL_SW_BIT BIT(16)57#define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)58#define MT_RXD2_NORMAL_TID GENMASK(11, 8)59#define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)60 61#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)62#define MT_RXD3_NORMAL_PF_MODE BIT(29)63#define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)64#define MT_RXD3_NORMAL_WOL GENMASK(18, 14)65#define MT_RXD3_NORMAL_MAGIC_PKT BIT(13)66#define MT_RXD3_NORMAL_OFLD GENMASK(12, 11)67#define MT_RXD3_NORMAL_CLS BIT(10)68#define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)69#define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8)70#define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)71 72#define MT_RXD4_FRAME_CONTROL GENMASK(15, 0)73 74#define MT_RXD6_SEQ_CTRL GENMASK(15, 0)75#define MT_RXD6_QOS_CTL GENMASK(31, 16)76 77#define MT_RXD7_HT_CONTROL GENMASK(31, 0)78 79#define MT_RXV1_ACID_DET_H BIT(31)80#define MT_RXV1_ACID_DET_L BIT(30)81#define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)82#define MT_RXV1_NUM_RX GENMASK(23, 22)83#define MT_RXV1_HT_NO_SOUND BIT(21)84#define MT_RXV1_HT_SMOOTH BIT(20)85#define MT_RXV1_HT_SHORT_GI BIT(19)86#define MT_RXV1_HT_AGGR BIT(18)87#define MT_RXV1_VHTA1_B22 BIT(17)88#define MT_RXV1_FRAME_MODE GENMASK(16, 15)89#define MT_RXV1_TX_MODE GENMASK(14, 12)90#define MT_RXV1_HT_EXT_LTF GENMASK(11, 10)91#define MT_RXV1_HT_AD_CODE BIT(9)92#define MT_RXV1_HT_STBC GENMASK(8, 7)93#define MT_RXV1_TX_RATE GENMASK(6, 0)94 95#define MT_RXV2_SEL_ANT BIT(31)96#define MT_RXV2_VALID_BIT BIT(30)97#define MT_RXV2_NSTS GENMASK(29, 27)98#define MT_RXV2_GROUP_ID GENMASK(26, 21)99#define MT_RXV2_LENGTH GENMASK(20, 0)100 101#define MT_RXV3_WB_RSSI GENMASK(31, 24)102#define MT_RXV3_IB_RSSI GENMASK(23, 16)103 104#define MT_RXV4_RCPI3 GENMASK(31, 24)105#define MT_RXV4_RCPI2 GENMASK(23, 16)106#define MT_RXV4_RCPI1 GENMASK(15, 8)107#define MT_RXV4_RCPI0 GENMASK(7, 0)108 109#define MT_RXV5_FOE GENMASK(11, 0)110 111#define MT_RXV6_NF3 GENMASK(31, 24)112#define MT_RXV6_NF2 GENMASK(23, 16)113#define MT_RXV6_NF1 GENMASK(15, 8)114#define MT_RXV6_NF0 GENMASK(7, 0)115 116enum tx_header_format {117 MT_HDR_FORMAT_802_3,118 MT_HDR_FORMAT_CMD,119 MT_HDR_FORMAT_802_11,120 MT_HDR_FORMAT_802_11_EXT,121};122 123enum tx_pkt_type {124 MT_TX_TYPE_CT,125 MT_TX_TYPE_SF,126 MT_TX_TYPE_CMD,127 MT_TX_TYPE_FW,128};129 130enum tx_port_idx {131 MT_TX_PORT_IDX_LMAC,132 MT_TX_PORT_IDX_MCU133};134 135enum tx_mcu_port_q_idx {136 MT_TX_MCU_PORT_RX_Q0 = 0,137 MT_TX_MCU_PORT_RX_Q1,138 MT_TX_MCU_PORT_RX_Q2,139 MT_TX_MCU_PORT_RX_Q3,140 MT_TX_MCU_PORT_RX_FWDL = 0x1e141};142 143enum tx_phy_bandwidth {144 MT_PHY_BW_20,145 MT_PHY_BW_40,146 MT_PHY_BW_80,147 MT_PHY_BW_160,148};149 150#define MT_CT_INFO_APPLY_TXD BIT(0)151#define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)152#define MT_CT_INFO_MGMT_FRAME BIT(2)153#define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)154#define MT_CT_INFO_HSR2_TX BIT(4)155 156#define MT_TXD0_P_IDX BIT(31)157#define MT_TXD0_Q_IDX GENMASK(30, 26)158#define MT_TXD0_UDP_TCP_SUM BIT(24)159#define MT_TXD0_IP_SUM BIT(23)160#define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)161#define MT_TXD0_TX_BYTES GENMASK(15, 0)162 163#define MT_TXD1_OWN_MAC GENMASK(31, 26)164#define MT_TXD1_PKT_FMT GENMASK(25, 24)165#define MT_TXD1_TID GENMASK(23, 21)166#define MT_TXD1_AMSDU BIT(20)167#define MT_TXD1_UNXV BIT(19)168#define MT_TXD1_HDR_PAD GENMASK(18, 17)169#define MT_TXD1_TXD_LEN BIT(16)170#define MT_TXD1_LONG_FORMAT BIT(15)171#define MT_TXD1_HDR_FORMAT GENMASK(14, 13)172#define MT_TXD1_HDR_INFO GENMASK(12, 8)173#define MT_TXD1_WLAN_IDX GENMASK(7, 0)174 175#define MT_TXD2_FIX_RATE BIT(31)176#define MT_TXD2_TIMING_MEASURE BIT(30)177#define MT_TXD2_BA_DISABLE BIT(29)178#define MT_TXD2_POWER_OFFSET GENMASK(28, 24)179#define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)180#define MT_TXD2_FRAG GENMASK(15, 14)181#define MT_TXD2_HTC_VLD BIT(13)182#define MT_TXD2_DURATION BIT(12)183#define MT_TXD2_BIP BIT(11)184#define MT_TXD2_MULTICAST BIT(10)185#define MT_TXD2_RTS BIT(9)186#define MT_TXD2_SOUNDING BIT(8)187#define MT_TXD2_NDPA BIT(7)188#define MT_TXD2_NDP BIT(6)189#define MT_TXD2_FRAME_TYPE GENMASK(5, 4)190#define MT_TXD2_SUB_TYPE GENMASK(3, 0)191 192#define MT_TXD3_SN_VALID BIT(31)193#define MT_TXD3_PN_VALID BIT(30)194#define MT_TXD3_SEQ GENMASK(27, 16)195#define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)196#define MT_TXD3_TX_COUNT GENMASK(10, 6)197#define MT_TXD3_PROTECT_FRAME BIT(1)198#define MT_TXD3_NO_ACK BIT(0)199 200#define MT_TXD4_PN_LOW GENMASK(31, 0)201 202#define MT_TXD5_PN_HIGH GENMASK(31, 16)203#define MT_TXD5_SW_POWER_MGMT BIT(13)204#define MT_TXD5_DA_SELECT BIT(11)205#define MT_TXD5_TX_STATUS_HOST BIT(10)206#define MT_TXD5_TX_STATUS_MCU BIT(9)207#define MT_TXD5_TX_STATUS_FMT BIT(8)208#define MT_TXD5_PID GENMASK(7, 0)209 210#define MT_TXD6_FIXED_RATE BIT(31)211#define MT_TXD6_SGI BIT(30)212#define MT_TXD6_LDPC BIT(29)213#define MT_TXD6_TX_BF BIT(28)214#define MT_TXD6_TX_RATE GENMASK(27, 16)215#define MT_TXD6_ANT_ID GENMASK(15, 4)216#define MT_TXD6_DYN_BW BIT(3)217#define MT_TXD6_FIXED_BW BIT(2)218#define MT_TXD6_BW GENMASK(1, 0)219 220/* MT7663 DW7 HW-AMSDU */221#define MT_TXD7_HW_AMSDU_CAP BIT(30)222#define MT_TXD7_TYPE GENMASK(21, 20)223#define MT_TXD7_SUB_TYPE GENMASK(19, 16)224#define MT_TXD7_SPE_IDX GENMASK(15, 11)225#define MT_TXD7_SPE_IDX_SLE BIT(10)226 227#define MT_TXD8_L_TYPE GENMASK(5, 4)228#define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)229 230#define MT_TX_RATE_STBC BIT(11)231#define MT_TX_RATE_NSS GENMASK(10, 9)232#define MT_TX_RATE_MODE GENMASK(8, 6)233#define MT_TX_RATE_IDX GENMASK(5, 0)234 235#define MT_TX_FREE_MSDU_ID_CNT GENMASK(6, 0)236 237#define MT_TXS0_PID GENMASK(31, 24)238#define MT_TXS0_BA_ERROR BIT(22)239#define MT_TXS0_PS_FLAG BIT(21)240#define MT_TXS0_TXOP_TIMEOUT BIT(20)241#define MT_TXS0_BIP_ERROR BIT(19)242 243#define MT_TXS0_QUEUE_TIMEOUT BIT(18)244#define MT_TXS0_RTS_TIMEOUT BIT(17)245#define MT_TXS0_ACK_TIMEOUT BIT(16)246#define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)247 248#define MT_TXS0_TX_STATUS_HOST BIT(15)249#define MT_TXS0_TX_STATUS_MCU BIT(14)250#define MT_TXS0_TXS_FORMAT BIT(13)251#define MT_TXS0_FIXED_RATE BIT(12)252#define MT_TXS0_TX_RATE GENMASK(11, 0)253 254#define MT_TXS1_ANT_ID GENMASK(31, 20)255#define MT_TXS1_RESP_RATE GENMASK(19, 16)256#define MT_TXS1_BW GENMASK(15, 14)257#define MT_TXS1_I_TXBF BIT(13)258#define MT_TXS1_E_TXBF BIT(12)259#define MT_TXS1_TID GENMASK(11, 9)260#define MT_TXS1_AMPDU BIT(8)261#define MT_TXS1_ACKED_MPDU BIT(7)262#define MT_TXS1_TX_POWER_DBM GENMASK(6, 0)263 264#define MT_TXS2_WCID GENMASK(31, 24)265#define MT_TXS2_RXV_SEQNO GENMASK(23, 16)266#define MT_TXS2_TX_DELAY GENMASK(15, 0)267 268#define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)269#define MT_TXS3_TX_COUNT GENMASK(28, 24)270#define MT_TXS3_F1_TSSI1 GENMASK(23, 12)271#define MT_TXS3_F1_TSSI0 GENMASK(11, 0)272#define MT_TXS3_F0_SEQNO GENMASK(11, 0)273 274#define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)275#define MT_TXS4_F1_TSSI3 GENMASK(23, 12)276#define MT_TXS4_F1_TSSI2 GENMASK(11, 0)277 278#define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)279#define MT_TXS5_F1_NOISE_2 GENMASK(23, 16)280#define MT_TXS5_F1_NOISE_1 GENMASK(15, 8)281#define MT_TXS5_F1_NOISE_0 GENMASK(7, 0)282 283#define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)284#define MT_TXS6_F1_RCPI_2 GENMASK(23, 16)285#define MT_TXS6_F1_RCPI_1 GENMASK(15, 8)286#define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)287 288struct mt7615_dfs_pulse {289 u32 max_width; /* us */290 int max_pwr; /* dbm */291 int min_pwr; /* dbm */292 u32 min_stgr_pri; /* us */293 u32 max_stgr_pri; /* us */294 u32 min_cr_pri; /* us */295 u32 max_cr_pri; /* us */296};297 298struct mt7615_dfs_pattern {299 u8 enb;300 u8 stgr;301 u8 min_crpn;302 u8 max_crpn;303 u8 min_crpr;304 u8 min_pw;305 u8 max_pw;306 u32 min_pri;307 u32 max_pri;308 u8 min_crbn;309 u8 max_crbn;310 u8 min_stgpn;311 u8 max_stgpn;312 u8 min_stgpr;313};314 315struct mt7615_dfs_radar_spec {316 struct mt7615_dfs_pulse pulse_th;317 struct mt7615_dfs_pattern radar_pattern[16];318};319 320static inline u32 mt7615_mac_wtbl_addr(struct mt7615_dev *dev, int wcid)321{322 return MT_WTBL_BASE(dev) + wcid * MT_WTBL_ENTRY_SIZE;323}324 325#endif326