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1/* SPDX-License-Identifier: ISC */2/*3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>5 */6 7#ifndef __MT76x02_EEPROM_H8#define __MT76x02_EEPROM_H9 10#include "mt76x02.h"11 12enum mt76x02_eeprom_field {13 MT_EE_CHIP_ID = 0x000,14 MT_EE_VERSION = 0x002,15 MT_EE_MAC_ADDR = 0x004,16 MT_EE_PCI_ID = 0x00A,17 MT_EE_ANTENNA = 0x022,18 MT_EE_CFG1_INIT = 0x024,19 MT_EE_NIC_CONF_0 = 0x034,20 MT_EE_NIC_CONF_1 = 0x036,21 MT_EE_COUNTRY_REGION_5GHZ = 0x038,22 MT_EE_COUNTRY_REGION_2GHZ = 0x039,23 MT_EE_FREQ_OFFSET = 0x03a,24 MT_EE_NIC_CONF_2 = 0x042,25 26 MT_EE_XTAL_TRIM_1 = 0x03a,27 MT_EE_XTAL_TRIM_2 = 0x09e,28 29 MT_EE_LNA_GAIN = 0x044,30 MT_EE_RSSI_OFFSET_2G_0 = 0x046,31 MT_EE_RSSI_OFFSET_2G_1 = 0x048,32 MT_EE_LNA_GAIN_5GHZ_1 = 0x049,33 MT_EE_RSSI_OFFSET_5G_0 = 0x04a,34 MT_EE_RSSI_OFFSET_5G_1 = 0x04c,35 MT_EE_LNA_GAIN_5GHZ_2 = 0x04d,36 37 MT_EE_TX_POWER_DELTA_BW40 = 0x050,38 MT_EE_TX_POWER_DELTA_BW80 = 0x052,39 40 MT_EE_TX_POWER_EXT_PA_5G = 0x054,41 42 MT_EE_TX_POWER_0_START_2G = 0x056,43 MT_EE_TX_POWER_1_START_2G = 0x05c,44 45 /* used as byte arrays */46#define MT_TX_POWER_GROUP_SIZE_5G 547#define MT_TX_POWER_GROUPS_5G 648 MT_EE_TX_POWER_0_START_5G = 0x062,49 MT_EE_TSSI_SLOPE_2G = 0x06e,50 51 MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x074,52 MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x076,53 54 MT_EE_TX_POWER_1_START_5G = 0x080,55 56 MT_EE_TX_POWER_CCK = 0x0a0,57 MT_EE_TX_POWER_OFDM_2G_6M = 0x0a2,58 MT_EE_TX_POWER_OFDM_2G_24M = 0x0a4,59 MT_EE_TX_POWER_OFDM_5G_6M = 0x0b2,60 MT_EE_TX_POWER_OFDM_5G_24M = 0x0b4,61 MT_EE_TX_POWER_HT_MCS0 = 0x0a6,62 MT_EE_TX_POWER_HT_MCS4 = 0x0a8,63 MT_EE_TX_POWER_HT_MCS8 = 0x0aa,64 MT_EE_TX_POWER_HT_MCS12 = 0x0ac,65 MT_EE_TX_POWER_VHT_MCS8 = 0x0be,66 67 MT_EE_2G_TARGET_POWER = 0x0d0,68 MT_EE_TEMP_OFFSET = 0x0d1,69 MT_EE_5G_TARGET_POWER = 0x0d2,70 MT_EE_TSSI_BOUND1 = 0x0d4,71 MT_EE_TSSI_BOUND2 = 0x0d6,72 MT_EE_TSSI_BOUND3 = 0x0d8,73 MT_EE_TSSI_BOUND4 = 0x0da,74 MT_EE_FREQ_OFFSET_COMPENSATION = 0x0db,75 MT_EE_TSSI_BOUND5 = 0x0dc,76 MT_EE_TX_POWER_BYRATE_BASE = 0x0de,77 78 MT_EE_TSSI_SLOPE_5G = 0x0f0,79 MT_EE_RF_TEMP_COMP_SLOPE_5G = 0x0f2,80 MT_EE_RF_TEMP_COMP_SLOPE_2G = 0x0f4,81 82 MT_EE_RF_2G_TSSI_OFF_TXPOWER = 0x0f6,83 MT_EE_RF_2G_RX_HIGH_GAIN = 0x0f8,84 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN = 0x0fa,85 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN = 0x0fc,86 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN = 0x0fe,87 88 MT_EE_BT_RCAL_RESULT = 0x138,89 MT_EE_BT_VCDL_CALIBRATION = 0x13c,90 MT_EE_BT_PMUCFG = 0x13e,91 92 MT_EE_USAGE_MAP_START = 0x1e0,93 MT_EE_USAGE_MAP_END = 0x1fc,94 95 __MT_EE_MAX96};97 98#define MT_EE_ANTENNA_DUAL BIT(15)99 100#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)101#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)102#define MT_EE_NIC_CONF_0_PA_TYPE GENMASK(9, 8)103#define MT_EE_NIC_CONF_0_PA_INT_2G BIT(8)104#define MT_EE_NIC_CONF_0_PA_INT_5G BIT(9)105#define MT_EE_NIC_CONF_0_PA_IO_CURRENT BIT(10)106#define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)107 108#define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0)109#define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1)110#define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2)111#define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3)112#define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13)113 114#define MT_EE_NIC_CONF_2_ANT_OPT BIT(3)115#define MT_EE_NIC_CONF_2_ANT_DIV BIT(4)116#define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)117 118#define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \119 MT_EE_USAGE_MAP_START + 1)120 121enum mt76x02_eeprom_modes {122 MT_EE_READ,123 MT_EE_PHYSICAL_READ,124};125 126enum mt76x02_board_type {127 BOARD_TYPE_2GHZ = 1,128 BOARD_TYPE_5GHZ = 2,129};130 131static inline bool mt76x02_field_valid(u8 val)132{133 return val != 0 && val != 0xff;134}135 136static inline int137mt76x02_sign_extend(u32 val, unsigned int size)138{139 bool sign = val & BIT(size - 1);140 141 val &= BIT(size - 1) - 1;142 143 return sign ? val : -val;144}145 146static inline int147mt76x02_sign_extend_optional(u32 val, unsigned int size)148{149 bool enable = val & BIT(size);150 151 return enable ? mt76x02_sign_extend(val, size) : 0;152}153 154static inline s8 mt76x02_rate_power_val(u8 val)155{156 if (!mt76x02_field_valid(val))157 return 0;158 159 return mt76x02_sign_extend_optional(val, 7);160}161 162static inline int163mt76x02_eeprom_get(struct mt76x02_dev *dev,164 enum mt76x02_eeprom_field field)165{166 if ((field & 1) || field >= __MT_EE_MAX)167 return -1;168 169 return get_unaligned_le16(dev->mt76.eeprom.data + field);170}171 172bool mt76x02_ext_pa_enabled(struct mt76x02_dev *dev, enum nl80211_band band);173int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf,174 int len, enum mt76x02_eeprom_modes mode);175void mt76x02_get_rx_gain(struct mt76x02_dev *dev, enum nl80211_band band,176 u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g);177u8 mt76x02_get_lna_gain(struct mt76x02_dev *dev,178 s8 *lna_2g, s8 *lna_5g,179 struct ieee80211_channel *chan);180void mt76x02_eeprom_parse_hw_cap(struct mt76x02_dev *dev);181int mt76x02_eeprom_copy(struct mt76x02_dev *dev,182 enum mt76x02_eeprom_field field,183 void *dest, int len);184 185#endif /* __MT76x02_EEPROM_H */186