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1/* SPDX-License-Identifier: ISC */2/* Copyright (C) 2020 MediaTek Inc. */3 4#ifndef __MT7915_H5#define __MT7915_H6 7#include <linux/interrupt.h>8#include <linux/ktime.h>9#include "../mt76_connac.h"10#include "regs.h"11 12#define MT7915_MAX_INTERFACES 1913#define MT7915_WTBL_SIZE 28814#define MT7916_WTBL_SIZE 54415#define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1)16#define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \17 MT7915_MAX_INTERFACES)18 19#define MT7915_WATCHDOG_TIME (HZ / 10)20#define MT7915_RESET_TIMEOUT (30 * HZ)21 22#define MT7915_TX_RING_SIZE 204823#define MT7915_TX_MCU_RING_SIZE 25624#define MT7915_TX_FWDL_RING_SIZE 12825 26#define MT7915_RX_RING_SIZE 153627#define MT7915_RX_MCU_RING_SIZE 51228 29#define MT7915_FIRMWARE_WA "mediatek/mt7915_wa.bin"30#define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin"31#define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin"32 33#define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin"34#define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin"35#define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin"36 37#define MT7981_FIRMWARE_WA "mediatek/mt7981_wa.bin"38#define MT7981_FIRMWARE_WM "mediatek/mt7981_wm.bin"39#define MT7981_ROM_PATCH "mediatek/mt7981_rom_patch.bin"40 41#define MT7986_FIRMWARE_WA "mediatek/mt7986_wa.bin"42#define MT7986_FIRMWARE_WM "mediatek/mt7986_wm.bin"43#define MT7986_FIRMWARE_WM_MT7975 "mediatek/mt7986_wm_mt7975.bin"44#define MT7986_ROM_PATCH "mediatek/mt7986_rom_patch.bin"45#define MT7986_ROM_PATCH_MT7975 "mediatek/mt7986_rom_patch_mt7975.bin"46 47#define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin"48#define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin"49#define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin"50 51#define MT7981_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7981_eeprom_mt7976_dbdc.bin"52 53#define MT7986_EEPROM_MT7975_DEFAULT "mediatek/mt7986_eeprom_mt7975.bin"54#define MT7986_EEPROM_MT7975_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7975_dual.bin"55#define MT7986_EEPROM_MT7976_DEFAULT "mediatek/mt7986_eeprom_mt7976.bin"56#define MT7986_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7986_eeprom_mt7976_dbdc.bin"57#define MT7986_EEPROM_MT7976_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7976_dual.bin"58 59#define MT7915_EEPROM_SIZE 358460#define MT7916_EEPROM_SIZE 409661 62#define MT7915_EEPROM_BLOCK_SIZE 1663#define MT7915_HW_TOKEN_SIZE 409664#define MT7915_TOKEN_SIZE 819265 66#define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */67#define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */68 69#define MT7915_THERMAL_THROTTLE_MAX 10070#define MT7915_CDEV_THROTTLE_MAX 9971 72#define MT7915_SKU_RATE_NUM 16173 74#define MT7915_MAX_TWT_AGRT 1675#define MT7915_MAX_STA_TWT_AGRT 876#define MT7915_MIN_TWT_DUR 6477#define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2)78 79#define MT7915_WED_RX_TOKEN_SIZE 1228880 81#define MT7915_CRIT_TEMP_IDX 082#define MT7915_MAX_TEMP_IDX 183#define MT7915_CRIT_TEMP 11084#define MT7915_MAX_TEMP 12085 86struct mt7915_vif;87struct mt7915_sta;88struct mt7915_dfs_pulse;89struct mt7915_dfs_pattern;90 91enum mt7915_txq_id {92 MT7915_TXQ_FWDL = 16,93 MT7915_TXQ_MCU_WM,94 MT7915_TXQ_BAND0,95 MT7915_TXQ_BAND1,96 MT7915_TXQ_MCU_WA,97};98 99enum mt7915_rxq_id {100 MT7915_RXQ_BAND0 = 0,101 MT7915_RXQ_BAND1,102 MT7915_RXQ_MCU_WM = 0,103 MT7915_RXQ_MCU_WA,104 MT7915_RXQ_MCU_WA_EXT,105};106 107enum mt7916_rxq_id {108 MT7916_RXQ_MCU_WM = 0,109 MT7916_RXQ_MCU_WA,110 MT7916_RXQ_MCU_WA_MAIN,111 MT7916_RXQ_MCU_WA_EXT,112 MT7916_RXQ_BAND0,113 MT7916_RXQ_BAND1,114};115 116struct mt7915_twt_flow {117 struct list_head list;118 u64 start_tsf;119 u64 tsf;120 u32 duration;121 u16 wcid;122 __le16 mantissa;123 u8 exp;124 u8 table_id;125 u8 id;126 u8 protection:1;127 u8 flowtype:1;128 u8 trigger:1;129 u8 sched:1;130};131 132DECLARE_EWMA(avg_signal, 10, 8)133 134struct mt7915_sta {135 struct mt76_wcid wcid; /* must be first */136 137 struct mt7915_vif *vif;138 139 struct list_head rc_list;140 u32 airtime_ac[8];141 142 int ack_signal;143 struct ewma_avg_signal avg_ack_signal;144 145 unsigned long changed;146 unsigned long jiffies;147 struct mt76_connac_sta_key_conf bip;148 149 struct {150 u8 flowid_mask;151 struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT];152 } twt;153};154 155struct mt7915_vif_cap {156 bool ht_ldpc:1;157 bool vht_ldpc:1;158 bool he_ldpc:1;159 bool vht_su_ebfer:1;160 bool vht_su_ebfee:1;161 bool vht_mu_ebfer:1;162 bool vht_mu_ebfee:1;163 bool he_su_ebfer:1;164 bool he_su_ebfee:1;165 bool he_mu_ebfer:1;166};167 168struct mt7915_vif {169 struct mt76_vif mt76; /* must be first */170 171 struct mt7915_vif_cap cap;172 struct mt7915_sta sta;173 struct mt7915_phy *phy;174 175 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];176 struct cfg80211_bitrate_mask bitrate_mask;177};178 179/* crash-dump */180struct mt7915_crash_data {181 guid_t guid;182 struct timespec64 timestamp;183 184 u8 *memdump_buf;185 size_t memdump_buf_len;186};187 188struct mt7915_hif {189 struct list_head list;190 191 struct device *dev;192 void __iomem *regs;193 int irq;194};195 196struct mt7915_phy {197 struct mt76_phy *mt76;198 struct mt7915_dev *dev;199 200 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];201 202 struct ieee80211_vif *monitor_vif;203 204 struct thermal_cooling_device *cdev;205 u8 cdev_state;206 u8 throttle_state;207 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */208 209 u32 rxfilter;210 u64 omac_mask;211 212 u16 noise;213 214 s16 coverage_class;215 u8 slottime;216 217 u8 rdd_state;218 219 u32 trb_ts;220 221 u32 rx_ampdu_ts;222 u32 ampdu_ref;223 224 struct mt76_mib_stats mib;225 struct mt76_channel_state state_ts;226 227#ifdef CONFIG_NL80211_TESTMODE228 struct {229 u32 *reg_backup;230 231 s32 last_freq_offset;232 u8 last_rcpi[4];233 s8 last_ib_rssi[4];234 s8 last_wb_rssi[4];235 u8 last_snr;236 237 u8 spe_idx;238 } test;239#endif240};241 242struct mt7915_dev {243 union { /* must be first */244 struct mt76_dev mt76;245 struct mt76_phy mphy;246 };247 248 struct mt7915_hif *hif2;249 struct mt7915_reg_desc reg;250 u8 q_id[MT7915_MAX_QUEUE];251 u32 q_int_mask[MT7915_MAX_QUEUE];252 u32 wfdma_mask;253 254 const struct mt76_bus_ops *bus_ops;255 struct mt7915_phy phy;256 257 /* monitor rx chain configured channel */258 struct cfg80211_chan_def rdd2_chandef;259 struct mt7915_phy *rdd2_phy;260 261 u16 chainmask;262 u16 chainshift;263 u32 hif_idx;264 265 struct work_struct init_work;266 struct work_struct rc_work;267 struct work_struct dump_work;268 struct work_struct reset_work;269 wait_queue_head_t reset_wait;270 271 struct {272 u32 state;273 u32 wa_reset_count;274 u32 wm_reset_count;275 bool hw_full_reset:1;276 bool hw_init_done:1;277 bool restart:1;278 } recovery;279 280 /* protects coredump data */281 struct mutex dump_mutex;282#ifdef CONFIG_DEV_COREDUMP283 struct {284 struct mt7915_crash_data *crash_data;285 } coredump;286#endif287 288 struct list_head sta_rc_list;289 struct list_head twt_list;290 spinlock_t reg_lock;291 292 u32 hw_pattern;293 294 bool dbdc_support;295 bool flash_mode;296 bool muru_debug;297 bool ibf;298 299 u8 monitor_mask;300 301 struct dentry *debugfs_dir;302 struct rchan *relay_fwlog;303 304 void *cal;305 u32 cur_prek_offset;306 u8 dpd_chan_num_2g;307 u8 dpd_chan_num_5g;308 u8 dpd_chan_num_6g;309 310 struct {311 u8 debug_wm;312 u8 debug_wa;313 u8 debug_bin;314 } fw;315 316 struct {317 u16 table_mask;318 u8 n_agrt;319 } twt;320 321 struct reset_control *rstc;322 void __iomem *dcm;323 void __iomem *sku;324};325 326enum {327 WFDMA0 = 0x0,328 WFDMA1,329 WFDMA_EXT,330 __MT_WFDMA_MAX,331};332 333enum {334 MT_RX_SEL0,335 MT_RX_SEL1,336 MT_RX_SEL2, /* monitor chain */337};338 339enum mt7915_rdd_cmd {340 RDD_STOP,341 RDD_START,342 RDD_DET_MODE,343 RDD_RADAR_EMULATE,344 RDD_START_TXQ = 20,345 RDD_SET_WF_ANT = 30,346 RDD_CAC_START = 50,347 RDD_CAC_END,348 RDD_NORMAL_START,349 RDD_DISABLE_DFS_CAL,350 RDD_PULSE_DBG,351 RDD_READ_PULSE,352 RDD_RESUME_BF,353 RDD_IRQ_OFF,354};355 356static inline struct mt7915_phy *357mt7915_hw_phy(struct ieee80211_hw *hw)358{359 struct mt76_phy *phy = hw->priv;360 361 return phy->priv;362}363 364static inline struct mt7915_dev *365mt7915_hw_dev(struct ieee80211_hw *hw)366{367 struct mt76_phy *phy = hw->priv;368 369 return container_of(phy->dev, struct mt7915_dev, mt76);370}371 372static inline struct mt7915_phy *373mt7915_ext_phy(struct mt7915_dev *dev)374{375 struct mt76_phy *phy = dev->mt76.phys[MT_BAND1];376 377 if (!phy)378 return NULL;379 380 return phy->priv;381}382 383static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku)384{385 u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK;386 if (!is_mt798x(&dev->mt76))387 return 0;388 389 return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask;390}391 392extern const struct ieee80211_ops mt7915_ops;393extern const struct mt76_testmode_ops mt7915_testmode_ops;394extern struct pci_driver mt7915_pci_driver;395extern struct pci_driver mt7915_hif_driver;396extern struct platform_driver mt798x_wmac_driver;397 398#ifdef CONFIG_MT798X_WMAC399int mt7986_wmac_enable(struct mt7915_dev *dev);400void mt7986_wmac_disable(struct mt7915_dev *dev);401#else402static inline int mt7986_wmac_enable(struct mt7915_dev *dev)403{404 return 0;405}406 407static inline void mt7986_wmac_disable(struct mt7915_dev *dev)408{409}410#endif411struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,412 void __iomem *mem_base, u32 device_id);413void mt7915_wfsys_reset(struct mt7915_dev *dev);414irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);415u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);416u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);417 418int mt7915_register_device(struct mt7915_dev *dev);419void mt7915_unregister_device(struct mt7915_dev *dev);420int mt7915_eeprom_init(struct mt7915_dev *dev);421void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,422 struct mt7915_phy *phy);423int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,424 struct ieee80211_channel *chan,425 u8 chain_idx);426s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band);427int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2);428void mt7915_dma_prefetch(struct mt7915_dev *dev);429void mt7915_dma_cleanup(struct mt7915_dev *dev);430int mt7915_dma_reset(struct mt7915_dev *dev, bool force);431int mt7915_dma_start(struct mt7915_dev *dev, bool reset, bool wed_reset);432int mt7915_txbf_init(struct mt7915_dev *dev);433void mt7915_init_txpower(struct mt7915_phy *phy);434void mt7915_reset(struct mt7915_dev *dev);435int mt7915_run(struct ieee80211_hw *hw);436int mt7915_mcu_init(struct mt7915_dev *dev);437int mt7915_mcu_init_firmware(struct mt7915_dev *dev);438int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,439 struct mt7915_vif *mvif,440 struct mt7915_twt_flow *flow,441 int cmd);442int mt7915_mcu_add_dev_info(struct mt7915_phy *phy,443 struct ieee80211_vif *vif, bool enable);444int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,445 struct ieee80211_vif *vif, int enable);446int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,447 struct ieee80211_sta *sta, int conn_state, bool newly);448int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev,449 struct ieee80211_ampdu_params *params,450 bool add);451int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev,452 struct ieee80211_ampdu_params *params,453 bool add);454int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif,455 struct cfg80211_he_bss_color *he_bss_color);456int mt7915_mcu_add_inband_discov(struct mt7915_dev *dev, struct ieee80211_vif *vif,457 u32 changed);458int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,459 int enable, u32 changed);460int mt7915_mcu_add_obss_spr(struct mt7915_phy *phy, struct ieee80211_vif *vif,461 struct ieee80211_he_obss_pd *he_obss_pd);462int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif,463 struct ieee80211_sta *sta, bool changed);464int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif,465 struct ieee80211_sta *sta);466int mt7915_set_channel(struct mt76_phy *mphy);467int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd);468int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif);469int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req);470int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,471 struct ieee80211_vif *vif,472 struct ieee80211_sta *sta,473 void *data, u32 field);474int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);475int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);476int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);477int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,478 bool hdr_trans);479int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode,480 u8 en);481int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band);482int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable);483int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy);484int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len);485int mt7915_mcu_set_txpower_frame_min(struct mt7915_phy *phy, s8 txpower);486int mt7915_mcu_set_txpower_frame(struct mt7915_phy *phy,487 struct ieee80211_vif *vif,488 struct ieee80211_sta *sta, s8 txpower);489int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action);490int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val);491int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev,492 const struct mt7915_dfs_pulse *pulse);493int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index,494 const struct mt7915_dfs_pattern *pattern);495int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val);496int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev);497int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy);498int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch);499int mt7915_mcu_get_temperature(struct mt7915_phy *phy);500int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state);501int mt7915_mcu_set_thermal_protect(struct mt7915_phy *phy);502int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif,503 struct ieee80211_sta *sta, struct rate_info *rate);504int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy,505 struct cfg80211_chan_def *chandef);506int mt7915_mcu_wed_wa_tx_stats(struct mt7915_dev *dev, u16 wcid);507int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set);508int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);509int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);510int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);511void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);512void mt7915_mcu_exit(struct mt7915_dev *dev);513 514static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)515{516 return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE;517}518 519static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev)520{521 return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE;522}523 524void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,525 u32 clear, u32 set);526 527static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask)528{529 if (dev->hif2)530 mt7915_dual_hif_set_irq_mask(dev, false, 0, mask);531 else532 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);533 534 tasklet_schedule(&dev->mt76.irq_tasklet);535}536 537static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask)538{539 if (dev->hif2)540 mt7915_dual_hif_set_irq_mask(dev, true, mask, 0);541 else542 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);543}544 545void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset,546 size_t len);547 548void mt7915_mac_init(struct mt7915_dev *dev);549u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw);550bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask);551void mt7915_mac_reset_counters(struct mt7915_phy *phy);552void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy);553void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy);554void mt7915_mac_enable_rtscts(struct mt7915_dev *dev,555 struct ieee80211_vif *vif, bool enable);556void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,557 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,558 struct ieee80211_key_conf *key,559 enum mt76_txq_id qid, u32 changed);560void mt7915_mac_set_timing(struct mt7915_phy *phy);561int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,562 struct ieee80211_sta *sta);563int mt7915_mac_sta_event(struct mt76_dev *mdev, struct ieee80211_vif *vif,564 struct ieee80211_sta *sta, enum mt76_sta_event ev);565void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,566 struct ieee80211_sta *sta);567void mt7915_mac_work(struct work_struct *work);568void mt7915_mac_reset_work(struct work_struct *work);569void mt7915_mac_dump_work(struct work_struct *work);570void mt7915_mac_sta_rc_work(struct work_struct *work);571void mt7915_mac_update_stats(struct mt7915_phy *phy);572void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,573 struct mt7915_sta *msta,574 u8 flowid);575void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,576 struct ieee80211_sta *sta,577 struct ieee80211_twt_setup *twt);578int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,579 enum mt76_txq_id qid, struct mt76_wcid *wcid,580 struct ieee80211_sta *sta,581 struct mt76_tx_info *tx_info);582void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,583 struct sk_buff *skb, u32 *info);584bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);585void mt7915_stats_work(struct work_struct *work);586int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force);587int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy);588void mt7915_set_stream_he_caps(struct mt7915_phy *phy);589void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy);590void mt7915_update_channel(struct mt76_phy *mphy);591int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable);592int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy);593int mt7915_mcu_wed_enable_rx_stats(struct mt7915_dev *dev);594int mt7915_init_debugfs(struct mt7915_phy *phy);595void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len);596bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len);597#ifdef CONFIG_MAC80211_DEBUGFS598void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,599 struct ieee80211_sta *sta, struct dentry *dir);600#endif601int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,602 bool pci, int *irq);603 604#endif605