791 lines · c
1// SPDX-License-Identifier: ISC2/* Copyright (C) 2020 MediaTek Inc. */3 4#include "mt7915.h"5#include "mac.h"6#include "mcu.h"7#include "testmode.h"8 9enum {10 TM_CHANGED_TXPOWER,11 TM_CHANGED_FREQ_OFFSET,12 13 /* must be last */14 NUM_TM_CHANGED15};16 17static const u8 tm_change_map[] = {18 [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,19 [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,20};21 22struct reg_band {23 u32 band[2];24};25 26#define REG_BAND(_list, _reg) \27 { _list.band[0] = MT_##_reg(0); \28 _list.band[1] = MT_##_reg(1); }29#define REG_BAND_IDX(_list, _reg, _idx) \30 { _list.band[0] = MT_##_reg(0, _idx); \31 _list.band[1] = MT_##_reg(1, _idx); }32 33#define TM_REG_MAX_ID 1734static struct reg_band reg_backup_list[TM_REG_MAX_ID];35 36 37static int38mt7915_tm_set_tx_power(struct mt7915_phy *phy)39{40 struct mt7915_dev *dev = phy->dev;41 struct mt76_phy *mphy = phy->mt76;42 struct cfg80211_chan_def *chandef = &mphy->chandef;43 int freq = chandef->center_freq1;44 int ret;45 struct {46 u8 format_id;47 u8 band_idx;48 s8 tx_power;49 u8 ant_idx; /* Only 0 is valid */50 u8 center_chan;51 u8 rsv[3];52 } __packed req = {53 .format_id = 0xf,54 .band_idx = phy->mt76->band_idx,55 .center_chan = ieee80211_frequency_to_channel(freq),56 };57 u8 *tx_power = NULL;58 59 if (phy->mt76->test.state != MT76_TM_STATE_OFF)60 tx_power = phy->mt76->test.tx_power;61 62 /* Tx power of the other antennas are the same as antenna 0 */63 if (tx_power && tx_power[0])64 req.tx_power = tx_power[0];65 66 ret = mt76_mcu_send_msg(&dev->mt76,67 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),68 &req, sizeof(req), false);69 70 return ret;71}72 73static int74mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val)75{76 struct mt7915_dev *dev = phy->dev;77 struct mt7915_tm_cmd req = {78 .testmode_en = en,79 .param_idx = MCU_ATE_SET_FREQ_OFFSET,80 .param.freq.band = phy->mt76->band_idx,81 .param.freq.freq_offset = cpu_to_le32(val),82 };83 84 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,85 sizeof(req), false);86}87 88static int89mt7915_tm_mode_ctrl(struct mt7915_dev *dev, bool enable)90{91 struct {92 u8 format_id;93 bool enable;94 u8 rsv[2];95 } __packed req = {96 .format_id = 0x6,97 .enable = enable,98 };99 100 return mt76_mcu_send_msg(&dev->mt76,101 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),102 &req, sizeof(req), false);103}104 105static int106mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en)107{108 struct mt7915_dev *dev = phy->dev;109 struct mt7915_tm_cmd req = {110 .testmode_en = 1,111 .param_idx = MCU_ATE_SET_TRX,112 .param.trx.type = type,113 .param.trx.enable = en,114 .param.trx.band = phy->mt76->band_idx,115 };116 117 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,118 sizeof(req), false);119}120 121static int122mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)123{124 struct mt7915_dev *dev = phy->dev;125 struct mt7915_tm_cmd req = {126 .testmode_en = 1,127 .param_idx = MCU_ATE_CLEAN_TXQUEUE,128 .param.clean.wcid = wcid,129 .param.clean.band = phy->mt76->band_idx,130 };131 132 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,133 sizeof(req), false);134}135 136static int137mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs)138{139 struct mt7915_dev *dev = phy->dev;140 struct mt7915_tm_cmd req = {141 .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF),142 .param_idx = MCU_ATE_SET_SLOT_TIME,143 .param.slot.slot_time = slot_time,144 .param.slot.sifs = sifs,145 .param.slot.rifs = 2,146 .param.slot.eifs = cpu_to_le16(60),147 .param.slot.band = phy->mt76->band_idx,148 };149 150 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,151 sizeof(req), false);152}153 154static int155mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu)156{157 struct mt7915_dev *dev = phy->dev;158 u32 op_mode;159 160 if (!enable)161 op_mode = TAM_ARB_OP_MODE_NORMAL;162 else if (mu)163 op_mode = TAM_ARB_OP_MODE_TEST;164 else165 op_mode = TAM_ARB_OP_MODE_FORCE_SU;166 167 return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode);168}169 170static int171mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,172 u16 cw_max, u16 txop)173{174 struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv;175 struct mt7915_mcu_tx req = { .total = 1 };176 struct edca *e = &req.edca[0];177 178 e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS;179 e->set = WMM_PARAM_SET;180 181 e->aifs = aifs;182 e->cw_min = cw_min;183 e->cw_max = cpu_to_le16(cw_max);184 e->txop = cpu_to_le16(txop);185 186 return mt7915_mcu_update_edca(phy->dev, &req);187}188 189static int190mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode)191{192#define TM_DEFAULT_SIFS 10193#define TM_MAX_SIFS 127194#define TM_MAX_AIFSN 0xf195#define TM_MIN_AIFSN 0x1196#define BBP_PROC_TIME 1500197 struct mt7915_dev *dev = phy->dev;198 u8 sig_ext = (mode == MT76_TM_TX_MODE_CCK) ? 0 : 6;199 u8 slot_time = 9, sifs = TM_DEFAULT_SIFS;200 u8 aifsn = TM_MIN_AIFSN;201 u8 band = phy->mt76->band_idx;202 u32 i2t_time, tr2t_time, txv_time;203 u16 cw = 0;204 205 if (ipg < sig_ext + slot_time + sifs)206 ipg = 0;207 208 if (!ipg)209 goto done;210 211 ipg -= sig_ext;212 213 if (ipg <= (TM_MAX_SIFS + slot_time)) {214 sifs = ipg - slot_time;215 } else {216 u32 val = (ipg + slot_time) / slot_time;217 218 while (val >>= 1)219 cw++;220 221 if (cw > 16)222 cw = 16;223 224 ipg -= ((1 << cw) - 1) * slot_time;225 226 aifsn = ipg / slot_time;227 if (aifsn > TM_MAX_AIFSN)228 aifsn = TM_MAX_AIFSN;229 230 ipg -= aifsn * slot_time;231 232 if (ipg > TM_DEFAULT_SIFS)233 sifs = min_t(u32, ipg, TM_MAX_SIFS);234 }235done:236 txv_time = mt76_get_field(dev, MT_TMAC_ATCR(band),237 MT_TMAC_ATCR_TXV_TOUT);238 txv_time *= 50; /* normal clock time */239 240 i2t_time = (slot_time * 1000 - txv_time - BBP_PROC_TIME) / 50;241 tr2t_time = (sifs * 1000 - txv_time - BBP_PROC_TIME) / 50;242 243 mt76_set(dev, MT_TMAC_TRCR0(band),244 FIELD_PREP(MT_TMAC_TRCR0_TR2T_CHK, tr2t_time) |245 FIELD_PREP(MT_TMAC_TRCR0_I2T_CHK, i2t_time));246 247 mt7915_tm_set_slot_time(phy, slot_time, sifs);248 249 return mt7915_tm_set_wmm_qid(phy,250 mt76_connac_lmac_mapping(IEEE80211_AC_BE),251 aifsn, cw, cw, 0);252}253 254static int255mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time)256{257 struct mt76_phy *mphy = phy->mt76;258 struct mt76_testmode_data *td = &mphy->test;259 struct ieee80211_supported_band *sband;260 struct rate_info rate = {};261 u16 flags = 0, tx_len;262 u32 bitrate;263 int ret;264 265 if (!tx_time)266 return 0;267 268 rate.mcs = td->tx_rate_idx;269 rate.nss = td->tx_rate_nss;270 271 switch (td->tx_rate_mode) {272 case MT76_TM_TX_MODE_CCK:273 case MT76_TM_TX_MODE_OFDM:274 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)275 sband = &mphy->sband_5g.sband;276 else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ)277 sband = &mphy->sband_6g.sband;278 else279 sband = &mphy->sband_2g.sband;280 281 rate.legacy = sband->bitrates[rate.mcs].bitrate;282 break;283 case MT76_TM_TX_MODE_HT:284 rate.mcs += rate.nss * 8;285 flags |= RATE_INFO_FLAGS_MCS;286 287 if (td->tx_rate_sgi)288 flags |= RATE_INFO_FLAGS_SHORT_GI;289 break;290 case MT76_TM_TX_MODE_VHT:291 flags |= RATE_INFO_FLAGS_VHT_MCS;292 293 if (td->tx_rate_sgi)294 flags |= RATE_INFO_FLAGS_SHORT_GI;295 break;296 case MT76_TM_TX_MODE_HE_SU:297 case MT76_TM_TX_MODE_HE_EXT_SU:298 case MT76_TM_TX_MODE_HE_TB:299 case MT76_TM_TX_MODE_HE_MU:300 rate.he_gi = td->tx_rate_sgi;301 flags |= RATE_INFO_FLAGS_HE_MCS;302 break;303 default:304 break;305 }306 rate.flags = flags;307 308 switch (mphy->chandef.width) {309 case NL80211_CHAN_WIDTH_160:310 case NL80211_CHAN_WIDTH_80P80:311 rate.bw = RATE_INFO_BW_160;312 break;313 case NL80211_CHAN_WIDTH_80:314 rate.bw = RATE_INFO_BW_80;315 break;316 case NL80211_CHAN_WIDTH_40:317 rate.bw = RATE_INFO_BW_40;318 break;319 default:320 rate.bw = RATE_INFO_BW_20;321 break;322 }323 324 bitrate = cfg80211_calculate_bitrate(&rate);325 tx_len = bitrate * tx_time / 10 / 8;326 327 ret = mt76_testmode_alloc_skb(phy->mt76, tx_len);328 if (ret)329 return ret;330 331 return 0;332}333 334static void335mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)336{337 int n_regs = ARRAY_SIZE(reg_backup_list);338 struct mt7915_dev *dev = phy->dev;339 u32 *b = phy->test.reg_backup;340 u8 band = phy->mt76->band_idx;341 int i;342 343 REG_BAND_IDX(reg_backup_list[0], AGG_PCR0, 0);344 REG_BAND_IDX(reg_backup_list[1], AGG_PCR0, 1);345 REG_BAND_IDX(reg_backup_list[2], AGG_AWSCR0, 0);346 REG_BAND_IDX(reg_backup_list[3], AGG_AWSCR0, 1);347 REG_BAND_IDX(reg_backup_list[4], AGG_AWSCR0, 2);348 REG_BAND_IDX(reg_backup_list[5], AGG_AWSCR0, 3);349 REG_BAND(reg_backup_list[6], AGG_MRCR);350 REG_BAND(reg_backup_list[7], TMAC_TFCR0);351 REG_BAND(reg_backup_list[8], TMAC_TCR0);352 REG_BAND(reg_backup_list[9], AGG_ATCR1);353 REG_BAND(reg_backup_list[10], AGG_ATCR3);354 REG_BAND(reg_backup_list[11], TMAC_TRCR0);355 REG_BAND(reg_backup_list[12], TMAC_ICR0);356 REG_BAND_IDX(reg_backup_list[13], ARB_DRNGR0, 0);357 REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 1);358 REG_BAND(reg_backup_list[15], WF_RFCR);359 REG_BAND(reg_backup_list[16], WF_RFCR1);360 361 if (phy->mt76->test.state == MT76_TM_STATE_OFF) {362 for (i = 0; i < n_regs; i++)363 mt76_wr(dev, reg_backup_list[i].band[band], b[i]);364 return;365 }366 367 if (!b) {368 b = devm_kzalloc(dev->mt76.dev, 4 * n_regs, GFP_KERNEL);369 if (!b)370 return;371 372 phy->test.reg_backup = b;373 for (i = 0; i < n_regs; i++)374 b[i] = mt76_rr(dev, reg_backup_list[i].band[band]);375 }376 377 mt76_clear(dev, MT_AGG_PCR0(band, 0), MT_AGG_PCR0_MM_PROT |378 MT_AGG_PCR0_GF_PROT | MT_AGG_PCR0_ERP_PROT |379 MT_AGG_PCR0_VHT_PROT | MT_AGG_PCR0_BW20_PROT |380 MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT);381 mt76_set(dev, MT_AGG_PCR0(band, 0), MT_AGG_PCR0_PTA_WIN_DIS);382 383 mt76_wr(dev, MT_AGG_PCR0(band, 1), MT_AGG_PCR1_RTS0_NUM_THRES |384 MT_AGG_PCR1_RTS0_LEN_THRES);385 386 mt76_clear(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_BAR_CNT_LIMIT |387 MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT |388 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT);389 390 mt76_rmw(dev, MT_AGG_MRCR(band), MT_AGG_MRCR_RTS_FAIL_LIMIT |391 MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT,392 FIELD_PREP(MT_AGG_MRCR_RTS_FAIL_LIMIT, 1) |393 FIELD_PREP(MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 1));394 395 mt76_wr(dev, MT_TMAC_TFCR0(band), 0);396 mt76_clear(dev, MT_TMAC_TCR0(band), MT_TMAC_TCR0_TBTT_STOP_CTRL);397 398 /* config rx filter for testmode rx */399 mt76_wr(dev, MT_WF_RFCR(band), 0xcf70a);400 mt76_wr(dev, MT_WF_RFCR1(band), 0);401}402 403static void404mt7915_tm_init(struct mt7915_phy *phy, bool en)405{406 struct mt7915_dev *dev = phy->dev;407 int state;408 409 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))410 return;411 412 mt7915_mcu_set_sku_en(phy, !en);413 414 mt7915_tm_mode_ctrl(dev, en);415 mt7915_tm_reg_backup_restore(phy);416 mt7915_tm_set_trx(phy, TM_MAC_TXRX, !en);417 418 mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en);419 state = en ? CONN_STATE_PORT_SECURE : CONN_STATE_DISCONNECT;420 mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, state, true);421 422 if (!en)423 mt7915_tm_set_tam_arb(phy, en, 0);424}425 426static void427mt7915_tm_update_channel(struct mt7915_phy *phy)428{429 mutex_unlock(&phy->dev->mt76.mutex);430 mt76_update_channel(phy->mt76);431 mutex_lock(&phy->dev->mt76.mutex);432 433 mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));434}435 436static void437mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)438{439 struct mt76_testmode_data *td = &phy->mt76->test;440 struct mt7915_dev *dev = phy->dev;441 struct ieee80211_tx_info *info;442 u8 duty_cycle = td->tx_duty_cycle;443 u32 tx_time = td->tx_time;444 u32 ipg = td->tx_ipg;445 446 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);447 mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx);448 449 if (en) {450 mt7915_tm_update_channel(phy);451 452 if (td->tx_spe_idx)453 phy->test.spe_idx = td->tx_spe_idx;454 else455 phy->test.spe_idx = mt76_connac_spe_idx(td->tx_antenna_mask);456 }457 458 mt7915_tm_set_tam_arb(phy, en,459 td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);460 461 /* if all three params are set, duty_cycle will be ignored */462 if (duty_cycle && tx_time && !ipg) {463 ipg = tx_time * 100 / duty_cycle - tx_time;464 } else if (duty_cycle && !tx_time && ipg) {465 if (duty_cycle < 100)466 tx_time = duty_cycle * ipg / (100 - duty_cycle);467 }468 469 mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);470 mt7915_tm_set_tx_len(phy, tx_time);471 472 if (ipg)473 td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;474 475 if (!en || !td->tx_skb)476 return;477 478 info = IEEE80211_SKB_CB(td->tx_skb);479 info->control.vif = phy->monitor_vif;480 481 mt7915_tm_set_trx(phy, TM_MAC_TX, en);482}483 484static void485mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)486{487 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);488 489 if (en) {490 struct mt7915_dev *dev = phy->dev;491 492 mt7915_tm_update_channel(phy);493 494 /* read-clear */495 mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx));496 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);497 }498}499 500static int501mt7915_tm_rf_switch_mode(struct mt7915_dev *dev, u32 oper)502{503 struct mt7915_tm_rf_test req = {504 .op.op_mode = cpu_to_le32(oper),505 };506 507 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,508 sizeof(req), true);509}510 511static int512mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en)513{514#define TX_CONT_START 0x05515#define TX_CONT_STOP 0x06516 struct mt7915_dev *dev = phy->dev;517 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;518 int freq1 = ieee80211_frequency_to_channel(chandef->center_freq1);519 struct mt76_testmode_data *td = &phy->mt76->test;520 u32 func_idx = en ? TX_CONT_START : TX_CONT_STOP;521 u8 rate_idx = td->tx_rate_idx, mode;522 u8 band = phy->mt76->band_idx;523 u16 rateval;524 struct mt7915_tm_rf_test req = {525 .action = 1,526 .icap_len = 120,527 .op.rf.func_idx = cpu_to_le32(func_idx),528 };529 struct tm_tx_cont *tx_cont = &req.op.rf.param.tx_cont;530 531 tx_cont->control_ch = chandef->chan->hw_value;532 tx_cont->center_ch = freq1;533 tx_cont->tx_ant = td->tx_antenna_mask;534 tx_cont->band = band;535 536 switch (chandef->width) {537 case NL80211_CHAN_WIDTH_40:538 tx_cont->bw = CMD_CBW_40MHZ;539 break;540 case NL80211_CHAN_WIDTH_80:541 tx_cont->bw = CMD_CBW_80MHZ;542 break;543 case NL80211_CHAN_WIDTH_80P80:544 tx_cont->bw = CMD_CBW_8080MHZ;545 break;546 case NL80211_CHAN_WIDTH_160:547 tx_cont->bw = CMD_CBW_160MHZ;548 break;549 case NL80211_CHAN_WIDTH_5:550 tx_cont->bw = CMD_CBW_5MHZ;551 break;552 case NL80211_CHAN_WIDTH_10:553 tx_cont->bw = CMD_CBW_10MHZ;554 break;555 case NL80211_CHAN_WIDTH_20:556 tx_cont->bw = CMD_CBW_20MHZ;557 break;558 case NL80211_CHAN_WIDTH_20_NOHT:559 tx_cont->bw = CMD_CBW_20MHZ;560 break;561 default:562 return -EINVAL;563 }564 565 if (!en) {566 req.op.rf.param.func_data = cpu_to_le32(band);567 goto out;568 }569 570 if (td->tx_rate_mode <= MT76_TM_TX_MODE_OFDM) {571 struct ieee80211_supported_band *sband;572 u8 idx = rate_idx;573 574 if (chandef->chan->band == NL80211_BAND_5GHZ)575 sband = &phy->mt76->sband_5g.sband;576 else if (chandef->chan->band == NL80211_BAND_6GHZ)577 sband = &phy->mt76->sband_6g.sband;578 else579 sband = &phy->mt76->sband_2g.sband;580 581 if (td->tx_rate_mode == MT76_TM_TX_MODE_OFDM)582 idx += 4;583 rate_idx = sband->bitrates[idx].hw_value & 0xff;584 }585 586 switch (td->tx_rate_mode) {587 case MT76_TM_TX_MODE_CCK:588 mode = MT_PHY_TYPE_CCK;589 break;590 case MT76_TM_TX_MODE_OFDM:591 mode = MT_PHY_TYPE_OFDM;592 break;593 case MT76_TM_TX_MODE_HT:594 mode = MT_PHY_TYPE_HT;595 break;596 case MT76_TM_TX_MODE_VHT:597 mode = MT_PHY_TYPE_VHT;598 break;599 case MT76_TM_TX_MODE_HE_SU:600 mode = MT_PHY_TYPE_HE_SU;601 break;602 case MT76_TM_TX_MODE_HE_EXT_SU:603 mode = MT_PHY_TYPE_HE_EXT_SU;604 break;605 case MT76_TM_TX_MODE_HE_TB:606 mode = MT_PHY_TYPE_HE_TB;607 break;608 case MT76_TM_TX_MODE_HE_MU:609 mode = MT_PHY_TYPE_HE_MU;610 break;611 default:612 return -EINVAL;613 }614 615 rateval = mode << 6 | rate_idx;616 tx_cont->rateval = cpu_to_le16(rateval);617 618out:619 if (!en) {620 int ret;621 622 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,623 sizeof(req), true);624 if (ret)625 return ret;626 627 return mt7915_tm_rf_switch_mode(dev, RF_OPER_NORMAL);628 }629 630 mt7915_tm_rf_switch_mode(dev, RF_OPER_RF_TEST);631 mt7915_tm_update_channel(phy);632 633 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,634 sizeof(req), true);635}636 637static void638mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed)639{640 struct mt76_testmode_data *td = &phy->mt76->test;641 bool en = phy->mt76->test.state != MT76_TM_STATE_OFF;642 643 if (changed & BIT(TM_CHANGED_FREQ_OFFSET))644 mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0);645 if (changed & BIT(TM_CHANGED_TXPOWER))646 mt7915_tm_set_tx_power(phy);647}648 649static int650mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state)651{652 struct mt76_testmode_data *td = &mphy->test;653 struct mt7915_phy *phy = mphy->priv;654 enum mt76_testmode_state prev_state = td->state;655 656 mphy->test.state = state;657 658 if (prev_state == MT76_TM_STATE_TX_FRAMES ||659 state == MT76_TM_STATE_TX_FRAMES)660 mt7915_tm_set_tx_frames(phy, state == MT76_TM_STATE_TX_FRAMES);661 else if (prev_state == MT76_TM_STATE_RX_FRAMES ||662 state == MT76_TM_STATE_RX_FRAMES)663 mt7915_tm_set_rx_frames(phy, state == MT76_TM_STATE_RX_FRAMES);664 else if (prev_state == MT76_TM_STATE_TX_CONT ||665 state == MT76_TM_STATE_TX_CONT)666 mt7915_tm_set_tx_cont(phy, state == MT76_TM_STATE_TX_CONT);667 else if (prev_state == MT76_TM_STATE_OFF ||668 state == MT76_TM_STATE_OFF)669 mt7915_tm_init(phy, !(state == MT76_TM_STATE_OFF));670 671 if ((state == MT76_TM_STATE_IDLE &&672 prev_state == MT76_TM_STATE_OFF) ||673 (state == MT76_TM_STATE_OFF &&674 prev_state == MT76_TM_STATE_IDLE)) {675 u32 changed = 0;676 int i;677 678 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {679 u16 cur = tm_change_map[i];680 681 if (td->param_set[cur / 32] & BIT(cur % 32))682 changed |= BIT(i);683 }684 685 mt7915_tm_update_params(phy, changed);686 }687 688 return 0;689}690 691static int692mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb,693 enum mt76_testmode_state new_state)694{695 struct mt76_testmode_data *td = &mphy->test;696 struct mt7915_phy *phy = mphy->priv;697 struct mt7915_dev *dev = phy->dev;698 u32 chainmask = mphy->chainmask, changed = 0;699 bool ext_phy = phy != &dev->phy;700 int i;701 702 BUILD_BUG_ON(NUM_TM_CHANGED >= 32);703 704 if (new_state == MT76_TM_STATE_OFF ||705 td->state == MT76_TM_STATE_OFF)706 return 0;707 708 chainmask = ext_phy ? chainmask >> dev->chainshift : chainmask;709 if (td->tx_antenna_mask > chainmask)710 return -EINVAL;711 712 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {713 if (tb[tm_change_map[i]])714 changed |= BIT(i);715 }716 717 mt7915_tm_update_params(phy, changed);718 719 return 0;720}721 722static int723mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)724{725 struct mt7915_phy *phy = mphy->priv;726 struct mt7915_dev *dev = phy->dev;727 enum mt76_rxq_id q;728 void *rx, *rssi;729 u16 fcs_err;730 int i;731 u32 cnt;732 733 rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);734 if (!rx)735 return -ENOMEM;736 737 if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, phy->test.last_freq_offset))738 return -ENOMEM;739 740 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI);741 if (!rssi)742 return -ENOMEM;743 744 for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++)745 if (nla_put_u8(msg, i, phy->test.last_rcpi[i]))746 return -ENOMEM;747 748 nla_nest_end(msg, rssi);749 750 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI);751 if (!rssi)752 return -ENOMEM;753 754 for (i = 0; i < ARRAY_SIZE(phy->test.last_ib_rssi); i++)755 if (nla_put_s8(msg, i, phy->test.last_ib_rssi[i]))756 return -ENOMEM;757 758 nla_nest_end(msg, rssi);759 760 rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI);761 if (!rssi)762 return -ENOMEM;763 764 for (i = 0; i < ARRAY_SIZE(phy->test.last_wb_rssi); i++)765 if (nla_put_s8(msg, i, phy->test.last_wb_rssi[i]))766 return -ENOMEM;767 768 nla_nest_end(msg, rssi);769 770 if (nla_put_u8(msg, MT76_TM_RX_ATTR_SNR, phy->test.last_snr))771 return -ENOMEM;772 773 nla_nest_end(msg, rx);774 775 cnt = mt76_rr(dev, MT_MIB_SDR3(phy->mt76->band_idx));776 fcs_err = is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :777 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);778 779 q = phy->mt76->band_idx ? MT_RXQ_BAND1 : MT_RXQ_MAIN;780 mphy->test.rx_stats.packets[q] += fcs_err;781 mphy->test.rx_stats.fcs_error[q] += fcs_err;782 783 return 0;784}785 786const struct mt76_testmode_ops mt7915_testmode_ops = {787 .set_state = mt7915_tm_set_state,788 .set_params = mt7915_tm_set_params,789 .dump_stats = mt7915_tm_dump_stats,790};791