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1// SPDX-License-Identifier: ISC2/*3 * Copyright (C) 2022 MediaTek Inc.4 */5 6#include <linux/relay.h>7#include "mt7996.h"8#include "eeprom.h"9#include "mcu.h"10#include "mac.h"11 12#define FW_BIN_LOG_MAGIC 0x44d9c99a13 14/** global debugfs **/15 16struct hw_queue_map {17 const char *name;18 u8 index;19 u8 pid;20 u8 qid;21};22 23static int24mt7996_implicit_txbf_set(void *data, u64 val)25{26 struct mt7996_dev *dev = data;27 28 /* The existing connected stations shall reconnect to apply29 * new implicit txbf configuration.30 */31 dev->ibf = !!val;32 33 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE);34}35 36static int37mt7996_implicit_txbf_get(void *data, u64 *val)38{39 struct mt7996_dev *dev = data;40 41 *val = dev->ibf;42 43 return 0;44}45 46DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7996_implicit_txbf_get,47 mt7996_implicit_txbf_set, "%lld\n");48 49/* test knob of system error recovery */50static ssize_t51mt7996_sys_recovery_set(struct file *file, const char __user *user_buf,52 size_t count, loff_t *ppos)53{54 struct mt7996_phy *phy = file->private_data;55 struct mt7996_dev *dev = phy->dev;56 bool band = phy->mt76->band_idx;57 char buf[16];58 int ret = 0;59 u16 val;60 61 if (count >= sizeof(buf))62 return -EINVAL;63 64 if (copy_from_user(buf, user_buf, count))65 return -EFAULT;66 67 if (count && buf[count - 1] == '\n')68 buf[count - 1] = '\0';69 else70 buf[count] = '\0';71 72 if (kstrtou16(buf, 0, &val))73 return -EINVAL;74 75 switch (val) {76 /*77 * 0: grab firmware current SER state.78 * 1: trigger & enable system error L1 recovery.79 * 2: trigger & enable system error L2 recovery.80 * 3: trigger & enable system error L3 rx abort.81 * 4: trigger & enable system error L3 tx abort82 * 5: trigger & enable system error L3 tx disable.83 * 6: trigger & enable system error L3 bf recovery.84 * 7: trigger & enable system error L4 mdp recovery.85 * 8: trigger & enable system error full recovery.86 * 9: trigger firmware crash.87 */88 case UNI_CMD_SER_QUERY:89 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_QUERY, 0, band);90 break;91 case UNI_CMD_SER_SET_RECOVER_L1:92 case UNI_CMD_SER_SET_RECOVER_L2:93 case UNI_CMD_SER_SET_RECOVER_L3_RX_ABORT:94 case UNI_CMD_SER_SET_RECOVER_L3_TX_ABORT:95 case UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE:96 case UNI_CMD_SER_SET_RECOVER_L3_BF:97 case UNI_CMD_SER_SET_RECOVER_L4_MDP:98 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_SET, BIT(val), band);99 if (ret)100 return ret;101 102 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, val, band);103 break;104 105 /* enable full chip reset */106 case UNI_CMD_SER_SET_RECOVER_FULL:107 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK);108 dev->recovery.state |= MT_MCU_CMD_WDT_MASK;109 mt7996_reset(dev);110 break;111 112 /* WARNING: trigger firmware crash */113 case UNI_CMD_SER_SET_SYSTEM_ASSERT:114 ret = mt7996_mcu_trigger_assert(dev);115 if (ret)116 return ret;117 break;118 default:119 break;120 }121 122 return ret ? ret : count;123}124 125static ssize_t126mt7996_sys_recovery_get(struct file *file, char __user *user_buf,127 size_t count, loff_t *ppos)128{129 struct mt7996_phy *phy = file->private_data;130 struct mt7996_dev *dev = phy->dev;131 char *buff;132 int desc = 0;133 ssize_t ret;134 static const size_t bufsz = 1024;135 136 buff = kmalloc(bufsz, GFP_KERNEL);137 if (!buff)138 return -ENOMEM;139 140 /* HELP */141 desc += scnprintf(buff + desc, bufsz - desc,142 "Please echo the correct value ...\n");143 desc += scnprintf(buff + desc, bufsz - desc,144 "0: grab firmware transient SER state\n");145 desc += scnprintf(buff + desc, bufsz - desc,146 "1: trigger system error L1 recovery\n");147 desc += scnprintf(buff + desc, bufsz - desc,148 "2: trigger system error L2 recovery\n");149 desc += scnprintf(buff + desc, bufsz - desc,150 "3: trigger system error L3 rx abort\n");151 desc += scnprintf(buff + desc, bufsz - desc,152 "4: trigger system error L3 tx abort\n");153 desc += scnprintf(buff + desc, bufsz - desc,154 "5: trigger system error L3 tx disable\n");155 desc += scnprintf(buff + desc, bufsz - desc,156 "6: trigger system error L3 bf recovery\n");157 desc += scnprintf(buff + desc, bufsz - desc,158 "7: trigger system error L4 mdp recovery\n");159 desc += scnprintf(buff + desc, bufsz - desc,160 "8: trigger system error full recovery\n");161 desc += scnprintf(buff + desc, bufsz - desc,162 "9: trigger firmware crash\n");163 164 /* SER statistics */165 desc += scnprintf(buff + desc, bufsz - desc,166 "\nlet's dump firmware SER statistics...\n");167 desc += scnprintf(buff + desc, bufsz - desc,168 "::E R , SER_STATUS = 0x%08x\n",169 mt76_rr(dev, MT_SWDEF_SER_STATS));170 desc += scnprintf(buff + desc, bufsz - desc,171 "::E R , SER_PLE_ERR = 0x%08x\n",172 mt76_rr(dev, MT_SWDEF_PLE_STATS));173 desc += scnprintf(buff + desc, bufsz - desc,174 "::E R , SER_PLE_ERR_1 = 0x%08x\n",175 mt76_rr(dev, MT_SWDEF_PLE1_STATS));176 desc += scnprintf(buff + desc, bufsz - desc,177 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n",178 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS));179 desc += scnprintf(buff + desc, bufsz - desc,180 "::E R , SER_PSE_ERR = 0x%08x\n",181 mt76_rr(dev, MT_SWDEF_PSE_STATS));182 desc += scnprintf(buff + desc, bufsz - desc,183 "::E R , SER_PSE_ERR_1 = 0x%08x\n",184 mt76_rr(dev, MT_SWDEF_PSE1_STATS));185 desc += scnprintf(buff + desc, bufsz - desc,186 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n",187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS));188 desc += scnprintf(buff + desc, bufsz - desc,189 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n",190 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS));191 desc += scnprintf(buff + desc, bufsz - desc,192 "::E R , SER_LMAC_WISR6_B2 = 0x%08x\n",193 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN2_STATS));194 desc += scnprintf(buff + desc, bufsz - desc,195 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n",196 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS));197 desc += scnprintf(buff + desc, bufsz - desc,198 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n",199 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS));200 desc += scnprintf(buff + desc, bufsz - desc,201 "::E R , SER_LMAC_WISR7_B2 = 0x%08x\n",202 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN2_STATS));203 desc += scnprintf(buff + desc, bufsz - desc,204 "\nSYS_RESET_COUNT: WM %d, WA %d\n",205 dev->recovery.wm_reset_count,206 dev->recovery.wa_reset_count);207 208 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc);209 kfree(buff);210 return ret;211}212 213static const struct file_operations mt7996_sys_recovery_ops = {214 .write = mt7996_sys_recovery_set,215 .read = mt7996_sys_recovery_get,216 .open = simple_open,217 .llseek = default_llseek,218};219 220static int221mt7996_radar_trigger(void *data, u64 val)222{223 struct mt7996_dev *dev = data;224 225 if (val > MT_RX_SEL2)226 return -EINVAL;227 228 if (val == MT_RX_SEL2 && !dev->rdd2_phy) {229 dev_err(dev->mt76.dev, "Background radar is not enabled\n");230 return -EINVAL;231 }232 233 return mt7996_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE,234 val, 0, 0);235}236 237DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL,238 mt7996_radar_trigger, "%lld\n");239 240static int241mt7996_rdd_monitor(struct seq_file *s, void *data)242{243 struct mt7996_dev *dev = dev_get_drvdata(s->private);244 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef;245 const char *bw;246 int ret = 0;247 248 mutex_lock(&dev->mt76.mutex);249 250 if (!cfg80211_chandef_valid(chandef)) {251 ret = -EINVAL;252 goto out;253 }254 255 if (!dev->rdd2_phy) {256 seq_puts(s, "not running\n");257 goto out;258 }259 260 switch (chandef->width) {261 case NL80211_CHAN_WIDTH_40:262 bw = "40";263 break;264 case NL80211_CHAN_WIDTH_80:265 bw = "80";266 break;267 case NL80211_CHAN_WIDTH_160:268 bw = "160";269 break;270 case NL80211_CHAN_WIDTH_80P80:271 bw = "80P80";272 break;273 default:274 bw = "20";275 break;276 }277 278 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n",279 chandef->chan->hw_value, chandef->chan->center_freq,280 bw, chandef->center_freq1);281out:282 mutex_unlock(&dev->mt76.mutex);283 284 return ret;285}286 287static int288mt7996_fw_debug_wm_set(void *data, u64 val)289{290 struct mt7996_dev *dev = data;291 enum {292 DEBUG_TXCMD = 62,293 DEBUG_CMD_RPT_TX,294 DEBUG_CMD_RPT_TRIG,295 DEBUG_SPL,296 DEBUG_RPT_RX,297 DEBUG_RPT_RA = 68,298 } debug;299 bool tx, rx, en;300 int ret;301 302 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;303 304 if (dev->fw_debug_bin)305 val = MCU_FW_LOG_RELAY;306 else307 val = dev->fw_debug_wm;308 309 tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1));310 rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2));311 en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0));312 313 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val);314 if (ret)315 return ret;316 317 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) {318 if (debug == 67)319 continue;320 321 if (debug == DEBUG_RPT_RX)322 val = en && rx;323 else324 val = en && tx;325 326 ret = mt7996_mcu_fw_dbg_ctrl(dev, debug, val);327 if (ret)328 return ret;329 }330 331 return 0;332}333 334static int335mt7996_fw_debug_wm_get(void *data, u64 *val)336{337 struct mt7996_dev *dev = data;338 339 *val = dev->fw_debug_wm;340 341 return 0;342}343 344DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7996_fw_debug_wm_get,345 mt7996_fw_debug_wm_set, "%lld\n");346 347static int348mt7996_fw_debug_wa_set(void *data, u64 val)349{350 struct mt7996_dev *dev = data;351 int ret;352 353 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0;354 355 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa);356 if (ret)357 return ret;358 359 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX,360 !!dev->fw_debug_wa, 0);361}362 363static int364mt7996_fw_debug_wa_get(void *data, u64 *val)365{366 struct mt7996_dev *dev = data;367 368 *val = dev->fw_debug_wa;369 370 return 0;371}372 373DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7996_fw_debug_wa_get,374 mt7996_fw_debug_wa_set, "%lld\n");375 376static struct dentry *377create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode,378 struct rchan_buf *buf, int *is_global)379{380 struct dentry *f;381 382 f = debugfs_create_file("fwlog_data", mode, parent, buf,383 &relay_file_operations);384 if (IS_ERR(f))385 return NULL;386 387 *is_global = 1;388 389 return f;390}391 392static int393remove_buf_file_cb(struct dentry *f)394{395 debugfs_remove(f);396 397 return 0;398}399 400static int401mt7996_fw_debug_bin_set(void *data, u64 val)402{403 static struct rchan_callbacks relay_cb = {404 .create_buf_file = create_buf_file_cb,405 .remove_buf_file = remove_buf_file_cb,406 };407 struct mt7996_dev *dev = data;408 409 if (!dev->relay_fwlog)410 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,411 1500, 512, &relay_cb, NULL);412 if (!dev->relay_fwlog)413 return -ENOMEM;414 415 dev->fw_debug_bin = val;416 417 relay_reset(dev->relay_fwlog);418 419 return mt7996_fw_debug_wm_set(dev, dev->fw_debug_wm);420}421 422static int423mt7996_fw_debug_bin_get(void *data, u64 *val)424{425 struct mt7996_dev *dev = data;426 427 *val = dev->fw_debug_bin;428 429 return 0;430}431 432DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7996_fw_debug_bin_get,433 mt7996_fw_debug_bin_set, "%lld\n");434 435static int436mt7996_fw_util_wa_show(struct seq_file *file, void *data)437{438 struct mt7996_dev *dev = file->private;439 440 if (dev->fw_debug_wa)441 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),442 MCU_WA_PARAM_CPU_UTIL, 0, 0);443 444 return 0;445}446 447DEFINE_SHOW_ATTRIBUTE(mt7996_fw_util_wa);448 449static void450mt7996_ampdu_stat_read_phy(struct mt7996_phy *phy, struct seq_file *file)451{452 struct mt7996_dev *dev = phy->dev;453 int bound[15], range[8], i;454 u8 band_idx = phy->mt76->band_idx;455 456 /* Tx ampdu stat */457 for (i = 0; i < ARRAY_SIZE(range); i++)458 range[i] = mt76_rr(dev, MT_MIB_ARNG(band_idx, i));459 460 for (i = 0; i < ARRAY_SIZE(bound); i++)461 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 2], i % 2) + 1;462 463 seq_printf(file, "\nPhy %s, Phy band %d\n",464 wiphy_name(phy->mt76->hw->wiphy), band_idx);465 466 seq_printf(file, "Length: %8d | ", bound[0]);467 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++)468 seq_printf(file, "%3d -%3d | ",469 bound[i] + 1, bound[i + 1]);470 471 seq_puts(file, "\nCount: ");472 for (i = 0; i < ARRAY_SIZE(bound); i++)473 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]);474 seq_puts(file, "\n");475 476 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt);477}478 479static void480mt7996_txbf_stat_read_phy(struct mt7996_phy *phy, struct seq_file *s)481{482 struct mt76_mib_stats *mib = &phy->mib;483 static const char * const bw[] = {484 "BW20", "BW40", "BW80", "BW160", "BW320"485 };486 487 /* Tx Beamformer monitor */488 seq_puts(s, "\nTx Beamformer applied PPDU counts: ");489 490 seq_printf(s, "iBF: %d, eBF: %d\n",491 mib->tx_bf_ibf_ppdu_cnt,492 mib->tx_bf_ebf_ppdu_cnt);493 494 /* Tx Beamformer Rx feedback monitor */495 seq_puts(s, "Tx Beamformer Rx feedback statistics: ");496 497 seq_printf(s, "All: %d, EHT: %d, HE: %d, VHT: %d, HT: %d, ",498 mib->tx_bf_rx_fb_all_cnt,499 mib->tx_bf_rx_fb_eht_cnt,500 mib->tx_bf_rx_fb_he_cnt,501 mib->tx_bf_rx_fb_vht_cnt,502 mib->tx_bf_rx_fb_ht_cnt);503 504 seq_printf(s, "%s, NC: %d, NR: %d\n",505 bw[mib->tx_bf_rx_fb_bw],506 mib->tx_bf_rx_fb_nc_cnt,507 mib->tx_bf_rx_fb_nr_cnt);508 509 /* Tx Beamformee Rx NDPA & Tx feedback report */510 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n",511 mib->tx_bf_fb_cpl_cnt);512 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n",513 mib->tx_bf_fb_trig_cnt);514 515 /* Tx SU & MU counters */516 seq_printf(s, "Tx multi-user Beamforming counts: %d\n",517 mib->tx_mu_bf_cnt);518 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt);519 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n",520 mib->tx_mu_acked_mpdu_cnt);521 seq_printf(s, "Tx single-user successful MPDU counts: %d\n",522 mib->tx_su_acked_mpdu_cnt);523 524 seq_puts(s, "\n");525}526 527static int528mt7996_tx_stats_show(struct seq_file *file, void *data)529{530 struct mt7996_phy *phy = file->private;531 struct mt7996_dev *dev = phy->dev;532 struct mt76_mib_stats *mib = &phy->mib;533 int i;534 u32 attempts, success, per;535 536 mutex_lock(&dev->mt76.mutex);537 538 mt7996_mac_update_stats(phy);539 mt7996_ampdu_stat_read_phy(phy, file);540 541 attempts = mib->tx_mpdu_attempts_cnt;542 success = mib->tx_mpdu_success_cnt;543 per = attempts ? 100 - success * 100 / attempts : 100;544 seq_printf(file, "Tx attempts: %8u (MPDUs)\n", attempts);545 seq_printf(file, "Tx success: %8u (MPDUs)\n", success);546 seq_printf(file, "Tx PER: %u%%\n", per);547 548 mt7996_txbf_stat_read_phy(phy, file);549 550 /* Tx amsdu info */551 seq_puts(file, "Tx MSDU statistics:\n");552 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {553 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ",554 i + 1, mib->tx_amsdu[i]);555 if (mib->tx_amsdu_cnt)556 seq_printf(file, "(%3d%%)\n",557 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt);558 else559 seq_puts(file, "\n");560 }561 562 mutex_unlock(&dev->mt76.mutex);563 564 return 0;565}566 567DEFINE_SHOW_ATTRIBUTE(mt7996_tx_stats);568 569static void570mt7996_hw_queue_read(struct seq_file *s, u32 size,571 const struct hw_queue_map *map)572{573 struct mt7996_phy *phy = s->private;574 struct mt7996_dev *dev = phy->dev;575 u32 i, val;576 577 val = mt76_rr(dev, MT_FL_Q_EMPTY);578 for (i = 0; i < size; i++) {579 u32 ctrl, head, tail, queued;580 581 if (val & BIT(map[i].index))582 continue;583 584 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24);585 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl);586 587 head = mt76_get_field(dev, MT_FL_Q2_CTRL,588 GENMASK(11, 0));589 tail = mt76_get_field(dev, MT_FL_Q2_CTRL,590 GENMASK(27, 16));591 queued = mt76_get_field(dev, MT_FL_Q3_CTRL,592 GENMASK(11, 0));593 594 seq_printf(s, "\t%s: ", map[i].name);595 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n",596 queued, head, tail);597 }598}599 600static void601mt7996_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)602{603 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv;604 struct mt7996_dev *dev = msta->vif->phy->dev;605 struct seq_file *s = data;606 u8 ac;607 608 for (ac = 0; ac < 4; ac++) {609 u32 qlen, ctrl, val;610 u32 idx = msta->wcid.idx >> 5;611 u8 offs = msta->wcid.idx & GENMASK(4, 0);612 613 ctrl = BIT(31) | BIT(11) | (ac << 24);614 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx));615 616 if (val & BIT(offs))617 continue;618 619 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);620 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL,621 GENMASK(11, 0));622 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",623 sta->addr, msta->wcid.idx,624 msta->vif->mt76.wmm_idx, ac, qlen);625 }626}627 628static int629mt7996_hw_queues_show(struct seq_file *file, void *data)630{631 struct mt7996_phy *phy = file->private;632 struct mt7996_dev *dev = phy->dev;633 static const struct hw_queue_map ple_queue_map[] = {634 { "CPU_Q0", 0, 1, MT_CTX0 },635 { "CPU_Q1", 1, 1, MT_CTX0 + 1 },636 { "CPU_Q2", 2, 1, MT_CTX0 + 2 },637 { "CPU_Q3", 3, 1, MT_CTX0 + 3 },638 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 },639 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 },640 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 },641 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 },642 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 },643 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 },644 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 },645 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 },646 };647 static const struct hw_queue_map pse_queue_map[] = {648 { "CPU Q0", 0, 1, MT_CTX0 },649 { "CPU Q1", 1, 1, MT_CTX0 + 1 },650 { "CPU Q2", 2, 1, MT_CTX0 + 2 },651 { "CPU Q3", 3, 1, MT_CTX0 + 3 },652 { "HIF_Q0", 8, 0, MT_HIF0 },653 { "HIF_Q1", 9, 0, MT_HIF0 + 1 },654 { "HIF_Q2", 10, 0, MT_HIF0 + 2 },655 { "HIF_Q3", 11, 0, MT_HIF0 + 3 },656 { "HIF_Q4", 12, 0, MT_HIF0 + 4 },657 { "HIF_Q5", 13, 0, MT_HIF0 + 5 },658 { "LMAC_Q", 16, 2, 0 },659 { "MDP_TXQ", 17, 2, 1 },660 { "MDP_RXQ", 18, 2, 2 },661 { "SEC_TXQ", 19, 2, 3 },662 { "SEC_RXQ", 20, 2, 4 },663 };664 u32 val, head, tail;665 666 /* ple queue */667 val = mt76_rr(dev, MT_PLE_FREEPG_CNT);668 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));669 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));670 seq_puts(file, "PLE page info:\n");671 seq_printf(file,672 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n",673 val, head, tail);674 675 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP);676 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));677 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));678 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n",679 val, head, tail);680 681 seq_puts(file, "PLE non-empty queue info:\n");682 mt7996_hw_queue_read(file, ARRAY_SIZE(ple_queue_map),683 &ple_queue_map[0]);684 685 /* iterate per-sta ple queue */686 ieee80211_iterate_stations_atomic(phy->mt76->hw,687 mt7996_sta_hw_queue_read, file);688 /* pse queue */689 seq_puts(file, "PSE non-empty queue info:\n");690 mt7996_hw_queue_read(file, ARRAY_SIZE(pse_queue_map),691 &pse_queue_map[0]);692 693 return 0;694}695 696DEFINE_SHOW_ATTRIBUTE(mt7996_hw_queues);697 698static int699mt7996_xmit_queues_show(struct seq_file *file, void *data)700{701 struct mt7996_phy *phy = file->private;702 struct mt7996_dev *dev = phy->dev;703 struct {704 struct mt76_queue *q;705 char *queue;706 } queue_map[] = {707 { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" },708 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" },709 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" },710 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" },711 };712 int i;713 714 seq_puts(file, " queue | hw-queued | head | tail |\n");715 for (i = 0; i < ARRAY_SIZE(queue_map); i++) {716 struct mt76_queue *q = queue_map[i].q;717 718 if (!q)719 continue;720 721 seq_printf(file, " %s | %9d | %9d | %9d |\n",722 queue_map[i].queue, q->queued, q->head,723 q->tail);724 }725 726 return 0;727}728 729DEFINE_SHOW_ATTRIBUTE(mt7996_xmit_queues);730 731static int732mt7996_twt_stats(struct seq_file *s, void *data)733{734 struct mt7996_dev *dev = dev_get_drvdata(s->private);735 struct mt7996_twt_flow *iter;736 737 rcu_read_lock();738 739 seq_puts(s, " wcid | id | flags | exp | mantissa");740 seq_puts(s, " | duration | tsf |\n");741 list_for_each_entry_rcu(iter, &dev->twt_list, list)742 seq_printf(s,743 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n",744 iter->wcid, iter->id,745 iter->sched ? 's' : 'u',746 iter->protection ? 'p' : '-',747 iter->trigger ? 't' : '-',748 iter->flowtype ? '-' : 'a',749 iter->exp, iter->mantissa,750 iter->duration, iter->tsf);751 752 rcu_read_unlock();753 754 return 0;755}756 757/* The index of RF registers use the generic regidx, combined with two parts:758 * WF selection [31:24] and offset [23:0].759 */760static int761mt7996_rf_regval_get(void *data, u64 *val)762{763 struct mt7996_dev *dev = data;764 u32 regval;765 int ret;766 767 ret = mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false);768 if (ret)769 return ret;770 771 *val = regval;772 773 return 0;774}775 776static int777mt7996_rf_regval_set(void *data, u64 val)778{779 struct mt7996_dev *dev = data;780 u32 val32 = val;781 782 return mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true);783}784 785DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7996_rf_regval_get,786 mt7996_rf_regval_set, "0x%08llx\n");787 788int mt7996_init_debugfs(struct mt7996_phy *phy)789{790 struct mt7996_dev *dev = phy->dev;791 struct dentry *dir;792 793 dir = mt76_register_debugfs_fops(phy->mt76, NULL);794 if (!dir)795 return -ENOMEM;796 debugfs_create_file("hw-queues", 0400, dir, phy,797 &mt7996_hw_queues_fops);798 debugfs_create_file("xmit-queues", 0400, dir, phy,799 &mt7996_xmit_queues_fops);800 debugfs_create_file("tx_stats", 0400, dir, phy, &mt7996_tx_stats_fops);801 debugfs_create_file("sys_recovery", 0600, dir, phy,802 &mt7996_sys_recovery_ops);803 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm);804 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa);805 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin);806 /* TODO: wm fw cpu utilization */807 debugfs_create_file("fw_util_wa", 0400, dir, dev,808 &mt7996_fw_util_wa_fops);809 debugfs_create_file("implicit_txbf", 0600, dir, dev,810 &fops_implicit_txbf);811 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir,812 mt7996_twt_stats);813 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval);814 815 if (phy->mt76->cap.has_5ghz) {816 debugfs_create_u32("dfs_hw_pattern", 0400, dir,817 &dev->hw_pattern);818 debugfs_create_file("radar_trigger", 0200, dir, dev,819 &fops_radar_trigger);820 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir,821 mt7996_rdd_monitor);822 }823 824 if (phy == &dev->phy)825 dev->debugfs_dir = dir;826 827 return 0;828}829 830static void831mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen,832 const void *data, int len)833{834 static DEFINE_SPINLOCK(lock);835 unsigned long flags;836 void *dest;837 838 spin_lock_irqsave(&lock, flags);839 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);840 if (dest) {841 *(u32 *)dest = hdrlen + len;842 dest += 4;843 844 if (hdrlen) {845 memcpy(dest, hdr, hdrlen);846 dest += hdrlen;847 }848 849 memcpy(dest, data, len);850 relay_flush(dev->relay_fwlog);851 }852 spin_unlock_irqrestore(&lock, flags);853}854 855void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len)856{857 struct {858 __le32 magic;859 u8 version;860 u8 _rsv;861 __le16 serial_id;862 __le32 timestamp;863 __le16 msg_type;864 __le16 len;865 } hdr = {866 .version = 0x1,867 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC),868 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),869 };870 871 if (!dev->relay_fwlog)872 return;873 874 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++);875 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));876 hdr.len = *(__le16 *)data;877 mt7996_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);878}879 880bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len)881{882 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)883 return false;884 885 if (dev->relay_fwlog)886 mt7996_debugfs_write_fwlog(dev, NULL, 0, data, len);887 888 return true;889}890 891#ifdef CONFIG_MAC80211_DEBUGFS892/** per-station debugfs **/893 894static ssize_t mt7996_sta_fixed_rate_set(struct file *file,895 const char __user *user_buf,896 size_t count, loff_t *ppos)897{898#define SHORT_PREAMBLE 0899#define LONG_PREAMBLE 1900 struct ieee80211_sta *sta = file->private_data;901 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv;902 struct mt7996_dev *dev = msta->vif->phy->dev;903 struct ra_rate phy = {};904 char buf[100];905 int ret;906 u16 gi, ltf;907 908 if (count >= sizeof(buf))909 return -EINVAL;910 911 if (copy_from_user(buf, user_buf, count))912 return -EFAULT;913 914 if (count && buf[count - 1] == '\n')915 buf[count - 1] = '\0';916 else917 buf[count] = '\0';918 919 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 EHT: 15920 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3, BW320: 4921 * nss - vht: 1~4, he: 1~4, eht: 1~4, others: ignore922 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2, eht: 0~13923 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2924 * preamble - short: 1, long: 0925 * ldpc - off: 0, on: 1926 * stbc - off: 0, on: 1927 * ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2928 */929 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hu %hhu %hhu %hhu %hhu %hu",930 &phy.mode, &phy.bw, &phy.mcs, &phy.nss, &gi,931 &phy.preamble, &phy.stbc, &phy.ldpc, &phy.spe, <f) != 10) {932 dev_warn(dev->mt76.dev,933 "format: Mode BW MCS NSS GI Preamble STBC LDPC SPE ltf\n");934 goto out;935 }936 937 phy.wlan_idx = cpu_to_le16(msta->wcid.idx);938 phy.gi = cpu_to_le16(gi);939 phy.ltf = cpu_to_le16(ltf);940 phy.ldpc = phy.ldpc ? 7 : 0;941 phy.preamble = phy.preamble ? SHORT_PREAMBLE : LONG_PREAMBLE;942 943 ret = mt7996_mcu_set_fixed_rate_ctrl(dev, &phy, 0);944 if (ret)945 return -EFAULT;946 947out:948 return count;949}950 951static const struct file_operations fops_fixed_rate = {952 .write = mt7996_sta_fixed_rate_set,953 .open = simple_open,954 .owner = THIS_MODULE,955 .llseek = default_llseek,956};957 958static int959mt7996_queues_show(struct seq_file *s, void *data)960{961 struct ieee80211_sta *sta = s->private;962 963 mt7996_sta_hw_queue_read(s, sta);964 965 return 0;966}967 968DEFINE_SHOW_ATTRIBUTE(mt7996_queues);969 970void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,971 struct ieee80211_sta *sta, struct dentry *dir)972{973 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate);974 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7996_queues_fops);975}976 977#endif978