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1/* SPDX-License-Identifier: ISC */2/*3 * Copyright (C) 2022 MediaTek Inc.4 */5 6#ifndef __MT7996_H7#define __MT7996_H8 9#include <linux/interrupt.h>10#include <linux/ktime.h>11#include "../mt76_connac.h"12#include "regs.h"13 14#define MT7996_MAX_INTERFACES 19 /* per-band */15#define MT7996_MAX_WMM_SETS 416#define MT7996_WTBL_BMC_SIZE (is_mt7992(&dev->mt76) ? 32 : 64)17#define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)18#define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \19 mt7996_max_interface_num(dev))20 21#define MT7996_WATCHDOG_TIME (HZ / 10)22#define MT7996_RESET_TIMEOUT (30 * HZ)23 24#define MT7996_TX_RING_SIZE 204825#define MT7996_TX_MCU_RING_SIZE 25626#define MT7996_TX_FWDL_RING_SIZE 12827 28#define MT7996_RX_RING_SIZE 153629#define MT7996_RX_MCU_RING_SIZE 51230#define MT7996_RX_MCU_RING_SIZE_WA 102431 32#define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"33#define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"34#define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin"35#define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"36 37#define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin"38#define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin"39#define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin"40#define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin"41 42#define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"43#define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin"44#define MT7996_EEPROM_SIZE 768045#define MT7996_EEPROM_BLOCK_SIZE 1646#define MT7996_TOKEN_SIZE 1638447#define MT7996_HW_TOKEN_SIZE 819248 49#define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */50#define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */51 52#define MT7996_SKU_RATE_NUM 41753#define MT7996_SKU_PATH_NUM 49454 55#define MT7996_MAX_TWT_AGRT 1656#define MT7996_MAX_STA_TWT_AGRT 857#define MT7996_MIN_TWT_DUR 6458#define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)59 60/* NOTE: used to map mt76_rates. idx may change if firmware expands table */61#define MT7996_BASIC_RATES_TBL 3162#define MT7996_BEACON_RATES_TBL 2563 64#define MT7996_THERMAL_THROTTLE_MAX 10065#define MT7996_CDEV_THROTTLE_MAX 9966#define MT7996_CRIT_TEMP_IDX 067#define MT7996_MAX_TEMP_IDX 168#define MT7996_CRIT_TEMP 11069#define MT7996_MAX_TEMP 12070 71#define MT7996_RRO_MAX_SESSION 102472#define MT7996_RRO_WINDOW_MAX_LEN 102473#define MT7996_RRO_ADDR_ELEM_LEN 12874#define MT7996_RRO_BA_BITMAP_LEN 275#define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \76 MT7996_RRO_BA_BITMAP_LEN)77#define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \78 MT7996_RRO_ADDR_ELEM_LEN)79#define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \80 MT7996_RRO_BA_BITMAP_SESSION_SIZE)81 82#define MT7996_RX_BUF_SIZE (1800 + \83 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))84#define MT7996_RX_MSDU_PAGE_SIZE (128 + \85 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))86 87struct mt7996_vif;88struct mt7996_sta;89struct mt7996_dfs_pulse;90struct mt7996_dfs_pattern;91 92enum mt7996_ram_type {93 MT7996_RAM_TYPE_WM,94 MT7996_RAM_TYPE_WA,95 MT7996_RAM_TYPE_DSP,96};97 98enum mt7996_txq_id {99 MT7996_TXQ_FWDL = 16,100 MT7996_TXQ_MCU_WM,101 MT7996_TXQ_BAND0,102 MT7996_TXQ_BAND1,103 MT7996_TXQ_MCU_WA,104 MT7996_TXQ_BAND2,105};106 107enum mt7996_rxq_id {108 MT7996_RXQ_MCU_WM = 0,109 MT7996_RXQ_MCU_WA,110 MT7996_RXQ_MCU_WA_MAIN = 2,111 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */112 MT7996_RXQ_MCU_WA_TRI = 3,113 MT7996_RXQ_BAND0 = 4,114 MT7996_RXQ_BAND1 = 5, /* for mt7992 */115 MT7996_RXQ_BAND2 = 5,116 MT7996_RXQ_RRO_BAND0 = 8,117 MT7996_RXQ_RRO_BAND1 = 8,/* unused */118 MT7996_RXQ_RRO_BAND2 = 6,119 MT7996_RXQ_MSDU_PG_BAND0 = 10,120 MT7996_RXQ_MSDU_PG_BAND1 = 11,121 MT7996_RXQ_MSDU_PG_BAND2 = 12,122 MT7996_RXQ_TXFREE0 = 9,123 MT7996_RXQ_TXFREE1 = 9,124 MT7996_RXQ_TXFREE2 = 7,125 MT7996_RXQ_RRO_IND = 0,126};127 128struct mt7996_twt_flow {129 struct list_head list;130 u64 start_tsf;131 u64 tsf;132 u32 duration;133 u16 wcid;134 __le16 mantissa;135 u8 exp;136 u8 table_id;137 u8 id;138 u8 protection:1;139 u8 flowtype:1;140 u8 trigger:1;141 u8 sched:1;142};143 144DECLARE_EWMA(avg_signal, 10, 8)145 146struct mt7996_sta {147 struct mt76_wcid wcid; /* must be first */148 149 struct mt7996_vif *vif;150 151 struct list_head rc_list;152 u32 airtime_ac[8];153 154 int ack_signal;155 struct ewma_avg_signal avg_ack_signal;156 157 unsigned long changed;158 159 struct mt76_connac_sta_key_conf bip;160 161 struct {162 u8 flowid_mask;163 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];164 } twt;165};166 167struct mt7996_vif {168 struct mt76_vif mt76; /* must be first */169 170 struct mt7996_sta sta;171 struct mt7996_phy *phy;172 173 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];174 struct cfg80211_bitrate_mask bitrate_mask;175};176 177/* crash-dump */178struct mt7996_crash_data {179 guid_t guid;180 struct timespec64 timestamp;181 182 u8 *memdump_buf;183 size_t memdump_buf_len;184};185 186struct mt7996_hif {187 struct list_head list;188 189 struct device *dev;190 void __iomem *regs;191 int irq;192};193 194struct mt7996_wed_rro_addr {195 u32 head_low;196 u32 head_high : 4;197 u32 count: 11;198 u32 oor: 1;199 u32 rsv : 8;200 u32 signature : 8;201};202 203struct mt7996_wed_rro_session_id {204 struct list_head list;205 u16 id;206};207 208struct mt7996_phy {209 struct mt76_phy *mt76;210 struct mt7996_dev *dev;211 212 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];213 214 struct ieee80211_vif *monitor_vif;215 216 struct thermal_cooling_device *cdev;217 u8 cdev_state;218 u8 throttle_state;219 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */220 221 u32 rxfilter;222 u64 omac_mask;223 224 u16 noise;225 226 s16 coverage_class;227 u8 slottime;228 229 u8 rdd_state;230 231 u16 beacon_rate;232 233 u32 rx_ampdu_ts;234 u32 ampdu_ref;235 236 struct mt76_mib_stats mib;237 struct mt76_channel_state state_ts;238 239 bool has_aux_rx;240};241 242struct mt7996_dev {243 union { /* must be first */244 struct mt76_dev mt76;245 struct mt76_phy mphy;246 };247 248 struct mt7996_hif *hif2;249 struct mt7996_reg_desc reg;250 u8 q_id[MT7996_MAX_QUEUE];251 u32 q_int_mask[MT7996_MAX_QUEUE];252 u32 q_wfdma_mask;253 254 const struct mt76_bus_ops *bus_ops;255 struct mt7996_phy phy;256 257 /* monitor rx chain configured channel */258 struct cfg80211_chan_def rdd2_chandef;259 struct mt7996_phy *rdd2_phy;260 261 u16 chainmask;262 u8 chainshift[__MT_MAX_BAND];263 u32 hif_idx;264 265 struct work_struct init_work;266 struct work_struct rc_work;267 struct work_struct dump_work;268 struct work_struct reset_work;269 wait_queue_head_t reset_wait;270 struct {271 u32 state;272 u32 wa_reset_count;273 u32 wm_reset_count;274 bool hw_full_reset:1;275 bool hw_init_done:1;276 bool restart:1;277 } recovery;278 279 /* protects coredump data */280 struct mutex dump_mutex;281#ifdef CONFIG_DEV_COREDUMP282 struct {283 struct mt7996_crash_data *crash_data;284 } coredump;285#endif286 287 struct list_head sta_rc_list;288 struct list_head twt_list;289 290 u32 hw_pattern;291 292 bool flash_mode:1;293 bool has_eht:1;294 bool has_rro:1;295 296 struct {297 struct {298 void *ptr;299 dma_addr_t phy_addr;300 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN];301 struct {302 void *ptr;303 dma_addr_t phy_addr;304 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN];305 struct {306 void *ptr;307 dma_addr_t phy_addr;308 } session;309 310 struct work_struct work;311 struct list_head poll_list;312 spinlock_t lock;313 } wed_rro;314 315 bool ibf;316 u8 fw_debug_wm;317 u8 fw_debug_wa;318 u8 fw_debug_bin;319 u16 fw_debug_seq;320 321 struct dentry *debugfs_dir;322 struct rchan *relay_fwlog;323 324 struct {325 u16 table_mask;326 u8 n_agrt;327 } twt;328 329 spinlock_t reg_lock;330 331 u8 wtbl_size_group;332};333 334enum {335 WFDMA0 = 0x0,336 WFDMA1,337 WFDMA_EXT,338 __MT_WFDMA_MAX,339};340 341enum {342 MT_RX_SEL0,343 MT_RX_SEL1,344 MT_RX_SEL2, /* monitor chain */345};346 347enum mt7996_rdd_cmd {348 RDD_STOP,349 RDD_START,350 RDD_DET_MODE,351 RDD_RADAR_EMULATE,352 RDD_START_TXQ = 20,353 RDD_CAC_START = 50,354 RDD_CAC_END,355 RDD_NORMAL_START,356 RDD_DISABLE_DFS_CAL,357 RDD_PULSE_DBG,358 RDD_READ_PULSE,359 RDD_RESUME_BF,360 RDD_IRQ_OFF,361};362 363static inline struct mt7996_phy *364mt7996_hw_phy(struct ieee80211_hw *hw)365{366 struct mt76_phy *phy = hw->priv;367 368 return phy->priv;369}370 371static inline struct mt7996_dev *372mt7996_hw_dev(struct ieee80211_hw *hw)373{374 struct mt76_phy *phy = hw->priv;375 376 return container_of(phy->dev, struct mt7996_dev, mt76);377}378 379static inline struct mt7996_phy *380__mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)381{382 struct mt76_phy *phy = dev->mt76.phys[band];383 384 if (!phy)385 return NULL;386 387 return phy->priv;388}389 390static inline struct mt7996_phy *391mt7996_phy2(struct mt7996_dev *dev)392{393 return __mt7996_phy(dev, MT_BAND1);394}395 396static inline struct mt7996_phy *397mt7996_phy3(struct mt7996_dev *dev)398{399 return __mt7996_phy(dev, MT_BAND2);400}401 402static inline bool403mt7996_band_valid(struct mt7996_dev *dev, u8 band)404{405 if (is_mt7992(&dev->mt76))406 return band <= MT_BAND1;407 408 /* tri-band support */409 if (band <= MT_BAND2 &&410 mt76_get_field(dev, MT_PAD_GPIO, MT_PAD_GPIO_ADIE_COMB) <= 1)411 return true;412 413 return band == MT_BAND0 || band == MT_BAND2;414}415 416extern const struct ieee80211_ops mt7996_ops;417extern struct pci_driver mt7996_pci_driver;418extern struct pci_driver mt7996_hif_driver;419 420struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,421 void __iomem *mem_base, u32 device_id);422void mt7996_wfsys_reset(struct mt7996_dev *dev);423irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);424u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif);425int mt7996_register_device(struct mt7996_dev *dev);426void mt7996_unregister_device(struct mt7996_dev *dev);427int mt7996_eeprom_init(struct mt7996_dev *dev);428int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);429int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,430 struct ieee80211_channel *chan);431s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);432int mt7996_dma_init(struct mt7996_dev *dev);433void mt7996_dma_reset(struct mt7996_dev *dev, bool force);434void mt7996_dma_prefetch(struct mt7996_dev *dev);435void mt7996_dma_cleanup(struct mt7996_dev *dev);436void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset);437int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx,438 int n_desc, int ring_base, struct mtk_wed_device *wed);439void mt7996_init_txpower(struct mt7996_phy *phy);440int mt7996_txbf_init(struct mt7996_dev *dev);441void mt7996_reset(struct mt7996_dev *dev);442int mt7996_run(struct ieee80211_hw *hw);443int mt7996_mcu_init(struct mt7996_dev *dev);444int mt7996_mcu_init_firmware(struct mt7996_dev *dev);445int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,446 struct mt7996_vif *mvif,447 struct mt7996_twt_flow *flow,448 int cmd);449int mt7996_mcu_add_dev_info(struct mt7996_phy *phy,450 struct ieee80211_vif *vif, bool enable);451int mt7996_mcu_add_bss_info(struct mt7996_phy *phy,452 struct ieee80211_vif *vif, int enable);453int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif,454 struct ieee80211_sta *sta, bool enable, bool newly);455int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,456 struct ieee80211_ampdu_params *params,457 bool add);458int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,459 struct ieee80211_ampdu_params *params,460 bool add);461int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif,462 struct cfg80211_he_bss_color *he_bss_color);463int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,464 int enable);465int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,466 struct ieee80211_vif *vif, u32 changed);467int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif,468 struct ieee80211_he_obss_pd *he_obss_pd);469int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif,470 struct ieee80211_sta *sta, bool changed);471int mt7996_set_channel(struct mt76_phy *mphy);472int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);473int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif);474int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,475 void *data, u16 version);476int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct ieee80211_vif *vif,477 struct ieee80211_sta *sta, void *data, u32 field);478int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);479int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset);480int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num);481int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);482int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);483int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);484int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);485int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,486 const struct mt7996_dfs_pulse *pulse);487int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,488 const struct mt7996_dfs_pattern *pattern);489int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);490int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);491int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif);492int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);493int mt7996_mcu_get_temperature(struct mt7996_phy *phy);494int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state);495int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable);496int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy);497int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index,498 u8 rx_sel, u8 val);499int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,500 struct cfg80211_chan_def *chandef);501int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,502 u16 rate_idx, bool beacon);503int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);504int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);505int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);506int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);507int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);508int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);509int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);510void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);511void mt7996_mcu_exit(struct mt7996_dev *dev);512int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag);513int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id);514 515static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)516{517 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) +518 mt7996_band_valid(dev, MT_BAND2)),519 MT7996_WTBL_BMC_SIZE);520}521 522static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)523{524 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE;525}526 527void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,528 u32 clear, u32 set);529 530static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)531{532 if (dev->hif2)533 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);534 else535 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);536 537 tasklet_schedule(&dev->mt76.irq_tasklet);538}539 540static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)541{542 if (dev->hif2)543 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);544 else545 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);546}547 548void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,549 size_t len);550 551static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy)552{553 int max_nss = hweight8(phy->mt76->hw->wiphy->available_antennas_tx);554 int cur_nss = hweight8(phy->mt76->antenna_mask);555 u16 tx_chainmask = phy->mt76->chainmask;556 557 if (cur_nss != max_nss)558 return tx_chainmask;559 560 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx);561}562 563void mt7996_mac_init(struct mt7996_dev *dev);564u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);565bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);566void mt7996_mac_reset_counters(struct mt7996_phy *phy);567void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);568void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);569void mt7996_mac_enable_rtscts(struct mt7996_dev *dev,570 struct ieee80211_vif *vif, bool enable);571void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,572 struct sk_buff *skb, struct mt76_wcid *wcid,573 struct ieee80211_key_conf *key, int pid,574 enum mt76_txq_id qid, u32 changed);575void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);576int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,577 struct ieee80211_sta *sta);578void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,579 struct ieee80211_sta *sta);580void mt7996_mac_work(struct work_struct *work);581void mt7996_mac_reset_work(struct work_struct *work);582void mt7996_mac_dump_work(struct work_struct *work);583void mt7996_mac_sta_rc_work(struct work_struct *work);584void mt7996_mac_update_stats(struct mt7996_phy *phy);585void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,586 struct mt7996_sta *msta,587 u8 flowid);588void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,589 struct ieee80211_sta *sta,590 struct ieee80211_twt_setup *twt);591int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,592 enum mt76_txq_id qid, struct mt76_wcid *wcid,593 struct ieee80211_sta *sta,594 struct mt76_tx_info *tx_info);595void mt7996_tx_token_put(struct mt7996_dev *dev);596void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,597 struct sk_buff *skb, u32 *info);598bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);599void mt7996_stats_work(struct work_struct *work);600int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);601int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);602void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);603void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);604void mt7996_update_channel(struct mt76_phy *mphy);605int mt7996_init_debugfs(struct mt7996_phy *phy);606void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);607bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);608int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,609 struct ieee80211_key_conf *key, int mcu_cmd,610 struct mt76_wcid *wcid, enum set_key_cmd cmd);611int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, struct ieee80211_vif *vif,612 struct ieee80211_key_conf *key);613int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,614 struct ieee80211_vif *vif,615 struct ieee80211_sta *sta);616int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode);617#ifdef CONFIG_MAC80211_DEBUGFS618void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,619 struct ieee80211_sta *sta, struct dentry *dir);620#endif621int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,622 bool hif2, int *irq);623u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);624 625#ifdef CONFIG_MTK_DEBUG626int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);627#endif628 629#ifdef CONFIG_NET_MEDIATEK_SOC_WED630int mt7996_dma_rro_init(struct mt7996_dev *dev);631#endif /* CONFIG_NET_MEDIATEK_SOC_WED */632 633#endif634