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1/* SPDX-License-Identifier: ISC */2/*3 * Copyright (C) 2022 MediaTek Inc.4 */5 6#ifndef __MT7996_REGS_H7#define __MT7996_REGS_H8 9struct __map {10 u32 phys;11 u32 mapped;12 u32 size;13};14 15struct __base {16 u32 band_base[__MT_MAX_BAND];17};18 19/* used to differentiate between generations */20struct mt7996_reg_desc {21 const struct __base *base;22 const u32 *offs_rev;23 const struct __map *map;24 u32 map_size;25};26 27enum base_rev {28 WF_AGG_BASE,29 WF_ARB_BASE,30 WF_TMAC_BASE,31 WF_RMAC_BASE,32 WF_DMA_BASE,33 WF_WTBLOFF_BASE,34 WF_ETBF_BASE,35 WF_LPON_BASE,36 WF_MIB_BASE,37 WF_RATE_BASE,38 __MT_REG_BASE_MAX,39};40 41#define __BASE(_id, _band) (dev->reg.base[(_id)].band_base[(_band)])42 43enum offs_rev {44 MIB_RVSR0,45 MIB_RVSR1,46 MIB_BTSCR5,47 MIB_BTSCR6,48 MIB_RSCR1,49 MIB_RSCR27,50 MIB_RSCR28,51 MIB_RSCR29,52 MIB_RSCR30,53 MIB_RSCR31,54 MIB_RSCR33,55 MIB_RSCR35,56 MIB_RSCR36,57 MIB_BSCR0,58 MIB_BSCR1,59 MIB_BSCR2,60 MIB_BSCR3,61 MIB_BSCR4,62 MIB_BSCR5,63 MIB_BSCR6,64 MIB_BSCR7,65 MIB_BSCR17,66 MIB_TRDR1,67 __MT_OFFS_MAX,68};69 70#define __OFFS(id) (dev->reg.offs_rev[(id)])71 72/* RRO TOP */73#define MT_RRO_TOP_BASE 0xA00074#define MT_RRO_TOP(ofs) (MT_RRO_TOP_BASE + (ofs))75 76#define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8)77#define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC)78#define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8)79#define WF_RRO_AXI_MST_CFG_DIDX_OK BIT(12)80#define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34)81#define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE BIT(31)82 83#define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38)84#define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C)85#define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40)86#define MT_RRO_IND_CMD_SIGNATURE_BASE1_EN BIT(31)87 88#define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C)89#define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60)90#define MT_RRO_PARTICULAR_CONFG_EN BIT(31)91#define MT_RRO_PARTICULAR_SID GENMASK(30, 16)92 93#define MT_RRO_BA_BITMAP_BASE_EXT0 MT_RRO_TOP(0x70)94#define MT_RRO_BA_BITMAP_BASE_EXT1 MT_RRO_TOP(0x74)95#define MT_RRO_HOST_INT_ENA MT_RRO_TOP(0x204)96#define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0)97 98#define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400)99 100#define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50)101#define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16)102#define MT_RRO_ACK_SN_CTRL_SESSION_MASK GENMASK(11, 0)103 104#define MT_RRO_DBG_RD_CTRL MT_RRO_TOP(0xe0)105#define MT_RRO_DBG_RD_ADDR GENMASK(15, 0)106#define MT_RRO_DBG_RD_EXEC BIT(31)107 108#define MT_RRO_DBG_RDAT_DW(_n) MT_RRO_TOP(0xf0 + (_n) * 0x4)109 110#define MT_MCU_INT_EVENT 0x2108111#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)112#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)113#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)114 115/* PLE */116#define MT_PLE_BASE 0x820c0000117#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))118 119#define MT_FL_Q_EMPTY MT_PLE(0x360)120#define MT_FL_Q0_CTRL MT_PLE(0x3e0)121#define MT_FL_Q2_CTRL MT_PLE(0x3e8)122#define MT_FL_Q3_CTRL MT_PLE(0x3ec)123 124#define MT_PLE_FREEPG_CNT MT_PLE(0x380)125#define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384)126#define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c)127#define MT_PLE_HIF_PG_INFO MT_PLE(0x388)128 129#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2))130#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))131 132/* WF MDP TOP */133#define MT_MDP_BASE 0x820cc000134#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))135 136#define MT_MDP_DCR2 MT_MDP(0x8e8)137#define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2)138 139/* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */140#define MT_WF_TMAC_BASE(_band) __BASE(WF_TMAC_BASE, (_band))141#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))142 143#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)144#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)145 146#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8)147#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc)148#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)149#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)150 151#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014)152#define MT_IFS_EIFS_OFDM GENMASK(8, 0)153#define MT_IFS_RIFS GENMASK(14, 10)154#define MT_IFS_SIFS GENMASK(22, 16)155#define MT_IFS_SLOT GENMASK(30, 24)156 157#define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018)158#define MT_IFS_EIFS_CCK GENMASK(8, 0)159 160/* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */161#define MT_WF_DMA_BASE(_band) __BASE(WF_DMA_BASE, (_band))162#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))163 164#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)165#define MT_DMA_DCR0_RXD_G5_EN BIT(23)166 167#define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054)168#define MT_DMA_TCRF1_QIDX GENMASK(15, 13)169 170/* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */171#define MT_WTBLOFF_BASE(_band) __BASE(WF_WTBLOFF_BASE, (_band))172#define MT_WTBLOFF(_band, ofs) (MT_WTBLOFF_BASE(_band) + (ofs))173 174#define MT_WTBLOFF_RSCR(_band) MT_WTBLOFF(_band, 0x008)175#define MT_WTBLOFF_RSCR_RCPI_MODE GENMASK(31, 30)176#define MT_WTBLOFF_RSCR_RCPI_PARAM GENMASK(25, 24)177 178/* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */179#define MT_WF_ETBF_BASE(_band) __BASE(WF_ETBF_BASE, (_band))180#define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs))181 182#define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100)183#define MT_ETBF_RX_FB_BW GENMASK(10, 8)184#define MT_ETBF_RX_FB_NC GENMASK(7, 4)185#define MT_ETBF_RX_FB_NR GENMASK(3, 0)186 187/* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */188#define MT_WF_LPON_BASE(_band) __BASE(WF_LPON_BASE, (_band))189#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))190 191#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360)192#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364)193#define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c)194 195#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4))196#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)197#define MT_LPON_TCR_SW_WRITE BIT(0)198#define MT_LPON_TCR_SW_ADJUST BIT(1)199#define MT_LPON_TCR_SW_READ GENMASK(1, 0)200 201/* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/202/* These counters are (mostly?) clear-on-read. So, some should not203 * be read at all in case firmware is already reading them. These204 * are commented with 'DNR' below. The DNR stats will be read by querying205 * the firmware API for the appropriate message. For counters the driver206 * does read, the driver should accumulate the counters.207 */208#define MT_WF_MIB_BASE(_band) __BASE(WF_MIB_BASE, (_band))209#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))210 211#define MT_MIB_BSCR0(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR0))212#define MT_MIB_BSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR1))213#define MT_MIB_BSCR2(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR2))214#define MT_MIB_BSCR3(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR3))215#define MT_MIB_BSCR4(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR4))216#define MT_MIB_BSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR5))217#define MT_MIB_BSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR6))218#define MT_MIB_BSCR7(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR7))219#define MT_MIB_BSCR17(_band) MT_WF_MIB(_band, __OFFS(MIB_BSCR17))220 221#define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4)222#define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8)223#define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0)224 225#define MT_MIB_RSCR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR1))226/* rx mpdu counter, full 32 bits */227#define MT_MIB_RSCR31(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR31))228#define MT_MIB_RSCR33(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR33))229 230#define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)231#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)232 233#define MT_MIB_RVSR0(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR0))234 235#define MT_MIB_RSCR35(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR35))236#define MT_MIB_RSCR36(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR36))237 238/* tx ampdu cnt, full 32 bits */239#define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0)240#define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8)241 242/* counts all mpdus in ampdu, regardless of success */243#define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc)244 245/* counts all successfully tx'd mpdus in ampdu */246#define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0)247 248/* rx ampdu count, 32-bit */249#define MT_MIB_RSCR27(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR27))250 251/* rx ampdu bytes count, 32-bit */252#define MT_MIB_RSCR28(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR28))253 254/* rx ampdu valid subframe count */255#define MT_MIB_RSCR29(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR29))256 257/* rx ampdu valid subframe bytes count, 32bits */258#define MT_MIB_RSCR30(_band) MT_WF_MIB(_band, __OFFS(MIB_RSCR30))259 260/* remaining windows protected stats */261#define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080)262#define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0)263 264#define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084)265#define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0)266 267#define MT_MIB_RVSR1(_band) MT_WF_MIB(_band, __OFFS(MIB_RVSR1))268 269/* rx blockack count, 32 bits */270#define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4)271 272#define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0)273#define MT_MIB_BTSCR5(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR5))274#define MT_MIB_BTSCR6(_band) MT_WF_MIB(_band, __OFFS(MIB_BTSCR6))275 276#define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0)277 278#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(MIB_TRDR1) + ((n) << 2))279#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))280#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0))281 282/* UMIB */283#define MT_WF_UMIB_BASE 0x820cd000284#define MT_WF_UMIB(ofs) (MT_WF_UMIB_BASE + (ofs))285 286#define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + (_band) * 0x164)287 288/* WTBLON TOP */289#define MT_WTBLON_TOP_BASE 0x820d4000290#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))291#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370)292#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)293 294#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380)295#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)296#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14)297#define MT_WTBL_UPDATE_BUSY BIT(31)298 299#define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0)300#define MT_WTBL_ITCR_WR BIT(16)301#define MT_WTBL_ITCR_EXEC BIT(31)302#define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8)303#define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc)304#define MT_WTBL_SPE_IDX_SEL BIT(6)305 306/* WTBL */307#define MT_WTBL_BASE 0x820d8000308#define MT_WTBL_LMAC_ID GENMASK(14, 8)309#define MT_WTBL_LMAC_DW GENMASK(7, 2)310#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \311 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \312 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))313 314/* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */315#define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band))316#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))317 318#define MT_AGG_ACR4(_band) MT_WF_AGG(_band, 0x3c)319#define MT_AGG_ACR_PPDU_TXS2H BIT(1)320 321/* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */322#define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band))323#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))324 325#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000)326#define MT_ARB_SCR_TX_DISABLE BIT(8)327#define MT_ARB_SCR_RX_DISABLE BIT(9)328 329/* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */330#define MT_WF_RMAC_BASE(_band) __BASE(WF_RMAC_BASE, (_band))331#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))332 333#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)334#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)335#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)336#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)337#define MT_WF_RFCR_DROP_MCAST BIT(5)338#define MT_WF_RFCR_DROP_BCAST BIT(6)339#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)340#define MT_WF_RFCR_DROP_A3_MAC BIT(8)341#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)342#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)343#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)344#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)345#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)346#define MT_WF_RFCR_DROP_CTS BIT(14)347#define MT_WF_RFCR_DROP_RTS BIT(15)348#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)349#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)350#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)351#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)352#define MT_WF_RFCR_DROP_NDPA BIT(20)353#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)354 355#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)356#define MT_WF_RFCR1_DROP_ACK BIT(4)357#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)358#define MT_WF_RFCR1_DROP_BA BIT(6)359#define MT_WF_RFCR1_DROP_CFEND BIT(7)360#define MT_WF_RFCR1_DROP_CFACK BIT(8)361 362#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)363#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)364#define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16)365#define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0)366 367#define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384)368#define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16)369 370#define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c)371#define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0)372 373#define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390)374#define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0)375 376#define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0)377#define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21)378 379/* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */380#define MT_WF_RATE_BASE(_band) __BASE(WF_RATE_BASE, (_band))381#define MT_WF_RATE(_band, ofs) (MT_WF_RATE_BASE(_band) + (ofs))382 383#define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050)384#define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0)385 386/* WFDMA0 */387#define MT_WFDMA0_BASE 0xd4000388#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))389 390#define MT_WFDMA0_RST MT_WFDMA0(0x100)391#define MT_WFDMA0_RST_LOGIC_RST BIT(4)392#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)393 394#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)395#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)396#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)397#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)398 399#define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154)400#define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3)401#define MT_WFDMA0_RX_INT_SEL_RING6 BIT(6)402 403#define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)404 405#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)406#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)407#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)408#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)409#define MT_WFDMA0_GLO_CFG_EXT_EN BIT(26)410#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)411#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)412 413#define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268)414#define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c)415#define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270)416#define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c)417 418#define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)419#define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18)420#define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14)421 422#define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)423#define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE BIT(31)424#define WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE BIT(28)425 426#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)427#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)428#define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)429#define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)430 431/* WFDMA1 */432#define MT_WFDMA1_BASE 0xd5000433 434/* WFDMA CSR */435#define MT_WFDMA_EXT_CSR_BASE 0xd7000436#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))437 438#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)439#define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)440#define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22)441 442#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)443#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)444 445#define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500)446#define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0)447 448#define MT_PCIE_RECOG_ID 0xd7090449#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)450#define MT_PCIE_RECOG_ID_SEM BIT(31)451 452/* WFDMA0 PCIE1 */453#define MT_WFDMA0_PCIE1_BASE 0xd8000454#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))455 456#define MT_INT_PCIE1_SOURCE_CSR_EXT MT_WFDMA0_PCIE1(0x118)457#define MT_INT_PCIE1_MASK_CSR MT_WFDMA0_PCIE1(0x11c)458 459#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)460#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)461#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)462#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)463 464/* WFDMA COMMON */465#define __RXQ(q) ((q) + __MT_MCUQ_MAX)466#define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX)467 468#define MT_Q_ID(q) (dev->q_id[(q)])469#define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \470 MT_WFDMA1_BASE : MT_WFDMA0_BASE)471 472#define MT_MCUQ_ID(q) MT_Q_ID(q)473#define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q))474#define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q))475 476#define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300)477#define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300)478#define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500)479#define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40)480 481#define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \482 MT_MCUQ_ID(q) * 0x4)483#define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \484 MT_RXQ_ID(q) * 0x4)485#define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \486 MT_TXQ_ID(q) * 0x4)487 488#define MT_INT_SOURCE_CSR MT_WFDMA0(0x200)489#define MT_INT_MASK_CSR MT_WFDMA0(0x204)490 491#define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200)492#define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204)493 494#define MT_INT_RX_DONE_BAND0 BIT(12)495#define MT_INT_RX_DONE_BAND1 BIT(13) /* for mt7992 */496#define MT_INT_RX_DONE_BAND2 BIT(13)497#define MT_INT_RX_DONE_WM BIT(0)498#define MT_INT_RX_DONE_WA BIT(1)499#define MT_INT_RX_DONE_WA_MAIN BIT(2)500#define MT_INT_RX_DONE_WA_EXT BIT(3) /* for mt7992 */501#define MT_INT_RX_DONE_WA_TRI BIT(3)502#define MT_INT_RX_TXFREE_MAIN BIT(17)503#define MT_INT_RX_TXFREE_TRI BIT(15)504#define MT_INT_RX_DONE_BAND2_EXT BIT(23)505#define MT_INT_RX_TXFREE_EXT BIT(26)506#define MT_INT_MCU_CMD BIT(29)507 508#define MT_INT_RX_DONE_RRO_BAND0 BIT(16)509#define MT_INT_RX_DONE_RRO_BAND1 BIT(16)510#define MT_INT_RX_DONE_RRO_BAND2 BIT(14)511#define MT_INT_RX_DONE_RRO_IND BIT(11)512#define MT_INT_RX_DONE_MSDU_PG_BAND0 BIT(18)513#define MT_INT_RX_DONE_MSDU_PG_BAND1 BIT(19)514#define MT_INT_RX_DONE_MSDU_PG_BAND2 BIT(23)515 516#define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)])517#define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)])518 519#define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \520 MT_INT_RX(MT_RXQ_MCU_WA))521 522#define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \523 MT_INT_RX(MT_RXQ_MAIN_WA) | \524 MT_INT_RX(MT_RXQ_TXFREE_BAND0))525 526#define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \527 MT_INT_RX(MT_RXQ_BAND1_WA) | \528 MT_INT_RX(MT_RXQ_MAIN_WA) | \529 MT_INT_RX(MT_RXQ_TXFREE_BAND0))530 531#define MT_INT_BAND2_RX_DONE (MT_INT_RX(MT_RXQ_BAND2) | \532 MT_INT_RX(MT_RXQ_BAND2_WA) | \533 MT_INT_RX(MT_RXQ_MAIN_WA) | \534 MT_INT_RX(MT_RXQ_TXFREE_BAND0))535 536#define MT_INT_RRO_RX_DONE (MT_INT_RX(MT_RXQ_RRO_BAND0) | \537 MT_INT_RX(MT_RXQ_RRO_BAND1) | \538 MT_INT_RX(MT_RXQ_RRO_BAND2) | \539 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND0) | \540 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND1) | \541 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND2))542 543#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \544 MT_INT_BAND0_RX_DONE | \545 MT_INT_BAND1_RX_DONE | \546 MT_INT_BAND2_RX_DONE | \547 MT_INT_RRO_RX_DONE)548 549#define MT_INT_TX_DONE_FWDL BIT(26)550#define MT_INT_TX_DONE_MCU_WM BIT(27)551#define MT_INT_TX_DONE_MCU_WA BIT(22)552#define MT_INT_TX_DONE_BAND0 BIT(30)553#define MT_INT_TX_DONE_BAND1 BIT(31)554#define MT_INT_TX_DONE_BAND2 BIT(15)555 556#define MT_INT_TX_RX_DONE_EXT (MT_INT_TX_DONE_BAND2 | \557 MT_INT_RX_DONE_BAND2_EXT | \558 MT_INT_RX_TXFREE_EXT)559 560#define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \561 MT_INT_TX_MCU(MT_MCUQ_WM) | \562 MT_INT_TX_MCU(MT_MCUQ_FWDL))563 564#define MT_MCU_CMD MT_WFDMA0(0x1f0)565#define MT_MCU_CMD_STOP_DMA BIT(2)566#define MT_MCU_CMD_RESET_DONE BIT(3)567#define MT_MCU_CMD_RECOVERY_DONE BIT(4)568#define MT_MCU_CMD_NORMAL_STATE BIT(5)569#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)570 571#define MT_MCU_CMD_WA_WDT BIT(31)572#define MT_MCU_CMD_WM_WDT BIT(30)573#define MT_MCU_CMD_WDT_MASK GENMASK(31, 30)574 575/* l1/l2 remap */576#define MT_HIF_REMAP_L1 0x155024577#define MT_HIF_REMAP_L1_MASK GENMASK(31, 16)578#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)579#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)580#define MT_HIF_REMAP_BASE_L1 0x130000581 582#define MT_HIF_REMAP_L2 0x1b4583#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)584#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)585#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)586#define MT_HIF_REMAP_BASE_L2 0x1000587 588#define MT_INFRA_BASE 0x18000000589#define MT_WFSYS0_PHY_START 0x18400000590#define MT_WFSYS1_PHY_START 0x18800000591#define MT_WFSYS1_PHY_END 0x18bfffff592#define MT_CBTOP1_PHY_START 0x70000000593#define MT_CBTOP1_PHY_END 0x77ffffff594#define MT_CBTOP2_PHY_START 0xf0000000595#define MT_INFRA_MCU_START 0x7c000000596#define MT_INFRA_MCU_END 0x7c3fffff597 598/* FW MODE SYNC */599#define MT_FW_ASSERT_CNT 0x02208274600#define MT_FW_DUMP_STATE 0x02209e90601 602#define MT_SWDEF_BASE 0x00401400603 604#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))605#define MT_SWDEF_MODE MT_SWDEF(0x3c)606#define MT_SWDEF_NORMAL_MODE 0607 608#define MT_SWDEF_SER_STATS MT_SWDEF(0x040)609#define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)610#define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)611#define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04c)612#define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)613#define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)614#define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058)615#define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05c)616#define MT_SWDEF_LAMC_WISR6_BN2_STATS MT_SWDEF(0x060)617#define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x064)618#define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x068)619#define MT_SWDEF_LAMC_WISR7_BN2_STATS MT_SWDEF(0x06c)620 621/* LED */622#define MT_LED_TOP_BASE 0x18013000623#define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n))624 625#define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4))626#define MT_LED_CTRL_KICK BIT(7)627#define MT_LED_CTRL_BLINK_BAND_SEL BIT(4)628#define MT_LED_CTRL_BLINK_MODE BIT(2)629#define MT_LED_CTRL_POLARITY BIT(1)630 631#define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4))632#define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)633#define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8)634 635#define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))636 637/* CONN DBG */638#define MT_CONN_DBG_CTL_BASE 0x18023000639#define MT_CONN_DBG_CTL(ofs) (MT_CONN_DBG_CTL_BASE + (ofs))640#define MT_CONN_DBG_CTL_OUT_SEL MT_CONN_DBG_CTL(0x604)641#define MT_CONN_DBG_CTL_PC_LOG_SEL MT_CONN_DBG_CTL(0x60c)642#define MT_CONN_DBG_CTL_PC_LOG MT_CONN_DBG_CTL(0x610)643 644#define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */645#define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */646#define MT_LED_GPIO_SEL_MASK GENMASK(11, 8)647 648/* MT TOP */649#define MT_TOP_BASE 0xe0000650#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))651 652#define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))653#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)654#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)655#define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2)656 657#define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))658#define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)659 660#define MT_TOP_MISC MT_TOP(0xf0)661#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)662 663#define MT_PAD_GPIO 0x700056f0664#define MT_PAD_GPIO_ADIE_COMB GENMASK(16, 15)665 666#define MT_HW_REV 0x70010204667#define MT_HW_REV1 0x8a00668 669#define MT_WF_SUBSYS_RST 0x70028600670 671/* PCIE MAC */672#define MT_PCIE_MAC_BASE 0x74030000673#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))674#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)675 676#define MT_PCIE1_MAC_BASE 0x74090000677#define MT_PCIE1_MAC(ofs) (MT_PCIE1_MAC_BASE + (ofs))678 679#define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)680 681/* PHYRX CSD */682#define MT_WF_PHYRX_CSD_BASE 0x83000000683#define MT_WF_PHYRX_CSD(_band, _wf, ofs) (MT_WF_PHYRX_CSD_BASE + \684 ((_band) << 20) + \685 ((_wf) << 16) + (ofs))686#define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000)687 688/* PHYRX CTRL */689#define MT_WF_PHYRX_BAND_BASE 0x83080000690#define MT_WF_PHYRX_BAND(_band, ofs) (MT_WF_PHYRX_BAND_BASE + \691 ((_band) << 20) + (ofs))692 693#define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) MT_WF_PHYRX_BAND(_band, 0x1054)694#define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) MT_WF_PHYRX_BAND(_band, 0x1058)695#define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) MT_WF_PHYRX_BAND(_band, 0x105c)696#define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) MT_WF_PHYRX_BAND(_band, 0x1060)697#define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) MT_WF_PHYRX_BAND(_band, 0x1064)698#define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) MT_WF_PHYRX_BAND(_band, 0x1068)699 700#define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004)701#define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0)702#define MT_WF_PHYRX_BAND_RX_CTRL1_STSCNT_EN GENMASK(11, 9)703 704/* PHYRX CSD BAND */705#define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230)706#define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR_ONLY BIT(18)707#define MT_WF_PHYRX_CSD_BAND_RXTD12_IRPI_SW_CLR BIT(29)708 709/* CONN MCU EXCP CON */710#define MT_MCU_WM_EXCP_BASE 0x89050000711#define MT_MCU_WM_EXCP(ofs) (MT_MCU_WM_EXCP_BASE + (ofs))712#define MT_MCU_WM_EXCP_PC_CTRL MT_MCU_WM_EXCP(0x100)713#define MT_MCU_WM_EXCP_PC_LOG MT_MCU_WM_EXCP(0x104)714#define MT_MCU_WM_EXCP_LR_CTRL MT_MCU_WM_EXCP(0x200)715#define MT_MCU_WM_EXCP_LR_LOG MT_MCU_WM_EXCP(0x204)716 717/* CONN AFE CTL CON */718#define MT_AFE_CTL_BASE 0x18043000719#define MT_AFE_CTL_BAND(_band, ofs) (MT_AFE_CTL_BASE + \720 ((_band) * 0x1000) + (ofs))721#define MT_AFE_CTL_BAND_PLL_03(_band) MT_AFE_CTL_BAND(_band, 0x2c)722#define MT_AFE_CTL_BAND_PLL_03_MSB_EN BIT(1)723 724#endif725