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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>5 */6 7#ifndef __MT76_REGS_H8#define __MT76_REGS_H9 10#include <linux/bitops.h>11 12#define MT_ASIC_VERSION 0x000013 14#define MT76XX_REV_E3 0x2215#define MT76XX_REV_E4 0x3316 17#define MT_CMB_CTRL 0x002018#define MT_CMB_CTRL_XTAL_RDY BIT(22)19#define MT_CMB_CTRL_PLL_LD BIT(23)20 21#define MT_EFUSE_CTRL 0x002422#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)23#define MT_EFUSE_CTRL_MODE GENMASK(7, 6)24#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)25#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)26#define MT_EFUSE_CTRL_AIN GENMASK(25, 16)27#define MT_EFUSE_CTRL_KICK BIT(30)28#define MT_EFUSE_CTRL_SEL BIT(31)29 30#define MT_EFUSE_DATA_BASE 0x002831#define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2))32 33#define MT_COEXCFG0 0x004034#define MT_COEXCFG0_COEX_EN BIT(0)35 36#define MT_WLAN_FUN_CTRL 0x008037#define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)38#define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)39#define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)40 41#define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */42#define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */43 44#define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4)45#define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5)46#define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6)47#define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7)48 49#define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */50#define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */51 52#define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */53#define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */54#define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */55 56#define MT_XO_CTRL0 0x010057#define MT_XO_CTRL1 0x010458#define MT_XO_CTRL2 0x010859#define MT_XO_CTRL3 0x010c60#define MT_XO_CTRL4 0x011061 62#define MT_XO_CTRL5 0x011463#define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)64 65#define MT_XO_CTRL6 0x011866#define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)67 68#define MT_XO_CTRL7 0x011c69 70#define MT_WLAN_MTC_CTRL 0x1014871#define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)72#define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12)73#define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13)74#define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)75#define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20)76#define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21)77#define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22)78#define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24)79#define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25)80#define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26)81#define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27)82#define MT_WLAN_MTC_CTRL_STATE_UP BIT(28)83 84#define MT_INT_SOURCE_CSR 0x020085#define MT_INT_MASK_CSR 0x020486 87#define MT_INT_RX_DONE(_n) BIT(_n)88#define MT_INT_RX_DONE_ALL GENMASK(1, 0)89#define MT_INT_TX_DONE_ALL GENMASK(13, 4)90#define MT_INT_TX_DONE(_n) BIT(_n + 4)91#define MT_INT_RX_COHERENT BIT(16)92#define MT_INT_TX_COHERENT BIT(17)93#define MT_INT_ANY_COHERENT BIT(18)94#define MT_INT_MCU_CMD BIT(19)95#define MT_INT_TBTT BIT(20)96#define MT_INT_PRE_TBTT BIT(21)97#define MT_INT_TX_STAT BIT(22)98#define MT_INT_AUTO_WAKEUP BIT(23)99#define MT_INT_GPTIMER BIT(24)100#define MT_INT_RXDELAYINT BIT(26)101#define MT_INT_TXDELAYINT BIT(27)102 103#define MT_WPDMA_GLO_CFG 0x0208104#define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)105#define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)106#define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)107#define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)108#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)109#define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)110#define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)111#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)112#define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)113#define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)114 115#define MT_WPDMA_RST_IDX 0x020c116 117#define MT_WPDMA_DELAY_INT_CFG 0x0210118 119#define MT_WMM_AIFSN 0x0214120#define MT_WMM_AIFSN_MASK GENMASK(3, 0)121#define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4)122 123#define MT_WMM_CWMIN 0x0218124#define MT_WMM_CWMIN_MASK GENMASK(3, 0)125#define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4)126 127#define MT_WMM_CWMAX 0x021c128#define MT_WMM_CWMAX_MASK GENMASK(3, 0)129#define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4)130 131#define MT_WMM_TXOP_BASE 0x0220132#define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2))133#define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16)134#define MT_WMM_TXOP_MASK GENMASK(15, 0)135 136#define MT_FCE_DMA_ADDR 0x0230137#define MT_FCE_DMA_LEN 0x0234138 139#define MT_USB_DMA_CFG 0x238140#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)141#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)142#define MT_USB_DMA_CFG_PHY_CLR BIT(16)143#define MT_USB_DMA_CFG_TX_CLR BIT(19)144#define MT_USB_DMA_CFG_TXOP_HALT BIT(20)145#define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21)146#define MT_USB_DMA_CFG_RX_BULK_EN BIT(22)147#define MT_USB_DMA_CFG_TX_BULK_EN BIT(23)148#define MT_USB_DMA_CFG_UDMA_RX_WL_DROP BIT(25)149#define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 27)150#define MT_USB_DMA_CFG_RX_BUSY BIT(30)151#define MT_USB_DMA_CFG_TX_BUSY BIT(31)152 153#define MT_TSO_CTRL 0x0250154#define MT_HEADER_TRANS_CTRL_REG 0x0260155 156#define MT_US_CYC_CFG 0x02a4157#define MT_US_CYC_CNT GENMASK(7, 0)158 159#define MT_TX_RING_BASE 0x0300160#define MT_RX_RING_BASE 0x03c0161#define MT_RING_SIZE 0x10162 163#define MT_TX_HW_QUEUE_MCU 8164#define MT_TX_HW_QUEUE_MGMT 9165 166#define MT_PBF_SYS_CTRL 0x0400167#define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)168#define MT_PBF_SYS_CTRL_DMA_RESET BIT(1)169#define MT_PBF_SYS_CTRL_MAC_RESET BIT(2)170#define MT_PBF_SYS_CTRL_PBF_RESET BIT(3)171#define MT_PBF_SYS_CTRL_ASY_RESET BIT(4)172 173#define MT_PBF_CFG 0x0404174#define MT_PBF_CFG_TX0Q_EN BIT(0)175#define MT_PBF_CFG_TX1Q_EN BIT(1)176#define MT_PBF_CFG_TX2Q_EN BIT(2)177#define MT_PBF_CFG_TX3Q_EN BIT(3)178#define MT_PBF_CFG_RX0Q_EN BIT(4)179#define MT_PBF_CFG_RX_DROP_EN BIT(8)180 181#define MT_PBF_TX_MAX_PCNT 0x0408182#define MT_PBF_RX_MAX_PCNT 0x040c183 184#define MT_BCN_OFFSET_BASE 0x041c185#define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2))186 187#define MT_RXQ_STA 0x0430188#define MT_TXQ_STA 0x0434189 190#define MT_RF_CSR_CFG 0x0500191#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)192#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)193#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14)194#define MT_RF_CSR_CFG_WR BIT(30)195#define MT_RF_CSR_CFG_KICK BIT(31)196 197#define MT_RF_BYPASS_0 0x0504198#define MT_RF_BYPASS_1 0x0508199#define MT_RF_SETTING_0 0x050c200 201#define MT_RF_DATA_WRITE 0x0524202 203#define MT_RF_CTRL 0x0528204#define MT_RF_CTRL_ADDR GENMASK(11, 0)205#define MT_RF_CTRL_WRITE BIT(12)206#define MT_RF_CTRL_BUSY BIT(13)207#define MT_RF_CTRL_IDX BIT(16)208 209#define MT_RF_DATA_READ 0x052c210 211#define MT_FCE_PSE_CTRL 0x0800212#define MT_FCE_PARAMETERS 0x0804213#define MT_FCE_CSO 0x0808214 215#define MT_FCE_L2_STUFF 0x080c216#define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)217#define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1)218#define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2)219#define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3)220#define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4)221#define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5)222#define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)223#define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)224#define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)225 226#define MT_FCE_WLAN_FLOW_CONTROL1 0x0824227 228#define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0229#define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4230#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8231 232#define MT_FCE_PDMA_GLOBAL_CONF 0x09c4233 234#define MT_PAUSE_ENABLE_CONTROL1 0x0a38235 236#define MT_FCE_SKIP_FS 0x0a6c237 238#define MT_MAC_CSR0 0x1000239 240#define MT_MAC_SYS_CTRL 0x1004241#define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)242#define MT_MAC_SYS_CTRL_RESET_BBP BIT(1)243#define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2)244#define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3)245 246#define MT_MAC_ADDR_DW0 0x1008247#define MT_MAC_ADDR_DW1 0x100c248#define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)249 250#define MT_MAC_BSSID_DW0 0x1010251#define MT_MAC_BSSID_DW1 0x1014252#define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)253#define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)254#define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)255#define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21)256#define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22)257#define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23)258#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)259 260#define MT_MAX_LEN_CFG 0x1018261#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)262 263#define MT_BBP_CSR_CFG 0x101c264#define MT_BBP_CSR_CFG_VAL GENMASK(7, 0)265#define MT_BBP_CSR_CFG_REG_NUM GENMASK(15, 8)266#define MT_BBP_CSR_CFG_READ BIT(16)267#define MT_BBP_CSR_CFG_BUSY BIT(17)268#define MT_BBP_CSR_CFG_PAR_DUR BIT(18)269#define MT_BBP_CSR_CFG_RW_MODE BIT(19)270 271#define MT_AMPDU_MAX_LEN_20M1S 0x1030272#define MT_AMPDU_MAX_LEN_20M2S 0x1034273#define MT_AMPDU_MAX_LEN_40M1S 0x1038274#define MT_AMPDU_MAX_LEN_40M2S 0x103c275#define MT_AMPDU_MAX_LEN 0x1040276 277#define MT_WCID_DROP_BASE 0x106c278#define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4)279#define MT_WCID_DROP_MASK(_n) BIT((_n) % 32)280 281#define MT_BCN_BYPASS_MASK 0x108c282 283#define MT_MAC_APC_BSSID_BASE 0x1090284#define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8))285#define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4))286#define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)287#define MT_MAC_APC_BSSID0_H_EN BIT(16)288 289#define MT_XIFS_TIME_CFG 0x1100290#define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)291#define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)292#define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)293#define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)294#define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29)295 296#define MT_BKOFF_SLOT_CFG 0x1104297#define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)298#define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)299 300#define MT_BEACON_TIME_CFG 0x1114301#define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)302#define MT_BEACON_TIME_CFG_TIMER_EN BIT(16)303#define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)304#define MT_BEACON_TIME_CFG_TBTT_EN BIT(19)305#define MT_BEACON_TIME_CFG_BEACON_TX BIT(20)306#define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)307 308#define MT_TBTT_SYNC_CFG 0x1118309#define MT_TBTT_TIMER_CFG 0x1124310 311#define MT_INT_TIMER_CFG 0x1128312#define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)313#define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)314 315#define MT_INT_TIMER_EN 0x112c316#define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)317#define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1)318 319#define MT_MAC_STATUS 0x1200320#define MT_MAC_STATUS_TX BIT(0)321#define MT_MAC_STATUS_RX BIT(1)322 323#define MT_PWR_PIN_CFG 0x1204324#define MT_AUX_CLK_CFG 0x120c325 326#define MT_BB_PA_MODE_CFG0 0x1214327#define MT_BB_PA_MODE_CFG1 0x1218328#define MT_RF_PA_MODE_CFG0 0x121c329#define MT_RF_PA_MODE_CFG1 0x1220330 331#define MT_RF_PA_MODE_ADJ0 0x1228332#define MT_RF_PA_MODE_ADJ1 0x122c333 334#define MT_DACCLK_EN_DLY_CFG 0x1264335 336#define MT_EDCA_CFG_BASE 0x1300337#define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2))338#define MT_EDCA_CFG_TXOP GENMASK(7, 0)339#define MT_EDCA_CFG_AIFSN GENMASK(11, 8)340#define MT_EDCA_CFG_CWMIN GENMASK(15, 12)341#define MT_EDCA_CFG_CWMAX GENMASK(19, 16)342 343#define MT_TX_PWR_CFG_0 0x1314344#define MT_TX_PWR_CFG_1 0x1318345#define MT_TX_PWR_CFG_2 0x131c346#define MT_TX_PWR_CFG_3 0x1320347#define MT_TX_PWR_CFG_4 0x1324348 349#define MT_TX_BAND_CFG 0x132c350#define MT_TX_BAND_CFG_UPPER_40M BIT(0)351#define MT_TX_BAND_CFG_5G BIT(1)352#define MT_TX_BAND_CFG_2G BIT(2)353 354#define MT_HT_FBK_TO_LEGACY 0x1384355#define MT_TX_MPDU_ADJ_INT 0x1388356 357#define MT_TX_PWR_CFG_7 0x13d4358#define MT_TX_PWR_CFG_8 0x13d8359#define MT_TX_PWR_CFG_9 0x13dc360 361#define MT_TX_SW_CFG0 0x1330362#define MT_TX_SW_CFG1 0x1334363#define MT_TX_SW_CFG2 0x1338364 365#define MT_TXOP_CTRL_CFG 0x1340366#define MT_TXOP_TRUN_EN GENMASK(5, 0)367#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)368#define MT_TXOP_CTRL369 370#define MT_TX_RTS_CFG 0x1344371#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)372#define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)373#define MT_TX_RTS_FALLBACK BIT(24)374 375#define MT_TX_TIMEOUT_CFG 0x1348376#define MT_TX_RETRY_CFG 0x134c377#define MT_TX_LINK_CFG 0x1350378#define MT_HT_FBK_CFG0 0x1354379#define MT_HT_FBK_CFG1 0x1358380#define MT_LG_FBK_CFG0 0x135c381#define MT_LG_FBK_CFG1 0x1360382 383#define MT_CCK_PROT_CFG 0x1364384#define MT_OFDM_PROT_CFG 0x1368385#define MT_MM20_PROT_CFG 0x136c386#define MT_MM40_PROT_CFG 0x1370387#define MT_GF20_PROT_CFG 0x1374388#define MT_GF40_PROT_CFG 0x1378389 390#define MT_PROT_RATE GENMASK(15, 0)391#define MT_PROT_CTRL_RTS_CTS BIT(16)392#define MT_PROT_CTRL_CTS2SELF BIT(17)393#define MT_PROT_NAV_SHORT BIT(18)394#define MT_PROT_NAV_LONG BIT(19)395#define MT_PROT_TXOP_ALLOW_CCK BIT(20)396#define MT_PROT_TXOP_ALLOW_OFDM BIT(21)397#define MT_PROT_TXOP_ALLOW_MM20 BIT(22)398#define MT_PROT_TXOP_ALLOW_MM40 BIT(23)399#define MT_PROT_TXOP_ALLOW_GF20 BIT(24)400#define MT_PROT_TXOP_ALLOW_GF40 BIT(25)401#define MT_PROT_RTS_THR_EN BIT(26)402#define MT_PROT_RATE_CCK_11 0x0003403#define MT_PROT_RATE_OFDM_6 0x4000404#define MT_PROT_RATE_OFDM_24 0x4004405#define MT_PROT_RATE_DUP_OFDM_24 0x4084406#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)407#define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \408 ~MT_PROT_TXOP_ALLOW_MM40 & \409 ~MT_PROT_TXOP_ALLOW_GF40)410 411#define MT_EXP_ACK_TIME 0x1380412 413#define MT_TX_PWR_CFG_0_EXT 0x1390414#define MT_TX_PWR_CFG_1_EXT 0x1394415 416#define MT_TX_FBK_LIMIT 0x1398417#define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)418#define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)419#define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16)420#define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17)421#define MT_TX_FBK_LIMIT_RATE_LUT BIT(18)422 423#define MT_TX0_RF_GAIN_CORR 0x13a0424#define MT_TX1_RF_GAIN_CORR 0x13a4425#define MT_TX0_RF_GAIN_ATTEN 0x13a8426 427#define MT_TX_ALC_CFG_0 0x13b0428#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)429#define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)430#define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)431#define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)432 433#define MT_TX_ALC_CFG_1 0x13b4434#define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)435 436#define MT_TX_ALC_CFG_2 0x13a8437#define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)438 439#define MT_TX0_BB_GAIN_ATTEN 0x13c0440 441#define MT_TX_ALC_VGA3 0x13c8442 443#define MT_TX_PROT_CFG6 0x13e0444#define MT_TX_PROT_CFG7 0x13e4445#define MT_TX_PROT_CFG8 0x13e8446 447#define MT_PIFS_TX_CFG 0x13ec448 449#define MT_RX_FILTR_CFG 0x1400450 451#define MT_RX_FILTR_CFG_CRC_ERR BIT(0)452#define MT_RX_FILTR_CFG_PHY_ERR BIT(1)453#define MT_RX_FILTR_CFG_PROMISC BIT(2)454#define MT_RX_FILTR_CFG_OTHER_BSS BIT(3)455#define MT_RX_FILTR_CFG_VER_ERR BIT(4)456#define MT_RX_FILTR_CFG_MCAST BIT(5)457#define MT_RX_FILTR_CFG_BCAST BIT(6)458#define MT_RX_FILTR_CFG_DUP BIT(7)459#define MT_RX_FILTR_CFG_CFACK BIT(8)460#define MT_RX_FILTR_CFG_CFEND BIT(9)461#define MT_RX_FILTR_CFG_ACK BIT(10)462#define MT_RX_FILTR_CFG_CTS BIT(11)463#define MT_RX_FILTR_CFG_RTS BIT(12)464#define MT_RX_FILTR_CFG_PSPOLL BIT(13)465#define MT_RX_FILTR_CFG_BA BIT(14)466#define MT_RX_FILTR_CFG_BAR BIT(15)467#define MT_RX_FILTR_CFG_CTRL_RSV BIT(16)468 469#define MT_AUTO_RSP_CFG 0x1404470 471#define MT_AUTO_RSP_PREAMB_SHORT BIT(4)472 473#define MT_LEGACY_BASIC_RATE 0x1408474#define MT_HT_BASIC_RATE 0x140c475 476#define MT_RX_PARSER_CFG 0x1418477#define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)478 479#define MT_EXT_CCA_CFG 0x141c480#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)481#define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)482#define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)483#define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)484#define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)485#define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)486 487#define MT_TX_SW_CFG3 0x1478488 489#define MT_PN_PAD_MODE 0x150c490 491#define MT_TXOP_HLDR_ET 0x1608492 493#define MT_PROT_AUTO_TX_CFG 0x1648494 495#define MT_RX_STA_CNT0 0x1700496#define MT_RX_STA_CNT1 0x1704497#define MT_RX_STA_CNT2 0x1708498#define MT_TX_STA_CNT0 0x170c499#define MT_TX_STA_CNT1 0x1710500#define MT_TX_STA_CNT2 0x1714501 502/* Vendor driver defines content of the second word of STAT_FIFO as follows:503 * MT_TX_STAT_FIFO_RATE GENMASK(26, 16)504 * MT_TX_STAT_FIFO_ETXBF BIT(27)505 * MT_TX_STAT_FIFO_SND BIT(28)506 * MT_TX_STAT_FIFO_ITXBF BIT(29)507 * However, tests show that b16-31 have the same layout as TXWI rate_ctl508 * with rate set to rate at which frame was acked.509 */510#define MT_TX_STAT_FIFO 0x1718511#define MT_TX_STAT_FIFO_VALID BIT(0)512#define MT_TX_STAT_FIFO_PID_TYPE GENMASK(4, 1)513#define MT_TX_STAT_FIFO_SUCCESS BIT(5)514#define MT_TX_STAT_FIFO_AGGR BIT(6)515#define MT_TX_STAT_FIFO_ACKREQ BIT(7)516#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)517#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)518 519#define MT_TX_AGG_STAT 0x171c520 521#define MT_TX_AGG_CNT_BASE0 0x1720522 523#define MT_MPDU_DENSITY_CNT 0x1740524 525#define MT_TX_AGG_CNT_BASE1 0x174c526 527#define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \528 MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \529 MT_TX_AGG_CNT_BASE1 + ((_id - 8) << 2))530 531#define MT_TX_STAT_FIFO_EXT 0x1798532#define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)533 534#define MT_BBP_CORE_BASE 0x2000535#define MT_BBP_IBI_BASE 0x2100536#define MT_BBP_AGC_BASE 0x2300537#define MT_BBP_TXC_BASE 0x2400538#define MT_BBP_RXC_BASE 0x2500539#define MT_BBP_TXO_BASE 0x2600540#define MT_BBP_TXBE_BASE 0x2700541#define MT_BBP_RXFE_BASE 0x2800542#define MT_BBP_RXO_BASE 0x2900543#define MT_BBP_DFS_BASE 0x2a00544#define MT_BBP_TR_BASE 0x2b00545#define MT_BBP_CAL_BASE 0x2c00546#define MT_BBP_DSC_BASE 0x2e00547#define MT_BBP_PFMU_BASE 0x2f00548 549#define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2))550 551#define MT_BBP_CORE_R1_BW GENMASK(4, 3)552 553#define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)554#define MT_BBP_AGC_R0_BW GENMASK(14, 12)555 556/* AGC, R4/R5 */557#define MT_BBP_AGC_LNA_GAIN GENMASK(21, 16)558 559/* AGC, R8/R9 */560#define MT_BBP_AGC_GAIN GENMASK(14, 8)561 562#define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)563#define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)564 565#define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)566 567#define MT_WCID_ADDR_BASE 0x1800568#define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8)569 570#define MT_SRAM_BASE 0x4000571 572#define MT_WCID_KEY_BASE 0x8000573#define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32)574 575#define MT_WCID_IV_BASE 0xa000576#define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8)577 578#define MT_WCID_ATTR_BASE 0xa800579#define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4)580 581#define MT_WCID_ATTR_PAIRWISE BIT(0)582#define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)583#define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)584#define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)585#define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10)586#define MT_WCID_ATTR_BSS_IDX_EXT BIT(11)587#define MT_WCID_ATTR_WAPI_MCBC BIT(15)588#define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)589 590#define MT_SKEY_BASE_0 0xac00591#define MT_SKEY_BASE_1 0xb400592#define MT_SKEY_0(_bss, _idx) \593 (MT_SKEY_BASE_0 + (4 * (_bss) + _idx) * 32)594#define MT_SKEY_1(_bss, _idx) \595 (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + _idx) * 32)596#define MT_SKEY(_bss, _idx) \597 ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx))598 599#define MT_SKEY_MODE_BASE_0 0xb000600#define MT_SKEY_MODE_BASE_1 0xb3f0601#define MT_SKEY_MODE_0(_bss) \602 (MT_SKEY_MODE_BASE_0 + ((_bss / 2) << 2))603#define MT_SKEY_MODE_1(_bss) \604 (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2))605#define MT_SKEY_MODE(_bss) \606 ((_bss & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss))607#define MT_SKEY_MODE_MASK GENMASK(3, 0)608#define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * (_bss & 1)))609 610#define MT_BEACON_BASE 0xc000611 612#define MT_TEMP_SENSOR 0x1d000613#define MT_TEMP_SENSOR_VAL GENMASK(6, 0)614 615enum mt76_cipher_type {616 MT_CIPHER_NONE,617 MT_CIPHER_WEP40,618 MT_CIPHER_WEP104,619 MT_CIPHER_TKIP,620 MT_CIPHER_AES_CCMP,621 MT_CIPHER_CKIP40,622 MT_CIPHER_CKIP104,623 MT_CIPHER_CKIP128,624 MT_CIPHER_WAPI,625};626 627#endif628