1069 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>4 <http://rt2x00.serialmonkey.com>5 6 */7 8/*9 Module: rt73usb10 Abstract: Data structures and registers for the rt73usb module.11 Supported chipsets: rt2571W & rt2671.12 */13 14#ifndef RT73USB_H15#define RT73USB_H16 17/*18 * RF chip defines.19 */20#define RF5226 0x000121#define RF2528 0x000222#define RF5225 0x000323#define RF2527 0x000424 25/*26 * Signal information.27 * Default offset is required for RSSI <-> dBm conversion.28 */29#define DEFAULT_RSSI_OFFSET 12030 31/*32 * Register layout information.33 */34#define CSR_REG_BASE 0x300035#define CSR_REG_SIZE 0x04b036#define EEPROM_BASE 0x000037#define EEPROM_SIZE 0x010038#define BBP_BASE 0x000039#define BBP_SIZE 0x008040#define RF_BASE 0x000441#define RF_SIZE 0x001042 43/*44 * Number of TX queues.45 */46#define NUM_TX_QUEUES 447 48/*49 * USB registers.50 */51 52/*53 * MCU_LEDCS: LED control for MCU Mailbox.54 */55#define MCU_LEDCS_LED_MODE FIELD16(0x001f)56#define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)57#define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)58#define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)59#define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)60#define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)61#define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)62#define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)63#define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)64#define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)65#define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)66#define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)67 68/*69 * 8051 firmware image.70 */71#define FIRMWARE_RT2571 "rt73.bin"72#define FIRMWARE_IMAGE_BASE 0x080073 74/*75 * Security key table memory.76 * 16 entries 32-byte for shared key table77 * 64 entries 32-byte for pairwise key table78 * 64 entries 8-byte for pairwise ta key table79 */80#define SHARED_KEY_TABLE_BASE 0x100081#define PAIRWISE_KEY_TABLE_BASE 0x120082#define PAIRWISE_TA_TABLE_BASE 0x1a0083 84#define SHARED_KEY_ENTRY(__idx) \85 ( SHARED_KEY_TABLE_BASE + \86 ((__idx) * sizeof(struct hw_key_entry)) )87#define PAIRWISE_KEY_ENTRY(__idx) \88 ( PAIRWISE_KEY_TABLE_BASE + \89 ((__idx) * sizeof(struct hw_key_entry)) )90#define PAIRWISE_TA_ENTRY(__idx) \91 ( PAIRWISE_TA_TABLE_BASE + \92 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )93 94struct hw_key_entry {95 u8 key[16];96 u8 tx_mic[8];97 u8 rx_mic[8];98} __packed;99 100struct hw_pairwise_ta_entry {101 u8 address[6];102 u8 cipher;103 u8 reserved;104} __packed;105 106/*107 * Since NULL frame won't be that long (256 byte),108 * We steal 16 tail bytes to save debugging settings.109 */110#define HW_DEBUG_SETTING_BASE 0x2bf0111 112/*113 * On-chip BEACON frame space.114 */115#define HW_BEACON_BASE0 0x2400116#define HW_BEACON_BASE1 0x2500117#define HW_BEACON_BASE2 0x2600118#define HW_BEACON_BASE3 0x2700119 120#define HW_BEACON_OFFSET(__index) \121 ( HW_BEACON_BASE0 + (__index * 0x0100) )122 123/*124 * MAC Control/Status Registers(CSR).125 * Some values are set in TU, whereas 1 TU == 1024 us.126 */127 128/*129 * MAC_CSR0: ASIC revision number.130 */131#define MAC_CSR0 0x3000132#define MAC_CSR0_REVISION FIELD32(0x0000000f)133#define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)134 135/*136 * MAC_CSR1: System control register.137 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.138 * BBP_RESET: Hardware reset BBP.139 * HOST_READY: Host is ready after initialization, 1: ready.140 */141#define MAC_CSR1 0x3004142#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)143#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)144#define MAC_CSR1_HOST_READY FIELD32(0x00000004)145 146/*147 * MAC_CSR2: STA MAC register 0.148 */149#define MAC_CSR2 0x3008150#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)151#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)152#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)153#define MAC_CSR2_BYTE3 FIELD32(0xff000000)154 155/*156 * MAC_CSR3: STA MAC register 1.157 * UNICAST_TO_ME_MASK:158 * Used to mask off bits from byte 5 of the MAC address159 * to determine the UNICAST_TO_ME bit for RX frames.160 * The full mask is complemented by BSS_ID_MASK:161 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK162 */163#define MAC_CSR3 0x300c164#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)165#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)166#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)167 168/*169 * MAC_CSR4: BSSID register 0.170 */171#define MAC_CSR4 0x3010172#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)173#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)174#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)175#define MAC_CSR4_BYTE3 FIELD32(0xff000000)176 177/*178 * MAC_CSR5: BSSID register 1.179 * BSS_ID_MASK:180 * This mask is used to mask off bits 0 and 1 of byte 5 of the181 * BSSID. This will make sure that those bits will be ignored182 * when determining the MY_BSS of RX frames.183 * 0: 1-BSSID mode (BSS index = 0)184 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)185 * 2: 2-BSSID mode (BSS index: byte5, bit 1)186 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)187 */188#define MAC_CSR5 0x3014189#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)190#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)191#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)192 193/*194 * MAC_CSR6: Maximum frame length register.195 */196#define MAC_CSR6 0x3018197#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)198 199/*200 * MAC_CSR7: Reserved201 */202#define MAC_CSR7 0x301c203 204/*205 * MAC_CSR8: SIFS/EIFS register.206 * All units are in US.207 */208#define MAC_CSR8 0x3020209#define MAC_CSR8_SIFS FIELD32(0x000000ff)210#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)211#define MAC_CSR8_EIFS FIELD32(0xffff0000)212 213/*214 * MAC_CSR9: Back-Off control register.215 * SLOT_TIME: Slot time, default is 20us for 802.11BG.216 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).217 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).218 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.219 */220#define MAC_CSR9 0x3024221#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)222#define MAC_CSR9_CWMIN FIELD32(0x00000f00)223#define MAC_CSR9_CWMAX FIELD32(0x0000f000)224#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)225 226/*227 * MAC_CSR10: Power state configuration.228 */229#define MAC_CSR10 0x3028230 231/*232 * MAC_CSR11: Power saving transition time register.233 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.234 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.235 * WAKEUP_LATENCY: In unit of TU.236 */237#define MAC_CSR11 0x302c238#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)239#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)240#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)241#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)242 243/*244 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).245 * CURRENT_STATE: 0:sleep, 1:awake.246 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.247 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.248 */249#define MAC_CSR12 0x3030250#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)251#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)252#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)253#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)254 255/*256 * MAC_CSR13: GPIO.257 * MAC_CSR13_VALx: GPIO value258 * MAC_CSR13_DIRx: GPIO direction: 0 = input; 1 = output259 */260#define MAC_CSR13 0x3034261#define MAC_CSR13_VAL0 FIELD32(0x00000001)262#define MAC_CSR13_VAL1 FIELD32(0x00000002)263#define MAC_CSR13_VAL2 FIELD32(0x00000004)264#define MAC_CSR13_VAL3 FIELD32(0x00000008)265#define MAC_CSR13_VAL4 FIELD32(0x00000010)266#define MAC_CSR13_VAL5 FIELD32(0x00000020)267#define MAC_CSR13_VAL6 FIELD32(0x00000040)268#define MAC_CSR13_VAL7 FIELD32(0x00000080)269#define MAC_CSR13_DIR0 FIELD32(0x00000100)270#define MAC_CSR13_DIR1 FIELD32(0x00000200)271#define MAC_CSR13_DIR2 FIELD32(0x00000400)272#define MAC_CSR13_DIR3 FIELD32(0x00000800)273#define MAC_CSR13_DIR4 FIELD32(0x00001000)274#define MAC_CSR13_DIR5 FIELD32(0x00002000)275#define MAC_CSR13_DIR6 FIELD32(0x00004000)276#define MAC_CSR13_DIR7 FIELD32(0x00008000)277 278/*279 * MAC_CSR14: LED control register.280 * ON_PERIOD: On period, default 70ms.281 * OFF_PERIOD: Off period, default 30ms.282 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.283 * SW_LED: s/w LED, 1: ON, 0: OFF.284 * HW_LED_POLARITY: 0: active low, 1: active high.285 */286#define MAC_CSR14 0x3038287#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)288#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)289#define MAC_CSR14_HW_LED FIELD32(0x00010000)290#define MAC_CSR14_SW_LED FIELD32(0x00020000)291#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)292#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)293 294/*295 * MAC_CSR15: NAV control.296 */297#define MAC_CSR15 0x303c298 299/*300 * TXRX control registers.301 * Some values are set in TU, whereas 1 TU == 1024 us.302 */303 304/*305 * TXRX_CSR0: TX/RX configuration register.306 * TSF_OFFSET: Default is 24.307 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.308 * DISABLE_RX: Disable Rx engine.309 * DROP_CRC: Drop CRC error.310 * DROP_PHYSICAL: Drop physical error.311 * DROP_CONTROL: Drop control frame.312 * DROP_NOT_TO_ME: Drop not to me unicast frame.313 * DROP_TO_DS: Drop fram ToDs bit is true.314 * DROP_VERSION_ERROR: Drop version error frame.315 * DROP_MULTICAST: Drop multicast frames.316 * DROP_BORADCAST: Drop broadcast frames.317 * DROP_ACK_CTS: Drop received ACK and CTS.318 */319#define TXRX_CSR0 0x3040320#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)321#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)322#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)323#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)324#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)325#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)326#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)327#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)328#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)329#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)330#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)331#define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)332#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)333#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)334 335/*336 * TXRX_CSR1337 */338#define TXRX_CSR1 0x3044339#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)340#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)341#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)342#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)343#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)344#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)345#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)346#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)347 348/*349 * TXRX_CSR2350 */351#define TXRX_CSR2 0x3048352#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)353#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)354#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)355#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)356#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)357#define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)358#define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)359#define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)360 361/*362 * TXRX_CSR3363 */364#define TXRX_CSR3 0x304c365#define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)366#define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)367#define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)368#define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)369#define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)370#define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)371#define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)372#define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)373 374/*375 * TXRX_CSR4: Auto-Responder/Tx-retry register.376 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.377 * OFDM_TX_RATE_DOWN: 1:enable.378 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.379 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.380 */381#define TXRX_CSR4 0x3050382#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)383#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)384#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)385#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)386#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)387#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)388#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)389#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)390#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)391#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)392 393/*394 * TXRX_CSR5395 */396#define TXRX_CSR5 0x3054397 398/*399 * TXRX_CSR6: ACK/CTS payload consumed time400 */401#define TXRX_CSR6 0x3058402 403/*404 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.405 */406#define TXRX_CSR7 0x305c407#define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)408#define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)409#define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)410#define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)411 412/*413 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.414 */415#define TXRX_CSR8 0x3060416#define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)417#define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)418#define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)419#define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)420 421/*422 * TXRX_CSR9: Synchronization control register.423 * BEACON_INTERVAL: In unit of 1/16 TU.424 * TSF_TICKING: Enable TSF auto counting.425 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.426 * BEACON_GEN: Enable beacon generator.427 */428#define TXRX_CSR9 0x3064429#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)430#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)431#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)432#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)433#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)434#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)435 436/*437 * TXRX_CSR10: BEACON alignment.438 */439#define TXRX_CSR10 0x3068440 441/*442 * TXRX_CSR11: AES mask.443 */444#define TXRX_CSR11 0x306c445 446/*447 * TXRX_CSR12: TSF low 32.448 */449#define TXRX_CSR12 0x3070450#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)451 452/*453 * TXRX_CSR13: TSF high 32.454 */455#define TXRX_CSR13 0x3074456#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)457 458/*459 * TXRX_CSR14: TBTT timer.460 */461#define TXRX_CSR14 0x3078462 463/*464 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.465 */466#define TXRX_CSR15 0x307c467 468/*469 * PHY control registers.470 * Some values are set in TU, whereas 1 TU == 1024 us.471 */472 473/*474 * PHY_CSR0: RF/PS control.475 */476#define PHY_CSR0 0x3080477#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)478#define PHY_CSR0_PA_PE_A FIELD32(0x00020000)479 480/*481 * PHY_CSR1482 */483#define PHY_CSR1 0x3084484#define PHY_CSR1_RF_RPI FIELD32(0x00010000)485 486/*487 * PHY_CSR2: Pre-TX BBP control.488 */489#define PHY_CSR2 0x3088490 491/*492 * PHY_CSR3: BBP serial control register.493 * VALUE: Register value to program into BBP.494 * REG_NUM: Selected BBP register.495 * READ_CONTROL: 0: Write BBP, 1: Read BBP.496 * BUSY: 1: ASIC is busy execute BBP programming.497 */498#define PHY_CSR3 0x308c499#define PHY_CSR3_VALUE FIELD32(0x000000ff)500#define PHY_CSR3_REGNUM FIELD32(0x00007f00)501#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)502#define PHY_CSR3_BUSY FIELD32(0x00010000)503 504/*505 * PHY_CSR4: RF serial control register506 * VALUE: Register value (include register id) serial out to RF/IF chip.507 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).508 * IF_SELECT: 1: select IF to program, 0: select RF to program.509 * PLL_LD: RF PLL_LD status.510 * BUSY: 1: ASIC is busy execute RF programming.511 */512#define PHY_CSR4 0x3090513#define PHY_CSR4_VALUE FIELD32(0x00ffffff)514#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)515#define PHY_CSR4_IF_SELECT FIELD32(0x20000000)516#define PHY_CSR4_PLL_LD FIELD32(0x40000000)517#define PHY_CSR4_BUSY FIELD32(0x80000000)518 519/*520 * PHY_CSR5: RX to TX signal switch timing control.521 */522#define PHY_CSR5 0x3094523#define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)524 525/*526 * PHY_CSR6: TX to RX signal timing control.527 */528#define PHY_CSR6 0x3098529#define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)530 531/*532 * PHY_CSR7: TX DAC switching timing control.533 */534#define PHY_CSR7 0x309c535 536/*537 * Security control register.538 */539 540/*541 * SEC_CSR0: Shared key table control.542 */543#define SEC_CSR0 0x30a0544#define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)545#define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)546#define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)547#define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)548#define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)549#define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)550#define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)551#define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)552#define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)553#define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)554#define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)555#define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)556#define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)557#define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)558#define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)559#define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)560 561/*562 * SEC_CSR1: Shared key table security mode register.563 */564#define SEC_CSR1 0x30a4565#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)566#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)567#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)568#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)569#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)570#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)571#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)572#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)573 574/*575 * Pairwise key table valid bitmap registers.576 * SEC_CSR2: pairwise key table valid bitmap 0.577 * SEC_CSR3: pairwise key table valid bitmap 1.578 */579#define SEC_CSR2 0x30a8580#define SEC_CSR3 0x30ac581 582/*583 * SEC_CSR4: Pairwise key table lookup control.584 */585#define SEC_CSR4 0x30b0586#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)587#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)588#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)589#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)590 591/*592 * SEC_CSR5: shared key table security mode register.593 */594#define SEC_CSR5 0x30b4595#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)596#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)597#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)598#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)599#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)600#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)601#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)602#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)603 604/*605 * STA control registers.606 */607 608/*609 * STA_CSR0: RX PLCP error count & RX FCS error count.610 */611#define STA_CSR0 0x30c0612#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)613#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)614 615/*616 * STA_CSR1: RX False CCA count & RX LONG frame count.617 */618#define STA_CSR1 0x30c4619#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)620#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)621 622/*623 * STA_CSR2: TX Beacon count and RX FIFO overflow count.624 */625#define STA_CSR2 0x30c8626#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)627#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)628 629/*630 * STA_CSR3: TX Beacon count.631 */632#define STA_CSR3 0x30cc633#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)634 635/*636 * STA_CSR4: TX Retry count.637 */638#define STA_CSR4 0x30d0639#define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)640#define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)641 642/*643 * STA_CSR5: TX Retry count.644 */645#define STA_CSR5 0x30d4646#define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)647#define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)648 649/*650 * QOS control registers.651 */652 653/*654 * QOS_CSR1: TXOP holder MAC address register.655 */656#define QOS_CSR1 0x30e4657#define QOS_CSR1_BYTE4 FIELD32(0x000000ff)658#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)659 660/*661 * QOS_CSR2: TXOP holder timeout register.662 */663#define QOS_CSR2 0x30e8664 665/*666 * RX QOS-CFPOLL MAC address register.667 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.668 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.669 */670#define QOS_CSR3 0x30ec671#define QOS_CSR4 0x30f0672 673/*674 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.675 */676#define QOS_CSR5 0x30f4677 678/*679 * WMM Scheduler Register680 */681 682/*683 * AIFSN_CSR: AIFSN for each EDCA AC.684 * AIFSN0: For AC_VO.685 * AIFSN1: For AC_VI.686 * AIFSN2: For AC_BE.687 * AIFSN3: For AC_BK.688 */689#define AIFSN_CSR 0x0400690#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)691#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)692#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)693#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)694 695/*696 * CWMIN_CSR: CWmin for each EDCA AC.697 * CWMIN0: For AC_VO.698 * CWMIN1: For AC_VI.699 * CWMIN2: For AC_BE.700 * CWMIN3: For AC_BK.701 */702#define CWMIN_CSR 0x0404703#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)704#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)705#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)706#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)707 708/*709 * CWMAX_CSR: CWmax for each EDCA AC.710 * CWMAX0: For AC_VO.711 * CWMAX1: For AC_VI.712 * CWMAX2: For AC_BE.713 * CWMAX3: For AC_BK.714 */715#define CWMAX_CSR 0x0408716#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)717#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)718#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)719#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)720 721/*722 * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.723 * AC0_TX_OP: For AC_VO, in unit of 32us.724 * AC1_TX_OP: For AC_VI, in unit of 32us.725 */726#define AC_TXOP_CSR0 0x040c727#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)728#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)729 730/*731 * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.732 * AC2_TX_OP: For AC_BE, in unit of 32us.733 * AC3_TX_OP: For AC_BK, in unit of 32us.734 */735#define AC_TXOP_CSR1 0x0410736#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)737#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)738 739/*740 * BBP registers.741 * The wordsize of the BBP is 8 bits.742 */743 744/*745 * R2746 */747#define BBP_R2_BG_MODE FIELD8(0x20)748 749/*750 * R3751 */752#define BBP_R3_SMART_MODE FIELD8(0x01)753 754/*755 * R4: RX antenna control756 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)757 */758 759/*760 * ANTENNA_CONTROL semantics (guessed):761 * 0x1: Software controlled antenna switching (fixed or SW diversity)762 * 0x2: Hardware diversity.763 */764#define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)765#define BBP_R4_RX_FRAME_END FIELD8(0x20)766 767/*768 * R77769 */770#define BBP_R77_RX_ANTENNA FIELD8(0x03)771 772/*773 * RF registers774 */775 776/*777 * RF 3778 */779#define RF3_TXPOWER FIELD32(0x00003e00)780 781/*782 * RF 4783 */784#define RF4_FREQ_OFFSET FIELD32(0x0003f000)785 786/*787 * EEPROM content.788 * The wordsize of the EEPROM is 16 bits.789 */790 791/*792 * HW MAC address.793 */794#define EEPROM_MAC_ADDR_0 0x0002795#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)796#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)797#define EEPROM_MAC_ADDR1 0x0003798#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)799#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)800#define EEPROM_MAC_ADDR_2 0x0004801#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)802#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)803 804/*805 * EEPROM antenna.806 * ANTENNA_NUM: Number of antennas.807 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.808 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.809 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.810 * DYN_TXAGC: Dynamic TX AGC control.811 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.812 * RF_TYPE: Rf_type of this adapter.813 */814#define EEPROM_ANTENNA 0x0010815#define EEPROM_ANTENNA_NUM FIELD16(0x0003)816#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)817#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)818#define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)819#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)820#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)821#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)822 823/*824 * EEPROM NIC config.825 * EXTERNAL_LNA: External LNA.826 */827#define EEPROM_NIC 0x0011828#define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)829 830/*831 * EEPROM geography.832 * GEO_A: Default geographical setting for 5GHz band833 * GEO: Default geographical setting.834 */835#define EEPROM_GEOGRAPHY 0x0012836#define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)837#define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)838 839/*840 * EEPROM BBP.841 */842#define EEPROM_BBP_START 0x0013843#define EEPROM_BBP_SIZE 16844#define EEPROM_BBP_VALUE FIELD16(0x00ff)845#define EEPROM_BBP_REG_ID FIELD16(0xff00)846 847/*848 * EEPROM TXPOWER 802.11G849 */850#define EEPROM_TXPOWER_G_START 0x0023851#define EEPROM_TXPOWER_G_SIZE 7852#define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)853#define EEPROM_TXPOWER_G_2 FIELD16(0xff00)854 855/*856 * EEPROM Frequency857 */858#define EEPROM_FREQ 0x002f859#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)860#define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)861#define EEPROM_FREQ_SEQ FIELD16(0x0300)862 863/*864 * EEPROM LED.865 * POLARITY_RDY_G: Polarity RDY_G setting.866 * POLARITY_RDY_A: Polarity RDY_A setting.867 * POLARITY_ACT: Polarity ACT setting.868 * POLARITY_GPIO_0: Polarity GPIO0 setting.869 * POLARITY_GPIO_1: Polarity GPIO1 setting.870 * POLARITY_GPIO_2: Polarity GPIO2 setting.871 * POLARITY_GPIO_3: Polarity GPIO3 setting.872 * POLARITY_GPIO_4: Polarity GPIO4 setting.873 * LED_MODE: Led mode.874 */875#define EEPROM_LED 0x0030876#define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)877#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)878#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)879#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)880#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)881#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)882#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)883#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)884#define EEPROM_LED_LED_MODE FIELD16(0x1f00)885 886/*887 * EEPROM TXPOWER 802.11A888 */889#define EEPROM_TXPOWER_A_START 0x0031890#define EEPROM_TXPOWER_A_SIZE 12891#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)892#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)893 894/*895 * EEPROM RSSI offset 802.11BG896 */897#define EEPROM_RSSI_OFFSET_BG 0x004d898#define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)899#define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)900 901/*902 * EEPROM RSSI offset 802.11A903 */904#define EEPROM_RSSI_OFFSET_A 0x004e905#define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)906#define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)907 908/*909 * DMA descriptor defines.910 */911#define TXD_DESC_SIZE ( 6 * sizeof(__le32) )912#define TXINFO_SIZE ( 6 * sizeof(__le32) )913#define RXD_DESC_SIZE ( 6 * sizeof(__le32) )914 915/*916 * TX descriptor format for TX, PRIO and Beacon Ring.917 */918 919/*920 * Word0921 * BURST: Next frame belongs to same "burst" event.922 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.923 * KEY_TABLE: Use per-client pairwise KEY table.924 * KEY_INDEX:925 * Key index (0~31) to the pairwise KEY table.926 * 0~3 to shared KEY table 0 (BSS0).927 * 4~7 to shared KEY table 1 (BSS1).928 * 8~11 to shared KEY table 2 (BSS2).929 * 12~15 to shared KEY table 3 (BSS3).930 * BURST2: For backward compatibility, set to same value as BURST.931 */932#define TXD_W0_BURST FIELD32(0x00000001)933#define TXD_W0_VALID FIELD32(0x00000002)934#define TXD_W0_MORE_FRAG FIELD32(0x00000004)935#define TXD_W0_ACK FIELD32(0x00000008)936#define TXD_W0_TIMESTAMP FIELD32(0x00000010)937#define TXD_W0_OFDM FIELD32(0x00000020)938#define TXD_W0_IFS FIELD32(0x00000040)939#define TXD_W0_RETRY_MODE FIELD32(0x00000080)940#define TXD_W0_TKIP_MIC FIELD32(0x00000100)941#define TXD_W0_KEY_TABLE FIELD32(0x00000200)942#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)943#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)944#define TXD_W0_BURST2 FIELD32(0x10000000)945#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)946 947/*948 * Word1949 * HOST_Q_ID: EDCA/HCCA queue ID.950 * HW_SEQUENCE: MAC overwrites the frame sequence number.951 * BUFFER_COUNT: Number of buffers in this TXD.952 */953#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)954#define TXD_W1_AIFSN FIELD32(0x000000f0)955#define TXD_W1_CWMIN FIELD32(0x00000f00)956#define TXD_W1_CWMAX FIELD32(0x0000f000)957#define TXD_W1_IV_OFFSET FIELD32(0x003f0000)958#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)959#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)960 961/*962 * Word2: PLCP information963 */964#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)965#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)966#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)967#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)968 969/*970 * Word3971 */972#define TXD_W3_IV FIELD32(0xffffffff)973 974/*975 * Word4976 */977#define TXD_W4_EIV FIELD32(0xffffffff)978 979/*980 * Word5981 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).982 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.983 * WAITING_DMA_DONE_INT: TXD been filled with data984 * and waiting for TxDoneISR housekeeping.985 */986#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)987#define TXD_W5_PACKET_ID FIELD32(0x0000ff00)988#define TXD_W5_TX_POWER FIELD32(0x00ff0000)989#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)990 991/*992 * RX descriptor format for RX Ring.993 */994 995/*996 * Word0997 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.998 * KEY_INDEX: Decryption key actually used.999 */1000#define RXD_W0_OWNER_NIC FIELD32(0x00000001)1001#define RXD_W0_DROP FIELD32(0x00000002)1002#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)1003#define RXD_W0_MULTICAST FIELD32(0x00000008)1004#define RXD_W0_BROADCAST FIELD32(0x00000010)1005#define RXD_W0_MY_BSS FIELD32(0x00000020)1006#define RXD_W0_CRC_ERROR FIELD32(0x00000040)1007#define RXD_W0_OFDM FIELD32(0x00000080)1008#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)1009#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)1010#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)1011#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)1012 1013/*1014 * WORD11015 * SIGNAL: RX raw data rate reported by BBP.1016 * RSSI: RSSI reported by BBP.1017 */1018#define RXD_W1_SIGNAL FIELD32(0x000000ff)1019#define RXD_W1_RSSI_AGC FIELD32(0x00001f00)1020#define RXD_W1_RSSI_LNA FIELD32(0x00006000)1021#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)1022 1023/*1024 * Word21025 * IV: Received IV of originally encrypted.1026 */1027#define RXD_W2_IV FIELD32(0xffffffff)1028 1029/*1030 * Word31031 * EIV: Received EIV of originally encrypted.1032 */1033#define RXD_W3_EIV FIELD32(0xffffffff)1034 1035/*1036 * Word41037 * ICV: Received ICV of originally encrypted.1038 * NOTE: This is a guess, the official definition is "reserved"1039 */1040#define RXD_W4_ICV FIELD32(0xffffffff)1041 1042/*1043 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block1044 * and passed to the HOST driver.1045 * The following fields are for DMA block and HOST usage only.1046 * Can't be touched by ASIC MAC block.1047 */1048 1049/*1050 * Word51051 */1052#define RXD_W5_RESERVED FIELD32(0xffffffff)1053 1054/*1055 * Macros for converting txpower from EEPROM to mac80211 value1056 * and from mac80211 value to register value.1057 */1058#define MIN_TXPOWER 01059#define MAX_TXPOWER 311060#define DEFAULT_TXPOWER 241061 1062#define TXPOWER_FROM_DEV(__txpower) \1063 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)1064 1065#define TXPOWER_TO_DEV(__txpower) \1066 clamp_t(u8, __txpower, MIN_TXPOWER, MAX_TXPOWER)1067 1068#endif /* RT73USB_H */1069