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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Definitions for RTL818x hardware4 *5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>7 *8 * Based on the r8187 driver, which is:9 * Copyright 2005 Andrea Merello <andrea.merello@gmail.com>, et al.10 */11 12#ifndef RTL818X_H13#define RTL818X_H14 15struct rtl818x_csr {16 17 u8 MAC[6];18 u8 reserved_0[2];19 20 union {21 __le32 MAR[2]; /* 0x8 */22 23 struct{ /* rtl8187se */24 u8 rf_sw_config; /* 0x8 */25 u8 reserved_01[3];26 __le32 TMGDA; /* 0xc */27 } __packed;28 } __packed;29 30 union { /* 0x10 */31 struct {32 u8 RX_FIFO_COUNT;33 u8 reserved_1;34 u8 TX_FIFO_COUNT;35 u8 BQREQ;36 } __packed;37 38 __le32 TBKDA; /* for 8187se */39 } __packed;40 41 __le32 TBEDA; /* 0x14 - for rtl8187se */42 43 __le32 TSFT[2];44 45 union { /* 0x20 */46 __le32 TLPDA;47 __le32 TVIDA; /* for 8187se */48 } __packed;49 50 union { /* 0x24 */51 __le32 TNPDA;52 __le32 TVODA; /* for 8187se */53 } __packed;54 55 /* hi pri ring for all cards */56 __le32 THPDA; /* 0x28 */57 58 union { /* 0x2c */59 struct {60 u8 reserved_2a;61 u8 EIFS_8187SE;62 } __packed;63 64 __le16 BRSR;65 } __packed;66 67 u8 BSSID[6]; /* 0x2e */68 69 union { /* 0x34 */70 struct {71 u8 RESP_RATE;72 u8 EIFS;73 } __packed;74 __le16 BRSR_8187SE;75 } __packed;76 77 u8 reserved_3[1]; /* 0x36 */78 u8 CMD; /* 0x37 */79#define RTL818X_CMD_TX_ENABLE (1 << 2)80#define RTL818X_CMD_RX_ENABLE (1 << 3)81#define RTL818X_CMD_RESET (1 << 4)82 u8 reserved_4[4]; /* 0x38 */83 union {84 struct {85 __le16 INT_MASK;86 __le16 INT_STATUS;87 } __packed;88 89 __le32 INT_STATUS_SE; /* 0x3c */90 } __packed;91/* status bits for rtl8187 and rtl8180/8185 */92#define RTL818X_INT_RX_OK (1 << 0)93#define RTL818X_INT_RX_ERR (1 << 1)94#define RTL818X_INT_TXL_OK (1 << 2)95#define RTL818X_INT_TXL_ERR (1 << 3)96#define RTL818X_INT_RX_DU (1 << 4)97#define RTL818X_INT_RX_FO (1 << 5)98#define RTL818X_INT_TXN_OK (1 << 6)99#define RTL818X_INT_TXN_ERR (1 << 7)100#define RTL818X_INT_TXH_OK (1 << 8)101#define RTL818X_INT_TXH_ERR (1 << 9)102#define RTL818X_INT_TXB_OK (1 << 10)103#define RTL818X_INT_TXB_ERR (1 << 11)104#define RTL818X_INT_ATIM (1 << 12)105#define RTL818X_INT_BEACON (1 << 13)106#define RTL818X_INT_TIME_OUT (1 << 14)107#define RTL818X_INT_TX_FO (1 << 15)108/* status bits for rtl8187se */109#define RTL818X_INT_SE_TIMER3 (1 << 0)110#define RTL818X_INT_SE_TIMER2 (1 << 1)111#define RTL818X_INT_SE_RQ0SOR (1 << 2)112#define RTL818X_INT_SE_TXBED_OK (1 << 3)113#define RTL818X_INT_SE_TXBED_ERR (1 << 4)114#define RTL818X_INT_SE_TXBE_OK (1 << 5)115#define RTL818X_INT_SE_TXBE_ERR (1 << 6)116#define RTL818X_INT_SE_RX_OK (1 << 7)117#define RTL818X_INT_SE_RX_ERR (1 << 8)118#define RTL818X_INT_SE_TXL_OK (1 << 9)119#define RTL818X_INT_SE_TXL_ERR (1 << 10)120#define RTL818X_INT_SE_RX_DU (1 << 11)121#define RTL818X_INT_SE_RX_FIFO (1 << 12)122#define RTL818X_INT_SE_TXN_OK (1 << 13)123#define RTL818X_INT_SE_TXN_ERR (1 << 14)124#define RTL818X_INT_SE_TXH_OK (1 << 15)125#define RTL818X_INT_SE_TXH_ERR (1 << 16)126#define RTL818X_INT_SE_TXB_OK (1 << 17)127#define RTL818X_INT_SE_TXB_ERR (1 << 18)128#define RTL818X_INT_SE_ATIM_TO (1 << 19)129#define RTL818X_INT_SE_BK_TO (1 << 20)130#define RTL818X_INT_SE_TIMER1 (1 << 21)131#define RTL818X_INT_SE_TX_FIFO (1 << 22)132#define RTL818X_INT_SE_WAKEUP (1 << 23)133#define RTL818X_INT_SE_BK_DMA (1 << 24)134#define RTL818X_INT_SE_TMGD_OK (1 << 30)135 __le32 TX_CONF; /* 0x40 */136#define RTL818X_TX_CONF_LOOPBACK_MAC (1 << 17)137#define RTL818X_TX_CONF_LOOPBACK_CONT (3 << 17)138#define RTL818X_TX_CONF_NO_ICV (1 << 19)139#define RTL818X_TX_CONF_DISCW (1 << 20)140#define RTL818X_TX_CONF_SAT_HWPLCP (1 << 24)141#define RTL818X_TX_CONF_R8180_ABCD (2 << 25)142#define RTL818X_TX_CONF_R8180_F (3 << 25)143#define RTL818X_TX_CONF_R8185_ABC (4 << 25)144#define RTL818X_TX_CONF_R8185_D (5 << 25)145#define RTL818X_TX_CONF_R8187vD (5 << 25)146#define RTL818X_TX_CONF_R8187vD_B (6 << 25)147#define RTL818X_TX_CONF_RTL8187SE (6 << 25)148#define RTL818X_TX_CONF_HWVER_MASK (7 << 25)149#define RTL818X_TX_CONF_DISREQQSIZE (1 << 28)150#define RTL818X_TX_CONF_PROBE_DTS (1 << 29)151#define RTL818X_TX_CONF_HW_SEQNUM (1 << 30)152#define RTL818X_TX_CONF_CW_MIN (1 << 31)153 __le32 RX_CONF;154#define RTL818X_RX_CONF_MONITOR (1 << 0)155#define RTL818X_RX_CONF_NICMAC (1 << 1)156#define RTL818X_RX_CONF_MULTICAST (1 << 2)157#define RTL818X_RX_CONF_BROADCAST (1 << 3)158#define RTL818X_RX_CONF_FCS (1 << 5)159#define RTL818X_RX_CONF_DATA (1 << 18)160#define RTL818X_RX_CONF_CTRL (1 << 19)161#define RTL818X_RX_CONF_MGMT (1 << 20)162#define RTL818X_RX_CONF_ADDR3 (1 << 21)163#define RTL818X_RX_CONF_PM (1 << 22)164#define RTL818X_RX_CONF_BSSID (1 << 23)165#define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28)166#define RTL818X_RX_CONF_CSDM1 (1 << 29)167#define RTL818X_RX_CONF_CSDM2 (1 << 30)168#define RTL818X_RX_CONF_ONLYERLPKT (1 << 31)169 __le32 INT_TIMEOUT;170 __le32 TBDA;171 u8 EEPROM_CMD;172#define RTL818X_EEPROM_CMD_READ (1 << 0)173#define RTL818X_EEPROM_CMD_WRITE (1 << 1)174#define RTL818X_EEPROM_CMD_CK (1 << 2)175#define RTL818X_EEPROM_CMD_CS (1 << 3)176#define RTL818X_EEPROM_CMD_NORMAL (0 << 6)177#define RTL818X_EEPROM_CMD_LOAD (1 << 6)178#define RTL818X_EEPROM_CMD_PROGRAM (2 << 6)179#define RTL818X_EEPROM_CMD_CONFIG (3 << 6)180 u8 CONFIG0;181 u8 CONFIG1;182 u8 CONFIG2;183#define RTL818X_CONFIG2_ANTENNA_DIV (1 << 6)184 __le32 ANAPARAM;185 u8 MSR;186#define RTL818X_MSR_NO_LINK (0 << 2)187#define RTL818X_MSR_ADHOC (1 << 2)188#define RTL818X_MSR_INFRA (2 << 2)189#define RTL818X_MSR_MASTER (3 << 2)190#define RTL818X_MSR_ENEDCA (4 << 2)191 u8 CONFIG3;192#define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6)193#define RTL818X_CONFIG3_GNT_SELECT (1 << 7)194 u8 CONFIG4;195#define RTL818X_CONFIG4_POWEROFF (1 << 6)196#define RTL818X_CONFIG4_VCOOFF (1 << 7)197 u8 TESTR;198 u8 reserved_9[2];199 u8 PGSELECT;200 u8 SECURITY;201 __le32 ANAPARAM2;202 u8 reserved_10[8];203 __le32 IMR; /* 0x6c - Interrupt mask reg for 8187se */204#define IMR_TMGDOK ((1 << 30))205#define IMR_DOT11HINT ((1 << 25)) /* 802.11h Measurement Interrupt */206#define IMR_BCNDMAINT ((1 << 24)) /* Beacon DMA Interrupt */207#define IMR_WAKEINT ((1 << 23)) /* Wake Up Interrupt */208#define IMR_TXFOVW ((1 << 22)) /* Tx FIFO Overflow */209#define IMR_TIMEOUT1 ((1 << 21)) /* Time Out Interrupt 1 */210#define IMR_BCNINT ((1 << 20)) /* Beacon Time out */211#define IMR_ATIMINT ((1 << 19)) /* ATIM Time Out */212#define IMR_TBDER ((1 << 18)) /* Tx Beacon Descriptor Error */213#define IMR_TBDOK ((1 << 17)) /* Tx Beacon Descriptor OK */214#define IMR_THPDER ((1 << 16)) /* Tx High Priority Descriptor Error */215#define IMR_THPDOK ((1 << 15)) /* Tx High Priority Descriptor OK */216#define IMR_TVODER ((1 << 14)) /* Tx AC_VO Descriptor Error Int */217#define IMR_TVODOK ((1 << 13)) /* Tx AC_VO Descriptor OK Interrupt */218#define IMR_FOVW ((1 << 12)) /* Rx FIFO Overflow Interrupt */219#define IMR_RDU ((1 << 11)) /* Rx Descriptor Unavailable */220#define IMR_TVIDER ((1 << 10)) /* Tx AC_VI Descriptor Error */221#define IMR_TVIDOK ((1 << 9)) /* Tx AC_VI Descriptor OK Interrupt */222#define IMR_RER ((1 << 8)) /* Rx Error Interrupt */223#define IMR_ROK ((1 << 7)) /* Receive OK Interrupt */224#define IMR_TBEDER ((1 << 6)) /* Tx AC_BE Descriptor Error */225#define IMR_TBEDOK ((1 << 5)) /* Tx AC_BE Descriptor OK */226#define IMR_TBKDER ((1 << 4)) /* Tx AC_BK Descriptor Error */227#define IMR_TBKDOK ((1 << 3)) /* Tx AC_BK Descriptor OK */228#define IMR_RQOSOK ((1 << 2)) /* Rx QoS OK Interrupt */229#define IMR_TIMEOUT2 ((1 << 1)) /* Time Out Interrupt 2 */230#define IMR_TIMEOUT3 ((1 << 0)) /* Time Out Interrupt 3 */231 __le16 BEACON_INTERVAL; /* 0x70 */232 __le16 ATIM_WND; /* 0x72 */233 __le16 BEACON_INTERVAL_TIME; /* 0x74 */234 __le16 ATIMTR_INTERVAL; /* 0x76 */235 u8 PHY_DELAY; /* 0x78 */236 u8 CARRIER_SENSE_COUNTER; /* 0x79 */237 u8 reserved_11[2]; /* 0x7a */238 u8 PHY[4]; /* 0x7c */239 __le16 RFPinsOutput; /* 0x80 */240 __le16 RFPinsEnable; /* 0x82 */241 __le16 RFPinsSelect; /* 0x84 */242 __le16 RFPinsInput; /* 0x86 */243 __le32 RF_PARA; /* 0x88 */244 __le32 RF_TIMING; /* 0x8c */245 u8 GP_ENABLE; /* 0x90 */246 u8 GPIO0; /* 0x91 */247 u8 GPIO1; /* 0x92 */248 u8 TPPOLL_STOP; /* 0x93 - rtl8187se only */249#define RTL818x_TPPOLL_STOP_BQ (1 << 7)250#define RTL818x_TPPOLL_STOP_VI (1 << 4)251#define RTL818x_TPPOLL_STOP_VO (1 << 5)252#define RTL818x_TPPOLL_STOP_BE (1 << 3)253#define RTL818x_TPPOLL_STOP_BK (1 << 2)254#define RTL818x_TPPOLL_STOP_MG (1 << 1)255#define RTL818x_TPPOLL_STOP_HI (1 << 6)256 257 __le32 HSSI_PARA; /* 0x94 */258 u8 reserved_13[4]; /* 0x98 */259 u8 TX_AGC_CTL; /* 0x9c */260#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN (1 << 0)261#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL (1 << 1)262#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT (1 << 2)263 u8 TX_GAIN_CCK;264 u8 TX_GAIN_OFDM;265 u8 TX_ANTENNA;266 u8 reserved_14[16];267 u8 WPA_CONF;268 u8 reserved_15[3];269 u8 SIFS;270 u8 DIFS;271 u8 SLOT;272 u8 reserved_16[5];273 u8 CW_CONF;274#define RTL818X_CW_CONF_PERPACKET_CW (1 << 0)275#define RTL818X_CW_CONF_PERPACKET_RETRY (1 << 1)276 u8 CW_VAL;277 u8 RATE_FALLBACK;278#define RTL818X_RATE_FALLBACK_ENABLE (1 << 7)279 u8 ACM_CONTROL;280 u8 reserved_17[24];281 u8 CONFIG5;282 u8 TX_DMA_POLLING;283 u8 PHY_PR;284 u8 reserved_18;285 __le16 CWR;286 u8 RETRY_CTR;287 u8 reserved_19[3];288 __le16 INT_MIG;289/* RTL818X_R8187B_*: magic numbers from ioregisters */290#define RTL818X_R8187B_B 0291#define RTL818X_R8187B_D 1292#define RTL818X_R8187B_E 2293 __le32 RDSAR;294 __le16 TID_AC_MAP;295 u8 reserved_20[4];296 union {297 __le16 ANAPARAM3; /* 0xee */298 u8 ANAPARAM3A; /* for rtl8187 */299 };300 301#define AC_PARAM_TXOP_LIMIT_SHIFT 16302#define AC_PARAM_ECW_MAX_SHIFT 12303#define AC_PARAM_ECW_MIN_SHIFT 8304#define AC_PARAM_AIFS_SHIFT 0305 306 __le32 AC_VO_PARAM; /* 0xf0 */307 308 union { /* 0xf4 */309 __le32 AC_VI_PARAM;310 __le16 FEMR;311 } __packed;312 313 union{ /* 0xf8 */314 __le32 AC_BE_PARAM; /* rtl8187se */315 struct{316 u8 reserved_21[2];317 __le16 TALLY_CNT; /* 0xfa */318 } __packed;319 } __packed;320 321 union {322 u8 TALLY_SEL; /* 0xfc */323 __le32 AC_BK_PARAM;324 325 } __packed;326 327} __packed;328 329/* These are addresses with NON-standard usage.330 * They have offsets very far from this struct.331 * I don't like to introduce a ton of "reserved"..332 * They are for RTL8187SE333 */334#define REG_ADDR1(addr) ((u8 __iomem *)priv->map + (addr))335#define REG_ADDR2(addr) ((__le16 __iomem *)priv->map + ((addr) >> 1))336#define REG_ADDR4(addr) ((__le32 __iomem *)priv->map + ((addr) >> 2))337 338#define FEMR_SE REG_ADDR2(0x1D4)339#define ARFR REG_ADDR2(0x1E0)340#define RFSW_CTRL REG_ADDR2(0x272)341#define SW_3W_DB0 REG_ADDR2(0x274)342#define SW_3W_DB0_4 REG_ADDR4(0x274)343#define SW_3W_DB1 REG_ADDR2(0x278)344#define SW_3W_DB1_4 REG_ADDR4(0x278)345#define SW_3W_CMD1 REG_ADDR1(0x27D)346#define PI_DATA_REG REG_ADDR2(0x360)347#define SI_DATA_REG REG_ADDR2(0x362)348 349struct rtl818x_rf_ops {350 char *name;351 void (*init)(struct ieee80211_hw *);352 void (*stop)(struct ieee80211_hw *);353 void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);354 u8 (*calc_rssi)(u8 agc, u8 sq);355};356 357/**358 * enum rtl818x_tx_desc_flags - Tx/Rx flags are common between RTL818X chips359 *360 * @RTL818X_TX_DESC_FLAG_NO_ENC: Disable hardware based encryption.361 * @RTL818X_TX_DESC_FLAG_TX_OK: TX frame was ACKed.362 * @RTL818X_TX_DESC_FLAG_SPLCP: Use short preamble.363 * @RTL818X_TX_DESC_FLAG_MOREFRAG: More fragments follow.364 * @RTL818X_TX_DESC_FLAG_CTS: Use CTS-to-self protection.365 * @RTL818X_TX_DESC_FLAG_RTS: Use RTS/CTS protection.366 * @RTL818X_TX_DESC_FLAG_LS: Last segment of the frame.367 * @RTL818X_TX_DESC_FLAG_FS: First segment of the frame.368 */369enum rtl818x_tx_desc_flags {370 RTL818X_TX_DESC_FLAG_NO_ENC = (1 << 15),371 RTL818X_TX_DESC_FLAG_TX_OK = (1 << 15),372 RTL818X_TX_DESC_FLAG_SPLCP = (1 << 16),373 RTL818X_TX_DESC_FLAG_RX_UNDER = (1 << 16),374 RTL818X_TX_DESC_FLAG_MOREFRAG = (1 << 17),375 RTL818X_TX_DESC_FLAG_CTS = (1 << 18),376 RTL818X_TX_DESC_FLAG_RTS = (1 << 23),377 RTL818X_TX_DESC_FLAG_LS = (1 << 28),378 RTL818X_TX_DESC_FLAG_FS = (1 << 29),379 RTL818X_TX_DESC_FLAG_DMA = (1 << 30),380 RTL818X_TX_DESC_FLAG_OWN = (1 << 31)381};382 383enum rtl818x_rx_desc_flags {384 RTL818X_RX_DESC_FLAG_ICV_ERR = (1 << 12),385 RTL818X_RX_DESC_FLAG_CRC32_ERR = (1 << 13),386 RTL818X_RX_DESC_FLAG_PM = (1 << 14),387 RTL818X_RX_DESC_FLAG_RX_ERR = (1 << 15),388 RTL818X_RX_DESC_FLAG_BCAST = (1 << 16),389 RTL818X_RX_DESC_FLAG_PAM = (1 << 17),390 RTL818X_RX_DESC_FLAG_MCAST = (1 << 18),391 RTL818X_RX_DESC_FLAG_QOS = (1 << 19), /* RTL8187(B) only */392 RTL818X_RX_DESC_FLAG_TRSW = (1 << 24), /* RTL8187(B) only */393 RTL818X_RX_DESC_FLAG_SPLCP = (1 << 25),394 RTL818X_RX_DESC_FLAG_FOF = (1 << 26),395 RTL818X_RX_DESC_FLAG_DMA_FAIL = (1 << 27),396 RTL818X_RX_DESC_FLAG_LS = (1 << 28),397 RTL818X_RX_DESC_FLAG_FS = (1 << 29),398 RTL818X_RX_DESC_FLAG_EOR = (1 << 30),399 RTL818X_RX_DESC_FLAG_OWN = (1 << 31)400};401 402#endif /* RTL818X_H */403