1886 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * RTL8XXXU mac80211 USB driver - 8188e specific subdriver4 *5 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@gmail.com>6 *7 * Portions, notably calibration code:8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.9 *10 * This driver was written as a replacement for the vendor provided11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in12 * their programming interface, I have started adding support for13 * additional 8xxx chips like the 8192cu, 8188cus, etc.14 */15 16#include "regs.h"17#include "rtl8xxxu.h"18 19static const struct rtl8xxxu_reg8val rtl8188e_mac_init_table[] = {20 {0x026, 0x41}, {0x027, 0x35}, {0x040, 0x00}, {0x421, 0x0f},21 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x01},22 {0x432, 0x02}, {0x433, 0x04}, {0x434, 0x05}, {0x435, 0x06},23 {0x436, 0x07}, {0x437, 0x08}, {0x438, 0x00}, {0x439, 0x00},24 {0x43a, 0x01}, {0x43b, 0x02}, {0x43c, 0x04}, {0x43d, 0x05},25 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},26 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},27 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},28 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x480, 0x08},29 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},30 {0x4ce, 0x01}, {0x4d3, 0x01}, {0x500, 0x26}, {0x501, 0xa2},31 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},32 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},33 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},34 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},35 {0x516, 0x0a}, {0x525, 0x4f}, {0x550, 0x10}, {0x551, 0x10},36 {0x559, 0x02}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e},37 {0x609, 0x2a}, {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff},38 {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff},39 {0x627, 0xff}, {0x63c, 0x08}, {0x63d, 0x08}, {0x63e, 0x0c},40 {0x63f, 0x0c}, {0x640, 0x40}, {0x652, 0x20}, {0x66e, 0x05},41 {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87},42 {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87},43 {0xffff, 0xff},44};45 46static const struct rtl8xxxu_reg32val rtl8188eu_phy_init_table[] = {47 {0x800, 0x80040000}, {0x804, 0x00000003},48 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},49 {0x810, 0x10001331}, {0x814, 0x020c3d10},50 {0x818, 0x02200385}, {0x81c, 0x00000000},51 {0x820, 0x01000100}, {0x824, 0x00390204},52 {0x828, 0x00000000}, {0x82c, 0x00000000},53 {0x830, 0x00000000}, {0x834, 0x00000000},54 {0x838, 0x00000000}, {0x83c, 0x00000000},55 {0x840, 0x00010000}, {0x844, 0x00000000},56 {0x848, 0x00000000}, {0x84c, 0x00000000},57 {0x850, 0x00000000}, {0x854, 0x00000000},58 {0x858, 0x569a11a9}, {0x85c, 0x01000014},59 {0x860, 0x66f60110}, {0x864, 0x061f0649},60 {0x868, 0x00000000}, {0x86c, 0x27272700},61 {0x870, 0x07000760}, {0x874, 0x25004000},62 {0x878, 0x00000808}, {0x87c, 0x00000000},63 {0x880, 0xb0000c1c}, {0x884, 0x00000001},64 {0x888, 0x00000000}, {0x88c, 0xccc000c0},65 {0x890, 0x00000800}, {0x894, 0xfffffffe},66 {0x898, 0x40302010}, {0x89c, 0x00706050},67 {0x900, 0x00000000}, {0x904, 0x00000023},68 {0x908, 0x00000000}, {0x90c, 0x81121111},69 {0x910, 0x00000002}, {0x914, 0x00000201},70 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},71 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},72 {0xa10, 0x9500bb7e}, {0xa14, 0x1114d028},73 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},74 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},75 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},76 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},77 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},78 {0xa80, 0x218075b1}, {0xb2c, 0x80000000},79 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},80 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},81 {0xc10, 0x08800000}, {0xc14, 0x40000100},82 {0xc18, 0x08800000}, {0xc1c, 0x40000100},83 {0xc20, 0x00000000}, {0xc24, 0x00000000},84 {0xc28, 0x00000000}, {0xc2c, 0x00000000},85 {0xc30, 0x69e9ac47}, {0xc34, 0x469652af},86 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},87 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},88 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},89 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},90 {0xc58, 0x00013169}, {0xc5c, 0x00250492},91 {0xc60, 0x00000000}, {0xc64, 0x7112848b},92 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},93 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},94 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},95 {0xc80, 0x390000e4}, {0xc84, 0x21f60000},96 {0xc88, 0x40000100}, {0xc8c, 0x20200000},97 {0xc90, 0x00091521}, {0xc94, 0x00000000},98 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},99 {0xca0, 0x00000000}, {0xca4, 0x000300a0},100 {0xca8, 0x00000000}, {0xcac, 0x00000000},101 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},102 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},103 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},104 {0xcc8, 0x00000000}, {0xccc, 0x00000000},105 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},106 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},107 {0xce0, 0x00222222}, {0xce4, 0x00000000},108 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},109 {0xd00, 0x00000740}, {0xd04, 0x00020401},110 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},111 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},112 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},113 {0xd30, 0x00000000}, {0xd34, 0x80608000},114 {0xd38, 0x00000000}, {0xd3c, 0x00127353},115 {0xd40, 0x00000000}, {0xd44, 0x00000000},116 {0xd48, 0x00000000}, {0xd4c, 0x00000000},117 {0xd50, 0x6437140a}, {0xd54, 0x00000000},118 {0xd58, 0x00000282}, {0xd5c, 0x30032064},119 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},120 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},121 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},122 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},123 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},124 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},125 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},126 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},127 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},128 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},129 {0xe44, 0x01004800}, {0xe48, 0xfb000000},130 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},131 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},132 {0xe5c, 0x28160d05}, {0xe60, 0x00000048},133 {0xe68, 0x001b25a4}, {0xe6c, 0x00c00014},134 {0xe70, 0x00c00014}, {0xe74, 0x01000014},135 {0xe78, 0x01000014}, {0xe7c, 0x01000014},136 {0xe80, 0x01000014}, {0xe84, 0x00c00014},137 {0xe88, 0x01000014}, {0xe8c, 0x00c00014},138 {0xed0, 0x00c00014}, {0xed4, 0x00c00014},139 {0xed8, 0x00c00014}, {0xedc, 0x00000014},140 {0xee0, 0x00000014}, {0xee8, 0x21555448},141 {0xeec, 0x01c00014}, {0xf14, 0x00000003},142 {0xf4c, 0x00000000}, {0xf00, 0x00000300},143 {0xffff, 0xffffffff},144};145 146static const struct rtl8xxxu_reg32val rtl8188e_agc_table[] = {147 {0xc78, 0xfb000001}, {0xc78, 0xfb010001},148 {0xc78, 0xfb020001}, {0xc78, 0xfb030001},149 {0xc78, 0xfb040001}, {0xc78, 0xfb050001},150 {0xc78, 0xfa060001}, {0xc78, 0xf9070001},151 {0xc78, 0xf8080001}, {0xc78, 0xf7090001},152 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},153 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},154 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},155 {0xc78, 0xf0100001}, {0xc78, 0xef110001},156 {0xc78, 0xee120001}, {0xc78, 0xed130001},157 {0xc78, 0xec140001}, {0xc78, 0xeb150001},158 {0xc78, 0xea160001}, {0xc78, 0xe9170001},159 {0xc78, 0xe8180001}, {0xc78, 0xe7190001},160 {0xc78, 0xe61a0001}, {0xc78, 0xe51b0001},161 {0xc78, 0xe41c0001}, {0xc78, 0xe31d0001},162 {0xc78, 0xe21e0001}, {0xc78, 0xe11f0001},163 {0xc78, 0x8a200001}, {0xc78, 0x89210001},164 {0xc78, 0x88220001}, {0xc78, 0x87230001},165 {0xc78, 0x86240001}, {0xc78, 0x85250001},166 {0xc78, 0x84260001}, {0xc78, 0x83270001},167 {0xc78, 0x82280001}, {0xc78, 0x6b290001},168 {0xc78, 0x6a2a0001}, {0xc78, 0x692b0001},169 {0xc78, 0x682c0001}, {0xc78, 0x672d0001},170 {0xc78, 0x662e0001}, {0xc78, 0x652f0001},171 {0xc78, 0x64300001}, {0xc78, 0x63310001},172 {0xc78, 0x62320001}, {0xc78, 0x61330001},173 {0xc78, 0x46340001}, {0xc78, 0x45350001},174 {0xc78, 0x44360001}, {0xc78, 0x43370001},175 {0xc78, 0x42380001}, {0xc78, 0x41390001},176 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},177 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},178 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},179 {0xc78, 0xfb400001}, {0xc78, 0xfb410001},180 {0xc78, 0xfb420001}, {0xc78, 0xfb430001},181 {0xc78, 0xfb440001}, {0xc78, 0xfb450001},182 {0xc78, 0xfb460001}, {0xc78, 0xfb470001},183 {0xc78, 0xfb480001}, {0xc78, 0xfa490001},184 {0xc78, 0xf94a0001}, {0xc78, 0xf84b0001},185 {0xc78, 0xf74c0001}, {0xc78, 0xf64d0001},186 {0xc78, 0xf54e0001}, {0xc78, 0xf44f0001},187 {0xc78, 0xf3500001}, {0xc78, 0xf2510001},188 {0xc78, 0xf1520001}, {0xc78, 0xf0530001},189 {0xc78, 0xef540001}, {0xc78, 0xee550001},190 {0xc78, 0xed560001}, {0xc78, 0xec570001},191 {0xc78, 0xeb580001}, {0xc78, 0xea590001},192 {0xc78, 0xe95a0001}, {0xc78, 0xe85b0001},193 {0xc78, 0xe75c0001}, {0xc78, 0xe65d0001},194 {0xc78, 0xe55e0001}, {0xc78, 0xe45f0001},195 {0xc78, 0xe3600001}, {0xc78, 0xe2610001},196 {0xc78, 0xc3620001}, {0xc78, 0xc2630001},197 {0xc78, 0xc1640001}, {0xc78, 0x8b650001},198 {0xc78, 0x8a660001}, {0xc78, 0x89670001},199 {0xc78, 0x88680001}, {0xc78, 0x87690001},200 {0xc78, 0x866a0001}, {0xc78, 0x856b0001},201 {0xc78, 0x846c0001}, {0xc78, 0x676d0001},202 {0xc78, 0x666e0001}, {0xc78, 0x656f0001},203 {0xc78, 0x64700001}, {0xc78, 0x63710001},204 {0xc78, 0x62720001}, {0xc78, 0x61730001},205 {0xc78, 0x60740001}, {0xc78, 0x46750001},206 {0xc78, 0x45760001}, {0xc78, 0x44770001},207 {0xc78, 0x43780001}, {0xc78, 0x42790001},208 {0xc78, 0x417a0001}, {0xc78, 0x407b0001},209 {0xc78, 0x407c0001}, {0xc78, 0x407d0001},210 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},211 {0xc50, 0x69553422}, {0xc50, 0x69553420},212 {0xffff, 0xffffffff}213};214 215static const struct rtl8xxxu_rfregval rtl8188eu_radioa_init_table[] = {216 {0x00, 0x00030000}, {0x08, 0x00084000},217 {0x18, 0x00000407}, {0x19, 0x00000012},218 {0x1e, 0x00080009}, {0x1f, 0x00000880},219 {0x2f, 0x0001a060}, {0x3f, 0x00000000},220 {0x42, 0x000060c0}, {0x57, 0x000d0000},221 {0x58, 0x000be180}, {0x67, 0x00001552},222 {0x83, 0x00000000}, {0xb0, 0x000ff8fc},223 {0xb1, 0x00054400}, {0xb2, 0x000ccc19},224 {0xb4, 0x00043003}, {0xb6, 0x0004953e},225 {0xb7, 0x0001c718}, {0xb8, 0x000060ff},226 {0xb9, 0x00080001}, {0xba, 0x00040000},227 {0xbb, 0x00000400}, {0xbf, 0x000c0000},228 {0xc2, 0x00002400}, {0xc3, 0x00000009},229 {0xc4, 0x00040c91}, {0xc5, 0x00099999},230 {0xc6, 0x000000a3}, {0xc7, 0x00088820},231 {0xc8, 0x00076c06}, {0xc9, 0x00000000},232 {0xca, 0x00080000}, {0xdf, 0x00000180},233 {0xef, 0x000001a0}, {0x51, 0x0006b27d},234 {0x52, 0x0007e49d}, /* Set to 0x0007e4dd for SDIO */235 {0x53, 0x00000073}, {0x56, 0x00051ff3},236 {0x35, 0x00000086}, {0x35, 0x00000186},237 {0x35, 0x00000286}, {0x36, 0x00001c25},238 {0x36, 0x00009c25}, {0x36, 0x00011c25},239 {0x36, 0x00019c25}, {0xb6, 0x00048538},240 {0x18, 0x00000c07}, {0x5a, 0x0004bd00},241 {0x19, 0x000739d0}, {0x34, 0x0000adf3},242 {0x34, 0x00009df0}, {0x34, 0x00008ded},243 {0x34, 0x00007dea}, {0x34, 0x00006de7},244 {0x34, 0x000054ee}, {0x34, 0x000044eb},245 {0x34, 0x000034e8}, {0x34, 0x0000246b},246 {0x34, 0x00001468}, {0x34, 0x0000006d},247 {0x00, 0x00030159}, {0x84, 0x00068200},248 {0x86, 0x000000ce}, {0x87, 0x00048a00},249 {0x8e, 0x00065540}, {0x8f, 0x00088000},250 {0xef, 0x000020a0}, {0x3b, 0x000f02b0},251 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},252 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},253 {0x3b, 0x000a0080}, {0x3b, 0x00090080},254 {0x3b, 0x0008f780}, {0x3b, 0x000722b0},255 {0x3b, 0x0006f7b0}, {0x3b, 0x00054fb0},256 {0x3b, 0x0004f060}, {0x3b, 0x00030090},257 {0x3b, 0x00020080}, {0x3b, 0x00010080},258 {0x3b, 0x0000f780}, {0xef, 0x000000a0},259 {0x00, 0x00010159}, {0x18, 0x0000f407},260 {0xFE, 0x00000000}, {0xFE, 0x00000000},261 {0x1F, 0x00080003}, {0xFE, 0x00000000},262 {0xFE, 0x00000000}, {0x1E, 0x00000001},263 {0x1F, 0x00080000}, {0x00, 0x00033e60},264 {0xff, 0xffffffff}265};266 267#define PERENTRY 23268#define RETRYSIZE 5269#define RATESIZE 28270#define TX_RPT2_ITEM_SIZE 8271 272static const u8 retry_penalty[PERENTRY][RETRYSIZE + 1] = {273 {5, 4, 3, 2, 0, 3}, /* 92 , idx=0 */274 {6, 5, 4, 3, 0, 4}, /* 86 , idx=1 */275 {6, 5, 4, 2, 0, 4}, /* 81 , idx=2 */276 {8, 7, 6, 4, 0, 6}, /* 75 , idx=3 */277 {10, 9, 8, 6, 0, 8}, /* 71 , idx=4 */278 {10, 9, 8, 4, 0, 8}, /* 66 , idx=5 */279 {10, 9, 8, 2, 0, 8}, /* 62 , idx=6 */280 {10, 9, 8, 0, 0, 8}, /* 59 , idx=7 */281 {18, 17, 16, 8, 0, 16}, /* 53 , idx=8 */282 {26, 25, 24, 16, 0, 24}, /* 50 , idx=9 */283 {34, 33, 32, 24, 0, 32}, /* 47 , idx=0x0a */284 {34, 31, 28, 20, 0, 32}, /* 43 , idx=0x0b */285 {34, 31, 27, 18, 0, 32}, /* 40 , idx=0x0c */286 {34, 31, 26, 16, 0, 32}, /* 37 , idx=0x0d */287 {34, 30, 22, 16, 0, 32}, /* 32 , idx=0x0e */288 {34, 30, 24, 16, 0, 32}, /* 26 , idx=0x0f */289 {49, 46, 40, 16, 0, 48}, /* 20 , idx=0x10 */290 {49, 45, 32, 0, 0, 48}, /* 17 , idx=0x11 */291 {49, 45, 22, 18, 0, 48}, /* 15 , idx=0x12 */292 {49, 40, 24, 16, 0, 48}, /* 12 , idx=0x13 */293 {49, 32, 18, 12, 0, 48}, /* 9 , idx=0x14 */294 {49, 22, 18, 14, 0, 48}, /* 6 , idx=0x15 */295 {49, 16, 16, 0, 0, 48} /* 3, idx=0x16 */296};297 298static const u8 pt_penalty[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32};299 300static const u8 retry_penalty_idx_normal[2][RATESIZE] = {301 { /* RSSI>TH */302 4, 4, 4, 5,303 4, 4, 5, 7, 7, 7, 8, 0x0a,304 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,305 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f306 },307 { /* RSSI<TH */308 0x0a, 0x0a, 0x0b, 0x0c,309 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13,310 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x13,311 9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13312 }313};314 315static const u8 retry_penalty_idx_cut_i[2][RATESIZE] = {316 { /* RSSI>TH */317 4, 4, 4, 5,318 4, 4, 5, 7, 7, 7, 8, 0x0a,319 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,320 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f321 },322 { /* RSSI<TH */323 0x0a, 0x0a, 0x0b, 0x0c,324 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13,325 0x06, 0x07, 0x08, 0x0d, 0x0e, 0x11, 0x11, 0x11,326 9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13327 }328};329 330static const u8 retry_penalty_up_idx_normal[RATESIZE] = {331 0x0c, 0x0d, 0x0d, 0x0f,332 0x0d, 0x0e, 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14,333 0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15,334 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15335};336 337static const u8 retry_penalty_up_idx_cut_i[RATESIZE] = {338 0x0c, 0x0d, 0x0d, 0x0f,339 0x0d, 0x0e, 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14,340 0x0b, 0x0b, 0x11, 0x11, 0x12, 0x12, 0x12, 0x12,341 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15342};343 344static const u8 rssi_threshold[RATESIZE] = {345 0, 0, 0, 0,346 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a,347 0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a,348 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c349};350 351static const u16 n_threshold_high[RATESIZE] = {352 4, 4, 8, 16,353 24, 36, 48, 72, 96, 144, 192, 216,354 60, 80, 100, 160, 240, 400, 600, 800,355 300, 320, 480, 720, 1000, 1200, 1600, 2000356};357 358static const u16 n_threshold_low[RATESIZE] = {359 2, 2, 4, 8,360 12, 18, 24, 36, 48, 72, 96, 108,361 30, 40, 50, 80, 120, 200, 300, 400,362 150, 160, 240, 360, 500, 600, 800, 1000363};364 365static const u8 dropping_necessary[RATESIZE] = {366 1, 1, 1, 1,367 1, 2, 3, 4, 5, 6, 7, 8,368 1, 2, 3, 4, 5, 6, 7, 8,369 5, 6, 7, 8, 9, 10, 11, 12370};371 372static const u8 pending_for_rate_up_fail[5] = {2, 10, 24, 40, 60};373 374static const u16 dynamic_tx_rpt_timing[6] = {375 0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c /* 200ms-1200ms */376};377 378enum rtl8188e_tx_rpt_timing {379 DEFAULT_TIMING = 0,380 INCREASE_TIMING,381 DECREASE_TIMING382};383 384static int rtl8188eu_identify_chip(struct rtl8xxxu_priv *priv)385{386 struct device *dev = &priv->udev->dev;387 u32 sys_cfg, vendor;388 int ret = 0;389 390 strscpy(priv->chip_name, "8188EU", sizeof(priv->chip_name));391 priv->rtl_chip = RTL8188E;392 priv->rf_paths = 1;393 priv->rx_paths = 1;394 priv->tx_paths = 1;395 priv->has_wifi = 1;396 397 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);398 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);399 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {400 dev_info(dev, "Unsupported test chip\n");401 return -EOPNOTSUPP;402 }403 404 /*405 * TODO: At a glance, I cut requires a different firmware,406 * different initialisation tables, and no software rate407 * control. The vendor driver is not configured to handle408 * I cut chips by default. Are there any in the wild?409 */410 if (priv->chip_cut == 8) {411 dev_info(dev, "RTL8188EU cut I is not supported. Please complain about it at linux-wireless@vger.kernel.org.\n");412 return -EOPNOTSUPP;413 }414 415 vendor = sys_cfg & SYS_CFG_VENDOR_ID;416 rtl8xxxu_identify_vendor_1bit(priv, vendor);417 418 ret = rtl8xxxu_config_endpoints_no_sie(priv);419 420 return ret;421}422 423static void rtl8188eu_config_channel(struct ieee80211_hw *hw)424{425 struct rtl8xxxu_priv *priv = hw->priv;426 u32 val32, rsr;427 u8 opmode;428 int sec_ch_above, channel;429 int i;430 431 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);432 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);433 channel = hw->conf.chandef.chan->hw_value;434 435 switch (hw->conf.chandef.width) {436 case NL80211_CHAN_WIDTH_20_NOHT:437 case NL80211_CHAN_WIDTH_20:438 opmode |= BW_OPMODE_20MHZ;439 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);440 441 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);442 val32 &= ~FPGA_RF_MODE;443 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);444 445 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);446 val32 &= ~FPGA_RF_MODE;447 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);448 break;449 case NL80211_CHAN_WIDTH_40:450 if (hw->conf.chandef.center_freq1 >451 hw->conf.chandef.chan->center_freq) {452 sec_ch_above = 1;453 channel += 2;454 } else {455 sec_ch_above = 0;456 channel -= 2;457 }458 459 opmode &= ~BW_OPMODE_20MHZ;460 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);461 rsr &= ~RSR_RSC_BANDWIDTH_40M;462 if (sec_ch_above)463 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;464 else465 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;466 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);467 468 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);469 val32 |= FPGA_RF_MODE;470 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);471 472 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);473 val32 |= FPGA_RF_MODE;474 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);475 476 /*477 * Set Control channel to upper or lower. These settings478 * are required only for 40MHz479 */480 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);481 val32 &= ~CCK0_SIDEBAND;482 if (!sec_ch_above)483 val32 |= CCK0_SIDEBAND;484 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);485 486 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);487 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */488 if (sec_ch_above)489 val32 |= OFDM_LSTF_PRIME_CH_LOW;490 else491 val32 |= OFDM_LSTF_PRIME_CH_HIGH;492 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);493 494 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);495 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);496 if (sec_ch_above)497 val32 |= FPGA0_PS_UPPER_CHANNEL;498 else499 val32 |= FPGA0_PS_LOWER_CHANNEL;500 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);501 break;502 503 default:504 break;505 }506 507 for (i = RF_A; i < priv->rf_paths; i++) {508 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);509 u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK);510 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);511 }512 513 for (i = RF_A; i < priv->rf_paths; i++) {514 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);515 val32 &= ~MODE_AG_BW_MASK;516 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)517 val32 |= MODE_AG_BW_40MHZ_8723B;518 else519 val32 |= MODE_AG_BW_20MHZ_8723B;520 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);521 }522}523 524static void rtl8188eu_init_aggregation(struct rtl8xxxu_priv *priv)525{526 u8 agg_ctrl, usb_spec;527 528 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);529 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;530 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);531 532 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);533 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;534 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);535}536 537static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv)538{539 struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu;540 541 if (efuse->rtl_id != cpu_to_le16(0x8129))542 return -EINVAL;543 544 ether_addr_copy(priv->mac_addr, efuse->mac_addr);545 546 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,547 sizeof(efuse->tx_power_index_A.cck_base));548 549 memcpy(priv->ht40_1s_tx_power_index_A,550 efuse->tx_power_index_A.ht40_base,551 sizeof(efuse->tx_power_index_A.ht40_base));552 553 priv->default_crystal_cap = efuse->xtal_k & 0x3f;554 555 return 0;556}557 558static void rtl8188eu_reset_8051(struct rtl8xxxu_priv *priv)559{560 u16 sys_func;561 562 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);563 sys_func &= ~SYS_FUNC_CPU_ENABLE;564 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);565 566 sys_func |= SYS_FUNC_CPU_ENABLE;567 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);568}569 570static int rtl8188eu_load_firmware(struct rtl8xxxu_priv *priv)571{572 const char *fw_name;573 int ret;574 575 fw_name = "rtlwifi/rtl8188eufw.bin";576 577 ret = rtl8xxxu_load_firmware(priv, fw_name);578 579 return ret;580}581 582static void rtl8188eu_init_phy_bb(struct rtl8xxxu_priv *priv)583{584 u8 val8;585 u16 val16;586 587 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);588 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;589 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);590 591 /*592 * Per vendor driver, run power sequence before init of RF593 */594 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;595 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);596 597 val8 = SYS_FUNC_USBA | SYS_FUNC_USBD |598 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;599 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);600 601 rtl8xxxu_init_phy_regs(priv, rtl8188eu_phy_init_table);602 rtl8xxxu_init_phy_regs(priv, rtl8188e_agc_table);603}604 605static int rtl8188eu_init_phy_rf(struct rtl8xxxu_priv *priv)606{607 return rtl8xxxu_init_phy_rf(priv, rtl8188eu_radioa_init_table, RF_A);608}609 610static int rtl8188eu_iqk_path_a(struct rtl8xxxu_priv *priv)611{612 u32 reg_eac, reg_e94, reg_e9c;613 int result = 0;614 615 /* Path A IQK setting */616 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c);617 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c);618 619 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214032a);620 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000);621 622 /* LO calibration setting */623 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);624 625 /* One shot, path A LOK & IQK */626 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);627 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);628 629 mdelay(10);630 631 /* Check failed */632 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);633 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);634 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);635 636 if (!(reg_eac & BIT(28)) &&637 ((reg_e94 & 0x03ff0000) != 0x01420000) &&638 ((reg_e9c & 0x03ff0000) != 0x00420000))639 result |= 0x01;640 641 return result;642}643 644static int rtl8188eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)645{646 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;647 int result = 0;648 649 /* Leave IQK mode */650 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);651 u32p_replace_bits(&val32, 0, 0xffffff00);652 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);653 654 /* Enable path A PA in TX IQK mode */655 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);656 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);657 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);658 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);659 660 /* Enter IQK mode */661 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);662 u32p_replace_bits(&val32, 0x808000, 0xffffff00);663 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);664 665 /* TX IQK setting */666 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);667 rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800);668 669 /* path-A IQK setting */670 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c);671 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c);672 673 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160804);674 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000);675 676 /* LO calibration setting */677 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);678 679 /* One shot, path A LOK & IQK */680 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);681 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);682 683 mdelay(10);684 685 /* Check failed */686 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);687 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);688 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);689 690 if (!(reg_eac & BIT(28)) &&691 ((reg_e94 & 0x03ff0000) != 0x01420000) &&692 ((reg_e9c & 0x03ff0000) != 0x00420000))693 result |= 0x01;694 else695 goto out;696 697 val32 = 0x80007c00 |698 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);699 rtl8xxxu_write32(priv, REG_TX_IQK, val32);700 701 /* Modify RX IQK mode table */702 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);703 u32p_replace_bits(&val32, 0, 0xffffff00);704 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);705 706 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);707 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);708 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);709 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);710 711 /* Enter IQK mode */712 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);713 u32p_replace_bits(&val32, 0x808000, 0xffffff00);714 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);715 716 /* IQK setting */717 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);718 719 /* Path A IQK setting */720 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c);721 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c);722 723 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c05);724 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c05);725 726 /* LO calibration setting */727 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);728 729 /* One shot, path A LOK & IQK */730 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);731 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);732 733 mdelay(10);734 735 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);736 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);737 738 if (!(reg_eac & BIT(27)) &&739 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&740 ((reg_eac & 0x03ff0000) != 0x00360000))741 result |= 0x02;742 else743 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",744 __func__);745 746out:747 return result;748}749 750static void rtl8188eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,751 int result[][8], int t)752{753 struct device *dev = &priv->udev->dev;754 u32 i, val32;755 int path_a_ok;756 int retry = 2;757 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {758 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,759 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,760 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,761 REG_TX_OFDM_BBON, REG_TX_TO_RX,762 REG_TX_TO_TX, REG_RX_CCK,763 REG_RX_OFDM, REG_RX_WAIT_RIFS,764 REG_RX_TO_RX, REG_STANDBY,765 REG_SLEEP, REG_PMPD_ANAEN766 };767 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {768 REG_TXPAUSE, REG_BEACON_CTRL,769 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG770 };771 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {772 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,773 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,774 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,775 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING776 };777 778 /*779 * Note: IQ calibration must be performed after loading780 * PHY_REG.txt , and radio_a, radio_b.txt781 */782 783 if (t == 0) {784 /* Save ADDA parameters, turn Path A ADDA on */785 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,786 RTL8XXXU_ADDA_REGS);787 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);788 rtl8xxxu_save_regs(priv, iqk_bb_regs,789 priv->bb_backup, RTL8XXXU_BB_REGS);790 }791 792 rtl8xxxu_path_adda_on(priv, adda_regs, true);793 794 if (t == 0) {795 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);796 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI);797 }798 799 if (!priv->pi_enabled) {800 /* Switch BB to PI mode to do IQ Calibration. */801 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);802 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);803 }804 805 /* MAC settings */806 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);807 808 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);809 u32p_replace_bits(&val32, 0xf, 0x0f000000);810 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);811 812 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);813 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);814 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);815 816 if (!priv->no_pape) {817 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);818 val32 |= (FPGA0_RF_PAPE |819 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));820 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);821 }822 823 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);824 val32 &= ~BIT(10);825 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);826 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);827 val32 &= ~BIT(10);828 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);829 830 /* Page B init */831 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);832 833 /* IQ calibration setting */834 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);835 u32p_replace_bits(&val32, 0x808000, 0xffffff00);836 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);837 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);838 rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800);839 840 for (i = 0; i < retry; i++) {841 path_a_ok = rtl8188eu_iqk_path_a(priv);842 if (path_a_ok == 0x01) {843 val32 = rtl8xxxu_read32(priv,844 REG_TX_POWER_BEFORE_IQK_A);845 result[t][0] = (val32 >> 16) & 0x3ff;846 val32 = rtl8xxxu_read32(priv,847 REG_TX_POWER_AFTER_IQK_A);848 result[t][1] = (val32 >> 16) & 0x3ff;849 break;850 }851 }852 853 if (!path_a_ok)854 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);855 856 for (i = 0; i < retry; i++) {857 path_a_ok = rtl8188eu_rx_iqk_path_a(priv);858 if (path_a_ok == 0x03) {859 val32 = rtl8xxxu_read32(priv,860 REG_RX_POWER_BEFORE_IQK_A_2);861 result[t][2] = (val32 >> 16) & 0x3ff;862 val32 = rtl8xxxu_read32(priv,863 REG_RX_POWER_AFTER_IQK_A_2);864 result[t][3] = (val32 >> 16) & 0x3ff;865 866 break;867 }868 }869 870 if (!path_a_ok)871 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);872 873 /* Back to BB mode, load original value */874 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);875 u32p_replace_bits(&val32, 0, 0xffffff00);876 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);877 878 if (t == 0)879 return;880 881 if (!priv->pi_enabled) {882 /* Switch back BB to SI mode after finishing IQ Calibration */883 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000);884 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000000);885 }886 887 /* Reload ADDA power saving parameters */888 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,889 RTL8XXXU_ADDA_REGS);890 891 /* Reload MAC parameters */892 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);893 894 /* Reload BB parameters */895 rtl8xxxu_restore_regs(priv, iqk_bb_regs,896 priv->bb_backup, RTL8XXXU_BB_REGS);897 898 /* Restore RX initial gain */899 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);900 901 /* Load 0xe30 IQC default value */902 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);903 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);904}905 906static void rtl8188eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)907{908 struct device *dev = &priv->udev->dev;909 int result[4][8]; /* last is final result */910 int i, candidate;911 bool path_a_ok;912 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;913 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;914 bool simu;915 916 memset(result, 0, sizeof(result));917 result[3][0] = 0x100;918 result[3][2] = 0x100;919 result[3][4] = 0x100;920 result[3][6] = 0x100;921 922 candidate = -1;923 924 path_a_ok = false;925 926 for (i = 0; i < 3; i++) {927 rtl8188eu_phy_iqcalibrate(priv, result, i);928 929 if (i == 1) {930 simu = rtl8xxxu_simularity_compare(priv,931 result, 0, 1);932 if (simu) {933 candidate = 0;934 break;935 }936 }937 938 if (i == 2) {939 simu = rtl8xxxu_simularity_compare(priv,940 result, 0, 2);941 if (simu) {942 candidate = 0;943 break;944 }945 946 simu = rtl8xxxu_simularity_compare(priv,947 result, 1, 2);948 if (simu)949 candidate = 1;950 else951 candidate = 3;952 }953 }954 955 if (candidate >= 0) {956 reg_e94 = result[candidate][0];957 priv->rege94 = reg_e94;958 reg_e9c = result[candidate][1];959 priv->rege9c = reg_e9c;960 reg_ea4 = result[candidate][2];961 reg_eac = result[candidate][3];962 reg_eb4 = result[candidate][4];963 priv->regeb4 = reg_eb4;964 reg_ebc = result[candidate][5];965 priv->regebc = reg_ebc;966 reg_ec4 = result[candidate][6];967 reg_ecc = result[candidate][7];968 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);969 dev_dbg(dev,970 "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",971 __func__, reg_e94, reg_e9c, reg_ea4, reg_eac,972 reg_eb4, reg_ebc, reg_ec4, reg_ecc);973 path_a_ok = true;974 } else {975 reg_e94 = 0x100;976 reg_eb4 = 0x100;977 priv->rege94 = 0x100;978 priv->regeb4 = 0x100;979 reg_e9c = 0x0;980 reg_ebc = 0x0;981 priv->rege9c = 0x0;982 priv->regebc = 0x0;983 }984 985 if (reg_e94 && candidate >= 0)986 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,987 candidate, (reg_ea4 == 0));988 989 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,990 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);991}992 993static void rtl8188e_disabled_to_emu(struct rtl8xxxu_priv *priv)994{995 u16 val16;996 997 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);998 val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);999 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);1000}1001 1002static int rtl8188e_emu_to_active(struct rtl8xxxu_priv *priv)1003{1004 u8 val8;1005 u32 val32;1006 u16 val16;1007 int count, ret = 0;1008 1009 /* wait till 0x04[17] = 1 power ready*/1010 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {1011 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);1012 if (val32 & BIT(17))1013 break;1014 1015 udelay(10);1016 }1017 1018 if (!count) {1019 ret = -EBUSY;1020 goto exit;1021 }1022 1023 /* reset baseband */1024 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);1025 val8 &= ~(SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN);1026 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);1027 1028 /*0x24[23] = 2b'01 schmit trigger */1029 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);1030 val32 |= BIT(23);1031 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);1032 1033 /* 0x04[15] = 0 disable HWPDN (control by DRV)*/1034 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);1035 val16 &= ~APS_FSMCO_HW_POWERDOWN;1036 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);1037 1038 /*0x04[12:11] = 2b'00 disable WL suspend*/1039 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);1040 val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);1041 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);1042 1043 /* set, then poll until 0 */1044 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);1045 val32 |= APS_FSMCO_MAC_ENABLE;1046 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);1047 1048 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {1049 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);1050 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {1051 ret = 0;1052 break;1053 }1054 udelay(10);1055 }1056 1057 if (!count) {1058 ret = -EBUSY;1059 goto exit;1060 }1061 1062 /* LDO normal mode*/1063 val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL);1064 val8 &= ~BIT(4);1065 rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8);1066 1067exit:1068 return ret;1069}1070 1071static int rtl8188eu_active_to_emu(struct rtl8xxxu_priv *priv)1072{1073 u8 val8;1074 1075 /* Turn off RF */1076 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);1077 val8 &= ~RF_ENABLE;1078 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);1079 1080 /* LDO Sleep mode */1081 val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL);1082 val8 |= BIT(4);1083 rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8);1084 1085 return 0;1086}1087 1088static int rtl8188eu_emu_to_disabled(struct rtl8xxxu_priv *priv)1089{1090 u32 val32;1091 u16 val16;1092 u8 val8;1093 1094 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);1095 val32 |= BIT(23);1096 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);1097 1098 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);1099 val16 &= ~APS_FSMCO_PCIE;1100 val16 |= APS_FSMCO_HW_SUSPEND;1101 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);1102 1103 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x00);1104 1105 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG + 1);1106 val8 &= ~BIT(4);1107 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG + 1, val8);1108 1109 /* Set USB suspend enable local register 0xfe10[4]=1 */1110 val8 = rtl8xxxu_read8(priv, 0xfe10);1111 val8 |= BIT(4);1112 rtl8xxxu_write8(priv, 0xfe10, val8);1113 1114 return 0;1115}1116 1117static int rtl8188eu_active_to_lps(struct rtl8xxxu_priv *priv)1118{1119 struct device *dev = &priv->udev->dev;1120 u8 val8;1121 u16 val16;1122 u32 val32;1123 int retry, retval;1124 1125 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x7f);1126 1127 retry = 100;1128 retval = -EBUSY;1129 /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */1130 do {1131 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);1132 if (!val32) {1133 retval = 0;1134 break;1135 }1136 } while (retry--);1137 1138 if (!retry) {1139 dev_warn(dev, "Failed to flush TX queue\n");1140 retval = -EBUSY;1141 goto out;1142 }1143 1144 /* Disable CCK and OFDM, clock gated */1145 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);1146 val8 &= ~SYS_FUNC_BBRSTB;1147 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);1148 1149 udelay(2);1150 1151 /* Reset MAC TRX */1152 val16 = rtl8xxxu_read16(priv, REG_CR);1153 val16 |= 0xff;1154 val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE);1155 rtl8xxxu_write16(priv, REG_CR, val16);1156 1157 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);1158 val8 |= DUAL_TSF_TX_OK;1159 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);1160 1161out:1162 return retval;1163}1164 1165static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv)1166{1167 u16 val16;1168 int ret;1169 1170 rtl8188e_disabled_to_emu(priv);1171 1172 ret = rtl8188e_emu_to_active(priv);1173 if (ret)1174 goto exit;1175 1176 /*1177 * Enable MAC DMA/WMAC/SCHEDULE/SEC block1178 * Set CR bit10 to enable 32k calibration.1179 * We do not set CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE here1180 * due to a hardware bug in the 88E, requiring those to be1181 * set after REG_TRXFF_BNDY is set. If not the RXFF bundary1182 * will get set to a larger buffer size than the real buffer1183 * size.1184 */1185 val16 = (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |1186 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |1187 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |1188 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);1189 rtl8xxxu_write16(priv, REG_CR, val16);1190 1191exit:1192 return ret;1193}1194 1195static void rtl8188eu_power_off(struct rtl8xxxu_priv *priv)1196{1197 u8 val8;1198 u16 val16;1199 1200 rtl8xxxu_flush_fifo(priv);1201 1202 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);1203 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;1204 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);1205 1206 /* Turn off RF */1207 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);1208 1209 rtl8188eu_active_to_lps(priv);1210 1211 /* Reset Firmware if running in RAM */1212 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)1213 rtl8xxxu_firmware_self_reset(priv);1214 1215 /* Reset MCU */1216 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);1217 val16 &= ~SYS_FUNC_CPU_ENABLE;1218 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);1219 1220 /* Reset MCU ready status */1221 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);1222 1223 /* 32K_CTRL looks to be very 8188e specific */1224 val8 = rtl8xxxu_read8(priv, REG_32K_CTRL);1225 val8 &= ~BIT(0);1226 rtl8xxxu_write8(priv, REG_32K_CTRL, val8);1227 1228 rtl8188eu_active_to_emu(priv);1229 rtl8188eu_emu_to_disabled(priv);1230 1231 /* Reset MCU IO Wrapper */1232 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);1233 val8 &= ~BIT(3);1234 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);1235 1236 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);1237 val8 |= BIT(3);1238 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);1239 1240 /* Vendor driver refers to GPIO_IN */1241 val8 = rtl8xxxu_read8(priv, REG_GPIO_PIN_CTRL);1242 /* Vendor driver refers to GPIO_OUT */1243 rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 1, val8);1244 rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 2, 0xff);1245 1246 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL);1247 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL, val8 << 4);1248 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL + 1);1249 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL + 1, val8 | 0x0f);1250 1251 /*1252 * Set LNA, TRSW, EX_PA Pin to output mode1253 * Referred to as REG_BB_PAD_CTRL in 8188eu vendor driver1254 */1255 rtl8xxxu_write32(priv, REG_PAD_CTRL1, 0x00080808);1256 1257 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x00);1258 1259 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, 0x00000000);1260}1261 1262static void rtl8188e_enable_rf(struct rtl8xxxu_priv *priv)1263{1264 u32 val32;1265 1266 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB);1267 1268 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);1269 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);1270 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A;1271 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);1272 1273 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);1274}1275 1276static void rtl8188e_disable_rf(struct rtl8xxxu_priv *priv)1277{1278 u32 val32;1279 1280 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);1281 val32 &= ~OFDM_RF_PATH_TX_MASK;1282 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);1283 1284 /* Power down RF module */1285 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);1286 1287 rtl8188eu_active_to_emu(priv);1288}1289 1290static void rtl8188e_usb_quirks(struct rtl8xxxu_priv *priv)1291{1292 u16 val16;1293 1294 /*1295 * Technically this is not a USB quirk, but a chip quirk.1296 * This has to be done after REG_TRXFF_BNDY is set, see1297 * rtl8188eu_power_on() for details.1298 */1299 val16 = rtl8xxxu_read16(priv, REG_CR);1300 val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE);1301 rtl8xxxu_write16(priv, REG_CR, val16);1302 1303 rtl8xxxu_gen2_usb_quirks(priv);1304 1305 /* Pre-TX enable WEP/TKIP security */1306 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8188E + 3, 0x01);1307}1308 1309static s8 rtl8188e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)1310{1311 /* only use lna 0/1/2/3/7 */1312 static const s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};1313 /* only use lna 3/7 */1314 static const s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33};1315 1316 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;1317 s8 rx_pwr_all = 0x00;1318 u8 vga_idx, lna_idx;1319 s8 lna_gain = 0;1320 1321 lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK);1322 vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK);1323 1324 if (priv->chip_cut >= 8) /* cut I */ /* SMIC */1325 lna_gain = lna_gain_table_0[lna_idx];1326 else /* TSMC */1327 lna_gain = lna_gain_table_1[lna_idx];1328 1329 rx_pwr_all = lna_gain - (2 * vga_idx);1330 1331 return rx_pwr_all;1332}1333 1334static int rtl8188eu_led_brightness_set(struct led_classdev *led_cdev,1335 enum led_brightness brightness)1336{1337 struct rtl8xxxu_priv *priv = container_of(led_cdev,1338 struct rtl8xxxu_priv,1339 led_cdev);1340 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2);1341 1342 if (brightness == LED_OFF) {1343 ledcfg &= ~LEDCFG2_HW_LED_CONTROL;1344 ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE;1345 } else if (brightness == LED_ON) {1346 ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE);1347 ledcfg |= LEDCFG2_SW_LED_CONTROL;1348 } else if (brightness == RTL8XXXU_HW_LED_CONTROL) {1349 ledcfg &= ~LEDCFG2_SW_LED_DISABLE;1350 ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE;1351 }1352 1353 rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg);1354 1355 return 0;1356}1357 1358static void rtl8188e_set_tx_rpt_timing(struct rtl8xxxu_ra_info *ra, u8 timing)1359{1360 u8 idx;1361 1362 for (idx = 0; idx < 5; idx++)1363 if (dynamic_tx_rpt_timing[idx] == ra->rpt_time)1364 break;1365 1366 if (timing == DEFAULT_TIMING) {1367 idx = 0; /* 200ms */1368 } else if (timing == INCREASE_TIMING) {1369 if (idx < 5)1370 idx++;1371 } else if (timing == DECREASE_TIMING) {1372 if (idx > 0)1373 idx--;1374 }1375 1376 ra->rpt_time = dynamic_tx_rpt_timing[idx];1377}1378 1379static void rtl8188e_rate_down(struct rtl8xxxu_ra_info *ra)1380{1381 u8 rate_id = ra->pre_rate;1382 u8 lowest_rate = ra->lowest_rate;1383 u8 highest_rate = ra->highest_rate;1384 s8 i;1385 1386 if (rate_id > highest_rate) {1387 rate_id = highest_rate;1388 } else if (ra->rate_sgi) {1389 ra->rate_sgi = 0;1390 } else if (rate_id > lowest_rate) {1391 if (rate_id > 0) {1392 for (i = rate_id - 1; i >= lowest_rate; i--) {1393 if (ra->ra_use_rate & BIT(i)) {1394 rate_id = i;1395 goto rate_down_finish;1396 }1397 }1398 }1399 } else if (rate_id <= lowest_rate) {1400 rate_id = lowest_rate;1401 }1402 1403rate_down_finish:1404 if (ra->ra_waiting_counter == 1) {1405 ra->ra_waiting_counter++;1406 ra->ra_pending_counter++;1407 } else if (ra->ra_waiting_counter > 1) {1408 ra->ra_waiting_counter = 0;1409 ra->ra_pending_counter = 0;1410 }1411 1412 if (ra->ra_pending_counter >= 4)1413 ra->ra_pending_counter = 4;1414 1415 ra->ra_drop_after_down = 1;1416 1417 ra->decision_rate = rate_id;1418 1419 rtl8188e_set_tx_rpt_timing(ra, DECREASE_TIMING);1420}1421 1422static void rtl8188e_rate_up(struct rtl8xxxu_ra_info *ra)1423{1424 u8 rate_id = ra->pre_rate;1425 u8 highest_rate = ra->highest_rate;1426 u8 i;1427 1428 if (ra->ra_waiting_counter == 1) {1429 ra->ra_waiting_counter = 0;1430 ra->ra_pending_counter = 0;1431 } else if (ra->ra_waiting_counter > 1) {1432 ra->pre_rssi_sta_ra = ra->rssi_sta_ra;1433 goto rate_up_finish;1434 }1435 1436 rtl8188e_set_tx_rpt_timing(ra, DEFAULT_TIMING);1437 1438 if (rate_id < highest_rate) {1439 for (i = rate_id + 1; i <= highest_rate; i++) {1440 if (ra->ra_use_rate & BIT(i)) {1441 rate_id = i;1442 goto rate_up_finish;1443 }1444 }1445 } else if (rate_id == highest_rate) {1446 if (ra->sgi_enable && !ra->rate_sgi)1447 ra->rate_sgi = 1;1448 else if (!ra->sgi_enable)1449 ra->rate_sgi = 0;1450 } else { /* rate_id > ra->highest_rate */1451 rate_id = highest_rate;1452 }1453 1454rate_up_finish:1455 if (ra->ra_waiting_counter == (4 + pending_for_rate_up_fail[ra->ra_pending_counter]))1456 ra->ra_waiting_counter = 0;1457 else1458 ra->ra_waiting_counter++;1459 1460 ra->decision_rate = rate_id;1461}1462 1463static void rtl8188e_reset_ra_counter(struct rtl8xxxu_ra_info *ra)1464{1465 u8 rate_id = ra->decision_rate;1466 1467 ra->nsc_up = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1;1468 ra->nsc_down = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1;1469}1470 1471static void rtl8188e_rate_decision(struct rtl8xxxu_ra_info *ra)1472{1473 struct rtl8xxxu_priv *priv = container_of(ra, struct rtl8xxxu_priv, ra_info);1474 const u8 *retry_penalty_idx_0;1475 const u8 *retry_penalty_idx_1;1476 const u8 *retry_penalty_up_idx;1477 u8 rate_id, penalty_id1, penalty_id2;1478 int i;1479 1480 if (ra->total == 0)1481 return;1482 1483 if (ra->ra_drop_after_down) {1484 ra->ra_drop_after_down--;1485 1486 rtl8188e_reset_ra_counter(ra);1487 1488 return;1489 }1490 1491 if (priv->chip_cut == 8) { /* cut I */1492 retry_penalty_idx_0 = retry_penalty_idx_cut_i[0];1493 retry_penalty_idx_1 = retry_penalty_idx_cut_i[1];1494 retry_penalty_up_idx = retry_penalty_up_idx_cut_i;1495 } else {1496 retry_penalty_idx_0 = retry_penalty_idx_normal[0];1497 retry_penalty_idx_1 = retry_penalty_idx_normal[1];1498 retry_penalty_up_idx = retry_penalty_up_idx_normal;1499 }1500 1501 if (ra->rssi_sta_ra < (ra->pre_rssi_sta_ra - 3) ||1502 ra->rssi_sta_ra > (ra->pre_rssi_sta_ra + 3)) {1503 ra->pre_rssi_sta_ra = ra->rssi_sta_ra;1504 ra->ra_waiting_counter = 0;1505 ra->ra_pending_counter = 0;1506 }1507 1508 /* Start RA decision */1509 if (ra->pre_rate > ra->highest_rate)1510 rate_id = ra->highest_rate;1511 else1512 rate_id = ra->pre_rate;1513 1514 /* rate down */1515 if (ra->rssi_sta_ra > rssi_threshold[rate_id])1516 penalty_id1 = retry_penalty_idx_0[rate_id];1517 else1518 penalty_id1 = retry_penalty_idx_1[rate_id];1519 1520 for (i = 0; i < 5; i++)1521 ra->nsc_down += ra->retry[i] * retry_penalty[penalty_id1][i];1522 1523 if (ra->nsc_down > (ra->total * retry_penalty[penalty_id1][5]))1524 ra->nsc_down -= ra->total * retry_penalty[penalty_id1][5];1525 else1526 ra->nsc_down = 0;1527 1528 /* rate up */1529 penalty_id2 = retry_penalty_up_idx[rate_id];1530 1531 for (i = 0; i < 5; i++)1532 ra->nsc_up += ra->retry[i] * retry_penalty[penalty_id2][i];1533 1534 if (ra->nsc_up > (ra->total * retry_penalty[penalty_id2][5]))1535 ra->nsc_up -= ra->total * retry_penalty[penalty_id2][5];1536 else1537 ra->nsc_up = 0;1538 1539 if (ra->nsc_down < n_threshold_low[rate_id] ||1540 ra->drop > dropping_necessary[rate_id]) {1541 rtl8188e_rate_down(ra);1542 1543 rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate,1544 ra->rate_sgi, priv->ra_report.txrate.bw);1545 } else if (ra->nsc_up > n_threshold_high[rate_id]) {1546 rtl8188e_rate_up(ra);1547 1548 rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate,1549 ra->rate_sgi, priv->ra_report.txrate.bw);1550 }1551 1552 if (ra->decision_rate == ra->pre_rate)1553 ra->dynamic_tx_rpt_timing_counter++;1554 else1555 ra->dynamic_tx_rpt_timing_counter = 0;1556 1557 if (ra->dynamic_tx_rpt_timing_counter >= 4) {1558 /* Rate didn't change 4 times, extend RPT timing */1559 rtl8188e_set_tx_rpt_timing(ra, INCREASE_TIMING);1560 ra->dynamic_tx_rpt_timing_counter = 0;1561 }1562 1563 ra->pre_rate = ra->decision_rate;1564 1565 rtl8188e_reset_ra_counter(ra);1566}1567 1568static void rtl8188e_power_training_try_state(struct rtl8xxxu_ra_info *ra)1569{1570 ra->pt_try_state = 0;1571 switch (ra->pt_mode_ss) {1572 case 3:1573 if (ra->decision_rate >= DESC_RATE_MCS13)1574 ra->pt_try_state = 1;1575 break;1576 case 2:1577 if (ra->decision_rate >= DESC_RATE_MCS5)1578 ra->pt_try_state = 1;1579 break;1580 case 1:1581 if (ra->decision_rate >= DESC_RATE_48M)1582 ra->pt_try_state = 1;1583 break;1584 case 0:1585 if (ra->decision_rate >= DESC_RATE_11M)1586 ra->pt_try_state = 1;1587 break;1588 default:1589 break;1590 }1591 1592 if (ra->rssi_sta_ra < 48) {1593 ra->pt_stage = 0;1594 } else if (ra->pt_try_state == 1) {1595 if ((ra->pt_stop_count >= 10) ||1596 (ra->pt_pre_rssi > ra->rssi_sta_ra + 5) ||1597 (ra->pt_pre_rssi < ra->rssi_sta_ra - 5) ||1598 (ra->decision_rate != ra->pt_pre_rate)) {1599 if (ra->pt_stage == 0)1600 ra->pt_stage = 1;1601 else if (ra->pt_stage == 1)1602 ra->pt_stage = 3;1603 else1604 ra->pt_stage = 5;1605 1606 ra->pt_pre_rssi = ra->rssi_sta_ra;1607 ra->pt_stop_count = 0;1608 } else {1609 ra->ra_stage = 0;1610 ra->pt_stop_count++;1611 }1612 } else {1613 ra->pt_stage = 0;1614 ra->ra_stage = 0;1615 }1616 1617 ra->pt_pre_rate = ra->decision_rate;1618 1619 /* TODO: implement the "false alarm" statistics for this */1620 /* Disable power training when noisy environment */1621 /* if (p_dm_odm->is_disable_power_training) { */1622 if (1) {1623 ra->pt_stage = 0;1624 ra->ra_stage = 0;1625 ra->pt_stop_count = 0;1626 }1627}1628 1629static void rtl8188e_power_training_decision(struct rtl8xxxu_ra_info *ra)1630{1631 u8 temp_stage;1632 u32 numsc;1633 u32 num_total;1634 u8 stage_id;1635 u8 j;1636 1637 numsc = 0;1638 num_total = ra->total * pt_penalty[5];1639 for (j = 0; j <= 4; j++) {1640 numsc += ra->retry[j] * pt_penalty[j];1641 1642 if (numsc > num_total)1643 break;1644 }1645 1646 j >>= 1;1647 temp_stage = (ra->pt_stage + 1) >> 1;1648 if (temp_stage > j)1649 stage_id = temp_stage - j;1650 else1651 stage_id = 0;1652 1653 ra->pt_smooth_factor = (ra->pt_smooth_factor >> 1) +1654 (ra->pt_smooth_factor >> 2) +1655 stage_id * 16 + 2;1656 if (ra->pt_smooth_factor > 192)1657 ra->pt_smooth_factor = 192;1658 stage_id = ra->pt_smooth_factor >> 6;1659 temp_stage = stage_id * 2;1660 if (temp_stage != 0)1661 temp_stage--;1662 if (ra->drop > 3)1663 temp_stage = 0;1664 ra->pt_stage = temp_stage;1665}1666 1667void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb)1668{1669 u32 *_rx_desc = (u32 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16));1670 struct rtl8xxxu_rxdesc16 *rx_desc = (struct rtl8xxxu_rxdesc16 *)_rx_desc;1671 struct device *dev = &priv->udev->dev;1672 struct rtl8xxxu_ra_info *ra = &priv->ra_info;1673 u32 tx_rpt_len = rx_desc->pktlen & 0x3ff;1674 u32 items = tx_rpt_len / TX_RPT2_ITEM_SIZE;1675 u64 macid_valid = ((u64)_rx_desc[5] << 32) | _rx_desc[4];1676 u32 macid;1677 u8 *rpt = skb->data;1678 bool valid;1679 u16 min_rpt_time = 0x927c;1680 1681 dev_dbg(dev, "%s: len: %d items: %d\n", __func__, tx_rpt_len, items);1682 1683 /* We only use macid 0, so only the first item is relevant.1684 * AP mode will use more of them if it's ever implemented.1685 */1686 if (!priv->vifs[0] || priv->vifs[0]->type == NL80211_IFTYPE_STATION)1687 items = 1;1688 1689 for (macid = 0; macid < items; macid++) {1690 valid = false;1691 1692 if (macid < 64)1693 valid = macid_valid & BIT(macid);1694 1695 if (valid) {1696 ra->retry[0] = le16_to_cpu(*(__le16 *)rpt);1697 ra->retry[1] = rpt[2];1698 ra->retry[2] = rpt[3];1699 ra->retry[3] = rpt[4];1700 ra->retry[4] = rpt[5];1701 ra->drop = rpt[6];1702 ra->total = ra->retry[0] + ra->retry[1] + ra->retry[2] +1703 ra->retry[3] + ra->retry[4] + ra->drop;1704 1705 if (ra->total > 0) {1706 if (ra->ra_stage < 5)1707 rtl8188e_rate_decision(ra);1708 else if (ra->ra_stage == 5)1709 rtl8188e_power_training_try_state(ra);1710 else /* ra->ra_stage == 6 */1711 rtl8188e_power_training_decision(ra);1712 1713 if (ra->ra_stage <= 5)1714 ra->ra_stage++;1715 else1716 ra->ra_stage = 0;1717 }1718 } else if (macid == 0) {1719 dev_warn(dev, "%s: TX report item 0 not valid\n", __func__);1720 }1721 1722 dev_dbg(dev, "%s: valid: %d retry: %d %d %d %d %d drop: %d\n",1723 __func__, valid,1724 ra->retry[0], ra->retry[1], ra->retry[2],1725 ra->retry[3], ra->retry[4], ra->drop);1726 1727 if (min_rpt_time > ra->rpt_time)1728 min_rpt_time = ra->rpt_time;1729 1730 rpt += TX_RPT2_ITEM_SIZE;1731 }1732 1733 if (min_rpt_time != ra->pre_min_rpt_time) {1734 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, min_rpt_time);1735 ra->pre_min_rpt_time = min_rpt_time;1736 }1737}1738 1739static void rtl8188e_arfb_refresh(struct rtl8xxxu_ra_info *ra)1740{1741 s8 i;1742 1743 ra->ra_use_rate = ra->rate_mask;1744 1745 /* Highest rate */1746 if (ra->ra_use_rate) {1747 for (i = RATESIZE; i >= 0; i--) {1748 if (ra->ra_use_rate & BIT(i)) {1749 ra->highest_rate = i;1750 break;1751 }1752 }1753 } else {1754 ra->highest_rate = 0;1755 }1756 1757 /* Lowest rate */1758 if (ra->ra_use_rate) {1759 for (i = 0; i < RATESIZE; i++) {1760 if (ra->ra_use_rate & BIT(i)) {1761 ra->lowest_rate = i;1762 break;1763 }1764 }1765 } else {1766 ra->lowest_rate = 0;1767 }1768 1769 if (ra->highest_rate > DESC_RATE_MCS7)1770 ra->pt_mode_ss = 3;1771 else if (ra->highest_rate > DESC_RATE_54M)1772 ra->pt_mode_ss = 2;1773 else if (ra->highest_rate > DESC_RATE_11M)1774 ra->pt_mode_ss = 1;1775 else1776 ra->pt_mode_ss = 0;1777}1778 1779static void1780rtl8188e_update_rate_mask(struct rtl8xxxu_priv *priv,1781 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,1782 u8 macid)1783{1784 struct rtl8xxxu_ra_info *ra = &priv->ra_info;1785 1786 ra->rate_id = rateid;1787 ra->rate_mask = ramask;1788 ra->sgi_enable = sgi;1789 1790 rtl8188e_arfb_refresh(ra);1791}1792 1793static void rtl8188e_ra_set_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)1794{1795 priv->ra_info.rssi_sta_ra = rssi;1796}1797 1798void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra)1799{1800 ra->decision_rate = DESC_RATE_MCS7;1801 ra->pre_rate = DESC_RATE_MCS7;1802 ra->highest_rate = DESC_RATE_MCS7;1803 ra->lowest_rate = 0;1804 ra->rate_id = 0;1805 ra->rate_mask = 0xfffff;1806 ra->rssi_sta_ra = 0;1807 ra->pre_rssi_sta_ra = 0;1808 ra->sgi_enable = 0;1809 ra->ra_use_rate = 0xfffff;1810 ra->nsc_down = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2;1811 ra->nsc_up = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2;1812 ra->rate_sgi = 0;1813 ra->rpt_time = 0x927c;1814 ra->drop = 0;1815 ra->retry[0] = 0;1816 ra->retry[1] = 0;1817 ra->retry[2] = 0;1818 ra->retry[3] = 0;1819 ra->retry[4] = 0;1820 ra->total = 0;1821 ra->ra_waiting_counter = 0;1822 ra->ra_pending_counter = 0;1823 ra->ra_drop_after_down = 0;1824 1825 ra->pt_try_state = 0;1826 ra->pt_stage = 5;1827 ra->pt_smooth_factor = 192;1828 ra->pt_stop_count = 0;1829 ra->pt_pre_rate = 0;1830 ra->pt_pre_rssi = 0;1831 ra->pt_mode_ss = 0;1832 ra->ra_stage = 0;1833}1834 1835struct rtl8xxxu_fileops rtl8188eu_fops = {1836 .identify_chip = rtl8188eu_identify_chip,1837 .parse_efuse = rtl8188eu_parse_efuse,1838 .load_firmware = rtl8188eu_load_firmware,1839 .power_on = rtl8188eu_power_on,1840 .power_off = rtl8188eu_power_off,1841 .read_efuse = rtl8xxxu_read_efuse,1842 .reset_8051 = rtl8188eu_reset_8051,1843 .llt_init = rtl8xxxu_init_llt_table,1844 .init_phy_bb = rtl8188eu_init_phy_bb,1845 .init_phy_rf = rtl8188eu_init_phy_rf,1846 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,1847 .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate,1848 .config_channel = rtl8188eu_config_channel,1849 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,1850 .parse_phystats = rtl8723au_rx_parse_phystats,1851 .init_aggregation = rtl8188eu_init_aggregation,1852 .enable_rf = rtl8188e_enable_rf,1853 .disable_rf = rtl8188e_disable_rf,1854 .usb_quirks = rtl8188e_usb_quirks,1855 .set_tx_power = rtl8188f_set_tx_power,1856 .update_rate_mask = rtl8188e_update_rate_mask,1857 .report_connect = rtl8xxxu_gen2_report_connect,1858 .report_rssi = rtl8188e_ra_set_rssi,1859 .fill_txdesc = rtl8xxxu_fill_txdesc_v3,1860 .set_crystal_cap = rtl8188f_set_crystal_cap,1861 .cck_rssi = rtl8188e_cck_rssi,1862 .led_classdev_brightness_set = rtl8188eu_led_brightness_set,1863 .writeN_block_size = 128,1864 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),1865 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),1866 .has_tx_report = 1,1867 .init_reg_pkt_life_time = 1,1868 .gen2_thermal_meter = 1,1869 .max_sec_cam_num = 32,1870 .adda_1t_init = 0x0b1b25a0,1871 .adda_1t_path_on = 0x0bdb25a0,1872 /*1873 * Use 9K for 8188e normal chip1874 * Max RX buffer = 10K - max(TxReportSize(64*8), WOLPattern(16*24))1875 */1876 .trxff_boundary = 0x25ff,1877 .pbp_rx = PBP_PAGE_SIZE_128,1878 .pbp_tx = PBP_PAGE_SIZE_128,1879 .mactable = rtl8188e_mac_init_table,1880 .total_page_num = TX_TOTAL_PAGE_NUM_8188E,1881 .page_num_hi = TX_PAGE_NUM_HI_PQ_8188E,1882 .page_num_lo = TX_PAGE_NUM_LO_PQ_8188E,1883 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188E,1884 .last_llt_entry = 175,1885};1886