1768 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * RTL8XXXU mac80211 USB driver - 8192e specific subdriver4 *5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>6 *7 * Portions, notably calibration code:8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.9 *10 * This driver was written as a replacement for the vendor provided11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in12 * their programming interface, I have started adding support for13 * additional 8xxx chips like the 8192cu, 8188cus, etc.14 */15 16#include "regs.h"17#include "rtl8xxxu.h"18 19static const struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {20 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},21 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},22 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},23 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},24 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},25 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},26 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},27 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},28 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},29 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},30 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},31 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},32 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},33 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},34 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},35 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},36 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},37 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},38 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},39 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},40 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},41 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},42 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},43 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},44 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},45 {0x70b, 0x87},46 {0xffff, 0xff},47};48 49static const struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {50 {0x800, 0x80040000}, {0x804, 0x00000003},51 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},52 {0x810, 0x10001331}, {0x814, 0x020c3d10},53 {0x818, 0x02220385}, {0x81c, 0x00000000},54 {0x820, 0x01000100}, {0x824, 0x00390204},55 {0x828, 0x01000100}, {0x82c, 0x00390204},56 {0x830, 0x32323232}, {0x834, 0x30303030},57 {0x838, 0x30303030}, {0x83c, 0x30303030},58 {0x840, 0x00010000}, {0x844, 0x00010000},59 {0x848, 0x28282828}, {0x84c, 0x28282828},60 {0x850, 0x00000000}, {0x854, 0x00000000},61 {0x858, 0x009a009a}, {0x85c, 0x01000014},62 {0x860, 0x66f60000}, {0x864, 0x061f0000},63 {0x868, 0x30303030}, {0x86c, 0x30303030},64 {0x870, 0x00000000}, {0x874, 0x55004200},65 {0x878, 0x08080808}, {0x87c, 0x00000000},66 {0x880, 0xb0000c1c}, {0x884, 0x00000001},67 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},68 {0x890, 0x00000800}, {0x894, 0xfffffffe},69 {0x898, 0x40302010}, {0x900, 0x00000000},70 {0x904, 0x00000023}, {0x908, 0x00000000},71 {0x90c, 0x81121313}, {0x910, 0x806c0001},72 {0x914, 0x00000001}, {0x918, 0x00000000},73 {0x91c, 0x00010000}, {0x924, 0x00000001},74 {0x928, 0x00000000}, {0x92c, 0x00000000},75 {0x930, 0x00000000}, {0x934, 0x00000000},76 {0x938, 0x00000000}, {0x93c, 0x00000000},77 {0x940, 0x00000000}, {0x944, 0x00000000},78 {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},79 {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},80 {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},81 {0xa14, 0x1114d028}, {0xa18, 0x00881117},82 {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},83 {0xa24, 0x090e1317}, {0xa28, 0x00000204},84 {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},85 {0xa74, 0x00000007}, {0xa78, 0x00000900},86 {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},87 {0xb38, 0x00000000}, {0xc00, 0x48071d40},88 {0xc04, 0x03a05633}, {0xc08, 0x000000e4},89 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},90 {0xc14, 0x40000100}, {0xc18, 0x08800000},91 {0xc1c, 0x40000100}, {0xc20, 0x00000000},92 {0xc24, 0x00000000}, {0xc28, 0x00000000},93 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},94 {0xc34, 0x469652af}, {0xc38, 0x49795994},95 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},96 {0xc44, 0x000100b7}, {0xc48, 0xec020107},97 {0xc4c, 0x007f037f},98#ifdef EXT_PA_8192EU99 /* External PA or external LNA */100 {0xc50, 0x00340220},101#else102 {0xc50, 0x00340020},103#endif104 {0xc54, 0x0080801f},105#ifdef EXT_PA_8192EU106 /* External PA or external LNA */107 {0xc58, 0x00000220},108#else109 {0xc58, 0x00000020},110#endif111 {0xc5c, 0x00248492}, {0xc60, 0x00000000},112 {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},113 {0xc6c, 0x00000036}, {0xc70, 0x00000600},114 {0xc74, 0x02013169}, {0xc78, 0x0000001f},115 {0xc7c, 0x00b91612},116#ifdef EXT_PA_8192EU117 /* External PA or external LNA */118 {0xc80, 0x2d4000b5},119#else120 {0xc80, 0x40000100},121#endif122 {0xc84, 0x21f60000},123#ifdef EXT_PA_8192EU124 /* External PA or external LNA */125 {0xc88, 0x2d4000b5},126#else127 {0xc88, 0x40000100},128#endif129 {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},130 {0xc94, 0x00000000}, {0xc98, 0x00121820},131 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},132 {0xca4, 0x000300a0}, {0xca8, 0x00000000},133 {0xcac, 0x00000000}, {0xcb0, 0x00000000},134 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},135 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},136 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},137 {0xccc, 0x00000000}, {0xcd0, 0x00000000},138 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},139 {0xcdc, 0x00766932}, {0xce0, 0x00222222},140 {0xce4, 0x00040000}, {0xce8, 0x77644302},141 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},142 {0xd04, 0x00020403}, {0xd08, 0x0000907f},143 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},144 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},145 {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},146 {0xd30, 0x00000000}, {0xd34, 0x80608000},147 {0xd38, 0x00000000}, {0xd3c, 0x00127353},148 {0xd40, 0x00000000}, {0xd44, 0x00000000},149 {0xd48, 0x00000000}, {0xd4c, 0x00000000},150 {0xd50, 0x6437140a}, {0xd54, 0x00000000},151 {0xd58, 0x00000282}, {0xd5c, 0x30032064},152 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},153 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},154 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},155 {0xd78, 0x000e3c24}, {0xd80, 0x01081008},156 {0xd84, 0x00000800}, {0xd88, 0xf0b50000},157 {0xe00, 0x30303030}, {0xe04, 0x30303030},158 {0xe08, 0x03903030}, {0xe10, 0x30303030},159 {0xe14, 0x30303030}, {0xe18, 0x30303030},160 {0xe1c, 0x30303030}, {0xe28, 0x00000000},161 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},162 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},163 {0xe40, 0x01007c00}, {0xe44, 0x01004800},164 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},165 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},166 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},167 {0xe60, 0x00000008}, {0xe68, 0x0fc05656},168 {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},169 {0xe74, 0x0c005656}, {0xe78, 0x0c005656},170 {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},171 {0xe84, 0x03c09696}, {0xe88, 0x0c005656},172 {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},173 {0xed4, 0x03c09696}, {0xed8, 0x03c09696},174 {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},175 {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},176 {0xee8, 0x00000001}, {0xf14, 0x00000003},177 {0xf4c, 0x00000000}, {0xf00, 0x00000300},178 {0xffff, 0xffffffff},179};180 181static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {182 {0xc78, 0xfb000001}, {0xc78, 0xfb010001},183 {0xc78, 0xfb020001}, {0xc78, 0xfb030001},184 {0xc78, 0xfb040001}, {0xc78, 0xfb050001},185 {0xc78, 0xfa060001}, {0xc78, 0xf9070001},186 {0xc78, 0xf8080001}, {0xc78, 0xf7090001},187 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},188 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},189 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},190 {0xc78, 0xf0100001}, {0xc78, 0xef110001},191 {0xc78, 0xee120001}, {0xc78, 0xed130001},192 {0xc78, 0xec140001}, {0xc78, 0xeb150001},193 {0xc78, 0xea160001}, {0xc78, 0xe9170001},194 {0xc78, 0xe8180001}, {0xc78, 0xe7190001},195 {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},196 {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},197 {0xc78, 0x061e0001}, {0xc78, 0x051f0001},198 {0xc78, 0x04200001}, {0xc78, 0x03210001},199 {0xc78, 0xaa220001}, {0xc78, 0xa9230001},200 {0xc78, 0xa8240001}, {0xc78, 0xa7250001},201 {0xc78, 0xa6260001}, {0xc78, 0x85270001},202 {0xc78, 0x84280001}, {0xc78, 0x83290001},203 {0xc78, 0x252a0001}, {0xc78, 0x242b0001},204 {0xc78, 0x232c0001}, {0xc78, 0x222d0001},205 {0xc78, 0x672e0001}, {0xc78, 0x662f0001},206 {0xc78, 0x65300001}, {0xc78, 0x64310001},207 {0xc78, 0x63320001}, {0xc78, 0x62330001},208 {0xc78, 0x61340001}, {0xc78, 0x45350001},209 {0xc78, 0x44360001}, {0xc78, 0x43370001},210 {0xc78, 0x42380001}, {0xc78, 0x41390001},211 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},212 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},213 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},214 {0xc78, 0xfb400001}, {0xc78, 0xfb410001},215 {0xc78, 0xfb420001}, {0xc78, 0xfb430001},216 {0xc78, 0xfb440001}, {0xc78, 0xfb450001},217 {0xc78, 0xfa460001}, {0xc78, 0xf9470001},218 {0xc78, 0xf8480001}, {0xc78, 0xf7490001},219 {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},220 {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},221 {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},222 {0xc78, 0xf0500001}, {0xc78, 0xef510001},223 {0xc78, 0xee520001}, {0xc78, 0xed530001},224 {0xc78, 0xec540001}, {0xc78, 0xeb550001},225 {0xc78, 0xea560001}, {0xc78, 0xe9570001},226 {0xc78, 0xe8580001}, {0xc78, 0xe7590001},227 {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},228 {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},229 {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},230 {0xc78, 0x8a600001}, {0xc78, 0x89610001},231 {0xc78, 0x88620001}, {0xc78, 0x87630001},232 {0xc78, 0x86640001}, {0xc78, 0x85650001},233 {0xc78, 0x84660001}, {0xc78, 0x83670001},234 {0xc78, 0x82680001}, {0xc78, 0x6b690001},235 {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},236 {0xc78, 0x686c0001}, {0xc78, 0x676d0001},237 {0xc78, 0x666e0001}, {0xc78, 0x656f0001},238 {0xc78, 0x64700001}, {0xc78, 0x63710001},239 {0xc78, 0x62720001}, {0xc78, 0x61730001},240 {0xc78, 0x49740001}, {0xc78, 0x48750001},241 {0xc78, 0x47760001}, {0xc78, 0x46770001},242 {0xc78, 0x45780001}, {0xc78, 0x44790001},243 {0xc78, 0x437a0001}, {0xc78, 0x427b0001},244 {0xc78, 0x417c0001}, {0xc78, 0x407d0001},245 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},246 {0xc50, 0x00040022}, {0xc50, 0x00040020},247 {0xffff, 0xffffffff}248};249 250static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {251 {0xc78, 0xfa000001}, {0xc78, 0xf9010001},252 {0xc78, 0xf8020001}, {0xc78, 0xf7030001},253 {0xc78, 0xf6040001}, {0xc78, 0xf5050001},254 {0xc78, 0xf4060001}, {0xc78, 0xf3070001},255 {0xc78, 0xf2080001}, {0xc78, 0xf1090001},256 {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},257 {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},258 {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},259 {0xc78, 0xea100001}, {0xc78, 0xe9110001},260 {0xc78, 0xe8120001}, {0xc78, 0xe7130001},261 {0xc78, 0xe6140001}, {0xc78, 0xe5150001},262 {0xc78, 0xe4160001}, {0xc78, 0xe3170001},263 {0xc78, 0xe2180001}, {0xc78, 0xe1190001},264 {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},265 {0xc78, 0x881c0001}, {0xc78, 0x871d0001},266 {0xc78, 0x861e0001}, {0xc78, 0x851f0001},267 {0xc78, 0x84200001}, {0xc78, 0x83210001},268 {0xc78, 0x82220001}, {0xc78, 0x6a230001},269 {0xc78, 0x69240001}, {0xc78, 0x68250001},270 {0xc78, 0x67260001}, {0xc78, 0x66270001},271 {0xc78, 0x65280001}, {0xc78, 0x64290001},272 {0xc78, 0x632a0001}, {0xc78, 0x622b0001},273 {0xc78, 0x612c0001}, {0xc78, 0x602d0001},274 {0xc78, 0x472e0001}, {0xc78, 0x462f0001},275 {0xc78, 0x45300001}, {0xc78, 0x44310001},276 {0xc78, 0x43320001}, {0xc78, 0x42330001},277 {0xc78, 0x41340001}, {0xc78, 0x40350001},278 {0xc78, 0x40360001}, {0xc78, 0x40370001},279 {0xc78, 0x40380001}, {0xc78, 0x40390001},280 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},281 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},282 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},283 {0xc78, 0xfa400001}, {0xc78, 0xf9410001},284 {0xc78, 0xf8420001}, {0xc78, 0xf7430001},285 {0xc78, 0xf6440001}, {0xc78, 0xf5450001},286 {0xc78, 0xf4460001}, {0xc78, 0xf3470001},287 {0xc78, 0xf2480001}, {0xc78, 0xf1490001},288 {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},289 {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},290 {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},291 {0xc78, 0xea500001}, {0xc78, 0xe9510001},292 {0xc78, 0xe8520001}, {0xc78, 0xe7530001},293 {0xc78, 0xe6540001}, {0xc78, 0xe5550001},294 {0xc78, 0xe4560001}, {0xc78, 0xe3570001},295 {0xc78, 0xe2580001}, {0xc78, 0xe1590001},296 {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},297 {0xc78, 0x885c0001}, {0xc78, 0x875d0001},298 {0xc78, 0x865e0001}, {0xc78, 0x855f0001},299 {0xc78, 0x84600001}, {0xc78, 0x83610001},300 {0xc78, 0x82620001}, {0xc78, 0x6a630001},301 {0xc78, 0x69640001}, {0xc78, 0x68650001},302 {0xc78, 0x67660001}, {0xc78, 0x66670001},303 {0xc78, 0x65680001}, {0xc78, 0x64690001},304 {0xc78, 0x636a0001}, {0xc78, 0x626b0001},305 {0xc78, 0x616c0001}, {0xc78, 0x606d0001},306 {0xc78, 0x476e0001}, {0xc78, 0x466f0001},307 {0xc78, 0x45700001}, {0xc78, 0x44710001},308 {0xc78, 0x43720001}, {0xc78, 0x42730001},309 {0xc78, 0x41740001}, {0xc78, 0x40750001},310 {0xc78, 0x40760001}, {0xc78, 0x40770001},311 {0xc78, 0x40780001}, {0xc78, 0x40790001},312 {0xc78, 0x407a0001}, {0xc78, 0x407b0001},313 {0xc78, 0x407c0001}, {0xc78, 0x407d0001},314 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},315 {0xc50, 0x00040222}, {0xc50, 0x00040220},316 {0xffff, 0xffffffff}317};318 319static const struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {320 {0x7f, 0x00000082}, {0x81, 0x0003fc00},321 {0x00, 0x00030000}, {0x08, 0x00008400},322 {0x18, 0x00000407}, {0x19, 0x00000012},323 {0x1b, 0x00000064}, {0x1e, 0x00080009},324 {0x1f, 0x00000880}, {0x2f, 0x0001a060},325 {0x3f, 0x00000000}, {0x42, 0x000060c0},326 {0x57, 0x000d0000}, {0x58, 0x000be180},327 {0x67, 0x00001552}, {0x83, 0x00000000},328 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},329 {0xb2, 0x0008cc00}, {0xb4, 0x00043083},330 {0xb5, 0x00008166}, {0xb6, 0x0000803e},331 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},332 {0xb9, 0x00080001}, {0xba, 0x00040001},333 {0xbb, 0x00000400}, {0xbf, 0x000c0000},334 {0xc2, 0x00002400}, {0xc3, 0x00000009},335 {0xc4, 0x00040c91}, {0xc5, 0x00099999},336 {0xc6, 0x000000a3}, {0xc7, 0x00088820},337 {0xc8, 0x00076c06}, {0xc9, 0x00000000},338 {0xca, 0x00080000}, {0xdf, 0x00000180},339 {0xef, 0x000001a0}, {0x51, 0x00069545},340 {0x52, 0x0007e45e}, {0x53, 0x00000071},341 {0x56, 0x00051ff3}, {0x35, 0x000000a8},342 {0x35, 0x000001e2}, {0x35, 0x000002a8},343 {0x36, 0x00001c24}, {0x36, 0x00009c24},344 {0x36, 0x00011c24}, {0x36, 0x00019c24},345 {0x18, 0x00000c07}, {0x5a, 0x00048000},346 {0x19, 0x000739d0},347#ifdef EXT_PA_8192EU348 /* External PA or external LNA */349 {0x34, 0x0000a093}, {0x34, 0x0000908f},350 {0x34, 0x0000808c}, {0x34, 0x0000704d},351 {0x34, 0x0000604a}, {0x34, 0x00005047},352 {0x34, 0x0000400a}, {0x34, 0x00003007},353 {0x34, 0x00002004}, {0x34, 0x00001001},354 {0x34, 0x00000000},355#else356 /* Regular */357 {0x34, 0x0000add7}, {0x34, 0x00009dd4},358 {0x34, 0x00008dd1}, {0x34, 0x00007dce},359 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},360 {0x34, 0x00004dc5}, {0x34, 0x000034cc},361 {0x34, 0x0000244f}, {0x34, 0x0000144c},362 {0x34, 0x00000014},363#endif364 {0x00, 0x00030159},365 {0x84, 0x00068180},366 {0x86, 0x0000014e},367 {0x87, 0x00048e00},368 {0x8e, 0x00065540},369 {0x8f, 0x00088000},370 {0xef, 0x000020a0},371#ifdef EXT_PA_8192EU372 /* External PA or external LNA */373 {0x3b, 0x000f07b0},374#else375 {0x3b, 0x000f02b0},376#endif377 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},378 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},379 {0x3b, 0x000a0080}, {0x3b, 0x00090080},380 {0x3b, 0x0008f780},381#ifdef EXT_PA_8192EU382 /* External PA or external LNA */383 {0x3b, 0x000787b0},384#else385 {0x3b, 0x00078730},386#endif387 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},388 {0x3b, 0x00040620}, {0x3b, 0x00037090},389 {0x3b, 0x00020080}, {0x3b, 0x0001f060},390 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},391 {0xfe, 0x00000000}, {0x18, 0x0000fc07},392 {0xfe, 0x00000000}, {0xfe, 0x00000000},393 {0xfe, 0x00000000}, {0xfe, 0x00000000},394 {0x1e, 0x00000001}, {0x1f, 0x00080000},395 {0x00, 0x00033e70},396 {0xff, 0xffffffff}397};398 399static const struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {400 {0x7f, 0x00000082}, {0x81, 0x0003fc00},401 {0x00, 0x00030000}, {0x08, 0x00008400},402 {0x18, 0x00000407}, {0x19, 0x00000012},403 {0x1b, 0x00000064}, {0x1e, 0x00080009},404 {0x1f, 0x00000880}, {0x2f, 0x0001a060},405 {0x3f, 0x00000000}, {0x42, 0x000060c0},406 {0x57, 0x000d0000}, {0x58, 0x000be180},407 {0x67, 0x00001552}, {0x7f, 0x00000082},408 {0x81, 0x0003f000}, {0x83, 0x00000000},409 {0xdf, 0x00000180}, {0xef, 0x000001a0},410 {0x51, 0x00069545}, {0x52, 0x0007e42e},411 {0x53, 0x00000071}, {0x56, 0x00051ff3},412 {0x35, 0x000000a8}, {0x35, 0x000001e0},413 {0x35, 0x000002a8}, {0x36, 0x00001ca8},414 {0x36, 0x00009c24}, {0x36, 0x00011c24},415 {0x36, 0x00019c24}, {0x18, 0x00000c07},416 {0x5a, 0x00048000}, {0x19, 0x000739d0},417#ifdef EXT_PA_8192EU418 /* External PA or external LNA */419 {0x34, 0x0000a093}, {0x34, 0x0000908f},420 {0x34, 0x0000808c}, {0x34, 0x0000704d},421 {0x34, 0x0000604a}, {0x34, 0x00005047},422 {0x34, 0x0000400a}, {0x34, 0x00003007},423 {0x34, 0x00002004}, {0x34, 0x00001001},424 {0x34, 0x00000000},425#else426 {0x34, 0x0000add7}, {0x34, 0x00009dd4},427 {0x34, 0x00008dd1}, {0x34, 0x00007dce},428 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},429 {0x34, 0x00004dc5}, {0x34, 0x000034cc},430 {0x34, 0x0000244f}, {0x34, 0x0000144c},431 {0x34, 0x00000014},432#endif433 {0x00, 0x00030159}, {0x84, 0x00068180},434 {0x86, 0x000000ce}, {0x87, 0x00048a00},435 {0x8e, 0x00065540}, {0x8f, 0x00088000},436 {0xef, 0x000020a0},437#ifdef EXT_PA_8192EU438 /* External PA or external LNA */439 {0x3b, 0x000f07b0},440#else441 {0x3b, 0x000f02b0},442#endif443 444 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},445 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},446 {0x3b, 0x000a0080}, {0x3b, 0x00090080},447 {0x3b, 0x0008f780},448#ifdef EXT_PA_8192EU449 /* External PA or external LNA */450 {0x3b, 0x000787b0},451#else452 {0x3b, 0x00078730},453#endif454 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},455 {0x3b, 0x00040620}, {0x3b, 0x00037090},456 {0x3b, 0x00020080}, {0x3b, 0x0001f060},457 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},458 {0x00, 0x00010159}, {0xfe, 0x00000000},459 {0xfe, 0x00000000}, {0xfe, 0x00000000},460 {0xfe, 0x00000000}, {0x1e, 0x00000001},461 {0x1f, 0x00080000}, {0x00, 0x00033e70},462 {0xff, 0xffffffff}463};464 465static int rtl8192eu_identify_chip(struct rtl8xxxu_priv *priv)466{467 struct device *dev = &priv->udev->dev;468 u32 val32, bonding, sys_cfg, vendor;469 int ret = 0;470 471 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);472 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);473 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {474 dev_info(dev, "Unsupported test chip\n");475 ret = -ENOTSUPP;476 goto out;477 }478 479 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);480 bonding &= HPON_FSM_BONDING_MASK;481 if (bonding == HPON_FSM_BONDING_1T2R) {482 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name));483 priv->tx_paths = 1;484 priv->rtl_chip = RTL8191E;485 } else {486 strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name));487 priv->tx_paths = 2;488 priv->rtl_chip = RTL8192E;489 }490 priv->rf_paths = 2;491 priv->rx_paths = 2;492 priv->has_wifi = 1;493 494 vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK;495 rtl8xxxu_identify_vendor_2bits(priv, vendor);496 497 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);498 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);499 500 rtl8xxxu_config_endpoints_sie(priv);501 502 /*503 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX504 */505 if (!priv->ep_tx_count)506 ret = rtl8xxxu_config_endpoints_no_sie(priv);507 508out:509 return ret;510}511 512static void513rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)514{515 u32 val32, ofdm, mcs;516 u8 cck, ofdmbase, mcsbase;517 int group, tx_idx;518 519 tx_idx = 0;520 group = rtl8xxxu_gen2_channel_to_group(channel);521 522 cck = priv->cck_tx_power_index_A[group];523 524 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);525 val32 &= 0xffff00ff;526 val32 |= (cck << 8);527 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);528 529 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);530 val32 &= 0xff;531 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));532 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);533 534 ofdmbase = priv->ht40_1s_tx_power_index_A[group];535 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;536 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;537 538 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);539 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);540 541 mcsbase = priv->ht40_1s_tx_power_index_A[group];542 if (ht40)543 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;544 else545 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;546 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;547 548 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);549 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);550 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);551 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);552 553 if (priv->tx_paths > 1) {554 cck = priv->cck_tx_power_index_B[group];555 556 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);557 val32 &= 0xff;558 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));559 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);560 561 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);562 val32 &= 0xffffff00;563 val32 |= cck;564 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);565 566 ofdmbase = priv->ht40_1s_tx_power_index_B[group];567 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;568 ofdm = ofdmbase | ofdmbase << 8 |569 ofdmbase << 16 | ofdmbase << 24;570 571 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);572 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);573 574 mcsbase = priv->ht40_1s_tx_power_index_B[group];575 if (ht40)576 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;577 else578 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;579 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;580 581 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);582 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);583 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);584 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);585 }586}587 588static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)589{590 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;591 int i;592 593 if (efuse->rtl_id != cpu_to_le16(0x8129))594 return -EINVAL;595 596 ether_addr_copy(priv->mac_addr, efuse->mac_addr);597 598 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,599 sizeof(efuse->tx_power_index_A.cck_base));600 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,601 sizeof(efuse->tx_power_index_B.cck_base));602 603 memcpy(priv->ht40_1s_tx_power_index_A,604 efuse->tx_power_index_A.ht40_base,605 sizeof(efuse->tx_power_index_A.ht40_base));606 memcpy(priv->ht40_1s_tx_power_index_B,607 efuse->tx_power_index_B.ht40_base,608 sizeof(efuse->tx_power_index_B.ht40_base));609 610 priv->ht20_tx_power_diff[0].a =611 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;612 priv->ht20_tx_power_diff[0].b =613 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;614 615 priv->ht40_tx_power_diff[0].a = 0;616 priv->ht40_tx_power_diff[0].b = 0;617 618 for (i = 1; i < RTL8723B_TX_COUNT; i++) {619 priv->ofdm_tx_power_diff[i].a =620 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;621 priv->ofdm_tx_power_diff[i].b =622 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;623 624 priv->ht20_tx_power_diff[i].a =625 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;626 priv->ht20_tx_power_diff[i].b =627 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;628 629 priv->ht40_tx_power_diff[i].a =630 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;631 priv->ht40_tx_power_diff[i].b =632 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;633 }634 635 priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;636 637 return 0;638}639 640static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)641{642 const char *fw_name;643 int ret;644 645 fw_name = "rtlwifi/rtl8192eu_nic.bin";646 647 ret = rtl8xxxu_load_firmware(priv, fw_name);648 649 return ret;650}651 652static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)653{654 u8 val8;655 u16 val16;656 657 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);658 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;659 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);660 661 /* 6. 0x1f[7:0] = 0x07 */662 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;663 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);664 665 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);666 val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |667 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);668 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);669 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;670 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);671 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);672 673 if (priv->hi_pa)674 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);675 else676 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);677}678 679static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)680{681 int ret;682 683 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);684 if (ret)685 goto exit;686 687 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);688 689exit:690 return ret;691}692 693static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)694{695 u32 reg_eac, reg_e94, reg_e9c;696 int result = 0;697 698 /*699 * TX IQK700 * PA/PAD controlled by 0x0701 */702 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);703 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00180);704 705 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);706 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);707 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);708 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77);709 710 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);711 712 /* Path A IQK setting */713 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);714 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);715 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);716 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);717 718 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);719 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);720 721 /* LO calibration setting */722 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);723 724 /* One shot, path A LOK & IQK */725 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);726 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);727 728 mdelay(10);729 730 /* Check failed */731 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);732 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);733 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);734 735 if (!(reg_eac & BIT(28)) &&736 ((reg_e94 & 0x03ff0000) != 0x01420000) &&737 ((reg_e9c & 0x03ff0000) != 0x00420000))738 result |= 0x01;739 740 return result;741}742 743static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)744{745 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;746 int result = 0;747 748 /* Leave IQK mode */749 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);750 751 /* Enable path A PA in TX IQK mode */752 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);753 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);754 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);755 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);756 757 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);758 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);759 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);760 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173);761 762 /* PA/PAD control by 0x56, and set = 0x0 */763 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980);764 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x511e0);765 766 /* Enter IQK mode */767 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);768 769 /* TX IQK setting */770 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);771 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);772 773 /* path-A IQK setting */774 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);775 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);776 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);777 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);778 779 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f);780 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f);781 782 /* LO calibration setting */783 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);784 785 /* One shot, path A LOK & IQK */786 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);787 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);788 789 mdelay(10);790 791 /* Check failed */792 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);793 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);794 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);795 796 if (!(reg_eac & BIT(28)) &&797 ((reg_e94 & 0x03ff0000) != 0x01420000) &&798 ((reg_e9c & 0x03ff0000) != 0x00420000)) {799 result |= 0x01;800 } else {801 /* PA/PAD controlled by 0x0 */802 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);803 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);804 goto out;805 }806 807 val32 = 0x80007c00 |808 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);809 rtl8xxxu_write32(priv, REG_TX_IQK, val32);810 811 /* Modify RX IQK mode table */812 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);813 814 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);815 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);816 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);817 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);818 819 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);820 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);821 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);822 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2);823 824 /* PA/PAD control by 0x56, and set = 0x0 */825 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980);826 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x510e0);827 828 /* Enter IQK mode */829 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);830 831 /* IQK setting */832 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);833 834 /* Path A IQK setting */835 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);836 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);837 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);838 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);839 840 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff);841 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff);842 843 /* LO calibration setting */844 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);845 846 /* One shot, path A LOK & IQK */847 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);848 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);849 850 mdelay(10);851 852 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);853 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);854 855 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);856 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);857 858 if (!(reg_eac & BIT(27)) &&859 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&860 ((reg_eac & 0x03ff0000) != 0x00360000))861 result |= 0x02;862 else863 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",864 __func__);865 866out:867 return result;868}869 870static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)871{872 u32 reg_eac, reg_eb4, reg_ebc;873 int result = 0;874 875 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);876 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00180);877 878 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);879 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000);880 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);881 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77);882 883 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);884 885 /* Path B IQK setting */886 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);887 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);888 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);889 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);890 891 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303);892 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);893 894 /* LO calibration setting */895 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);896 897 /* One shot, path A LOK & IQK */898 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);899 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);900 901 mdelay(1);902 903 /* Check failed */904 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);905 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);906 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);907 908 if (!(reg_eac & BIT(31)) &&909 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&910 ((reg_ebc & 0x03ff0000) != 0x00420000))911 result |= 0x01;912 else913 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",914 __func__);915 916 return result;917}918 919static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)920{921 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;922 int result = 0;923 924 /* Leave IQK mode */925 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);926 927 /* Enable path A PA in TX IQK mode */928 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);929 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);930 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);931 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173);932 933 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);934 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);935 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);936 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);937 938 /* PA/PAD control by 0x56, and set = 0x0 */939 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980);940 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x511e0);941 942 /* Enter IQK mode */943 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);944 945 /* TX IQK setting */946 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);947 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);948 949 /* path-A IQK setting */950 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);951 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);952 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);953 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);954 955 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f);956 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f);957 958 /* LO calibration setting */959 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);960 961 /* One shot, path A LOK & IQK */962 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);963 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);964 965 mdelay(10);966 967 /* Check failed */968 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);969 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);970 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);971 972 if (!(reg_eac & BIT(31)) &&973 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&974 ((reg_ebc & 0x03ff0000) != 0x00420000)) {975 result |= 0x01;976 } else {977 /*978 * PA/PAD controlled by 0x0979 * Vendor driver restores RF_A here which I believe is a bug980 */981 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);982 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180);983 goto out;984 }985 986 val32 = 0x80007c00 |987 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);988 rtl8xxxu_write32(priv, REG_TX_IQK, val32);989 990 /* Modify RX IQK mode table */991 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);992 993 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);994 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);995 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);996 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2);997 998 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);999 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);1000 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);1001 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);1002 1003 /* PA/PAD control by 0x56, and set = 0x0 */1004 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980);1005 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x510e0);1006 1007 /* Enter IQK mode */1008 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);1009 1010 /* IQK setting */1011 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);1012 1013 /* Path A IQK setting */1014 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);1015 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);1016 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);1017 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);1018 1019 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff);1020 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff);1021 1022 /* LO calibration setting */1023 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);1024 1025 /* One shot, path A LOK & IQK */1026 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);1027 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);1028 1029 mdelay(10);1030 1031 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);1032 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);1033 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);1034 1035 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);1036 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180);1037 1038 if (!(reg_eac & BIT(30)) &&1039 ((reg_ec4 & 0x03ff0000) != 0x01320000) &&1040 ((reg_ecc & 0x03ff0000) != 0x00360000))1041 result |= 0x02;1042 else1043 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",1044 __func__);1045 1046out:1047 return result;1048}1049 1050static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,1051 int result[][8], int t)1052{1053 struct device *dev = &priv->udev->dev;1054 u32 i, val32;1055 int path_a_ok, path_b_ok;1056 int retry = 2;1057 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {1058 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,1059 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,1060 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,1061 REG_TX_OFDM_BBON, REG_TX_TO_RX,1062 REG_TX_TO_TX, REG_RX_CCK,1063 REG_RX_OFDM, REG_RX_WAIT_RIFS,1064 REG_RX_TO_RX, REG_STANDBY,1065 REG_SLEEP, REG_PMPD_ANAEN1066 };1067 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {1068 REG_TXPAUSE, REG_BEACON_CTRL,1069 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG1070 };1071 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {1072 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,1073 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,1074 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,1075 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING1076 };1077 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;1078 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;1079 1080 /*1081 * Note: IQ calibration must be performed after loading1082 * PHY_REG.txt , and radio_a, radio_b.txt1083 */1084 1085 if (t == 0) {1086 /* Save ADDA parameters, turn Path A ADDA on */1087 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,1088 RTL8XXXU_ADDA_REGS);1089 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);1090 rtl8xxxu_save_regs(priv, iqk_bb_regs,1091 priv->bb_backup, RTL8XXXU_BB_REGS);1092 }1093 1094 rtl8xxxu_path_adda_on(priv, adda_regs, true);1095 1096 /* MAC settings */1097 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);1098 1099 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);1100 val32 |= 0x0f000000;1101 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);1102 1103 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);1104 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);1105 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);1106 1107 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);1108 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));1109 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);1110 1111 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);1112 val32 |= BIT(10);1113 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);1114 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);1115 val32 |= BIT(10);1116 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);1117 1118 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);1119 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);1120 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);1121 1122 for (i = 0; i < retry; i++) {1123 path_a_ok = rtl8192eu_iqk_path_a(priv);1124 if (path_a_ok == 0x01) {1125 val32 = rtl8xxxu_read32(priv,1126 REG_TX_POWER_BEFORE_IQK_A);1127 result[t][0] = (val32 >> 16) & 0x3ff;1128 val32 = rtl8xxxu_read32(priv,1129 REG_TX_POWER_AFTER_IQK_A);1130 result[t][1] = (val32 >> 16) & 0x3ff;1131 1132 break;1133 }1134 }1135 1136 if (!path_a_ok)1137 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);1138 1139 for (i = 0; i < retry; i++) {1140 path_a_ok = rtl8192eu_rx_iqk_path_a(priv);1141 if (path_a_ok == 0x03) {1142 val32 = rtl8xxxu_read32(priv,1143 REG_RX_POWER_BEFORE_IQK_A_2);1144 result[t][2] = (val32 >> 16) & 0x3ff;1145 val32 = rtl8xxxu_read32(priv,1146 REG_RX_POWER_AFTER_IQK_A_2);1147 result[t][3] = (val32 >> 16) & 0x3ff;1148 1149 break;1150 }1151 }1152 1153 if (!path_a_ok)1154 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);1155 1156 if (priv->rf_paths > 1) {1157 /* Path A into standby */1158 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);1159 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);1160 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);1161 1162 /* Turn Path B ADDA on */1163 rtl8xxxu_path_adda_on(priv, adda_regs, false);1164 1165 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);1166 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);1167 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);1168 1169 for (i = 0; i < retry; i++) {1170 path_b_ok = rtl8192eu_iqk_path_b(priv);1171 if (path_b_ok == 0x01) {1172 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);1173 result[t][4] = (val32 >> 16) & 0x3ff;1174 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);1175 result[t][5] = (val32 >> 16) & 0x3ff;1176 break;1177 }1178 }1179 1180 if (!path_b_ok)1181 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);1182 1183 for (i = 0; i < retry; i++) {1184 path_b_ok = rtl8192eu_rx_iqk_path_b(priv);1185 if (path_b_ok == 0x03) {1186 val32 = rtl8xxxu_read32(priv,1187 REG_RX_POWER_BEFORE_IQK_B_2);1188 result[t][6] = (val32 >> 16) & 0x3ff;1189 val32 = rtl8xxxu_read32(priv,1190 REG_RX_POWER_AFTER_IQK_B_2);1191 result[t][7] = (val32 >> 16) & 0x3ff;1192 break;1193 }1194 }1195 1196 if (!path_b_ok)1197 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);1198 }1199 1200 /* Back to BB mode, load original value */1201 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);1202 1203 if (t) {1204 /* Reload ADDA power saving parameters */1205 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,1206 RTL8XXXU_ADDA_REGS);1207 1208 /* Reload MAC parameters */1209 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);1210 1211 /* Reload BB parameters */1212 rtl8xxxu_restore_regs(priv, iqk_bb_regs,1213 priv->bb_backup, RTL8XXXU_BB_REGS);1214 1215 /* Restore RX initial gain */1216 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);1217 val32 &= 0xffffff00;1218 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);1219 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);1220 1221 if (priv->rf_paths > 1) {1222 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);1223 val32 &= 0xffffff00;1224 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,1225 val32 | 0x50);1226 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,1227 val32 | xb_agc);1228 }1229 1230 /* Load 0xe30 IQC default value */1231 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);1232 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);1233 }1234}1235 1236static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)1237{1238 struct device *dev = &priv->udev->dev;1239 int result[4][8]; /* last is final result */1240 int i, candidate;1241 bool path_a_ok, path_b_ok;1242 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;1243 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;1244 bool simu;1245 1246 memset(result, 0, sizeof(result));1247 candidate = -1;1248 1249 path_a_ok = false;1250 path_b_ok = false;1251 1252 for (i = 0; i < 3; i++) {1253 rtl8192eu_phy_iqcalibrate(priv, result, i);1254 1255 if (i == 1) {1256 simu = rtl8xxxu_gen2_simularity_compare(priv,1257 result, 0, 1);1258 if (simu) {1259 candidate = 0;1260 break;1261 }1262 }1263 1264 if (i == 2) {1265 simu = rtl8xxxu_gen2_simularity_compare(priv,1266 result, 0, 2);1267 if (simu) {1268 candidate = 0;1269 break;1270 }1271 1272 simu = rtl8xxxu_gen2_simularity_compare(priv,1273 result, 1, 2);1274 if (simu)1275 candidate = 1;1276 else1277 candidate = 3;1278 }1279 }1280 1281 for (i = 0; i < 4; i++) {1282 reg_e94 = result[i][0];1283 reg_e9c = result[i][1];1284 reg_ea4 = result[i][2];1285 reg_eb4 = result[i][4];1286 reg_ebc = result[i][5];1287 reg_ec4 = result[i][6];1288 }1289 1290 if (candidate >= 0) {1291 reg_e94 = result[candidate][0];1292 priv->rege94 = reg_e94;1293 reg_e9c = result[candidate][1];1294 priv->rege9c = reg_e9c;1295 reg_ea4 = result[candidate][2];1296 reg_eac = result[candidate][3];1297 reg_eb4 = result[candidate][4];1298 priv->regeb4 = reg_eb4;1299 reg_ebc = result[candidate][5];1300 priv->regebc = reg_ebc;1301 reg_ec4 = result[candidate][6];1302 reg_ecc = result[candidate][7];1303 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);1304 dev_dbg(dev,1305 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",1306 __func__, reg_e94, reg_e9c,1307 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);1308 path_a_ok = true;1309 path_b_ok = true;1310 } else {1311 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;1312 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;1313 }1314 1315 if (reg_e94 && candidate >= 0)1316 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,1317 candidate, (reg_ea4 == 0));1318 1319 if (priv->rf_paths > 1)1320 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,1321 candidate, (reg_ec4 == 0));1322 1323 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,1324 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);1325}1326 1327/*1328 * This is needed for 8723bu as well, presumable1329 */1330static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)1331{1332 u8 val8;1333 u32 val32;1334 1335 /*1336 * 40Mhz crystal source, MAC 0x28[2]=01337 */1338 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);1339 val8 &= 0xfb;1340 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);1341 1342 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);1343 val32 &= 0xfffffc7f;1344 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);1345 1346 /*1347 * 92e AFE parameter1348 * AFE PLL KVCO selection, MAC 0x28[6]=11349 */1350 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);1351 val8 &= 0xbf;1352 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);1353 1354 /*1355 * AFE PLL KVCO selection, MAC 0x78[21]=01356 */1357 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);1358 val32 &= 0xffdfffff;1359 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);1360}1361 1362static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)1363{1364 u8 val8;1365 1366 /* Clear suspend enable and power down enable*/1367 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);1368 val8 &= ~(BIT(3) | BIT(4));1369 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);1370}1371 1372static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)1373{1374 u8 val8;1375 u32 val32;1376 int count, ret = 0;1377 1378 /* disable HWPDN 0x04[15]=0*/1379 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);1380 val8 &= ~BIT(7);1381 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);1382 1383 /* disable SW LPS 0x04[10]= 0 */1384 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);1385 val8 &= ~BIT(2);1386 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);1387 1388 /* disable WL suspend*/1389 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);1390 val8 &= ~(BIT(3) | BIT(4));1391 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);1392 1393 /* wait till 0x04[17] = 1 power ready*/1394 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {1395 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);1396 if (val32 & BIT(17))1397 break;1398 1399 udelay(10);1400 }1401 1402 if (!count) {1403 ret = -EBUSY;1404 goto exit;1405 }1406 1407 /* We should be able to optimize the following three entries into one */1408 1409 /* release WLON reset 0x04[16]= 1*/1410 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);1411 val8 |= BIT(0);1412 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);1413 1414 /* set, then poll until 0 */1415 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);1416 val32 |= APS_FSMCO_MAC_ENABLE;1417 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);1418 1419 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {1420 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);1421 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {1422 ret = 0;1423 break;1424 }1425 udelay(10);1426 }1427 1428 if (!count) {1429 ret = -EBUSY;1430 goto exit;1431 }1432 1433exit:1434 return ret;1435}1436 1437static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv)1438{1439 struct device *dev = &priv->udev->dev;1440 u8 val8;1441 u16 val16;1442 u32 val32;1443 int retry, retval;1444 1445 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);1446 1447 retry = 100;1448 retval = -EBUSY;1449 /*1450 * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.1451 */1452 do {1453 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);1454 if (!val32) {1455 retval = 0;1456 break;1457 }1458 } while (retry--);1459 1460 if (!retry) {1461 dev_warn(dev, "Failed to flush TX queue\n");1462 retval = -EBUSY;1463 goto out;1464 }1465 1466 /* Disable CCK and OFDM, clock gated */1467 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);1468 val8 &= ~SYS_FUNC_BBRSTB;1469 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);1470 1471 udelay(2);1472 1473 /* Reset whole BB */1474 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);1475 val8 &= ~SYS_FUNC_BB_GLB_RSTN;1476 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);1477 1478 /* Reset MAC TRX */1479 val16 = rtl8xxxu_read16(priv, REG_CR);1480 val16 &= 0xff00;1481 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE);1482 rtl8xxxu_write16(priv, REG_CR, val16);1483 1484 val16 = rtl8xxxu_read16(priv, REG_CR);1485 val16 &= ~CR_SECURITY_ENABLE;1486 rtl8xxxu_write16(priv, REG_CR, val16);1487 1488 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);1489 val8 |= DUAL_TSF_TX_OK;1490 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);1491 1492out:1493 return retval;1494}1495 1496static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv)1497{1498 u8 val8;1499 int count, ret = 0;1500 1501 /* Turn off RF */1502 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);1503 val8 &= ~RF_ENABLE;1504 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);1505 1506 /* Switch DPDT_SEL_P output from register 0x65[2] */1507 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);1508 val8 &= ~LEDCFG2_DPDT_SELECT;1509 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);1510 1511 /* 0x0005[1] = 1 turn off MAC by HW state machine*/1512 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);1513 val8 |= BIT(1);1514 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);1515 1516 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {1517 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);1518 if ((val8 & BIT(1)) == 0)1519 break;1520 udelay(10);1521 }1522 1523 if (!count) {1524 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",1525 __func__);1526 ret = -EBUSY;1527 goto exit;1528 }1529 1530exit:1531 return ret;1532}1533 1534static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv)1535{1536 u8 val8;1537 1538 /* 0x04[12:11] = 01 enable WL suspend */1539 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);1540 val8 &= ~(BIT(3) | BIT(4));1541 val8 |= BIT(3);1542 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);1543 1544 return 0;1545}1546 1547static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)1548{1549 u16 val16;1550 u32 val32;1551 int ret;1552 1553 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);1554 if (val32 & SYS_CFG_SPS_LDO_SEL) {1555 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);1556 } else {1557 /*1558 * Raise 1.2V voltage1559 */1560 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);1561 val32 &= 0xff0fffff;1562 val32 |= 0x00500000;1563 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);1564 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);1565 }1566 1567 /*1568 * Adjust AFE before enabling PLL1569 */1570 rtl8192e_crystal_afe_adjust(priv);1571 rtl8192e_disabled_to_emu(priv);1572 1573 ret = rtl8192e_emu_to_active(priv);1574 if (ret)1575 goto exit;1576 1577 rtl8xxxu_write16(priv, REG_CR, 0x0000);1578 1579 /*1580 * Enable MAC DMA/WMAC/SCHEDULE/SEC block1581 * Set CR bit10 to enable 32k calibration.1582 */1583 val16 = rtl8xxxu_read16(priv, REG_CR);1584 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |1585 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |1586 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |1587 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |1588 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);1589 rtl8xxxu_write16(priv, REG_CR, val16);1590 1591exit:1592 return ret;1593}1594 1595static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv)1596{1597 u8 val8;1598 u16 val16;1599 1600 rtl8xxxu_flush_fifo(priv);1601 1602 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);1603 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;1604 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);1605 1606 /* Turn off RF */1607 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);1608 1609 rtl8192eu_active_to_lps(priv);1610 1611 /* Reset Firmware if running in RAM */1612 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)1613 rtl8xxxu_firmware_self_reset(priv);1614 1615 /* Reset MCU */1616 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);1617 val16 &= ~SYS_FUNC_CPU_ENABLE;1618 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);1619 1620 /* Reset MCU ready status */1621 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);1622 1623 rtl8xxxu_reset_8051(priv);1624 1625 rtl8192eu_active_to_emu(priv);1626 rtl8192eu_emu_to_disabled(priv);1627}1628 1629static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)1630{1631 u32 val32;1632 u8 val8;1633 1634 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);1635 val32 |= (BIT(22) | BIT(23));1636 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);1637 1638 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);1639 val8 |= BIT(5);1640 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);1641 1642 /*1643 * WLAN action by PTA1644 */1645 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);1646 1647 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);1648 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;1649 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);1650 1651 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);1652 val32 |= (BIT(0) | BIT(1));1653 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);1654 1655 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);1656 1657 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);1658 val32 &= ~BIT(24);1659 val32 |= BIT(23);1660 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);1661 1662 /*1663 * Fix external switch Main->S1, Aux->S01664 */1665 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);1666 val8 &= ~BIT(0);1667 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);1668 1669 /*1670 * Fix transmission failure of rtl8192e.1671 */1672 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);1673}1674 1675static s8 rtl8192e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)1676{1677 static const s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44};1678 static const s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};1679 1680 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;1681 s8 rx_pwr_all = 0x00;1682 u8 vga_idx, lna_idx;1683 s8 lna_gain = 0;1684 1685 lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK);1686 vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK);1687 1688 if (priv->cck_agc_report_type == 0)1689 lna_gain = lna_gain_table_0[lna_idx];1690 else1691 lna_gain = lna_gain_table_1[lna_idx];1692 1693 rx_pwr_all = lna_gain - (2 * vga_idx);1694 1695 return rx_pwr_all;1696}1697 1698static int rtl8192eu_led_brightness_set(struct led_classdev *led_cdev,1699 enum led_brightness brightness)1700{1701 struct rtl8xxxu_priv *priv = container_of(led_cdev,1702 struct rtl8xxxu_priv,1703 led_cdev);1704 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG1);1705 1706 if (brightness == LED_OFF) {1707 ledcfg &= ~LEDCFG1_HW_LED_CONTROL;1708 ledcfg |= LEDCFG1_LED_DISABLE;1709 } else if (brightness == LED_ON) {1710 ledcfg &= ~(LEDCFG1_HW_LED_CONTROL | LEDCFG1_LED_DISABLE);1711 } else if (brightness == RTL8XXXU_HW_LED_CONTROL) {1712 ledcfg &= ~LEDCFG1_LED_DISABLE;1713 ledcfg |= LEDCFG1_HW_LED_CONTROL;1714 }1715 1716 rtl8xxxu_write8(priv, REG_LEDCFG1, ledcfg);1717 1718 return 0;1719}1720 1721struct rtl8xxxu_fileops rtl8192eu_fops = {1722 .identify_chip = rtl8192eu_identify_chip,1723 .parse_efuse = rtl8192eu_parse_efuse,1724 .load_firmware = rtl8192eu_load_firmware,1725 .power_on = rtl8192eu_power_on,1726 .power_off = rtl8192eu_power_off,1727 .read_efuse = rtl8xxxu_read_efuse,1728 .reset_8051 = rtl8xxxu_reset_8051,1729 .llt_init = rtl8xxxu_auto_llt_table,1730 .init_phy_bb = rtl8192eu_init_phy_bb,1731 .init_phy_rf = rtl8192eu_init_phy_rf,1732 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,1733 .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,1734 .config_channel = rtl8xxxu_gen2_config_channel,1735 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,1736 .parse_phystats = rtl8723au_rx_parse_phystats,1737 .enable_rf = rtl8192e_enable_rf,1738 .disable_rf = rtl8xxxu_gen2_disable_rf,1739 .usb_quirks = rtl8xxxu_gen2_usb_quirks,1740 .set_tx_power = rtl8192e_set_tx_power,1741 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,1742 .report_connect = rtl8xxxu_gen2_report_connect,1743 .report_rssi = rtl8xxxu_gen2_report_rssi,1744 .fill_txdesc = rtl8xxxu_fill_txdesc_v2,1745 .set_crystal_cap = rtl8723a_set_crystal_cap,1746 .cck_rssi = rtl8192e_cck_rssi,1747 .led_classdev_brightness_set = rtl8192eu_led_brightness_set,1748 .writeN_block_size = 128,1749 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),1750 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),1751 .has_s0s1 = 0,1752 .gen2_thermal_meter = 1,1753 .needs_full_init = 1,1754 .supports_ap = 1,1755 .max_macid_num = 128,1756 .max_sec_cam_num = 64,1757 .adda_1t_init = 0x0fc01616,1758 .adda_1t_path_on = 0x0fc01616,1759 .adda_2t_path_on_a = 0x0fc01616,1760 .adda_2t_path_on_b = 0x0fc01616,1761 .trxff_boundary = 0x3cff,1762 .mactable = rtl8192e_mac_init_table,1763 .total_page_num = TX_TOTAL_PAGE_NUM_8192E,1764 .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,1765 .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,1766 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,1767};1768