1876 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * RTL8XXXU mac80211 USB driver - 8710bu aka 8188gu specific subdriver4 *5 * Copyright (c) 2023 Bitterblue Smith <rtl8821cerfe2@gmail.com>6 *7 * Portions copied from existing rtl8xxxu code:8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>9 *10 * Portions, notably calibration code:11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.12 */13 14#include "regs.h"15#include "rtl8xxxu.h"16 17static const struct rtl8xxxu_reg8val rtl8710b_mac_init_table[] = {18 {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},19 {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},20 {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},21 {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},22 {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},23 {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},24 {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},25 {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},26 {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},27 {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},28 {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, {0x501, 0xA2},29 {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xA3},30 {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, {0x509, 0xA4},31 {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, {0x50D, 0xA4},32 {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, {0x514, 0x0A},33 {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, {0x551, 0x10},34 {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, {0x605, 0x30},35 {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, {0x621, 0xFF},36 {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, {0x625, 0xFF},37 {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, {0x63C, 0x0A},38 {0x63D, 0x0A}, {0x63E, 0x0C}, {0x63F, 0x0C}, {0x640, 0x40},39 {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, {0x66A, 0xB0},40 {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},41 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65},42 {0x70B, 0x87},43 {0xffff, 0xff},44};45 46/* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */47static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_u_phy_init_table[] = {48 {0x800, 0x80045700}, {0x804, 0x00000001},49 {0x808, 0x00FC8000}, {0x80C, 0x0000000A},50 {0x810, 0x10001331}, {0x814, 0x020C3D10},51 {0x818, 0x00200385}, {0x81C, 0x00000000},52 {0x820, 0x01000100}, {0x824, 0x00390204},53 {0x828, 0x00000000}, {0x82C, 0x00000000},54 {0x830, 0x00000000}, {0x834, 0x00000000},55 {0x838, 0x00000000}, {0x83C, 0x00000000},56 {0x840, 0x00010000}, {0x844, 0x00000000},57 {0x848, 0x00000000}, {0x84C, 0x00000000},58 {0x850, 0x00030000}, {0x854, 0x00000000},59 {0x858, 0x7E1A569A}, {0x85C, 0x569A569A},60 {0x860, 0x00000130}, {0x864, 0x20000000},61 {0x868, 0x00000000}, {0x86C, 0x27272700},62 {0x870, 0x00050000}, {0x874, 0x25005000},63 {0x878, 0x00000808}, {0x87C, 0x004F0201},64 {0x880, 0xB0000B1E}, {0x884, 0x00000007},65 {0x888, 0x00000000}, {0x88C, 0xCCC400C0},66 {0x890, 0x00000800}, {0x894, 0xFFFFFFFE},67 {0x898, 0x40302010}, {0x89C, 0x00706050},68 {0x900, 0x00000000}, {0x904, 0x00000023},69 {0x908, 0x00000000}, {0x90C, 0x81121111},70 {0x910, 0x00000402}, {0x914, 0x00000201},71 {0x920, 0x18C6318C}, {0x924, 0x0000018C},72 {0x948, 0x99000000}, {0x94C, 0x00000010},73 {0x950, 0x00003000}, {0x954, 0x5A880000},74 {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79},75 {0x96C, 0x00000003}, {0x970, 0x00000000},76 {0x974, 0x00000000}, {0x978, 0x00000000},77 {0x97C, 0x13000000}, {0x980, 0x00000000},78 {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C},79 {0xA08, 0x84838300}, {0xA0C, 0x2E20100F},80 {0xA10, 0x9500BB78}, {0xA14, 0x1114D028},81 {0xA18, 0x00881117}, {0xA1C, 0x89140F00},82 {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C},83 {0xA28, 0x00008810}, {0xA2C, 0x00D30000},84 {0xA70, 0x101FBF00}, {0xA74, 0x00000007},85 {0xA78, 0x00000900}, {0xA7C, 0x225B0606},86 {0xA80, 0x218075B1}, {0xA84, 0x00200000},87 {0xA88, 0x040C0000}, {0xA8C, 0x12345678},88 {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89},89 {0xA98, 0x00000000}, {0xA9C, 0x80020000},90 {0xAA0, 0x00000000}, {0xAA4, 0x0000000C},91 {0xAA8, 0xCA110058}, {0xAAC, 0x01235667},92 {0xAB0, 0x00000000}, {0xAB4, 0x20201402},93 {0xB2C, 0x00000000}, {0xC00, 0x48071D40},94 {0xC04, 0x03A05611}, {0xC08, 0x000000E4},95 {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000},96 {0xC14, 0x40000100}, {0xC18, 0x08800000},97 {0xC1C, 0x40000100}, {0xC20, 0x00000000},98 {0xC24, 0x00000000}, {0xC28, 0x00000000},99 {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A},100 {0xC34, 0x31000040}, {0xC38, 0x21688080},101 {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F},102 {0xC44, 0x00010036}, {0xC48, 0xEC020107},103 {0xC4C, 0x007F037F}, {0xC50, 0x69553420},104 {0xC54, 0x43BC0094}, {0xC58, 0x00013169},105 {0xC5C, 0x00250492}, {0xC60, 0x00280A00},106 {0xC64, 0x7112848B}, {0xC68, 0x47C074FF},107 {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D},108 {0xC74, 0x020600DB}, {0xC78, 0x0000001F},109 {0xC7C, 0x00B91612}, {0xC80, 0x390000E4},110 {0xC84, 0x11F60000}, {0xC88, 0x1051B75F},111 {0xC8C, 0x20200109}, {0xC90, 0x00091521},112 {0xC94, 0x00000000}, {0xC98, 0x00121820},113 {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000},114 {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606},115 {0xCAC, 0x00000060}, {0xCB0, 0x00000000},116 {0xCB4, 0x00000000}, {0xCB8, 0x00000000},117 {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F},118 {0xCC4, 0x00000109}, {0xCC8, 0x000442D6},119 {0xCCC, 0x00000000}, {0xCD0, 0x000001C8},120 {0xCD4, 0x001C8000}, {0xCD8, 0x00000100},121 {0xCDC, 0x40100000}, {0xCE0, 0x00222220},122 {0xCE4, 0x10000000}, {0xCE8, 0x37644302},123 {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740},124 {0xD04, 0x40020401}, {0xD08, 0x0000907F},125 {0xD0C, 0x20010201}, {0xD10, 0xA0633333},126 {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F},127 {0xD2C, 0xCB979975}, {0xD30, 0x00000000},128 {0xD34, 0x40608000}, {0xD38, 0x88000000},129 {0xD3C, 0xC0127353}, {0xD40, 0x00000000},130 {0xD44, 0x00000000}, {0xD48, 0x00000000},131 {0xD4C, 0x00000000}, {0xD50, 0x00006528},132 {0xD54, 0x00000000}, {0xD58, 0x00000282},133 {0xD5C, 0x30032064}, {0xD60, 0x4653DE68},134 {0xD64, 0x04518A3C}, {0xD68, 0x00002101},135 {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D},136 {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D},137 {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D},138 {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000},139 {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F},140 {0xE38, 0x02140102}, {0xE3C, 0x681604C2},141 {0xE40, 0x01007C00}, {0xE44, 0x01004800},142 {0xE48, 0xFB000000}, {0xE4C, 0x000028D1},143 {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F},144 {0xE58, 0x02140102}, {0xE5C, 0x28160D05},145 {0xE60, 0x0000C008}, {0xE68, 0x001B25A4},146 {0xE64, 0x281600A0}, {0xE6C, 0x01C00010},147 {0xE70, 0x01C00010}, {0xE74, 0x02000010},148 {0xE78, 0x02000010}, {0xE7C, 0x02000010},149 {0xE80, 0x02000010}, {0xE84, 0x01C00010},150 {0xE88, 0x02000010}, {0xE8C, 0x01C00010},151 {0xED0, 0x01C00010}, {0xED4, 0x01C00010},152 {0xED8, 0x01C00010}, {0xEDC, 0x00000010},153 {0xEE0, 0x00000010}, {0xEEC, 0x03C00010},154 {0xF14, 0x00000003}, {0xF00, 0x00100300},155 {0xF08, 0x0000800B}, {0xF0C, 0x0000F007},156 {0xF10, 0x0000A487}, {0xF1C, 0x80000064},157 {0xF38, 0x00030155}, {0xF3C, 0x0000003A},158 {0xF4C, 0x13000000}, {0xF50, 0x00000000},159 {0xF18, 0x00000000},160 {0xffff, 0xffffffff},161};162 163/* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */164static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_s_phy_init_table[] = {165 {0x800, 0x80045700}, {0x804, 0x00000001},166 {0x808, 0x00FC8000}, {0x80C, 0x0000000A},167 {0x810, 0x10001331}, {0x814, 0x020C3D10},168 {0x818, 0x00200385}, {0x81C, 0x00000000},169 {0x820, 0x01000100}, {0x824, 0x00390204},170 {0x828, 0x00000000}, {0x82C, 0x00000000},171 {0x830, 0x00000000}, {0x834, 0x00000000},172 {0x838, 0x00000000}, {0x83C, 0x00000000},173 {0x840, 0x00010000}, {0x844, 0x00000000},174 {0x848, 0x00000000}, {0x84C, 0x00000000},175 {0x850, 0x00030000}, {0x854, 0x00000000},176 {0x858, 0x7E1A569A}, {0x85C, 0x569A569A},177 {0x860, 0x00000130}, {0x864, 0x20000000},178 {0x868, 0x00000000}, {0x86C, 0x27272700},179 {0x870, 0x00050000}, {0x874, 0x25005000},180 {0x878, 0x00000808}, {0x87C, 0x004F0201},181 {0x880, 0xB0000B1E}, {0x884, 0x00000007},182 {0x888, 0x00000000}, {0x88C, 0xCCC400C0},183 {0x890, 0x00000800}, {0x894, 0xFFFFFFFE},184 {0x898, 0x40302010}, {0x89C, 0x00706050},185 {0x900, 0x00000000}, {0x904, 0x00000023},186 {0x908, 0x00000000}, {0x90C, 0x81121111},187 {0x910, 0x00000402}, {0x914, 0x00000201},188 {0x920, 0x18C6318C}, {0x924, 0x0000018C},189 {0x948, 0x99000000}, {0x94C, 0x00000010},190 {0x950, 0x00003000}, {0x954, 0x5A880000},191 {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79},192 {0x96C, 0x00000003}, {0x970, 0x00000000},193 {0x974, 0x00000000}, {0x978, 0x00000000},194 {0x97C, 0x13000000}, {0x980, 0x00000000},195 {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C},196 {0xA08, 0x84838300}, {0xA0C, 0x2A20100F},197 {0xA10, 0x9500BB78}, {0xA14, 0x1114D028},198 {0xA18, 0x00881117}, {0xA1C, 0x89140F00},199 {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C},200 {0xA28, 0x00008810}, {0xA2C, 0x00D30000},201 {0xA70, 0x101FBF00}, {0xA74, 0x00000007},202 {0xA78, 0x00000900}, {0xA7C, 0x225B0606},203 {0xA80, 0x218075B1}, {0xA84, 0x00200000},204 {0xA88, 0x040C0000}, {0xA8C, 0x12345678},205 {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89},206 {0xA98, 0x00000000}, {0xA9C, 0x80020000},207 {0xAA0, 0x00000000}, {0xAA4, 0x0000000C},208 {0xAA8, 0xCA110058}, {0xAAC, 0x01235667},209 {0xAB0, 0x00000000}, {0xAB4, 0x20201402},210 {0xB2C, 0x00000000}, {0xC00, 0x48071D40},211 {0xC04, 0x03A05611}, {0xC08, 0x000000E4},212 {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000},213 {0xC14, 0x40000100}, {0xC18, 0x08800000},214 {0xC1C, 0x40000100}, {0xC20, 0x00000000},215 {0xC24, 0x00000000}, {0xC28, 0x00000000},216 {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A},217 {0xC34, 0x31000040}, {0xC38, 0x21688080},218 {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F},219 {0xC44, 0x00010036}, {0xC48, 0xEC020107},220 {0xC4C, 0x007F037F}, {0xC50, 0x69553420},221 {0xC54, 0x43BC0094}, {0xC58, 0x00013169},222 {0xC5C, 0x00250492}, {0xC60, 0x00280A00},223 {0xC64, 0x7112848B}, {0xC68, 0x47C074FF},224 {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D},225 {0xC74, 0x020600DB}, {0xC78, 0x0000001F},226 {0xC7C, 0x00B91612}, {0xC80, 0x390000E4},227 {0xC84, 0x11F60000}, {0xC88, 0x1051B75F},228 {0xC8C, 0x20200109}, {0xC90, 0x00091521},229 {0xC94, 0x00000000}, {0xC98, 0x00121820},230 {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000},231 {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606},232 {0xCAC, 0x00000060}, {0xCB0, 0x00000000},233 {0xCB4, 0x00000000}, {0xCB8, 0x00000000},234 {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F},235 {0xCC4, 0x00000109}, {0xCC8, 0x000442D6},236 {0xCCC, 0x00000000}, {0xCD0, 0x000001C8},237 {0xCD4, 0x001C8000}, {0xCD8, 0x00000100},238 {0xCDC, 0x40100000}, {0xCE0, 0x00222220},239 {0xCE4, 0x10000000}, {0xCE8, 0x37644302},240 {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740},241 {0xD04, 0x40020401}, {0xD08, 0x0000907F},242 {0xD0C, 0x20010201}, {0xD10, 0xA0633333},243 {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F},244 {0xD2C, 0xCB979975}, {0xD30, 0x00000000},245 {0xD34, 0x40608000}, {0xD38, 0x88000000},246 {0xD3C, 0xC0127353}, {0xD40, 0x00000000},247 {0xD44, 0x00000000}, {0xD48, 0x00000000},248 {0xD4C, 0x00000000}, {0xD50, 0x00006528},249 {0xD54, 0x00000000}, {0xD58, 0x00000282},250 {0xD5C, 0x30032064}, {0xD60, 0x4653DE68},251 {0xD64, 0x04518A3C}, {0xD68, 0x00002101},252 {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D},253 {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D},254 {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D},255 {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000},256 {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F},257 {0xE38, 0x02140102}, {0xE3C, 0x681604C2},258 {0xE40, 0x01007C00}, {0xE44, 0x01004800},259 {0xE48, 0xFB000000}, {0xE4C, 0x000028D1},260 {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F},261 {0xE58, 0x02140102}, {0xE5C, 0x28160D05},262 {0xE60, 0x0000C008}, {0xE68, 0x001B25A4},263 {0xE64, 0x281600A0}, {0xE6C, 0x01C00010},264 {0xE70, 0x01C00010}, {0xE74, 0x02000010},265 {0xE78, 0x02000010}, {0xE7C, 0x02000010},266 {0xE80, 0x02000010}, {0xE84, 0x01C00010},267 {0xE88, 0x02000010}, {0xE8C, 0x01C00010},268 {0xED0, 0x01C00010}, {0xED4, 0x01C00010},269 {0xED8, 0x01C00010}, {0xEDC, 0x00000010},270 {0xEE0, 0x00000010}, {0xEEC, 0x03C00010},271 {0xF14, 0x00000003}, {0xF00, 0x00100300},272 {0xF08, 0x0000800B}, {0xF0C, 0x0000F007},273 {0xF10, 0x0000A487}, {0xF1C, 0x80000064},274 {0xF38, 0x00030155}, {0xF3C, 0x0000003A},275 {0xF4C, 0x13000000}, {0xF50, 0x00000000},276 {0xF18, 0x00000000},277 {0xffff, 0xffffffff},278};279 280static const struct rtl8xxxu_reg32val rtl8710b_agc_table[] = {281 {0xC78, 0xFC000001}, {0xC78, 0xFB010001},282 {0xC78, 0xFA020001}, {0xC78, 0xF9030001},283 {0xC78, 0xF8040001}, {0xC78, 0xF7050001},284 {0xC78, 0xF6060001}, {0xC78, 0xF5070001},285 {0xC78, 0xF4080001}, {0xC78, 0xF3090001},286 {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001},287 {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001},288 {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001},289 {0xC78, 0xEC100001}, {0xC78, 0xEB110001},290 {0xC78, 0xEA120001}, {0xC78, 0xE9130001},291 {0xC78, 0xE8140001}, {0xC78, 0xE7150001},292 {0xC78, 0xE6160001}, {0xC78, 0xE5170001},293 {0xC78, 0xE4180001}, {0xC78, 0xE3190001},294 {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001},295 {0xC78, 0xE01C0001}, {0xC78, 0xC31D0001},296 {0xC78, 0xC21E0001}, {0xC78, 0xC11F0001},297 {0xC78, 0xC0200001}, {0xC78, 0xA3210001},298 {0xC78, 0xA2220001}, {0xC78, 0xA1230001},299 {0xC78, 0xA0240001}, {0xC78, 0x86250001},300 {0xC78, 0x85260001}, {0xC78, 0x84270001},301 {0xC78, 0x83280001}, {0xC78, 0x82290001},302 {0xC78, 0x812A0001}, {0xC78, 0x802B0001},303 {0xC78, 0x632C0001}, {0xC78, 0x622D0001},304 {0xC78, 0x612E0001}, {0xC78, 0x602F0001},305 {0xC78, 0x42300001}, {0xC78, 0x41310001},306 {0xC78, 0x40320001}, {0xC78, 0x23330001},307 {0xC78, 0x22340001}, {0xC78, 0x21350001},308 {0xC78, 0x20360001}, {0xC78, 0x02370001},309 {0xC78, 0x01380001}, {0xC78, 0x00390001},310 {0xC78, 0x003A0001}, {0xC78, 0x003B0001},311 {0xC78, 0x003C0001}, {0xC78, 0x003D0001},312 {0xC78, 0x003E0001}, {0xC78, 0x003F0001},313 {0xC78, 0xF7400001}, {0xC78, 0xF7410001},314 {0xC78, 0xF7420001}, {0xC78, 0xF7430001},315 {0xC78, 0xF7440001}, {0xC78, 0xF7450001},316 {0xC78, 0xF7460001}, {0xC78, 0xF7470001},317 {0xC78, 0xF7480001}, {0xC78, 0xF6490001},318 {0xC78, 0xF34A0001}, {0xC78, 0xF24B0001},319 {0xC78, 0xF14C0001}, {0xC78, 0xF04D0001},320 {0xC78, 0xD14E0001}, {0xC78, 0xD04F0001},321 {0xC78, 0xB5500001}, {0xC78, 0xB4510001},322 {0xC78, 0xB3520001}, {0xC78, 0xB2530001},323 {0xC78, 0xB1540001}, {0xC78, 0xB0550001},324 {0xC78, 0xAF560001}, {0xC78, 0xAE570001},325 {0xC78, 0xAD580001}, {0xC78, 0xAC590001},326 {0xC78, 0xAB5A0001}, {0xC78, 0xAA5B0001},327 {0xC78, 0xA95C0001}, {0xC78, 0xA85D0001},328 {0xC78, 0xA75E0001}, {0xC78, 0xA65F0001},329 {0xC78, 0xA5600001}, {0xC78, 0xA4610001},330 {0xC78, 0xA3620001}, {0xC78, 0xA2630001},331 {0xC78, 0xA1640001}, {0xC78, 0xA0650001},332 {0xC78, 0x87660001}, {0xC78, 0x86670001},333 {0xC78, 0x85680001}, {0xC78, 0x84690001},334 {0xC78, 0x836A0001}, {0xC78, 0x826B0001},335 {0xC78, 0x816C0001}, {0xC78, 0x806D0001},336 {0xC78, 0x636E0001}, {0xC78, 0x626F0001},337 {0xC78, 0x61700001}, {0xC78, 0x60710001},338 {0xC78, 0x42720001}, {0xC78, 0x41730001},339 {0xC78, 0x40740001}, {0xC78, 0x23750001},340 {0xC78, 0x22760001}, {0xC78, 0x21770001},341 {0xC78, 0x20780001}, {0xC78, 0x03790001},342 {0xC78, 0x027A0001}, {0xC78, 0x017B0001},343 {0xC78, 0x007C0001}, {0xC78, 0x007D0001},344 {0xC78, 0x007E0001}, {0xC78, 0x007F0001},345 {0xC50, 0x69553422}, {0xC50, 0x69553420},346 {0xffff, 0xffffffff}347};348 349static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_u_radioa_init_table[] = {350 {0x00, 0x00030000}, {0x08, 0x00008400},351 {0x17, 0x00000000}, {0x18, 0x00000C01},352 {0x19, 0x000739D2}, {0x1C, 0x00000C4C},353 {0x1B, 0x00000C6C}, {0x1E, 0x00080009},354 {0x1F, 0x00000880}, {0x2F, 0x0001A060},355 {0x3F, 0x00015000}, {0x42, 0x000060C0},356 {0x57, 0x000D0000}, {0x58, 0x000C0160},357 {0x67, 0x00001552}, {0x83, 0x00000000},358 {0xB0, 0x000FF9F0}, {0xB1, 0x00010018},359 {0xB2, 0x00054C00}, {0xB4, 0x0004486B},360 {0xB5, 0x0000112A}, {0xB6, 0x0000053E},361 {0xB7, 0x00014408}, {0xB8, 0x00010200},362 {0xB9, 0x00080801}, {0xBA, 0x00040001},363 {0xBB, 0x00000400}, {0xBF, 0x000C0000},364 {0xC2, 0x00002400}, {0xC3, 0x00000009},365 {0xC4, 0x00040C91}, {0xC5, 0x00099999},366 {0xC6, 0x000000A3}, {0xC7, 0x00088820},367 {0xC8, 0x00076C06}, {0xC9, 0x00000000},368 {0xCA, 0x00080000}, {0xDF, 0x00000180},369 {0xEF, 0x000001A8}, {0x3D, 0x00000003},370 {0x3D, 0x00080003}, {0x51, 0x000F1E69},371 {0x52, 0x000FBF6C}, {0x53, 0x0000032F},372 {0x54, 0x00055007}, {0x56, 0x000517F0},373 {0x35, 0x000000F4}, {0x35, 0x00000179},374 {0x35, 0x000002F4}, {0x36, 0x00000BF8},375 {0x36, 0x00008BF8}, {0x36, 0x00010BF8},376 {0x36, 0x00018BF8}, {0x18, 0x00000C01},377 {0x5A, 0x00048000}, {0x5A, 0x00048000},378 {0x34, 0x0000ADF5}, {0x34, 0x00009DF2},379 {0x34, 0x00008DEF}, {0x34, 0x00007DEC},380 {0x34, 0x00006DE9}, {0x34, 0x00005CEC},381 {0x34, 0x00004CE9}, {0x34, 0x00003C6C},382 {0x34, 0x00002C69}, {0x34, 0x0000106E},383 {0x34, 0x0000006B}, {0x84, 0x00048000},384 {0x87, 0x00000065}, {0x8E, 0x00065540},385 {0xDF, 0x00000110}, {0x86, 0x0000002A},386 {0x8F, 0x00088000}, {0x81, 0x0003FD80},387 {0xEF, 0x00082000}, {0x3B, 0x000F0F00},388 {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00},389 {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00},390 {0x3B, 0x000A0500}, {0x3B, 0x00090400},391 {0x3B, 0x00080000}, {0x3B, 0x00070F00},392 {0x3B, 0x00060E00}, {0x3B, 0x00050A00},393 {0x3B, 0x00040D00}, {0x3B, 0x00030C00},394 {0x3B, 0x00020500}, {0x3B, 0x00010400},395 {0x3B, 0x00000000}, {0xEF, 0x00080000},396 {0xEF, 0x00088000}, {0x3B, 0x00000170},397 {0x3B, 0x000C0030}, {0xEF, 0x00080000},398 {0xEF, 0x00080000}, {0x30, 0x00010000},399 {0x31, 0x0000000F}, {0x32, 0x00047EFE},400 {0xEF, 0x00000000}, {0x00, 0x00010159},401 {0x18, 0x0000FC01}, {0xFE, 0x00000000},402 {0x00, 0x00033D95},403 {0xff, 0xffffffff}404};405 406static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_s_radioa_init_table[] = {407 {0x00, 0x00030000}, {0x08, 0x00008400},408 {0x17, 0x00000000}, {0x18, 0x00000C01},409 {0x19, 0x000739D2}, {0x1C, 0x00000C4C},410 {0x1B, 0x00000C6C}, {0x1E, 0x00080009},411 {0x1F, 0x00000880}, {0x2F, 0x0001A060},412 {0x3F, 0x00015000}, {0x42, 0x000060C0},413 {0x57, 0x000D0000}, {0x58, 0x000C0160},414 {0x67, 0x00001552}, {0x83, 0x00000000},415 {0xB0, 0x000FF9F0}, {0xB1, 0x00010018},416 {0xB2, 0x00054C00}, {0xB4, 0x0004486B},417 {0xB5, 0x0000112A}, {0xB6, 0x0000053E},418 {0xB7, 0x00014408}, {0xB8, 0x00010200},419 {0xB9, 0x00080801}, {0xBA, 0x00040001},420 {0xBB, 0x00000400}, {0xBF, 0x000C0000},421 {0xC2, 0x00002400}, {0xC3, 0x00000009},422 {0xC4, 0x00040C91}, {0xC5, 0x00099999},423 {0xC6, 0x000000A3}, {0xC7, 0x00088820},424 {0xC8, 0x00076C06}, {0xC9, 0x00000000},425 {0xCA, 0x00080000}, {0xDF, 0x00000180},426 {0xEF, 0x000001A8}, {0x3D, 0x00000003},427 {0x3D, 0x00080003}, {0x51, 0x000F1E69},428 {0x52, 0x000FBF6C}, {0x53, 0x0000032F},429 {0x54, 0x00055007}, {0x56, 0x000517F0},430 {0x35, 0x000000F4}, {0x35, 0x00000179},431 {0x35, 0x000002F4}, {0x36, 0x00000BF8},432 {0x36, 0x00008BF8}, {0x36, 0x00010BF8},433 {0x36, 0x00018BF8}, {0x18, 0x00000C01},434 {0x5A, 0x00048000}, {0x5A, 0x00048000},435 {0x34, 0x0000ADF5}, {0x34, 0x00009DF2},436 {0x34, 0x00008DEF}, {0x34, 0x00007DEC},437 {0x34, 0x00006DE9}, {0x34, 0x00005CEC},438 {0x34, 0x00004CE9}, {0x34, 0x00003C6C},439 {0x34, 0x00002C69}, {0x34, 0x0000106E},440 {0x34, 0x0000006B}, {0x84, 0x00048000},441 {0x87, 0x00000065}, {0x8E, 0x00065540},442 {0xDF, 0x00000110}, {0x86, 0x0000002A},443 {0x8F, 0x00088000}, {0x81, 0x0003FD80},444 {0xEF, 0x00082000}, {0x3B, 0x000F0F00},445 {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00},446 {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00},447 {0x3B, 0x000A0500}, {0x3B, 0x00090400},448 {0x3B, 0x00080000}, {0x3B, 0x00070F00},449 {0x3B, 0x00060E00}, {0x3B, 0x00050A00},450 {0x3B, 0x00040D00}, {0x3B, 0x00030C00},451 {0x3B, 0x00020500}, {0x3B, 0x00010400},452 {0x3B, 0x00000000}, {0xEF, 0x00080000},453 {0xEF, 0x00088000}, {0x3B, 0x000000B0},454 {0x3B, 0x000C0030}, {0xEF, 0x00080000},455 {0xEF, 0x00080000}, {0x30, 0x00010000},456 {0x31, 0x0000000F}, {0x32, 0x00047EFE},457 {0xEF, 0x00000000}, {0x00, 0x00010159},458 {0x18, 0x0000FC01}, {0xFE, 0x00000000},459 {0x00, 0x00033D95},460 {0xff, 0xffffffff}461};462 463static u32 rtl8710b_indirect_read32(struct rtl8xxxu_priv *priv, u32 addr)464{465 struct device *dev = &priv->udev->dev;466 u32 val32, value = 0xffffffff;467 u8 polling_count = 0xff;468 469 if (!IS_ALIGNED(addr, 4)) {470 dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n",471 __func__, addr);472 return value;473 }474 475 mutex_lock(&priv->syson_indirect_access_mutex);476 477 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr);478 rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_READ_OFFSET);479 480 do481 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);482 while ((val32 & BIT(31)) && (--polling_count > 0));483 484 if (polling_count == 0)485 dev_warn(dev, "%s: Failed to read from 0x%x, 0x806c = 0x%x\n",486 __func__, addr, val32);487 else488 value = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B);489 490 mutex_unlock(&priv->syson_indirect_access_mutex);491 492 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)493 dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, value);494 495 return value;496}497 498static void rtl8710b_indirect_write32(struct rtl8xxxu_priv *priv, u32 addr, u32 val)499{500 struct device *dev = &priv->udev->dev;501 u8 polling_count = 0xff;502 u32 val32;503 504 if (!IS_ALIGNED(addr, 4)) {505 dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n",506 __func__, addr);507 return;508 }509 510 mutex_lock(&priv->syson_indirect_access_mutex);511 512 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr);513 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_DATA_8710B, val);514 rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_WRITE_OFFSET);515 516 do517 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);518 while ((val32 & BIT(31)) && (--polling_count > 0));519 520 if (polling_count == 0)521 dev_warn(dev, "%s: Failed to write 0x%x to 0x%x, 0x806c = 0x%x\n",522 __func__, val, addr, val32);523 524 mutex_unlock(&priv->syson_indirect_access_mutex);525 526 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)527 dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, val);528}529 530static u32 rtl8710b_read_syson_reg(struct rtl8xxxu_priv *priv, u32 addr)531{532 return rtl8710b_indirect_read32(priv, addr | SYSON_REG_BASE_ADDR_8710B);533}534 535static void rtl8710b_write_syson_reg(struct rtl8xxxu_priv *priv, u32 addr, u32 val)536{537 rtl8710b_indirect_write32(priv, addr | SYSON_REG_BASE_ADDR_8710B, val);538}539 540static int rtl8710b_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)541{542 u32 val32;543 int i;544 545 /* Write Address */546 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, offset);547 548 rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, EFUSE_READ_OFFSET);549 550 /* Poll for data read */551 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);552 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {553 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);554 if (!(val32 & BIT(31)))555 break;556 }557 558 if (i == RTL8XXXU_MAX_REG_POLL)559 return -EIO;560 561 val32 = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B);562 563 *data = val32 & 0xff;564 return 0;565}566 567#define EEPROM_PACKAGE_TYPE_8710B 0xF8568#define PACKAGE_QFN48M_U 0xee569#define PACKAGE_QFN48M_S 0xfe570 571static int rtl8710bu_identify_chip(struct rtl8xxxu_priv *priv)572{573 struct device *dev = &priv->udev->dev;574 u32 cfg0, cfg2, vendor;575 u8 package_type = 0x7; /* a nonsense value */576 577 sprintf(priv->chip_name, "8710BU");578 priv->rtl_chip = RTL8710B;579 priv->rf_paths = 1;580 priv->rx_paths = 1;581 priv->tx_paths = 1;582 priv->has_wifi = 1;583 584 cfg0 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG0_8710B);585 priv->chip_cut = cfg0 & 0xf;586 587 if (cfg0 & BIT(16)) {588 dev_info(dev, "%s: Unsupported test chip\n", __func__);589 return -EOPNOTSUPP;590 }591 592 vendor = u32_get_bits(cfg0, 0xc0);593 594 /* SMIC and TSMC are swapped compared to rtl8xxxu_identify_vendor_2bits */595 switch (vendor) {596 case 0:597 sprintf(priv->chip_vendor, "SMIC");598 priv->vendor_smic = 1;599 break;600 case 1:601 sprintf(priv->chip_vendor, "TSMC");602 break;603 case 2:604 sprintf(priv->chip_vendor, "UMC");605 priv->vendor_umc = 1;606 break;607 default:608 sprintf(priv->chip_vendor, "unknown");609 break;610 }611 612 rtl8710b_read_efuse8(priv, EEPROM_PACKAGE_TYPE_8710B, &package_type);613 614 if (package_type == 0xff) {615 dev_warn(dev, "Package type is undefined. Assuming it based on the vendor.\n");616 617 if (priv->vendor_umc) {618 package_type = PACKAGE_QFN48M_U;619 } else if (priv->vendor_smic) {620 package_type = PACKAGE_QFN48M_S;621 } else {622 dev_warn(dev, "The vendor is neither UMC nor SMIC. Assuming the package type is QFN48M_U.\n");623 624 /*625 * In this case the vendor driver doesn't set626 * the package type to anything, which is the627 * same as setting it to PACKAGE_DEFAULT (0).628 */629 package_type = PACKAGE_QFN48M_U;630 }631 } else if (package_type != PACKAGE_QFN48M_S &&632 package_type != PACKAGE_QFN48M_U) {633 dev_warn(dev, "Failed to read the package type. Assuming it's the default QFN48M_U.\n");634 635 /*636 * In this case the vendor driver actually sets it to637 * PACKAGE_DEFAULT, but that selects the same values638 * from the init tables as PACKAGE_QFN48M_U.639 */640 package_type = PACKAGE_QFN48M_U;641 }642 643 priv->package_type = package_type;644 645 dev_dbg(dev, "Package type: 0x%x\n", package_type);646 647 cfg2 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG2_8710B);648 priv->rom_rev = cfg2 & 0xf;649 650 return rtl8xxxu_config_endpoints_no_sie(priv);651}652 653static void rtl8710b_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel)654{655 if (channel == 13) {656 /* Normal values */657 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);658 rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810);659 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);660 /* Special value for channel 13 */661 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xd1d80001);662 } else if (channel == 14) {663 /* Special values for channel 14 */664 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C);665 rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00000000);666 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667);667 /* Normal value */668 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);669 } else {670 /* Restore normal values from the phy init table */671 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);672 rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810);673 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);674 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);675 }676}677 678static void rtl8710bu_config_channel(struct ieee80211_hw *hw)679{680 struct rtl8xxxu_priv *priv = hw->priv;681 bool ht40 = conf_is_ht40(&hw->conf);682 u8 channel, subchannel = 0;683 bool sec_ch_above = 0;684 u32 val32;685 u16 val16;686 687 channel = (u8)hw->conf.chandef.chan->hw_value;688 689 if (conf_is_ht40_plus(&hw->conf)) {690 sec_ch_above = 1;691 channel += 2;692 subchannel = 2;693 } else if (conf_is_ht40_minus(&hw->conf)) {694 sec_ch_above = 0;695 channel -= 2;696 subchannel = 1;697 }698 699 /* Set channel */700 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);701 u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK);702 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);703 704 rtl8710b_revise_cck_tx_psf(priv, channel);705 706 /* Set bandwidth mode */707 val16 = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);708 val16 &= ~WMAC_TRXPTCL_CTL_BW_MASK;709 if (ht40)710 val16 |= WMAC_TRXPTCL_CTL_BW_40;711 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, val16);712 713 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);714 715 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);716 u32p_replace_bits(&val32, ht40, FPGA_RF_MODE);717 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);718 719 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);720 u32p_replace_bits(&val32, ht40, FPGA_RF_MODE);721 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);722 723 if (ht40) {724 /* Set Control channel to upper or lower. */725 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);726 u32p_replace_bits(&val32, !sec_ch_above, CCK0_SIDEBAND);727 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);728 }729 730 /* RXADC CLK */731 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);732 val32 |= GENMASK(10, 8);733 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);734 735 /* TXDAC CLK */736 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);737 val32 |= BIT(14) | BIT(12);738 val32 &= ~BIT(13);739 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);740 741 /* small BW */742 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);743 val32 &= ~GENMASK(31, 30);744 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);745 746 /* adc buffer clk */747 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);748 val32 &= ~BIT(29);749 val32 |= BIT(28);750 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);751 752 /* adc buffer clk */753 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE);754 val32 &= ~BIT(29);755 val32 |= BIT(28);756 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32);757 758 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);759 val32 &= ~BIT(30);760 val32 |= BIT(29);761 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);762 763 if (ht40) {764 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);765 val32 &= ~BIT(19);766 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);767 768 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);769 val32 &= ~GENMASK(23, 20);770 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);771 772 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);773 val32 &= ~GENMASK(27, 24);774 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);775 776 /* RF TRX_BW */777 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);778 val32 &= ~MODE_AG_BW_MASK;779 val32 |= MODE_AG_BW_40MHZ_8723B;780 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);781 } else {782 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);783 val32 |= BIT(19);784 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);785 786 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);787 val32 &= ~GENMASK(23, 20);788 val32 |= BIT(23);789 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);790 791 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);792 val32 &= ~GENMASK(27, 24);793 val32 |= BIT(27) | BIT(25);794 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);795 796 /* RF TRX_BW */797 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);798 val32 &= ~MODE_AG_BW_MASK;799 val32 |= MODE_AG_BW_20MHZ_8723B;800 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);801 }802}803 804static void rtl8710bu_init_aggregation(struct rtl8xxxu_priv *priv)805{806 u32 agg_rx;807 u8 agg_ctrl;808 809 /* RX aggregation */810 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);811 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;812 813 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);814 agg_rx &= ~RXDMA_USB_AGG_ENABLE;815 agg_rx &= ~0xFF0F; /* reset agg size and timeout */816 817 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);818 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);819}820 821static void rtl8710bu_init_statistics(struct rtl8xxxu_priv *priv)822{823 u32 val32;824 825 /* Time duration for NHM unit: 4us, 0xc350=200ms */826 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350);827 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);828 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50);829 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);830 831 /* TH8 */832 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);833 val32 |= 0xff;834 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);835 836 /* Enable CCK */837 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);838 val32 &= ~(BIT(8) | BIT(9) | BIT(10));839 val32 |= BIT(8);840 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);841 842 /* Max power amongst all RX antennas */843 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);844 val32 |= BIT(7);845 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);846}847 848static int rtl8710b_read_efuse(struct rtl8xxxu_priv *priv)849{850 struct device *dev = &priv->udev->dev;851 u8 val8, word_mask, header, extheader;852 u16 efuse_addr, offset;853 int i, ret = 0;854 u32 val32;855 856 val32 = rtl8710b_read_syson_reg(priv, REG_SYS_EEPROM_CTRL0_8710B);857 priv->boot_eeprom = u32_get_bits(val32, EEPROM_BOOT);858 priv->has_eeprom = u32_get_bits(val32, EEPROM_ENABLE);859 860 /* Default value is 0xff */861 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);862 863 efuse_addr = 0;864 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {865 u16 map_addr;866 867 ret = rtl8710b_read_efuse8(priv, efuse_addr++, &header);868 if (ret || header == 0xff)869 goto exit;870 871 if ((header & 0x1f) == 0x0f) { /* extended header */872 offset = (header & 0xe0) >> 5;873 874 ret = rtl8710b_read_efuse8(priv, efuse_addr++, &extheader);875 if (ret)876 goto exit;877 878 /* All words disabled */879 if ((extheader & 0x0f) == 0x0f)880 continue;881 882 offset |= ((extheader & 0xf0) >> 1);883 word_mask = extheader & 0x0f;884 } else {885 offset = (header >> 4) & 0x0f;886 word_mask = header & 0x0f;887 }888 889 /* Get word enable value from PG header */890 891 /* We have 8 bits to indicate validity */892 map_addr = offset * 8;893 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {894 /* Check word enable condition in the section */895 if (word_mask & BIT(i)) {896 map_addr += 2;897 continue;898 }899 900 ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8);901 if (ret)902 goto exit;903 if (map_addr >= EFUSE_MAP_LEN - 1) {904 dev_warn(dev, "%s: Illegal map_addr (%04x), efuse corrupt!\n",905 __func__, map_addr);906 ret = -EINVAL;907 goto exit;908 }909 priv->efuse_wifi.raw[map_addr++] = val8;910 911 ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8);912 if (ret)913 goto exit;914 priv->efuse_wifi.raw[map_addr++] = val8;915 }916 }917 918exit:919 920 return ret;921}922 923static int rtl8710bu_parse_efuse(struct rtl8xxxu_priv *priv)924{925 struct rtl8710bu_efuse *efuse = &priv->efuse_wifi.efuse8710bu;926 927 if (efuse->rtl_id != cpu_to_le16(0x8195))928 return -EINVAL;929 930 ether_addr_copy(priv->mac_addr, efuse->mac_addr);931 932 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,933 sizeof(efuse->tx_power_index_A.cck_base));934 935 memcpy(priv->ht40_1s_tx_power_index_A,936 efuse->tx_power_index_A.ht40_base,937 sizeof(efuse->tx_power_index_A.ht40_base));938 939 priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;940 priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;941 942 priv->default_crystal_cap = efuse->xtal_k & 0x3f;943 944 return 0;945}946 947static int rtl8710bu_load_firmware(struct rtl8xxxu_priv *priv)948{949 if (priv->vendor_smic) {950 return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8710bufw_SMIC.bin");951 } else if (priv->vendor_umc) {952 return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8710bufw_UMC.bin");953 } else {954 dev_err(&priv->udev->dev, "We have no suitable firmware for this chip.\n");955 return -1;956 }957}958 959static void rtl8710bu_init_phy_bb(struct rtl8xxxu_priv *priv)960{961 const struct rtl8xxxu_reg32val *phy_init_table;962 u32 val32;963 964 /* Enable BB and RF */965 val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B);966 val32 |= GENMASK(17, 16) | GENMASK(26, 24);967 rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32);968 969 if (priv->package_type == PACKAGE_QFN48M_U)970 phy_init_table = rtl8710bu_qfn48m_u_phy_init_table;971 else972 phy_init_table = rtl8710bu_qfn48m_s_phy_init_table;973 974 rtl8xxxu_init_phy_regs(priv, phy_init_table);975 976 rtl8xxxu_init_phy_regs(priv, rtl8710b_agc_table);977}978 979static int rtl8710bu_init_phy_rf(struct rtl8xxxu_priv *priv)980{981 const struct rtl8xxxu_rfregval *radioa_init_table;982 983 if (priv->package_type == PACKAGE_QFN48M_U)984 radioa_init_table = rtl8710bu_qfn48m_u_radioa_init_table;985 else986 radioa_init_table = rtl8710bu_qfn48m_s_radioa_init_table;987 988 return rtl8xxxu_init_phy_rf(priv, radioa_init_table, RF_A);989}990 991static int rtl8710bu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result)992{993 u32 reg_eac, reg_e94, reg_e9c, val32, path_sel_bb;994 int result = 0;995 996 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);997 998 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000);999 1000 /*1001 * Leave IQK mode1002 */1003 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1004 u32p_replace_bits(&val32, 0, 0xffffff00);1005 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1006 1007 /*1008 * Enable path A PA in TX IQK mode1009 */1010 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);1011 val32 |= 0x80000;1012 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);1013 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);1014 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);1015 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7);1016 1017 /* PA,PAD gain adjust */1018 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);1019 val32 |= BIT(11);1020 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);1021 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);1022 u32p_replace_bits(&val32, 0x1ed, 0x00fff);1023 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);1024 1025 /* enter IQK mode */1026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1027 u32p_replace_bits(&val32, 0x808000, 0xffffff00);1028 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1029 1030 /* path-A IQK setting */1031 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);1032 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);1033 1034 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff);1035 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c06);1036 1037 /* LO calibration setting */1038 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x02002911);1039 1040 /* One shot, path A LOK & IQK */1041 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);1042 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);1043 1044 mdelay(10);1045 1046 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);1047 1048 /*1049 * Leave IQK mode1050 */1051 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1052 u32p_replace_bits(&val32, 0, 0xffffff00);1053 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1054 1055 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);1056 val32 &= ~BIT(11);1057 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);1058 1059 /* save LOK result */1060 *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC);1061 1062 /* Check failed */1063 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);1064 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);1065 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);1066 1067 if (!(reg_eac & BIT(28)) &&1068 ((reg_e94 & 0x03ff0000) != 0x01420000) &&1069 ((reg_e9c & 0x03ff0000) != 0x00420000))1070 result |= 0x01;1071 1072 return result;1073}1074 1075static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)1076{1077 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32, path_sel_bb, tmp;1078 int result = 0;1079 1080 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);1081 1082 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000);1083 1084 /*1085 * Leave IQK mode1086 */1087 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1088 u32p_replace_bits(&val32, 0, 0xffffff00);1089 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1090 1091 /* modify RXIQK mode table */1092 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);1093 val32 |= 0x80000;1094 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);1095 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);1096 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);1097 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);1098 1099 /* PA,PAD gain adjust */1100 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);1101 val32 |= BIT(11);1102 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);1103 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);1104 u32p_replace_bits(&val32, 0xf, 0x003e0);1105 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);1106 1107 /*1108 * Enter IQK mode1109 */1110 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1111 u32p_replace_bits(&val32, 0x808000, 0xffffff00);1112 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1113 1114 /* path-A IQK setting */1115 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);1116 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);1117 1118 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216129f);1119 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c00);1120 1121 /*1122 * Tx IQK setting1123 */1124 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);1125 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);1126 1127 /* LO calibration setting */1128 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);1129 1130 /* One shot, path A LOK & IQK */1131 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);1132 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);1133 1134 mdelay(10);1135 1136 /* Check failed */1137 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);1138 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);1139 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);1140 1141 if (!(reg_eac & BIT(28)) &&1142 ((reg_e94 & 0x03ff0000) != 0x01420000) &&1143 ((reg_e9c & 0x03ff0000) != 0x00420000)) {1144 result |= 0x01;1145 } else { /* If TX not OK, ignore RX */1146 1147 /* reload RF path */1148 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);1149 1150 /*1151 * Leave IQK mode1152 */1153 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1154 u32p_replace_bits(&val32, 0, 0xffffff00);1155 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1156 1157 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);1158 val32 &= ~BIT(11);1159 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);1160 1161 return result;1162 }1163 1164 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16);1165 rtl8xxxu_write32(priv, REG_TX_IQK, val32);1166 1167 /*1168 * Modify RX IQK mode table1169 */1170 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1171 u32p_replace_bits(&val32, 0, 0xffffff00);1172 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1173 1174 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);1175 val32 |= 0x80000;1176 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);1177 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);1178 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);1179 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);1180 1181 /*1182 * PA, PAD setting1183 */1184 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);1185 val32 |= BIT(11);1186 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);1187 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);1188 u32p_replace_bits(&val32, 0x2a, 0x00fff);1189 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);1190 1191 /*1192 * Enter IQK mode1193 */1194 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1195 u32p_replace_bits(&val32, 0x808000, 0xffffff00);1196 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1197 1198 /*1199 * RX IQK setting1200 */1201 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);1202 1203 /* path-A IQK setting */1204 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);1205 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);1206 1207 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816169f);1208 1209 /* LO calibration setting */1210 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);1211 1212 /* One shot, path A LOK & IQK */1213 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);1214 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);1215 1216 mdelay(10);1217 1218 /* reload RF path */1219 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);1220 1221 /*1222 * Leave IQK mode1223 */1224 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1225 u32p_replace_bits(&val32, 0, 0xffffff00);1226 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1227 1228 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);1229 val32 &= ~BIT(11);1230 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);1231 1232 /* reload LOK value */1233 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result);1234 1235 /* Check failed */1236 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);1237 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);1238 1239 tmp = (reg_eac & 0x03ff0000) >> 16;1240 if ((tmp & 0x200) > 0)1241 tmp = 0x400 - tmp;1242 1243 if (!(reg_eac & BIT(27)) &&1244 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&1245 ((reg_eac & 0x03ff0000) != 0x00360000) &&1246 (((reg_ea4 & 0x03ff0000) >> 16) < 0x11a) &&1247 (((reg_ea4 & 0x03ff0000) >> 16) > 0xe6) &&1248 (tmp < 0x1a))1249 result |= 0x02;1250 1251 return result;1252}1253 1254static void rtl8710bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,1255 int result[][8], int t)1256{1257 struct device *dev = &priv->udev->dev;1258 u32 i, val32, rx_initial_gain, lok_result;1259 u32 path_sel_bb, path_sel_rf;1260 int path_a_ok;1261 int retry = 2;1262 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {1263 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,1264 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,1265 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,1266 REG_TX_OFDM_BBON, REG_TX_TO_RX,1267 REG_TX_TO_TX, REG_RX_CCK,1268 REG_RX_OFDM, REG_RX_WAIT_RIFS,1269 REG_RX_TO_RX, REG_STANDBY,1270 REG_SLEEP, REG_PMPD_ANAEN1271 };1272 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {1273 REG_TXPAUSE, REG_BEACON_CTRL,1274 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG1275 };1276 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {1277 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,1278 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,1279 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,1280 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING1281 };1282 1283 /*1284 * Note: IQ calibration must be performed after loading1285 * PHY_REG.txt , and radio_a, radio_b.txt1286 */1287 1288 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);1289 1290 if (t == 0) {1291 /* Save ADDA parameters, turn Path A ADDA on */1292 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,1293 RTL8XXXU_ADDA_REGS);1294 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);1295 rtl8xxxu_save_regs(priv, iqk_bb_regs,1296 priv->bb_backup, RTL8XXXU_BB_REGS);1297 }1298 1299 rtl8xxxu_path_adda_on(priv, adda_regs, true);1300 1301 if (t == 0) {1302 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);1303 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI);1304 }1305 1306 if (!priv->pi_enabled) {1307 /* Switch BB to PI mode to do IQ Calibration */1308 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);1309 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);1310 }1311 1312 /* MAC settings */1313 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL);1314 val32 |= 0x00ff0000;1315 rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32);1316 1317 /* save RF path */1318 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);1319 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1);1320 1321 /* BB setting */1322 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);1323 val32 |= 0x0f000000;1324 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);1325 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x03c00010);1326 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05601);1327 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);1328 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000);1329 1330 /* IQ calibration setting */1331 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1332 u32p_replace_bits(&val32, 0x808000, 0xffffff00);1333 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1334 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);1335 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);1336 1337 for (i = 0; i < retry; i++) {1338 path_a_ok = rtl8710bu_iqk_path_a(priv, &lok_result);1339 1340 if (path_a_ok == 0x01) {1341 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);1342 result[t][0] = (val32 >> 16) & 0x3ff;1343 1344 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);1345 result[t][1] = (val32 >> 16) & 0x3ff;1346 break;1347 } else {1348 result[t][0] = 0x100;1349 result[t][1] = 0x0;1350 }1351 }1352 1353 for (i = 0; i < retry; i++) {1354 path_a_ok = rtl8710bu_rx_iqk_path_a(priv, lok_result);1355 1356 if (path_a_ok == 0x03) {1357 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);1358 result[t][2] = (val32 >> 16) & 0x3ff;1359 1360 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);1361 result[t][3] = (val32 >> 16) & 0x3ff;1362 break;1363 } else {1364 result[t][2] = 0x100;1365 result[t][3] = 0x0;1366 }1367 }1368 1369 if (!path_a_ok)1370 dev_warn(dev, "%s: Path A IQK failed!\n", __func__);1371 1372 /* Back to BB mode, load original value */1373 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);1374 u32p_replace_bits(&val32, 0, 0xffffff00);1375 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);1376 1377 if (t == 0)1378 return;1379 1380 /* Reload ADDA power saving parameters */1381 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, RTL8XXXU_ADDA_REGS);1382 1383 /* Reload MAC parameters */1384 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);1385 1386 /* Reload BB parameters */1387 rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS);1388 1389 /* Reload RF path */1390 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);1391 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf);1392 1393 /* Restore RX initial gain */1394 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);1395 u32p_replace_bits(&val32, 0x50, 0x000000ff);1396 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32);1397 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);1398 u32p_replace_bits(&val32, rx_initial_gain & 0xff, 0x000000ff);1399 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32);1400 1401 /* Load 0xe30 IQC default value */1402 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);1403 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);1404}1405 1406static void rtl8710bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)1407{1408 struct device *dev = &priv->udev->dev;1409 int result[4][8]; /* last is final result */1410 int i, candidate;1411 bool path_a_ok;1412 s32 reg_e94, reg_e9c, reg_ea4, reg_eac;1413 s32 reg_tmp = 0;1414 bool simu;1415 u32 path_sel_bb;1416 1417 /* Save RF path */1418 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);1419 1420 memset(result, 0, sizeof(result));1421 candidate = -1;1422 1423 path_a_ok = false;1424 1425 for (i = 0; i < 3; i++) {1426 rtl8710bu_phy_iqcalibrate(priv, result, i);1427 1428 if (i == 1) {1429 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1);1430 if (simu) {1431 candidate = 0;1432 break;1433 }1434 }1435 1436 if (i == 2) {1437 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2);1438 if (simu) {1439 candidate = 0;1440 break;1441 }1442 1443 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2);1444 if (simu) {1445 candidate = 1;1446 } else {1447 for (i = 0; i < 8; i++)1448 reg_tmp += result[3][i];1449 1450 if (reg_tmp)1451 candidate = 3;1452 else1453 candidate = -1;1454 }1455 }1456 }1457 1458 if (candidate >= 0) {1459 reg_e94 = result[candidate][0];1460 reg_e9c = result[candidate][1];1461 reg_ea4 = result[candidate][2];1462 reg_eac = result[candidate][3];1463 1464 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);1465 dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x\n",1466 __func__, reg_e94, reg_e9c, reg_ea4, reg_eac);1467 1468 path_a_ok = true;1469 1470 if (reg_e94)1471 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,1472 candidate, (reg_ea4 == 0));1473 }1474 1475 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,1476 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);1477 1478 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);1479}1480 1481static int rtl8710b_emu_to_active(struct rtl8xxxu_priv *priv)1482{1483 u8 val8;1484 int count, ret = 0;1485 1486 /* AFE power mode selection: 1: LDO mode, 0: Power-cut mode */1487 val8 = rtl8xxxu_read8(priv, 0x5d);1488 val8 &= ~BIT(0);1489 rtl8xxxu_write8(priv, 0x5d, val8);1490 1491 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B);1492 val8 |= BIT(0);1493 rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8);1494 1495 rtl8xxxu_write8(priv, 0x56, 0x0e);1496 1497 val8 = rtl8xxxu_read8(priv, 0x20);1498 val8 |= BIT(0);1499 rtl8xxxu_write8(priv, 0x20, val8);1500 1501 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {1502 val8 = rtl8xxxu_read8(priv, 0x20);1503 if (!(val8 & BIT(0)))1504 break;1505 1506 udelay(10);1507 }1508 1509 if (!count)1510 ret = -EBUSY;1511 1512 return ret;1513}1514 1515static int rtl8710bu_active_to_emu(struct rtl8xxxu_priv *priv)1516{1517 u8 val8;1518 u32 val32;1519 int count, ret = 0;1520 1521 /* Turn off RF */1522 val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B);1523 val32 &= ~GENMASK(26, 24);1524 rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32);1525 1526 /* BB reset */1527 val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B);1528 val32 &= ~GENMASK(17, 16);1529 rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32);1530 1531 /* Turn off MAC by HW state machine */1532 val8 = rtl8xxxu_read8(priv, 0x20);1533 val8 |= BIT(1);1534 rtl8xxxu_write8(priv, 0x20, val8);1535 1536 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {1537 val8 = rtl8xxxu_read8(priv, 0x20);1538 if ((val8 & BIT(1)) == 0) {1539 ret = 0;1540 break;1541 }1542 udelay(10);1543 }1544 1545 if (!count)1546 ret = -EBUSY;1547 1548 return ret;1549}1550 1551static int rtl8710bu_active_to_lps(struct rtl8xxxu_priv *priv)1552{1553 struct device *dev = &priv->udev->dev;1554 u8 val8;1555 u16 val16;1556 u32 val32;1557 int retry, retval;1558 1559 /* Tx Pause */1560 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);1561 1562 retry = 100;1563 retval = -EBUSY;1564 /*1565 * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending.1566 */1567 do {1568 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);1569 if (!val32) {1570 retval = 0;1571 break;1572 }1573 udelay(10);1574 } while (retry--);1575 1576 if (!retry) {1577 dev_warn(dev, "Failed to flush TX queue\n");1578 retval = -EBUSY;1579 return retval;1580 }1581 1582 /* Disable CCK and OFDM, clock gated */1583 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);1584 val8 &= ~SYS_FUNC_BBRSTB;1585 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);1586 1587 udelay(2);1588 1589 /* Whole BB is reset */1590 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);1591 val8 &= ~SYS_FUNC_BB_GLB_RSTN;1592 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);1593 1594 /* Reset MAC TRX */1595 val16 = rtl8xxxu_read16(priv, REG_CR);1596 val16 &= 0xff00;1597 val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE;1598 val16 &= ~CR_SECURITY_ENABLE;1599 rtl8xxxu_write16(priv, REG_CR, val16);1600 1601 /* Respond TxOK to scheduler */1602 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);1603 val8 |= DUAL_TSF_TX_OK;1604 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);1605 1606 return retval;1607}1608 1609static int rtl8710bu_power_on(struct rtl8xxxu_priv *priv)1610{1611 u32 val32;1612 u16 val16;1613 u8 val8;1614 int ret;1615 1616 rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80);1617 1618 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);1619 val8 &= ~BIT(5);1620 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);1621 1622 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B);1623 val8 |= BIT(0);1624 rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8);1625 1626 val8 = rtl8xxxu_read8(priv, 0x20);1627 val8 |= BIT(0);1628 rtl8xxxu_write8(priv, 0x20, val8);1629 1630 rtl8xxxu_write8(priv, REG_AFE_CTRL_8710B, 0);1631 1632 val8 = rtl8xxxu_read8(priv, REG_WL_STATUS_8710B);1633 val8 |= BIT(1);1634 rtl8xxxu_write8(priv, REG_WL_STATUS_8710B, val8);1635 1636 ret = rtl8710b_emu_to_active(priv);1637 if (ret)1638 return ret;1639 1640 rtl8xxxu_write16(priv, REG_CR, 0);1641 1642 val16 = rtl8xxxu_read16(priv, REG_CR);1643 1644 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |1645 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |1646 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |1647 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE;1648 rtl8xxxu_write16(priv, REG_CR, val16);1649 1650 /* Enable hardware sequence number. */1651 val8 = rtl8xxxu_read8(priv, REG_HWSEQ_CTRL);1652 val8 |= 0x7f;1653 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, val8);1654 1655 udelay(2);1656 1657 /*1658 * Technically the rest was in the rtl8710bu_hal_init function,1659 * not the power_on function, but it's fine because we only1660 * call power_on from init_device.1661 */1662 1663 val8 = rtl8xxxu_read8(priv, 0xfef9);1664 val8 &= ~BIT(0);1665 rtl8xxxu_write8(priv, 0xfef9, val8);1666 1667 /* Clear the 0x40000138[5] to prevent CM4 Suspend */1668 val32 = rtl8710b_read_syson_reg(priv, 0x138);1669 val32 &= ~BIT(5);1670 rtl8710b_write_syson_reg(priv, 0x138, val32);1671 1672 return ret;1673}1674 1675static void rtl8710bu_power_off(struct rtl8xxxu_priv *priv)1676{1677 u32 val32;1678 u8 val8;1679 1680 rtl8xxxu_flush_fifo(priv);1681 1682 rtl8xxxu_write32(priv, REG_HISR0_8710B, 0xffffffff);1683 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0x0);1684 1685 /* Set the 0x40000138[5] to allow CM4 Suspend */1686 val32 = rtl8710b_read_syson_reg(priv, 0x138);1687 val32 |= BIT(5);1688 rtl8710b_write_syson_reg(priv, 0x138, val32);1689 1690 /* Stop rx */1691 rtl8xxxu_write8(priv, REG_CR, 0x00);1692 1693 rtl8710bu_active_to_lps(priv);1694 1695 /* Reset MCU ? */1696 val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3);1697 val8 &= ~BIT(0);1698 rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8);1699 1700 /* Reset MCU ready status */1701 rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B, 0x00);1702 1703 rtl8710bu_active_to_emu(priv);1704}1705 1706static void rtl8710b_reset_8051(struct rtl8xxxu_priv *priv)1707{1708 u8 val8;1709 1710 val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3);1711 val8 &= ~BIT(0);1712 rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8);1713 1714 udelay(50);1715 1716 val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3);1717 val8 |= BIT(0);1718 rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8);1719}1720 1721static void rtl8710b_enable_rf(struct rtl8xxxu_priv *priv)1722{1723 u32 val32;1724 1725 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB);1726 1727 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);1728 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);1729 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A;1730 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);1731 1732 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);1733}1734 1735static void rtl8710b_disable_rf(struct rtl8xxxu_priv *priv)1736{1737 u32 val32;1738 1739 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);1740 val32 &= ~OFDM_RF_PATH_TX_MASK;1741 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);1742 1743 /* Power down RF module */1744 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);1745}1746 1747static void rtl8710b_usb_quirks(struct rtl8xxxu_priv *priv)1748{1749 u16 val16;1750 1751 rtl8xxxu_gen2_usb_quirks(priv);1752 1753 val16 = rtl8xxxu_read16(priv, REG_CR);1754 val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE);1755 rtl8xxxu_write16(priv, REG_CR, val16);1756}1757 1758#define XTAL1 GENMASK(29, 24)1759#define XTAL0 GENMASK(23, 18)1760 1761static void rtl8710b_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap)1762{1763 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;1764 u32 val32;1765 1766 if (crystal_cap == cfo->crystal_cap)1767 return;1768 1769 val32 = rtl8710b_read_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B);1770 1771 dev_dbg(&priv->udev->dev,1772 "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n",1773 __func__,1774 cfo->crystal_cap,1775 u32_get_bits(val32, XTAL1),1776 u32_get_bits(val32, XTAL0),1777 crystal_cap);1778 1779 u32p_replace_bits(&val32, crystal_cap, XTAL1);1780 u32p_replace_bits(&val32, crystal_cap, XTAL0);1781 rtl8710b_write_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B, val32);1782 1783 cfo->crystal_cap = crystal_cap;1784}1785 1786static s8 rtl8710b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)1787{1788 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;1789 u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l;1790 u8 vga_idx = phy_stats0->vga;1791 s8 rx_pwr_all = 0x00;1792 1793 switch (lna_idx) {1794 case 7:1795 rx_pwr_all = -52 - (2 * vga_idx);1796 break;1797 case 6:1798 rx_pwr_all = -42 - (2 * vga_idx);1799 break;1800 case 5:1801 rx_pwr_all = -36 - (2 * vga_idx);1802 break;1803 case 3:1804 rx_pwr_all = -12 - (2 * vga_idx);1805 break;1806 case 2:1807 rx_pwr_all = 0 - (2 * vga_idx);1808 break;1809 default:1810 rx_pwr_all = 0;1811 break;1812 }1813 1814 return rx_pwr_all;1815}1816 1817struct rtl8xxxu_fileops rtl8710bu_fops = {1818 .identify_chip = rtl8710bu_identify_chip,1819 .parse_efuse = rtl8710bu_parse_efuse,1820 .load_firmware = rtl8710bu_load_firmware,1821 .power_on = rtl8710bu_power_on,1822 .power_off = rtl8710bu_power_off,1823 .read_efuse = rtl8710b_read_efuse,1824 .reset_8051 = rtl8710b_reset_8051,1825 .llt_init = rtl8xxxu_auto_llt_table,1826 .init_phy_bb = rtl8710bu_init_phy_bb,1827 .init_phy_rf = rtl8710bu_init_phy_rf,1828 .phy_lc_calibrate = rtl8188f_phy_lc_calibrate,1829 .phy_iq_calibrate = rtl8710bu_phy_iq_calibrate,1830 .config_channel = rtl8710bu_config_channel,1831 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,1832 .parse_phystats = jaguar2_rx_parse_phystats,1833 .init_aggregation = rtl8710bu_init_aggregation,1834 .init_statistics = rtl8710bu_init_statistics,1835 .init_burst = rtl8xxxu_init_burst,1836 .enable_rf = rtl8710b_enable_rf,1837 .disable_rf = rtl8710b_disable_rf,1838 .usb_quirks = rtl8710b_usb_quirks,1839 .set_tx_power = rtl8188f_set_tx_power,1840 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,1841 .report_connect = rtl8xxxu_gen2_report_connect,1842 .report_rssi = rtl8xxxu_gen2_report_rssi,1843 .fill_txdesc = rtl8xxxu_fill_txdesc_v2,1844 .set_crystal_cap = rtl8710b_set_crystal_cap,1845 .cck_rssi = rtl8710b_cck_rssi,1846 .writeN_block_size = 4,1847 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),1848 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),1849 .has_tx_report = 1,1850 .gen2_thermal_meter = 1,1851 .needs_full_init = 1,1852 .init_reg_rxfltmap = 1,1853 .init_reg_pkt_life_time = 1,1854 .init_reg_hmtfr = 1,1855 .ampdu_max_time = 0x5e,1856 /*1857 * The RTL8710BU vendor driver uses 0x50 here and it works fine,1858 * but in rtl8xxxu 0x50 causes slow upload and random packet loss. Why?1859 */1860 .ustime_tsf_edca = 0x28,1861 .max_aggr_num = 0x0c14,1862 .supports_ap = 1,1863 .max_macid_num = 16,1864 .max_sec_cam_num = 32,1865 .adda_1t_init = 0x03c00016,1866 .adda_1t_path_on = 0x03c00016,1867 .trxff_boundary = 0x3f7f,1868 .pbp_rx = PBP_PAGE_SIZE_256,1869 .pbp_tx = PBP_PAGE_SIZE_256,1870 .mactable = rtl8710b_mac_init_table,1871 .total_page_num = TX_TOTAL_PAGE_NUM_8723B,1872 .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B,1873 .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B,1874 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B,1875};1876