8294 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * RTL8XXXU mac80211 USB driver4 *5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>6 *7 * Portions, notably calibration code:8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.9 *10 * This driver was written as a replacement for the vendor provided11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in12 * their programming interface, I have started adding support for13 * additional 8xxx chips like the 8192cu, 8188cus, etc.14 */15 16#include <linux/firmware.h>17#include "regs.h"18#include "rtl8xxxu.h"19 20#define DRIVER_NAME "rtl8xxxu"21 22int rtl8xxxu_debug;23static bool rtl8xxxu_ht40_2g;24static bool rtl8xxxu_dma_aggregation;25static int rtl8xxxu_dma_agg_timeout = -1;26static int rtl8xxxu_dma_agg_pages = -1;27 28MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");29MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");30MODULE_LICENSE("GPL");31MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");32MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");33MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");34MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin");35MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");36MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");37MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");38MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");39MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");40MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");41MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin");42MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin");43MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin");44MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin");45 46module_param_named(debug, rtl8xxxu_debug, int, 0600);47MODULE_PARM_DESC(debug, "Set debug mask");48module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);49MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");50module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);51MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");52module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);53MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");54module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);55MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");56 57#define USB_VENDOR_ID_REALTEK 0x0bda58#define RTL8XXXU_RX_URBS 3259#define RTL8XXXU_RX_URB_PENDING_WATER 860#define RTL8XXXU_TX_URBS 6461#define RTL8XXXU_TX_URB_LOW_WATER 2562#define RTL8XXXU_TX_URB_HIGH_WATER 3263 64static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,65 struct rtl8xxxu_rx_urb *rx_urb);66 67static struct ieee80211_rate rtl8xxxu_rates[] = {68 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },69 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },70 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },71 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },72 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },73 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },74 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },75 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },76 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },77 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },78 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },79 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },80};81 82static struct ieee80211_channel rtl8xxxu_channels_2g[] = {83 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,84 .hw_value = 1, .max_power = 30 },85 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,86 .hw_value = 2, .max_power = 30 },87 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,88 .hw_value = 3, .max_power = 30 },89 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,90 .hw_value = 4, .max_power = 30 },91 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,92 .hw_value = 5, .max_power = 30 },93 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,94 .hw_value = 6, .max_power = 30 },95 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,96 .hw_value = 7, .max_power = 30 },97 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,98 .hw_value = 8, .max_power = 30 },99 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,100 .hw_value = 9, .max_power = 30 },101 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,102 .hw_value = 10, .max_power = 30 },103 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,104 .hw_value = 11, .max_power = 30 },105 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,106 .hw_value = 12, .max_power = 30 },107 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,108 .hw_value = 13, .max_power = 30 },109 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,110 .hw_value = 14, .max_power = 30 }111};112 113static struct ieee80211_supported_band rtl8xxxu_supported_band = {114 .channels = rtl8xxxu_channels_2g,115 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),116 .bitrates = rtl8xxxu_rates,117 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),118};119 120static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {121 {0x800, 0x80040000}, {0x804, 0x00000003},122 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},123 {0x810, 0x10001331}, {0x814, 0x020c3d10},124 {0x818, 0x02200385}, {0x81c, 0x00000000},125 {0x820, 0x01000100}, {0x824, 0x00390004},126 {0x828, 0x00000000}, {0x82c, 0x00000000},127 {0x830, 0x00000000}, {0x834, 0x00000000},128 {0x838, 0x00000000}, {0x83c, 0x00000000},129 {0x840, 0x00010000}, {0x844, 0x00000000},130 {0x848, 0x00000000}, {0x84c, 0x00000000},131 {0x850, 0x00000000}, {0x854, 0x00000000},132 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},133 {0x860, 0x66f60110}, {0x864, 0x061f0130},134 {0x868, 0x00000000}, {0x86c, 0x32323200},135 {0x870, 0x07000760}, {0x874, 0x22004000},136 {0x878, 0x00000808}, {0x87c, 0x00000000},137 {0x880, 0xc0083070}, {0x884, 0x000004d5},138 {0x888, 0x00000000}, {0x88c, 0xccc000c0},139 {0x890, 0x00000800}, {0x894, 0xfffffffe},140 {0x898, 0x40302010}, {0x89c, 0x00706050},141 {0x900, 0x00000000}, {0x904, 0x00000023},142 {0x908, 0x00000000}, {0x90c, 0x81121111},143 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},144 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},145 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},146 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},147 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},148 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},149 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},150 {0xa78, 0x00000900},151 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},152 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},153 {0xc10, 0x08800000}, {0xc14, 0x40000100},154 {0xc18, 0x08800000}, {0xc1c, 0x40000100},155 {0xc20, 0x00000000}, {0xc24, 0x00000000},156 {0xc28, 0x00000000}, {0xc2c, 0x00000000},157 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},158 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},159 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},160 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},161 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},162 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},163 {0xc60, 0x00000000}, {0xc64, 0x7112848b},164 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},165 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},166 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},167 {0xc80, 0x40000100}, {0xc84, 0x20f60000},168 {0xc88, 0x40000100}, {0xc8c, 0x20200000},169 {0xc90, 0x00121820}, {0xc94, 0x00000000},170 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},171 {0xca0, 0x00000000}, {0xca4, 0x00000080},172 {0xca8, 0x00000000}, {0xcac, 0x00000000},173 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},174 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},175 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},176 {0xcc8, 0x00000000}, {0xccc, 0x00000000},177 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},178 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},179 {0xce0, 0x00222222}, {0xce4, 0x00000000},180 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},181 {0xd00, 0x00080740}, {0xd04, 0x00020401},182 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},183 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},184 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},185 {0xd30, 0x00000000}, {0xd34, 0x80608000},186 {0xd38, 0x00000000}, {0xd3c, 0x00027293},187 {0xd40, 0x00000000}, {0xd44, 0x00000000},188 {0xd48, 0x00000000}, {0xd4c, 0x00000000},189 {0xd50, 0x6437140a}, {0xd54, 0x00000000},190 {0xd58, 0x00000000}, {0xd5c, 0x30032064},191 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},192 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},193 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},194 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},195 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},196 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},197 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},198 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},199 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},200 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},201 {0xe44, 0x01004800}, {0xe48, 0xfb000000},202 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},203 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},204 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},205 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},206 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},207 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},208 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},209 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},210 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},211 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},212 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},213 {0xf14, 0x00000003}, {0xf4c, 0x00000000},214 {0xf00, 0x00000300},215 {0xffff, 0xffffffff},216};217 218static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {219 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},220 {0x800, 0x80040002}, {0x804, 0x00000003},221 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},222 {0x810, 0x10000330}, {0x814, 0x020c3d10},223 {0x818, 0x02200385}, {0x81c, 0x00000000},224 {0x820, 0x01000100}, {0x824, 0x00390004},225 {0x828, 0x01000100}, {0x82c, 0x00390004},226 {0x830, 0x27272727}, {0x834, 0x27272727},227 {0x838, 0x27272727}, {0x83c, 0x27272727},228 {0x840, 0x00010000}, {0x844, 0x00010000},229 {0x848, 0x27272727}, {0x84c, 0x27272727},230 {0x850, 0x00000000}, {0x854, 0x00000000},231 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},232 {0x860, 0x66e60230}, {0x864, 0x061f0130},233 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},234 {0x870, 0x07000700}, {0x874, 0x22184000},235 {0x878, 0x08080808}, {0x87c, 0x00000000},236 {0x880, 0xc0083070}, {0x884, 0x000004d5},237 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},238 {0x890, 0x00000800}, {0x894, 0xfffffffe},239 {0x898, 0x40302010}, {0x89c, 0x00706050},240 {0x900, 0x00000000}, {0x904, 0x00000023},241 {0x908, 0x00000000}, {0x90c, 0x81121313},242 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},243 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},244 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},245 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},246 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},247 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},248 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},249 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},250 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},251 {0xc10, 0x08800000}, {0xc14, 0x40000100},252 {0xc18, 0x08800000}, {0xc1c, 0x40000100},253 {0xc20, 0x00000000}, {0xc24, 0x00000000},254 {0xc28, 0x00000000}, {0xc2c, 0x00000000},255 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},256 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},257 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},258 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},259 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},260 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},261 {0xc60, 0x00000000}, {0xc64, 0x5116848b},262 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},263 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},264 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},265 {0xc80, 0x40000100}, {0xc84, 0x20f60000},266 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},267 {0xc90, 0x00121820}, {0xc94, 0x00000000},268 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},269 {0xca0, 0x00000000}, {0xca4, 0x00000080},270 {0xca8, 0x00000000}, {0xcac, 0x00000000},271 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},272 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},273 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},274 {0xcc8, 0x00000000}, {0xccc, 0x00000000},275 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},276 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},277 {0xce0, 0x00222222}, {0xce4, 0x00000000},278 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},279 {0xd00, 0x00080740}, {0xd04, 0x00020403},280 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},281 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},282 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},283 {0xd30, 0x00000000}, {0xd34, 0x80608000},284 {0xd38, 0x00000000}, {0xd3c, 0x00027293},285 {0xd40, 0x00000000}, {0xd44, 0x00000000},286 {0xd48, 0x00000000}, {0xd4c, 0x00000000},287 {0xd50, 0x6437140a}, {0xd54, 0x00000000},288 {0xd58, 0x00000000}, {0xd5c, 0x30032064},289 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},290 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},291 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},292 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},293 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},294 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},295 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},296 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},297 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},298 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},299 {0xe44, 0x01004800}, {0xe48, 0xfb000000},300 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},301 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},302 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},303 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},304 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},305 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},306 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},307 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},308 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},309 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},310 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},311 {0xf14, 0x00000003}, {0xf4c, 0x00000000},312 {0xf00, 0x00000300},313 {0xffff, 0xffffffff},314};315 316static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {317 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},318 {0x040, 0x000c0004}, {0x800, 0x80040000},319 {0x804, 0x00000001}, {0x808, 0x0000fc00},320 {0x80c, 0x0000000a}, {0x810, 0x10005388},321 {0x814, 0x020c3d10}, {0x818, 0x02200385},322 {0x81c, 0x00000000}, {0x820, 0x01000100},323 {0x824, 0x00390204}, {0x828, 0x00000000},324 {0x82c, 0x00000000}, {0x830, 0x00000000},325 {0x834, 0x00000000}, {0x838, 0x00000000},326 {0x83c, 0x00000000}, {0x840, 0x00010000},327 {0x844, 0x00000000}, {0x848, 0x00000000},328 {0x84c, 0x00000000}, {0x850, 0x00000000},329 {0x854, 0x00000000}, {0x858, 0x569a569a},330 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},331 {0x864, 0x061f0130}, {0x868, 0x00000000},332 {0x86c, 0x20202000}, {0x870, 0x03000300},333 {0x874, 0x22004000}, {0x878, 0x00000808},334 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},335 {0x884, 0x000004d5}, {0x888, 0x00000000},336 {0x88c, 0xccc000c0}, {0x890, 0x00000800},337 {0x894, 0xfffffffe}, {0x898, 0x40302010},338 {0x89c, 0x00706050}, {0x900, 0x00000000},339 {0x904, 0x00000023}, {0x908, 0x00000000},340 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},341 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},342 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},343 {0xa14, 0x11144028}, {0xa18, 0x00881117},344 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},345 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},346 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},347 {0xa74, 0x00000007}, {0xc00, 0x48071d40},348 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},349 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},350 {0xc14, 0x40000100}, {0xc18, 0x08800000},351 {0xc1c, 0x40000100}, {0xc20, 0x00000000},352 {0xc24, 0x00000000}, {0xc28, 0x00000000},353 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},354 {0xc34, 0x469652cf}, {0xc38, 0x49795994},355 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},356 {0xc44, 0x000100b7}, {0xc48, 0xec020107},357 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},358 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},359 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},360 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},361 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},362 {0xc74, 0x018610db}, {0xc78, 0x0000001f},363 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},364 {0xc84, 0x20f60000}, {0xc88, 0x24000090},365 {0xc8c, 0x20200000}, {0xc90, 0x00121820},366 {0xc94, 0x00000000}, {0xc98, 0x00121820},367 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},368 {0xca4, 0x00000080}, {0xca8, 0x00000000},369 {0xcac, 0x00000000}, {0xcb0, 0x00000000},370 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},371 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},372 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},373 {0xccc, 0x00000000}, {0xcd0, 0x00000000},374 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},375 {0xcdc, 0x00766932}, {0xce0, 0x00222222},376 {0xce4, 0x00000000}, {0xce8, 0x37644302},377 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},378 {0xd04, 0x00020401}, {0xd08, 0x0000907f},379 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},380 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},381 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},382 {0xd34, 0x80608000}, {0xd38, 0x00000000},383 {0xd3c, 0x00027293}, {0xd40, 0x00000000},384 {0xd44, 0x00000000}, {0xd48, 0x00000000},385 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},386 {0xd54, 0x00000000}, {0xd58, 0x00000000},387 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},388 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},389 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},390 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},391 {0xe00, 0x24242424}, {0xe04, 0x24242424},392 {0xe08, 0x03902024}, {0xe10, 0x24242424},393 {0xe14, 0x24242424}, {0xe18, 0x24242424},394 {0xe1c, 0x24242424}, {0xe28, 0x00000000},395 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},396 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},397 {0xe40, 0x01007c00}, {0xe44, 0x01004800},398 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},399 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},400 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},401 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},402 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},403 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},404 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},405 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},406 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},407 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},408 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},409 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},410 {0xf14, 0x00000003}, {0xf4c, 0x00000000},411 {0xf00, 0x00000300},412 {0xffff, 0xffffffff},413};414 415static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {416 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},417 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},418 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},419 {0xc78, 0x7a060001}, {0xc78, 0x79070001},420 {0xc78, 0x78080001}, {0xc78, 0x77090001},421 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},422 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},423 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},424 {0xc78, 0x70100001}, {0xc78, 0x6f110001},425 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},426 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},427 {0xc78, 0x6a160001}, {0xc78, 0x69170001},428 {0xc78, 0x68180001}, {0xc78, 0x67190001},429 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},430 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},431 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},432 {0xc78, 0x60200001}, {0xc78, 0x49210001},433 {0xc78, 0x48220001}, {0xc78, 0x47230001},434 {0xc78, 0x46240001}, {0xc78, 0x45250001},435 {0xc78, 0x44260001}, {0xc78, 0x43270001},436 {0xc78, 0x42280001}, {0xc78, 0x41290001},437 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},438 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},439 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},440 {0xc78, 0x21300001}, {0xc78, 0x20310001},441 {0xc78, 0x06320001}, {0xc78, 0x05330001},442 {0xc78, 0x04340001}, {0xc78, 0x03350001},443 {0xc78, 0x02360001}, {0xc78, 0x01370001},444 {0xc78, 0x00380001}, {0xc78, 0x00390001},445 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},446 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},447 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},448 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},449 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},450 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},451 {0xc78, 0x7a460001}, {0xc78, 0x79470001},452 {0xc78, 0x78480001}, {0xc78, 0x77490001},453 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},454 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},455 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},456 {0xc78, 0x70500001}, {0xc78, 0x6f510001},457 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},458 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},459 {0xc78, 0x6a560001}, {0xc78, 0x69570001},460 {0xc78, 0x68580001}, {0xc78, 0x67590001},461 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},462 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},463 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},464 {0xc78, 0x60600001}, {0xc78, 0x49610001},465 {0xc78, 0x48620001}, {0xc78, 0x47630001},466 {0xc78, 0x46640001}, {0xc78, 0x45650001},467 {0xc78, 0x44660001}, {0xc78, 0x43670001},468 {0xc78, 0x42680001}, {0xc78, 0x41690001},469 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},470 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},471 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},472 {0xc78, 0x21700001}, {0xc78, 0x20710001},473 {0xc78, 0x06720001}, {0xc78, 0x05730001},474 {0xc78, 0x04740001}, {0xc78, 0x03750001},475 {0xc78, 0x02760001}, {0xc78, 0x01770001},476 {0xc78, 0x00780001}, {0xc78, 0x00790001},477 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},478 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},479 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},480 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},481 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},482 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},483 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},484 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},485 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},486 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},487 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},488 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},489 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},490 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},491 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},492 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},493 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},494 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},495 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},496 {0xffff, 0xffffffff}497};498 499static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {500 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},501 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},502 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},503 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},504 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},505 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},506 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},507 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},508 {0xc78, 0x73100001}, {0xc78, 0x72110001},509 {0xc78, 0x71120001}, {0xc78, 0x70130001},510 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},511 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},512 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},513 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},514 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},515 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},516 {0xc78, 0x63200001}, {0xc78, 0x62210001},517 {0xc78, 0x61220001}, {0xc78, 0x60230001},518 {0xc78, 0x46240001}, {0xc78, 0x45250001},519 {0xc78, 0x44260001}, {0xc78, 0x43270001},520 {0xc78, 0x42280001}, {0xc78, 0x41290001},521 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},522 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},523 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},524 {0xc78, 0x21300001}, {0xc78, 0x20310001},525 {0xc78, 0x06320001}, {0xc78, 0x05330001},526 {0xc78, 0x04340001}, {0xc78, 0x03350001},527 {0xc78, 0x02360001}, {0xc78, 0x01370001},528 {0xc78, 0x00380001}, {0xc78, 0x00390001},529 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},530 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},531 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},532 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},533 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},534 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},535 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},536 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},537 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},538 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},539 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},540 {0xc78, 0x73500001}, {0xc78, 0x72510001},541 {0xc78, 0x71520001}, {0xc78, 0x70530001},542 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},543 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},544 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},545 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},546 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},547 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},548 {0xc78, 0x63600001}, {0xc78, 0x62610001},549 {0xc78, 0x61620001}, {0xc78, 0x60630001},550 {0xc78, 0x46640001}, {0xc78, 0x45650001},551 {0xc78, 0x44660001}, {0xc78, 0x43670001},552 {0xc78, 0x42680001}, {0xc78, 0x41690001},553 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},554 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},555 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},556 {0xc78, 0x21700001}, {0xc78, 0x20710001},557 {0xc78, 0x06720001}, {0xc78, 0x05730001},558 {0xc78, 0x04740001}, {0xc78, 0x03750001},559 {0xc78, 0x02760001}, {0xc78, 0x01770001},560 {0xc78, 0x00780001}, {0xc78, 0x00790001},561 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},562 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},563 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},564 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},565 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},566 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},567 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},568 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},569 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},570 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},571 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},572 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},573 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},574 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},575 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},576 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},577 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},578 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},579 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},580 {0xffff, 0xffffffff}581};582 583static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {584 { /* RF_A */585 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,586 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,587 .lssiparm = REG_FPGA0_XA_LSSI_PARM,588 .hspiread = REG_HSPI_XA_READBACK,589 .lssiread = REG_FPGA0_XA_LSSI_READBACK,590 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,591 },592 { /* RF_B */593 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,594 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,595 .lssiparm = REG_FPGA0_XB_LSSI_PARM,596 .hspiread = REG_HSPI_XB_READBACK,597 .lssiread = REG_FPGA0_XB_LSSI_READBACK,598 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,599 },600};601 602const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {603 REG_OFDM0_XA_RX_IQ_IMBALANCE,604 REG_OFDM0_XB_RX_IQ_IMBALANCE,605 REG_OFDM0_ENERGY_CCA_THRES,606 REG_OFDM0_AGC_RSSI_TABLE,607 REG_OFDM0_XA_TX_IQ_IMBALANCE,608 REG_OFDM0_XB_TX_IQ_IMBALANCE,609 REG_OFDM0_XC_TX_AFE,610 REG_OFDM0_XD_TX_AFE,611 REG_OFDM0_RX_IQ_EXT_ANTA612};613 614u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)615{616 struct usb_device *udev = priv->udev;617 int len;618 u8 data;619 620 if (priv->rtl_chip == RTL8710B && addr <= 0xff)621 addr |= 0x8000;622 623 mutex_lock(&priv->usb_buf_mutex);624 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),625 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,626 addr, 0, &priv->usb_buf.val8, sizeof(u8),627 RTW_USB_CONTROL_MSG_TIMEOUT);628 data = priv->usb_buf.val8;629 mutex_unlock(&priv->usb_buf_mutex);630 631 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)632 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",633 __func__, addr, data, len);634 return data;635}636 637u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)638{639 struct usb_device *udev = priv->udev;640 int len;641 u16 data;642 643 if (priv->rtl_chip == RTL8710B && addr <= 0xff)644 addr |= 0x8000;645 646 mutex_lock(&priv->usb_buf_mutex);647 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),648 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,649 addr, 0, &priv->usb_buf.val16, sizeof(u16),650 RTW_USB_CONTROL_MSG_TIMEOUT);651 data = le16_to_cpu(priv->usb_buf.val16);652 mutex_unlock(&priv->usb_buf_mutex);653 654 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)655 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",656 __func__, addr, data, len);657 return data;658}659 660u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)661{662 struct usb_device *udev = priv->udev;663 int len;664 u32 data;665 666 if (priv->rtl_chip == RTL8710B && addr <= 0xff)667 addr |= 0x8000;668 669 mutex_lock(&priv->usb_buf_mutex);670 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),671 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,672 addr, 0, &priv->usb_buf.val32, sizeof(u32),673 RTW_USB_CONTROL_MSG_TIMEOUT);674 data = le32_to_cpu(priv->usb_buf.val32);675 mutex_unlock(&priv->usb_buf_mutex);676 677 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)678 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",679 __func__, addr, data, len);680 return data;681}682 683int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)684{685 struct usb_device *udev = priv->udev;686 int ret;687 688 if (priv->rtl_chip == RTL8710B && addr <= 0xff)689 addr |= 0x8000;690 691 mutex_lock(&priv->usb_buf_mutex);692 priv->usb_buf.val8 = val;693 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),694 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,695 addr, 0, &priv->usb_buf.val8, sizeof(u8),696 RTW_USB_CONTROL_MSG_TIMEOUT);697 698 mutex_unlock(&priv->usb_buf_mutex);699 700 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)701 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",702 __func__, addr, val);703 return ret;704}705 706int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)707{708 struct usb_device *udev = priv->udev;709 int ret;710 711 if (priv->rtl_chip == RTL8710B && addr <= 0xff)712 addr |= 0x8000;713 714 mutex_lock(&priv->usb_buf_mutex);715 priv->usb_buf.val16 = cpu_to_le16(val);716 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),717 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,718 addr, 0, &priv->usb_buf.val16, sizeof(u16),719 RTW_USB_CONTROL_MSG_TIMEOUT);720 mutex_unlock(&priv->usb_buf_mutex);721 722 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)723 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",724 __func__, addr, val);725 return ret;726}727 728int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)729{730 struct usb_device *udev = priv->udev;731 int ret;732 733 if (priv->rtl_chip == RTL8710B && addr <= 0xff)734 addr |= 0x8000;735 736 mutex_lock(&priv->usb_buf_mutex);737 priv->usb_buf.val32 = cpu_to_le32(val);738 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),739 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,740 addr, 0, &priv->usb_buf.val32, sizeof(u32),741 RTW_USB_CONTROL_MSG_TIMEOUT);742 mutex_unlock(&priv->usb_buf_mutex);743 744 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)745 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",746 __func__, addr, val);747 return ret;748}749 750int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)751{752 u8 val8;753 754 val8 = rtl8xxxu_read8(priv, addr);755 val8 |= bits;756 return rtl8xxxu_write8(priv, addr, val8);757}758 759int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)760{761 u8 val8;762 763 val8 = rtl8xxxu_read8(priv, addr);764 val8 &= ~bits;765 return rtl8xxxu_write8(priv, addr, val8);766}767 768int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)769{770 u16 val16;771 772 val16 = rtl8xxxu_read16(priv, addr);773 val16 |= bits;774 return rtl8xxxu_write16(priv, addr, val16);775}776 777int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)778{779 u16 val16;780 781 val16 = rtl8xxxu_read16(priv, addr);782 val16 &= ~bits;783 return rtl8xxxu_write16(priv, addr, val16);784}785 786int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)787{788 u32 val32;789 790 val32 = rtl8xxxu_read32(priv, addr);791 val32 |= bits;792 return rtl8xxxu_write32(priv, addr, val32);793}794 795int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)796{797 u32 val32;798 799 val32 = rtl8xxxu_read32(priv, addr);800 val32 &= ~bits;801 return rtl8xxxu_write32(priv, addr, val32);802}803 804int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr,805 u32 mask, u32 val)806{807 u32 orig, new, shift;808 809 shift = __ffs(mask);810 811 orig = rtl8xxxu_read32(priv, addr);812 new = (orig & ~mask) | ((val << shift) & mask);813 return rtl8xxxu_write32(priv, addr, new);814}815 816int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv,817 enum rtl8xxxu_rfpath path, u8 reg,818 u32 mask, u32 val)819{820 u32 orig, new, shift;821 822 shift = __ffs(mask);823 824 orig = rtl8xxxu_read_rfreg(priv, path, reg);825 new = (orig & ~mask) | ((val << shift) & mask);826 return rtl8xxxu_write_rfreg(priv, path, reg, new);827}828 829static int830rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)831{832 struct usb_device *udev = priv->udev;833 int blocksize = priv->fops->writeN_block_size;834 int ret, i, count, remainder;835 836 count = len / blocksize;837 remainder = len % blocksize;838 839 for (i = 0; i < count; i++) {840 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),841 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,842 addr, 0, buf, blocksize,843 RTW_USB_CONTROL_MSG_TIMEOUT);844 if (ret != blocksize)845 goto write_error;846 847 addr += blocksize;848 buf += blocksize;849 }850 851 if (remainder) {852 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),853 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,854 addr, 0, buf, remainder,855 RTW_USB_CONTROL_MSG_TIMEOUT);856 if (ret != remainder)857 goto write_error;858 }859 860 return len;861 862write_error:863 dev_info(&udev->dev,864 "%s: Failed to write block at addr: %04x size: %04x\n",865 __func__, addr, blocksize);866 return -EAGAIN;867}868 869u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,870 enum rtl8xxxu_rfpath path, u8 reg)871{872 u32 hssia, val32, retval;873 874 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);875 if (path != RF_A)876 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);877 else878 val32 = hssia;879 880 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;881 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);882 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;883 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;884 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);885 886 udelay(10);887 888 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);889 udelay(100);890 891 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;892 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);893 udelay(10);894 895 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);896 if (val32 & FPGA0_HSSI_PARM1_PI)897 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);898 else899 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);900 901 retval &= 0xfffff;902 903 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)904 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",905 __func__, reg, retval);906 return retval;907}908 909/*910 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can911 * have write issues in high temperature conditions. We may have to912 * retry writing them.913 */914int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,915 enum rtl8xxxu_rfpath path, u8 reg, u32 data)916{917 int ret, retval;918 u32 dataaddr, val32;919 920 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)921 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",922 __func__, reg, data);923 924 data &= FPGA0_LSSI_PARM_DATA_MASK;925 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;926 927 if (priv->rtl_chip == RTL8192E) {928 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);929 val32 &= ~0x20000;930 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);931 }932 933 /* Use XB for path B */934 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);935 if (ret != sizeof(dataaddr))936 retval = -EIO;937 else938 retval = 0;939 940 udelay(1);941 942 if (priv->rtl_chip == RTL8192E) {943 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);944 val32 |= 0x20000;945 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);946 }947 948 return retval;949}950 951static int952rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)953{954 struct device *dev = &priv->udev->dev;955 int mbox_nr, retry, retval = 0;956 int mbox_reg, mbox_ext_reg;957 u8 val8;958 959 mutex_lock(&priv->h2c_mutex);960 961 mbox_nr = priv->next_mbox;962 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);963 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);964 965 /*966 * MBOX ready?967 */968 retry = 100;969 do {970 val8 = rtl8xxxu_read8(priv, REG_HMTFR);971 if (!(val8 & BIT(mbox_nr)))972 break;973 } while (retry--);974 975 if (!retry) {976 dev_info(dev, "%s: Mailbox busy\n", __func__);977 retval = -EBUSY;978 goto error;979 }980 981 /*982 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()983 */984 if (len > sizeof(u32)) {985 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));986 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)987 dev_info(dev, "H2C_EXT %04x\n",988 le16_to_cpu(h2c->raw.ext));989 }990 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));991 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)992 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));993 994 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;995 996error:997 mutex_unlock(&priv->h2c_mutex);998 return retval;999}1000 1001int1002rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)1003{1004 struct device *dev = &priv->udev->dev;1005 int mbox_nr, retry, retval = 0;1006 int mbox_reg, mbox_ext_reg;1007 u8 val8;1008 1009 mutex_lock(&priv->h2c_mutex);1010 1011 mbox_nr = priv->next_mbox;1012 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);1013 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);1014 1015 /*1016 * MBOX ready?1017 */1018 retry = 100;1019 do {1020 val8 = rtl8xxxu_read8(priv, REG_HMTFR);1021 if (!(val8 & BIT(mbox_nr)))1022 break;1023 } while (retry--);1024 1025 if (!retry) {1026 dev_info(dev, "%s: Mailbox busy\n", __func__);1027 retval = -EBUSY;1028 goto error;1029 }1030 1031 /*1032 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()1033 */1034 if (len > sizeof(u32)) {1035 rtl8xxxu_write32(priv, mbox_ext_reg,1036 le32_to_cpu(h2c->raw_wide.ext));1037 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)1038 dev_info(dev, "H2C_EXT %08x\n",1039 le32_to_cpu(h2c->raw_wide.ext));1040 }1041 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));1042 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)1043 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));1044 1045 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;1046 1047error:1048 mutex_unlock(&priv->h2c_mutex);1049 return retval;1050}1051 1052void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)1053{1054 u8 val8;1055 u32 val32;1056 1057 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);1058 val8 |= BIT(0) | BIT(3);1059 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);1060 1061 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);1062 val32 &= ~(BIT(4) | BIT(5));1063 val32 |= BIT(3);1064 if (priv->rf_paths == 2) {1065 val32 &= ~(BIT(20) | BIT(21));1066 val32 |= BIT(19);1067 }1068 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);1069 1070 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);1071 val32 &= ~OFDM_RF_PATH_TX_MASK;1072 if (priv->tx_paths == 2)1073 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;1074 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)1075 val32 |= OFDM_RF_PATH_TX_B;1076 else1077 val32 |= OFDM_RF_PATH_TX_A;1078 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);1079 1080 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);1081 val32 &= ~FPGA_RF_MODE_JAPAN;1082 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);1083 1084 if (priv->rf_paths == 2)1085 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);1086 else1087 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);1088 1089 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);1090 if (priv->rf_paths == 2)1091 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);1092 1093 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);1094}1095 1096void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)1097{1098 u8 sps0;1099 u32 val32;1100 1101 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);1102 1103 /* RF RX code for preamble power saving */1104 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);1105 val32 &= ~(BIT(3) | BIT(4) | BIT(5));1106 if (priv->rf_paths == 2)1107 val32 &= ~(BIT(19) | BIT(20) | BIT(21));1108 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);1109 1110 /* Disable TX for four paths */1111 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);1112 val32 &= ~OFDM_RF_PATH_TX_MASK;1113 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);1114 1115 /* Enable power saving */1116 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);1117 val32 |= FPGA_RF_MODE_JAPAN;1118 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);1119 1120 /* AFE control register to power down bits [30:22] */1121 if (priv->rf_paths == 2)1122 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);1123 else1124 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);1125 1126 /* Power down RF module */1127 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);1128 if (priv->rf_paths == 2)1129 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);1130 1131 sps0 &= ~(BIT(0) | BIT(3));1132 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);1133}1134 1135static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)1136{1137 u8 val8;1138 1139 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);1140 val8 &= ~BIT(6);1141 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);1142 1143 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);1144 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);1145 val8 &= ~BIT(0);1146 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);1147}1148 1149static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv)1150{1151 u8 val8;1152 1153 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);1154 val8 |= EN_BCNQ_DL >> 16;1155 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);1156 1157 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80);1158 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);1159 val8 &= 0xF0;1160 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);1161}1162 1163 1164/*1165 * The rtl8723a has 3 channel groups for it's efuse settings. It only1166 * supports the 2.4GHz band, so channels 1 - 14:1167 * group 0: channels 1 - 31168 * group 1: channels 4 - 91169 * group 2: channels 10 - 141170 *1171 * Note: We index from 0 in the code1172 */1173static int rtl8xxxu_gen1_channel_to_group(int channel)1174{1175 int group;1176 1177 if (channel < 4)1178 group = 0;1179 else if (channel < 10)1180 group = 1;1181 else1182 group = 2;1183 1184 return group;1185}1186 1187/*1188 * Valid for rtl8723bu and rtl8192eu1189 */1190int rtl8xxxu_gen2_channel_to_group(int channel)1191{1192 int group;1193 1194 if (channel < 3)1195 group = 0;1196 else if (channel < 6)1197 group = 1;1198 else if (channel < 9)1199 group = 2;1200 else if (channel < 12)1201 group = 3;1202 else1203 group = 4;1204 1205 return group;1206}1207 1208void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)1209{1210 struct rtl8xxxu_priv *priv = hw->priv;1211 u32 val32, rsr;1212 u8 val8, opmode;1213 bool ht = true;1214 int sec_ch_above, channel;1215 int i;1216 1217 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);1218 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);1219 channel = hw->conf.chandef.chan->hw_value;1220 1221 switch (hw->conf.chandef.width) {1222 case NL80211_CHAN_WIDTH_20_NOHT:1223 ht = false;1224 fallthrough;1225 case NL80211_CHAN_WIDTH_20:1226 opmode |= BW_OPMODE_20MHZ;1227 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);1228 1229 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);1230 val32 &= ~FPGA_RF_MODE;1231 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);1232 1233 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);1234 val32 &= ~FPGA_RF_MODE;1235 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);1236 1237 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);1238 val32 |= FPGA0_ANALOG2_20MHZ;1239 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);1240 break;1241 case NL80211_CHAN_WIDTH_40:1242 if (hw->conf.chandef.center_freq1 >1243 hw->conf.chandef.chan->center_freq) {1244 sec_ch_above = 1;1245 channel += 2;1246 } else {1247 sec_ch_above = 0;1248 channel -= 2;1249 }1250 1251 opmode &= ~BW_OPMODE_20MHZ;1252 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);1253 rsr &= ~RSR_RSC_BANDWIDTH_40M;1254 if (sec_ch_above)1255 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;1256 else1257 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;1258 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);1259 1260 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);1261 val32 |= FPGA_RF_MODE;1262 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);1263 1264 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);1265 val32 |= FPGA_RF_MODE;1266 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);1267 1268 /*1269 * Set Control channel to upper or lower. These settings1270 * are required only for 40MHz1271 */1272 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);1273 val32 &= ~CCK0_SIDEBAND;1274 if (!sec_ch_above)1275 val32 |= CCK0_SIDEBAND;1276 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);1277 1278 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);1279 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */1280 if (sec_ch_above)1281 val32 |= OFDM_LSTF_PRIME_CH_LOW;1282 else1283 val32 |= OFDM_LSTF_PRIME_CH_HIGH;1284 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);1285 1286 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);1287 val32 &= ~FPGA0_ANALOG2_20MHZ;1288 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);1289 1290 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);1291 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);1292 if (sec_ch_above)1293 val32 |= FPGA0_PS_UPPER_CHANNEL;1294 else1295 val32 |= FPGA0_PS_LOWER_CHANNEL;1296 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);1297 break;1298 1299 default:1300 break;1301 }1302 1303 for (i = RF_A; i < priv->rf_paths; i++) {1304 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);1305 val32 &= ~MODE_AG_CHANNEL_MASK;1306 val32 |= channel;1307 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);1308 }1309 1310 if (ht)1311 val8 = 0x0e;1312 else1313 val8 = 0x0a;1314 1315 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);1316 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);1317 1318 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);1319 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);1320 1321 for (i = RF_A; i < priv->rf_paths; i++) {1322 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);1323 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)1324 val32 &= ~MODE_AG_CHANNEL_20MHZ;1325 else1326 val32 |= MODE_AG_CHANNEL_20MHZ;1327 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);1328 }1329}1330 1331void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)1332{1333 struct rtl8xxxu_priv *priv = hw->priv;1334 u32 val32;1335 u8 val8, subchannel;1336 u16 rf_mode_bw;1337 bool ht = true;1338 int sec_ch_above, channel;1339 int i;1340 1341 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);1342 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;1343 channel = hw->conf.chandef.chan->hw_value;1344 1345/* Hack */1346 subchannel = 0;1347 1348 switch (hw->conf.chandef.width) {1349 case NL80211_CHAN_WIDTH_20_NOHT:1350 ht = false;1351 fallthrough;1352 case NL80211_CHAN_WIDTH_20:1353 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;1354 subchannel = 0;1355 1356 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);1357 val32 &= ~FPGA_RF_MODE;1358 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);1359 1360 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);1361 val32 &= ~FPGA_RF_MODE;1362 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);1363 1364 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);1365 val32 &= ~(BIT(30) | BIT(31));1366 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);1367 1368 break;1369 case NL80211_CHAN_WIDTH_40:1370 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;1371 1372 if (hw->conf.chandef.center_freq1 >1373 hw->conf.chandef.chan->center_freq) {1374 sec_ch_above = 1;1375 channel += 2;1376 } else {1377 sec_ch_above = 0;1378 channel -= 2;1379 }1380 1381 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);1382 val32 |= FPGA_RF_MODE;1383 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);1384 1385 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);1386 val32 |= FPGA_RF_MODE;1387 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);1388 1389 /*1390 * Set Control channel to upper or lower. These settings1391 * are required only for 40MHz1392 */1393 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);1394 val32 &= ~CCK0_SIDEBAND;1395 if (!sec_ch_above)1396 val32 |= CCK0_SIDEBAND;1397 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);1398 1399 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);1400 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */1401 if (sec_ch_above)1402 val32 |= OFDM_LSTF_PRIME_CH_LOW;1403 else1404 val32 |= OFDM_LSTF_PRIME_CH_HIGH;1405 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);1406 1407 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);1408 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);1409 if (sec_ch_above)1410 val32 |= FPGA0_PS_UPPER_CHANNEL;1411 else1412 val32 |= FPGA0_PS_LOWER_CHANNEL;1413 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);1414 break;1415 case NL80211_CHAN_WIDTH_80:1416 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;1417 break;1418 default:1419 break;1420 }1421 1422 for (i = RF_A; i < priv->rf_paths; i++) {1423 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);1424 val32 &= ~MODE_AG_CHANNEL_MASK;1425 val32 |= channel;1426 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);1427 }1428 1429 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);1430 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);1431 1432 if (ht)1433 val8 = 0x0e;1434 else1435 val8 = 0x0a;1436 1437 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);1438 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);1439 1440 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);1441 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);1442 1443 for (i = RF_A; i < priv->rf_paths; i++) {1444 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);1445 val32 &= ~MODE_AG_BW_MASK;1446 switch(hw->conf.chandef.width) {1447 case NL80211_CHAN_WIDTH_80:1448 val32 |= MODE_AG_BW_80MHZ_8723B;1449 break;1450 case NL80211_CHAN_WIDTH_40:1451 val32 |= MODE_AG_BW_40MHZ_8723B;1452 break;1453 default:1454 val32 |= MODE_AG_BW_20MHZ_8723B;1455 break;1456 }1457 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);1458 }1459}1460 1461void1462rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)1463{1464 struct rtl8xxxu_power_base *power_base = priv->power_base;1465 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];1466 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];1467 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;1468 u8 val8, base;1469 int group, i;1470 1471 group = rtl8xxxu_gen1_channel_to_group(channel);1472 1473 cck[0] = priv->cck_tx_power_index_A[group];1474 cck[1] = priv->cck_tx_power_index_B[group];1475 1476 if (priv->hi_pa) {1477 if (cck[0] > 0x20)1478 cck[0] = 0x20;1479 if (cck[1] > 0x20)1480 cck[1] = 0x20;1481 }1482 1483 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];1484 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];1485 1486 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;1487 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;1488 1489 mcsbase[0] = ofdm[0];1490 mcsbase[1] = ofdm[1];1491 if (!ht40) {1492 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;1493 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;1494 }1495 1496 if (priv->tx_paths > 1) {1497 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)1498 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;1499 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)1500 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;1501 }1502 1503 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)1504 dev_info(&priv->udev->dev,1505 "%s: Setting TX power CCK A: %02x, "1506 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",1507 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);1508 1509 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {1510 if (cck[i] > RF6052_MAX_TX_PWR)1511 cck[i] = RF6052_MAX_TX_PWR;1512 if (ofdm[i] > RF6052_MAX_TX_PWR)1513 ofdm[i] = RF6052_MAX_TX_PWR;1514 }1515 1516 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);1517 val32 &= 0xffff00ff;1518 val32 |= (cck[0] << 8);1519 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);1520 1521 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);1522 val32 &= 0xff;1523 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));1524 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);1525 1526 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);1527 val32 &= 0xffffff00;1528 val32 |= cck[1];1529 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);1530 1531 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);1532 val32 &= 0xff;1533 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));1534 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);1535 1536 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |1537 ofdmbase[0] << 16 | ofdmbase[0] << 24;1538 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |1539 ofdmbase[1] << 16 | ofdmbase[1] << 24;1540 1541 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,1542 ofdm_a + power_base->reg_0e00);1543 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,1544 ofdm_b + power_base->reg_0830);1545 1546 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,1547 ofdm_a + power_base->reg_0e04);1548 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,1549 ofdm_b + power_base->reg_0834);1550 1551 mcs_a = mcsbase[0] | mcsbase[0] << 8 |1552 mcsbase[0] << 16 | mcsbase[0] << 24;1553 mcs_b = mcsbase[1] | mcsbase[1] << 8 |1554 mcsbase[1] << 16 | mcsbase[1] << 24;1555 1556 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,1557 mcs_a + power_base->reg_0e10);1558 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,1559 mcs_b + power_base->reg_083c);1560 1561 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,1562 mcs_a + power_base->reg_0e14);1563 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,1564 mcs_b + power_base->reg_0848);1565 1566 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,1567 mcs_a + power_base->reg_0e18);1568 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,1569 mcs_b + power_base->reg_084c);1570 1571 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,1572 mcs_a + power_base->reg_0e1c);1573 val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000);1574 for (i = 0; i < 3; i++) {1575 base = i != 2 ? 8 : 6;1576 val8 = max_t(int, val8 - base, 0);1577 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);1578 }1579 1580 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,1581 mcs_b + power_base->reg_0868);1582 val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000);1583 for (i = 0; i < 3; i++) {1584 base = i != 2 ? 8 : 6;1585 val8 = max_t(int, val8 - base, 0);1586 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);1587 }1588}1589 1590static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,1591 enum nl80211_iftype linktype, int port_num)1592{1593 u8 val8, type;1594 1595 switch (linktype) {1596 case NL80211_IFTYPE_UNSPECIFIED:1597 type = MSR_LINKTYPE_NONE;1598 break;1599 case NL80211_IFTYPE_ADHOC:1600 type = MSR_LINKTYPE_ADHOC;1601 break;1602 case NL80211_IFTYPE_STATION:1603 type = MSR_LINKTYPE_STATION;1604 break;1605 case NL80211_IFTYPE_AP:1606 type = MSR_LINKTYPE_AP;1607 break;1608 default:1609 return;1610 }1611 1612 switch (port_num) {1613 case 0:1614 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x0c;1615 val8 |= type;1616 break;1617 case 1:1618 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x03;1619 val8 |= type << 2;1620 break;1621 default:1622 return;1623 }1624 1625 rtl8xxxu_write8(priv, REG_MSR, val8);1626}1627 1628static void1629rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)1630{1631 u16 val16;1632 1633 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &1634 RETRY_LIMIT_SHORT_MASK) |1635 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &1636 RETRY_LIMIT_LONG_MASK);1637 1638 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);1639}1640 1641static void1642rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)1643{1644 u16 val16;1645 1646 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |1647 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);1648 1649 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);1650}1651 1652static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)1653{1654 struct device *dev = &priv->udev->dev;1655 char cut = 'A' + priv->chip_cut;1656 1657 dev_info(dev,1658 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",1659 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev,1660 priv->tx_paths, priv->rx_paths, priv->ep_tx_count,1661 priv->has_wifi, priv->has_bluetooth, priv->has_gps,1662 priv->hi_pa);1663 1664 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);1665}1666 1667void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor)1668{1669 if (vendor) {1670 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));1671 priv->vendor_umc = 1;1672 } else {1673 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));1674 }1675}1676 1677void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor)1678{1679 switch (vendor) {1680 case SYS_CFG_VENDOR_ID_TSMC:1681 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));1682 break;1683 case SYS_CFG_VENDOR_ID_SMIC:1684 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor));1685 priv->vendor_smic = 1;1686 break;1687 case SYS_CFG_VENDOR_ID_UMC:1688 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));1689 priv->vendor_umc = 1;1690 break;1691 default:1692 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor));1693 }1694}1695 1696void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv)1697{1698 u16 val16;1699 1700 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);1701 1702 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {1703 priv->ep_tx_high_queue = 1;1704 priv->ep_tx_count++;1705 }1706 1707 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {1708 priv->ep_tx_normal_queue = 1;1709 priv->ep_tx_count++;1710 }1711 1712 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {1713 priv->ep_tx_low_queue = 1;1714 priv->ep_tx_count++;1715 }1716}1717 1718int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv)1719{1720 struct device *dev = &priv->udev->dev;1721 1722 switch (priv->nr_out_eps) {1723 case 6:1724 case 5:1725 case 4:1726 case 3:1727 priv->ep_tx_low_queue = 1;1728 priv->ep_tx_count++;1729 fallthrough;1730 case 2:1731 priv->ep_tx_normal_queue = 1;1732 priv->ep_tx_count++;1733 fallthrough;1734 case 1:1735 priv->ep_tx_high_queue = 1;1736 priv->ep_tx_count++;1737 break;1738 default:1739 dev_info(dev, "Unsupported USB TX end-points\n");1740 return -ENOTSUPP;1741 }1742 1743 return 0;1744}1745 1746int1747rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)1748{1749 int i;1750 u8 val8;1751 u32 val32;1752 1753 /* Write Address */1754 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);1755 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);1756 val8 &= 0xfc;1757 val8 |= (offset >> 8) & 0x03;1758 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);1759 1760 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);1761 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);1762 1763 /* Poll for data read */1764 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);1765 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {1766 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);1767 if (val32 & BIT(31))1768 break;1769 }1770 1771 if (i == RTL8XXXU_MAX_REG_POLL)1772 return -EIO;1773 1774 udelay(50);1775 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);1776 1777 *data = val32 & 0xff;1778 return 0;1779}1780 1781int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)1782{1783 struct device *dev = &priv->udev->dev;1784 int i, ret = 0;1785 u8 val8, word_mask, header, extheader;1786 u16 val16, efuse_addr, offset;1787 u32 val32;1788 1789 val16 = rtl8xxxu_read16(priv, REG_9346CR);1790 if (val16 & EEPROM_ENABLE)1791 priv->has_eeprom = 1;1792 if (val16 & EEPROM_BOOT)1793 priv->boot_eeprom = 1;1794 1795 if (priv->is_multi_func) {1796 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);1797 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;1798 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);1799 }1800 1801 dev_dbg(dev, "Booting from %s\n",1802 priv->boot_eeprom ? "EEPROM" : "EFUSE");1803 1804 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);1805 1806 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */1807 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);1808 if (!(val16 & SYS_ISO_PWC_EV12V)) {1809 val16 |= SYS_ISO_PWC_EV12V;1810 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);1811 }1812 /* Reset: 0x0000[28], default valid */1813 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);1814 if (!(val16 & SYS_FUNC_ELDR)) {1815 val16 |= SYS_FUNC_ELDR;1816 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);1817 }1818 1819 /*1820 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid1821 */1822 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);1823 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {1824 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);1825 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);1826 }1827 1828 /* Default value is 0xff */1829 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);1830 1831 efuse_addr = 0;1832 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {1833 u16 map_addr;1834 1835 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);1836 if (ret || header == 0xff)1837 goto exit;1838 1839 if ((header & 0x1f) == 0x0f) { /* extended header */1840 offset = (header & 0xe0) >> 5;1841 1842 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,1843 &extheader);1844 if (ret)1845 goto exit;1846 /* All words disabled */1847 if ((extheader & 0x0f) == 0x0f)1848 continue;1849 1850 offset |= ((extheader & 0xf0) >> 1);1851 word_mask = extheader & 0x0f;1852 } else {1853 offset = (header >> 4) & 0x0f;1854 word_mask = header & 0x0f;1855 }1856 1857 /* Get word enable value from PG header */1858 1859 /* We have 8 bits to indicate validity */1860 map_addr = offset * 8;1861 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {1862 /* Check word enable condition in the section */1863 if (word_mask & BIT(i)) {1864 map_addr += 2;1865 continue;1866 }1867 1868 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);1869 if (ret)1870 goto exit;1871 if (map_addr >= EFUSE_MAP_LEN - 1) {1872 dev_warn(dev, "%s: Illegal map_addr (%04x), "1873 "efuse corrupt!\n",1874 __func__, map_addr);1875 ret = -EINVAL;1876 goto exit;1877 }1878 priv->efuse_wifi.raw[map_addr++] = val8;1879 1880 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);1881 if (ret)1882 goto exit;1883 priv->efuse_wifi.raw[map_addr++] = val8;1884 }1885 }1886 1887exit:1888 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);1889 1890 return ret;1891}1892 1893static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv)1894{1895 dev_info(&priv->udev->dev,1896 "Dumping efuse for RTL%s (0x%02x bytes):\n",1897 priv->chip_name, EFUSE_MAP_LEN);1898 1899 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,1900 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true);1901}1902 1903void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)1904{1905 u8 val8;1906 u16 sys_func;1907 1908 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);1909 val8 &= ~BIT(0);1910 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);1911 1912 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);1913 sys_func &= ~SYS_FUNC_CPU_ENABLE;1914 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);1915 1916 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);1917 val8 |= BIT(0);1918 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);1919 1920 sys_func |= SYS_FUNC_CPU_ENABLE;1921 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);1922}1923 1924static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)1925{1926 struct device *dev = &priv->udev->dev;1927 u16 reg_mcu_fw_dl;1928 int ret = 0, i;1929 u32 val32;1930 1931 if (priv->rtl_chip == RTL8710B)1932 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;1933 else1934 reg_mcu_fw_dl = REG_MCU_FW_DL;1935 1936 /* Poll checksum report */1937 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {1938 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);1939 if (val32 & MCU_FW_DL_CSUM_REPORT)1940 break;1941 }1942 1943 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {1944 dev_warn(dev, "Firmware checksum poll timed out\n");1945 ret = -EAGAIN;1946 goto exit;1947 }1948 1949 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);1950 val32 |= MCU_FW_DL_READY;1951 val32 &= ~MCU_WINT_INIT_READY;1952 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);1953 1954 /*1955 * Reset the 8051 in order for the firmware to start running,1956 * otherwise it won't come up on the 8192eu1957 */1958 priv->fops->reset_8051(priv);1959 1960 /* Wait for firmware to become ready */1961 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {1962 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);1963 if (val32 & MCU_WINT_INIT_READY)1964 break;1965 1966 udelay(100);1967 }1968 1969 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {1970 dev_warn(dev, "Firmware failed to start\n");1971 ret = -EAGAIN;1972 goto exit;1973 }1974 1975 /*1976 * Init H2C command1977 */1978 if (priv->fops->init_reg_hmtfr)1979 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);1980exit:1981 return ret;1982}1983 1984static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)1985{1986 int pages, remainder, i, ret;1987 u16 reg_fw_start_address;1988 u16 reg_mcu_fw_dl;1989 u8 val8;1990 u16 val16;1991 u32 val32;1992 u8 *fwptr;1993 1994 if (priv->rtl_chip == RTL8192F)1995 reg_fw_start_address = REG_FW_START_ADDRESS_8192F;1996 else1997 reg_fw_start_address = REG_FW_START_ADDRESS;1998 1999 if (priv->rtl_chip == RTL8710B) {2000 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;2001 } else {2002 reg_mcu_fw_dl = REG_MCU_FW_DL;2003 2004 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);2005 val8 |= 4;2006 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);2007 2008 /* 8051 enable */2009 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);2010 val16 |= SYS_FUNC_CPU_ENABLE;2011 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);2012 }2013 2014 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);2015 if (val8 & MCU_FW_RAM_SEL) {2016 dev_info(&priv->udev->dev,2017 "Firmware is already running, resetting the MCU.\n");2018 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00);2019 priv->fops->reset_8051(priv);2020 }2021 2022 /* MCU firmware download enable */2023 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);2024 val8 |= MCU_FW_DL_ENABLE;2025 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);2026 2027 /* 8051 reset */2028 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);2029 val32 &= ~BIT(19);2030 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);2031 2032 if (priv->rtl_chip == RTL8710B) {2033 /* We must set 0x8090[8]=1 before download FW. */2034 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1);2035 val8 |= BIT(0);2036 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8);2037 }2038 2039 /* Reset firmware download checksum */2040 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);2041 val8 |= MCU_FW_DL_CSUM_REPORT;2042 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);2043 2044 pages = priv->fw_size / RTL_FW_PAGE_SIZE;2045 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;2046 2047 fwptr = priv->fw_data->data;2048 2049 for (i = 0; i < pages; i++) {2050 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;2051 val8 |= i;2052 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);2053 2054 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,2055 fwptr, RTL_FW_PAGE_SIZE);2056 if (ret != RTL_FW_PAGE_SIZE) {2057 ret = -EAGAIN;2058 goto fw_abort;2059 }2060 2061 fwptr += RTL_FW_PAGE_SIZE;2062 }2063 2064 if (remainder) {2065 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;2066 val8 |= i;2067 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);2068 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,2069 fwptr, remainder);2070 if (ret != remainder) {2071 ret = -EAGAIN;2072 goto fw_abort;2073 }2074 }2075 2076 ret = 0;2077fw_abort:2078 /* MCU firmware download disable */2079 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl);2080 val16 &= ~MCU_FW_DL_ENABLE;2081 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16);2082 2083 return ret;2084}2085 2086int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name)2087{2088 struct device *dev = &priv->udev->dev;2089 const struct firmware *fw;2090 int ret = 0;2091 u16 signature;2092 2093 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);2094 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {2095 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);2096 ret = -EAGAIN;2097 goto exit;2098 }2099 if (!fw) {2100 dev_warn(dev, "Firmware data not available\n");2101 ret = -EINVAL;2102 goto exit;2103 }2104 2105 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);2106 if (!priv->fw_data) {2107 ret = -ENOMEM;2108 goto exit;2109 }2110 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);2111 2112 signature = le16_to_cpu(priv->fw_data->signature);2113 switch (signature & 0xfff0) {2114 case 0x92e0:2115 case 0x92c0:2116 case 0x88e0:2117 case 0x88c0:2118 case 0x5300:2119 case 0x2300:2120 case 0x88f0:2121 case 0x10b0:2122 case 0x92f0:2123 break;2124 default:2125 ret = -EINVAL;2126 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",2127 __func__, signature);2128 }2129 2130 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",2131 le16_to_cpu(priv->fw_data->major_version),2132 priv->fw_data->minor_version, signature);2133 2134exit:2135 release_firmware(fw);2136 return ret;2137}2138 2139void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)2140{2141 u16 val16;2142 int i = 100;2143 2144 /* Inform 8051 to perform reset */2145 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);2146 2147 for (i = 100; i > 0; i--) {2148 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);2149 2150 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {2151 dev_dbg(&priv->udev->dev,2152 "%s: Firmware self reset success!\n", __func__);2153 break;2154 }2155 udelay(50);2156 }2157 2158 if (!i) {2159 /* Force firmware reset */2160 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);2161 val16 &= ~SYS_FUNC_CPU_ENABLE;2162 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);2163 }2164}2165 2166static int2167rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)2168{2169 const struct rtl8xxxu_reg8val *array = priv->fops->mactable;2170 int i, ret;2171 u16 reg;2172 u8 val;2173 2174 for (i = 0; ; i++) {2175 reg = array[i].reg;2176 val = array[i].val;2177 2178 if (reg == 0xffff && val == 0xff)2179 break;2180 2181 ret = rtl8xxxu_write8(priv, reg, val);2182 if (ret != 1) {2183 dev_warn(&priv->udev->dev,2184 "Failed to initialize MAC "2185 "(reg: %04x, val %02x)\n", reg, val);2186 return -EAGAIN;2187 }2188 }2189 2190 switch (priv->rtl_chip) {2191 case RTL8188C:2192 case RTL8188R:2193 case RTL8191C:2194 case RTL8192C:2195 case RTL8723A:2196 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);2197 break;2198 case RTL8188E:2199 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707);2200 break;2201 default:2202 break;2203 }2204 2205 return 0;2206}2207 2208int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,2209 const struct rtl8xxxu_reg32val *array)2210{2211 int i, ret;2212 u16 reg;2213 u32 val;2214 2215 for (i = 0; ; i++) {2216 reg = array[i].reg;2217 val = array[i].val;2218 2219 if (reg == 0xffff && val == 0xffffffff)2220 break;2221 2222 ret = rtl8xxxu_write32(priv, reg, val);2223 if (ret != sizeof(val)) {2224 dev_warn(&priv->udev->dev,2225 "Failed to initialize PHY\n");2226 return -EAGAIN;2227 }2228 udelay(1);2229 }2230 2231 return 0;2232}2233 2234void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)2235{2236 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;2237 u16 val16;2238 u32 val32;2239 2240 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);2241 udelay(2);2242 val8 |= AFE_PLL_320_ENABLE;2243 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);2244 udelay(2);2245 2246 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);2247 udelay(2);2248 2249 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);2250 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;2251 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);2252 2253 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);2254 val32 &= ~AFE_XTAL_RF_GATE;2255 if (priv->has_bluetooth)2256 val32 &= ~AFE_XTAL_BT_GATE;2257 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);2258 2259 /* 6. 0x1f[7:0] = 0x07 */2260 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;2261 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);2262 2263 if (priv->hi_pa)2264 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);2265 else if (priv->tx_paths == 2)2266 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);2267 else2268 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);2269 2270 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&2271 priv->vendor_umc && priv->chip_cut == 1)2272 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);2273 2274 if (priv->hi_pa)2275 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);2276 else2277 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);2278 2279 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;2280 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);2281 ldohci12 = 0x57;2282 lpldo = 1;2283 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;2284 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);2285}2286 2287/*2288 * Most of this is black magic retrieved from the old rtl8723au driver2289 */2290static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)2291{2292 u32 val32;2293 2294 priv->fops->init_phy_bb(priv);2295 2296 if (priv->tx_paths == 1 && priv->rx_paths == 2) {2297 /*2298 * For 1T2R boards, patch the registers.2299 *2300 * It looks like 8191/2 1T2R boards use path B for TX2301 */2302 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);2303 val32 &= ~(BIT(0) | BIT(1));2304 val32 |= BIT(1);2305 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);2306 2307 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);2308 val32 &= ~0x300033;2309 val32 |= 0x200022;2310 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);2311 2312 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);2313 val32 &= ~CCK0_AFE_RX_MASK;2314 val32 &= 0x00ffffff;2315 val32 |= 0x40000000;2316 val32 |= CCK0_AFE_RX_ANT_B;2317 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);2318 2319 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);2320 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);2321 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |2322 OFDM_RF_PATH_TX_B);2323 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);2324 2325 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);2326 val32 &= ~(BIT(4) | BIT(5));2327 val32 |= BIT(4);2328 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);2329 2330 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);2331 val32 &= ~(BIT(27) | BIT(26));2332 val32 |= BIT(27);2333 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);2334 2335 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);2336 val32 &= ~(BIT(27) | BIT(26));2337 val32 |= BIT(27);2338 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);2339 2340 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);2341 val32 &= ~(BIT(27) | BIT(26));2342 val32 |= BIT(27);2343 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);2344 2345 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);2346 val32 &= ~(BIT(27) | BIT(26));2347 val32 |= BIT(27);2348 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);2349 2350 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);2351 val32 &= ~(BIT(27) | BIT(26));2352 val32 |= BIT(27);2353 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);2354 }2355 2356 if (priv->fops->set_crystal_cap)2357 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap);2358 2359 if (priv->rtl_chip == RTL8192E)2360 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);2361 2362 return 0;2363}2364 2365static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,2366 const struct rtl8xxxu_rfregval *array,2367 enum rtl8xxxu_rfpath path)2368{2369 int i, ret;2370 u8 reg;2371 u32 val;2372 2373 for (i = 0; ; i++) {2374 reg = array[i].reg;2375 val = array[i].val;2376 2377 if (reg == 0xff && val == 0xffffffff)2378 break;2379 2380 switch (reg) {2381 case 0xfe:2382 msleep(50);2383 continue;2384 case 0xfd:2385 mdelay(5);2386 continue;2387 case 0xfc:2388 mdelay(1);2389 continue;2390 case 0xfb:2391 udelay(50);2392 continue;2393 case 0xfa:2394 udelay(5);2395 continue;2396 case 0xf9:2397 udelay(1);2398 continue;2399 }2400 2401 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);2402 if (ret) {2403 dev_warn(&priv->udev->dev,2404 "Failed to initialize RF\n");2405 return -EAGAIN;2406 }2407 udelay(1);2408 }2409 2410 return 0;2411}2412 2413int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,2414 const struct rtl8xxxu_rfregval *table,2415 enum rtl8xxxu_rfpath path)2416{2417 u32 val32;2418 u16 val16, rfsi_rfenv;2419 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;2420 2421 switch (path) {2422 case RF_A:2423 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;2424 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;2425 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;2426 break;2427 case RF_B:2428 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;2429 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;2430 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;2431 break;2432 default:2433 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",2434 __func__, path + 'A');2435 return -EINVAL;2436 }2437 /* For path B, use XB */2438 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);2439 rfsi_rfenv &= FPGA0_RF_RFENV;2440 2441 /*2442 * These two we might be able to optimize into one2443 */2444 val32 = rtl8xxxu_read32(priv, reg_int_oe);2445 val32 |= BIT(20); /* 0x10 << 16 */2446 rtl8xxxu_write32(priv, reg_int_oe, val32);2447 udelay(1);2448 2449 val32 = rtl8xxxu_read32(priv, reg_int_oe);2450 val32 |= BIT(4);2451 rtl8xxxu_write32(priv, reg_int_oe, val32);2452 udelay(1);2453 2454 /*2455 * These two we might be able to optimize into one2456 */2457 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);2458 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;2459 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);2460 udelay(1);2461 2462 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);2463 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;2464 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);2465 udelay(1);2466 2467 rtl8xxxu_init_rf_regs(priv, table, path);2468 2469 /* For path B, use XB */2470 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);2471 val16 &= ~FPGA0_RF_RFENV;2472 val16 |= rfsi_rfenv;2473 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);2474 2475 return 0;2476}2477 2478static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)2479{2480 int ret = -EBUSY;2481 int count = 0;2482 u32 value;2483 2484 value = LLT_OP_WRITE | address << 8 | data;2485 2486 rtl8xxxu_write32(priv, REG_LLT_INIT, value);2487 2488 do {2489 value = rtl8xxxu_read32(priv, REG_LLT_INIT);2490 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {2491 ret = 0;2492 break;2493 }2494 } while (count++ < 20);2495 2496 return ret;2497}2498 2499int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)2500{2501 int ret;2502 int i, last_entry;2503 u8 last_tx_page;2504 2505 last_tx_page = priv->fops->total_page_num;2506 2507 if (priv->fops->last_llt_entry)2508 last_entry = priv->fops->last_llt_entry;2509 else2510 last_entry = 255;2511 2512 for (i = 0; i < last_tx_page; i++) {2513 ret = rtl8xxxu_llt_write(priv, i, i + 1);2514 if (ret)2515 goto exit;2516 }2517 2518 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);2519 if (ret)2520 goto exit;2521 2522 /* Mark remaining pages as a ring buffer */2523 for (i = last_tx_page + 1; i < last_entry; i++) {2524 ret = rtl8xxxu_llt_write(priv, i, (i + 1));2525 if (ret)2526 goto exit;2527 }2528 2529 /* Let last entry point to the start entry of ring buffer */2530 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1);2531 if (ret)2532 goto exit;2533 2534exit:2535 return ret;2536}2537 2538int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)2539{2540 u32 val32;2541 int ret = 0;2542 int i;2543 2544 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);2545 val32 |= AUTO_LLT_INIT_LLT;2546 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);2547 2548 for (i = 500; i; i--) {2549 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);2550 if (!(val32 & AUTO_LLT_INIT_LLT))2551 break;2552 usleep_range(2, 4);2553 }2554 2555 if (!i) {2556 ret = -EBUSY;2557 dev_warn(&priv->udev->dev, "LLT table init failed\n");2558 }2559 2560 return ret;2561}2562 2563static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)2564{2565 u16 val16, hi, lo;2566 u16 hiq, mgq, bkq, beq, viq, voq;2567 int hip, mgp, bkp, bep, vip, vop;2568 int ret = 0;2569 u32 val32;2570 2571 switch (priv->ep_tx_count) {2572 case 1:2573 if (priv->ep_tx_high_queue) {2574 hi = TRXDMA_QUEUE_HIGH;2575 } else if (priv->ep_tx_low_queue) {2576 hi = TRXDMA_QUEUE_LOW;2577 } else if (priv->ep_tx_normal_queue) {2578 hi = TRXDMA_QUEUE_NORMAL;2579 } else {2580 hi = 0;2581 ret = -EINVAL;2582 }2583 2584 hiq = hi;2585 mgq = hi;2586 bkq = hi;2587 beq = hi;2588 viq = hi;2589 voq = hi;2590 2591 hip = 0;2592 mgp = 0;2593 bkp = 0;2594 bep = 0;2595 vip = 0;2596 vop = 0;2597 break;2598 case 2:2599 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {2600 hi = TRXDMA_QUEUE_HIGH;2601 lo = TRXDMA_QUEUE_LOW;2602 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {2603 hi = TRXDMA_QUEUE_NORMAL;2604 lo = TRXDMA_QUEUE_LOW;2605 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {2606 hi = TRXDMA_QUEUE_HIGH;2607 lo = TRXDMA_QUEUE_NORMAL;2608 } else {2609 ret = -EINVAL;2610 hi = 0;2611 lo = 0;2612 }2613 2614 hiq = hi;2615 mgq = hi;2616 bkq = lo;2617 beq = lo;2618 viq = hi;2619 voq = hi;2620 2621 hip = 0;2622 mgp = 0;2623 bkp = 1;2624 bep = 1;2625 vip = 0;2626 vop = 0;2627 break;2628 case 3:2629 beq = TRXDMA_QUEUE_LOW;2630 bkq = TRXDMA_QUEUE_LOW;2631 viq = TRXDMA_QUEUE_NORMAL;2632 voq = TRXDMA_QUEUE_HIGH;2633 mgq = TRXDMA_QUEUE_HIGH;2634 hiq = TRXDMA_QUEUE_HIGH;2635 2636 hip = hiq ^ 3;2637 mgp = mgq ^ 3;2638 bkp = bkq ^ 3;2639 bep = beq ^ 3;2640 vip = viq ^ 3;2641 vop = viq ^ 3;2642 break;2643 default:2644 ret = -EINVAL;2645 }2646 2647 /*2648 * None of the vendor drivers are configuring the beacon2649 * queue here .... why?2650 */2651 if (!ret) {2652 /* Only RTL8192F seems to do it like this. */2653 if (priv->rtl_chip == RTL8192F) {2654 val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL);2655 val32 &= 0x7;2656 val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) |2657 (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) |2658 (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) |2659 (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) |2660 (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) |2661 (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F);2662 rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32);2663 } else {2664 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);2665 val16 &= 0x7;2666 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |2667 (viq << TRXDMA_CTRL_VIQ_SHIFT) |2668 (beq << TRXDMA_CTRL_BEQ_SHIFT) |2669 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |2670 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |2671 (hiq << TRXDMA_CTRL_HIQ_SHIFT);2672 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);2673 }2674 2675 priv->pipe_out[TXDESC_QUEUE_VO] =2676 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);2677 priv->pipe_out[TXDESC_QUEUE_VI] =2678 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);2679 priv->pipe_out[TXDESC_QUEUE_BE] =2680 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);2681 priv->pipe_out[TXDESC_QUEUE_BK] =2682 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);2683 priv->pipe_out[TXDESC_QUEUE_BEACON] =2684 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);2685 priv->pipe_out[TXDESC_QUEUE_MGNT] =2686 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);2687 priv->pipe_out[TXDESC_QUEUE_HIGH] =2688 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);2689 priv->pipe_out[TXDESC_QUEUE_CMD] =2690 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);2691 }2692 2693 return ret;2694}2695 2696void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,2697 int result[][8], int candidate, bool tx_only)2698{2699 u32 oldval, x, tx0_a, reg;2700 int y, tx0_c;2701 u32 val32;2702 2703 if (!iqk_ok)2704 return;2705 2706 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);2707 oldval = val32 >> 22;2708 2709 x = result[candidate][0];2710 if ((x & 0x00000200) != 0)2711 x = x | 0xfffffc00;2712 tx0_a = (x * oldval) >> 8;2713 2714 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);2715 val32 &= ~0x3ff;2716 val32 |= tx0_a;2717 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);2718 2719 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);2720 val32 &= ~BIT(31);2721 if ((x * oldval >> 7) & 0x1)2722 val32 |= BIT(31);2723 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);2724 2725 y = result[candidate][1];2726 if ((y & 0x00000200) != 0)2727 y = y | 0xfffffc00;2728 tx0_c = (y * oldval) >> 8;2729 2730 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);2731 val32 &= ~0xf0000000;2732 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);2733 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);2734 2735 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);2736 val32 &= ~0x003f0000;2737 val32 |= ((tx0_c & 0x3f) << 16);2738 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);2739 2740 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);2741 val32 &= ~BIT(29);2742 if ((y * oldval >> 7) & 0x1)2743 val32 |= BIT(29);2744 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);2745 2746 if (tx_only) {2747 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);2748 return;2749 }2750 2751 reg = result[candidate][2];2752 2753 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);2754 val32 &= ~0x3ff;2755 val32 |= (reg & 0x3ff);2756 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);2757 2758 reg = result[candidate][3] & 0x3F;2759 2760 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);2761 val32 &= ~0xfc00;2762 val32 |= ((reg << 10) & 0xfc00);2763 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);2764 2765 reg = (result[candidate][3] >> 6) & 0xF;2766 2767 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);2768 val32 &= ~0xf0000000;2769 val32 |= (reg << 28);2770 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);2771}2772 2773void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,2774 int result[][8], int candidate, bool tx_only)2775{2776 u32 oldval, x, tx1_a, reg;2777 int y, tx1_c;2778 u32 val32;2779 2780 if (!iqk_ok)2781 return;2782 2783 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);2784 oldval = val32 >> 22;2785 2786 x = result[candidate][4];2787 if ((x & 0x00000200) != 0)2788 x = x | 0xfffffc00;2789 tx1_a = (x * oldval) >> 8;2790 2791 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);2792 val32 &= ~0x3ff;2793 val32 |= tx1_a;2794 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);2795 2796 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);2797 val32 &= ~BIT(27);2798 if ((x * oldval >> 7) & 0x1)2799 val32 |= BIT(27);2800 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);2801 2802 y = result[candidate][5];2803 if ((y & 0x00000200) != 0)2804 y = y | 0xfffffc00;2805 tx1_c = (y * oldval) >> 8;2806 2807 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);2808 val32 &= ~0xf0000000;2809 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);2810 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);2811 2812 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);2813 val32 &= ~0x003f0000;2814 val32 |= ((tx1_c & 0x3f) << 16);2815 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);2816 2817 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);2818 val32 &= ~BIT(25);2819 if ((y * oldval >> 7) & 0x1)2820 val32 |= BIT(25);2821 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);2822 2823 if (tx_only) {2824 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);2825 return;2826 }2827 2828 reg = result[candidate][6];2829 2830 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);2831 val32 &= ~0x3ff;2832 val32 |= (reg & 0x3ff);2833 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);2834 2835 reg = result[candidate][7] & 0x3f;2836 2837 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);2838 val32 &= ~0xfc00;2839 val32 |= ((reg << 10) & 0xfc00);2840 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);2841 2842 reg = (result[candidate][7] >> 6) & 0xf;2843 2844 if (priv->rtl_chip == RTL8192F) {2845 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg);2846 } else {2847 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE);2848 val32 &= ~0x0000f000;2849 val32 |= (reg << 12);2850 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32);2851 }2852}2853 2854#define MAX_TOLERANCE 52855 2856bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,2857 int result[][8], int c1, int c2)2858{2859 u32 i, j, diff, simubitmap, bound = 0;2860 int candidate[2] = {-1, -1}; /* for path A and path B */2861 bool retval = true;2862 2863 if (priv->tx_paths > 1)2864 bound = 8;2865 else2866 bound = 4;2867 2868 simubitmap = 0;2869 2870 for (i = 0; i < bound; i++) {2871 diff = (result[c1][i] > result[c2][i]) ?2872 (result[c1][i] - result[c2][i]) :2873 (result[c2][i] - result[c1][i]);2874 if (diff > MAX_TOLERANCE) {2875 if ((i == 2 || i == 6) && !simubitmap) {2876 if (result[c1][i] + result[c1][i + 1] == 0)2877 candidate[(i / 4)] = c2;2878 else if (result[c2][i] + result[c2][i + 1] == 0)2879 candidate[(i / 4)] = c1;2880 else2881 simubitmap = simubitmap | (1 << i);2882 } else {2883 simubitmap = simubitmap | (1 << i);2884 }2885 }2886 }2887 2888 if (simubitmap == 0) {2889 for (i = 0; i < (bound / 4); i++) {2890 if (candidate[i] >= 0) {2891 for (j = i * 4; j < (i + 1) * 4 - 2; j++)2892 result[3][j] = result[candidate[i]][j];2893 retval = false;2894 }2895 }2896 return retval;2897 } else if (!(simubitmap & 0x0f)) {2898 /* path A OK */2899 for (i = 0; i < 4; i++)2900 result[3][i] = result[c1][i];2901 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {2902 /* path B OK */2903 for (i = 4; i < 8; i++)2904 result[3][i] = result[c1][i];2905 }2906 2907 return false;2908}2909 2910bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,2911 int result[][8], int c1, int c2)2912{2913 u32 i, j, diff, simubitmap, bound = 0;2914 int candidate[2] = {-1, -1}; /* for path A and path B */2915 int tmp1, tmp2;2916 bool retval = true;2917 2918 if (priv->tx_paths > 1)2919 bound = 8;2920 else2921 bound = 4;2922 2923 simubitmap = 0;2924 2925 for (i = 0; i < bound; i++) {2926 if (i & 1) {2927 if ((result[c1][i] & 0x00000200))2928 tmp1 = result[c1][i] | 0xfffffc00;2929 else2930 tmp1 = result[c1][i];2931 2932 if ((result[c2][i]& 0x00000200))2933 tmp2 = result[c2][i] | 0xfffffc00;2934 else2935 tmp2 = result[c2][i];2936 } else {2937 tmp1 = result[c1][i];2938 tmp2 = result[c2][i];2939 }2940 2941 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);2942 2943 if (diff > MAX_TOLERANCE) {2944 if ((i == 2 || i == 6) && !simubitmap) {2945 if (result[c1][i] + result[c1][i + 1] == 0)2946 candidate[(i / 4)] = c2;2947 else if (result[c2][i] + result[c2][i + 1] == 0)2948 candidate[(i / 4)] = c1;2949 else2950 simubitmap = simubitmap | (1 << i);2951 } else {2952 simubitmap = simubitmap | (1 << i);2953 }2954 }2955 }2956 2957 if (simubitmap == 0) {2958 for (i = 0; i < (bound / 4); i++) {2959 if (candidate[i] >= 0) {2960 for (j = i * 4; j < (i + 1) * 4 - 2; j++)2961 result[3][j] = result[candidate[i]][j];2962 retval = false;2963 }2964 }2965 return retval;2966 } else {2967 if (!(simubitmap & 0x03)) {2968 /* path A TX OK */2969 for (i = 0; i < 2; i++)2970 result[3][i] = result[c1][i];2971 }2972 2973 if (!(simubitmap & 0x0c)) {2974 /* path A RX OK */2975 for (i = 2; i < 4; i++)2976 result[3][i] = result[c1][i];2977 }2978 2979 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {2980 /* path B TX OK */2981 for (i = 4; i < 6; i++)2982 result[3][i] = result[c1][i];2983 }2984 2985 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) {2986 /* path B RX OK */2987 for (i = 6; i < 8; i++)2988 result[3][i] = result[c1][i];2989 }2990 }2991 2992 return false;2993}2994 2995void2996rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)2997{2998 int i;2999 3000 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)3001 backup[i] = rtl8xxxu_read8(priv, reg[i]);3002 3003 backup[i] = rtl8xxxu_read32(priv, reg[i]);3004}3005 3006void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,3007 const u32 *reg, u32 *backup)3008{3009 int i;3010 3011 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)3012 rtl8xxxu_write8(priv, reg[i], backup[i]);3013 3014 rtl8xxxu_write32(priv, reg[i], backup[i]);3015}3016 3017void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,3018 u32 *backup, int count)3019{3020 int i;3021 3022 for (i = 0; i < count; i++)3023 backup[i] = rtl8xxxu_read32(priv, regs[i]);3024}3025 3026void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,3027 u32 *backup, int count)3028{3029 int i;3030 3031 for (i = 0; i < count; i++)3032 rtl8xxxu_write32(priv, regs[i], backup[i]);3033}3034 3035 3036void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,3037 bool path_a_on)3038{3039 u32 path_on;3040 int i;3041 3042 if (priv->tx_paths == 1) {3043 path_on = priv->fops->adda_1t_path_on;3044 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);3045 } else {3046 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :3047 priv->fops->adda_2t_path_on_b;3048 3049 rtl8xxxu_write32(priv, regs[0], path_on);3050 }3051 3052 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)3053 rtl8xxxu_write32(priv, regs[i], path_on);3054}3055 3056void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,3057 const u32 *regs, u32 *backup)3058{3059 int i = 0;3060 3061 rtl8xxxu_write8(priv, regs[i], 0x3f);3062 3063 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)3064 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));3065 3066 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));3067}3068 3069static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)3070{3071 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;3072 int result = 0;3073 3074 /* path-A IQK setting */3075 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);3076 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);3077 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);3078 3079 val32 = (priv->rf_paths > 1) ? 0x28160202 :3080 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */3081 0x28160502;3082 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);3083 3084 /* path-B IQK setting */3085 if (priv->rf_paths > 1) {3086 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);3087 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);3088 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);3089 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);3090 }3091 3092 /* LO calibration setting */3093 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);3094 3095 /* One shot, path A LOK & IQK */3096 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);3097 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);3098 3099 mdelay(1);3100 3101 /* Check failed */3102 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);3103 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);3104 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);3105 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);3106 3107 if (!(reg_eac & BIT(28)) &&3108 ((reg_e94 & 0x03ff0000) != 0x01420000) &&3109 ((reg_e9c & 0x03ff0000) != 0x00420000))3110 result |= 0x01;3111 else /* If TX not OK, ignore RX */3112 goto out;3113 3114 /* If TX is OK, check whether RX is OK */3115 if (!(reg_eac & BIT(27)) &&3116 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&3117 ((reg_eac & 0x03ff0000) != 0x00360000))3118 result |= 0x02;3119 else3120 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",3121 __func__);3122out:3123 return result;3124}3125 3126static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)3127{3128 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;3129 int result = 0;3130 3131 /* One shot, path B LOK & IQK */3132 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);3133 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);3134 3135 mdelay(1);3136 3137 /* Check failed */3138 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);3139 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);3140 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);3141 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);3142 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);3143 3144 if (!(reg_eac & BIT(31)) &&3145 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&3146 ((reg_ebc & 0x03ff0000) != 0x00420000))3147 result |= 0x01;3148 else3149 goto out;3150 3151 if (!(reg_eac & BIT(30)) &&3152 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&3153 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))3154 result |= 0x02;3155 else3156 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",3157 __func__);3158out:3159 return result;3160}3161 3162static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,3163 int result[][8], int t)3164{3165 struct device *dev = &priv->udev->dev;3166 u32 i, val32;3167 int path_a_ok, path_b_ok;3168 int retry = 2;3169 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {3170 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,3171 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,3172 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,3173 REG_TX_OFDM_BBON, REG_TX_TO_RX,3174 REG_TX_TO_TX, REG_RX_CCK,3175 REG_RX_OFDM, REG_RX_WAIT_RIFS,3176 REG_RX_TO_RX, REG_STANDBY,3177 REG_SLEEP, REG_PMPD_ANAEN3178 };3179 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {3180 REG_TXPAUSE, REG_BEACON_CTRL,3181 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG3182 };3183 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {3184 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,3185 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,3186 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,3187 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE3188 };3189 3190 /*3191 * Note: IQ calibration must be performed after loading3192 * PHY_REG.txt , and radio_a, radio_b.txt3193 */3194 3195 if (t == 0) {3196 /* Save ADDA parameters, turn Path A ADDA on */3197 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,3198 RTL8XXXU_ADDA_REGS);3199 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);3200 rtl8xxxu_save_regs(priv, iqk_bb_regs,3201 priv->bb_backup, RTL8XXXU_BB_REGS);3202 }3203 3204 rtl8xxxu_path_adda_on(priv, adda_regs, true);3205 3206 if (t == 0) {3207 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);3208 if (val32 & FPGA0_HSSI_PARM1_PI)3209 priv->pi_enabled = 1;3210 }3211 3212 if (!priv->pi_enabled) {3213 /* Switch BB to PI mode to do IQ Calibration. */3214 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);3215 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);3216 }3217 3218 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);3219 val32 &= ~FPGA_RF_MODE_CCK;3220 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);3221 3222 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);3223 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);3224 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);3225 3226 if (!priv->no_pape) {3227 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);3228 val32 |= (FPGA0_RF_PAPE |3229 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));3230 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);3231 }3232 3233 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);3234 val32 &= ~BIT(10);3235 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);3236 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);3237 val32 &= ~BIT(10);3238 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);3239 3240 if (priv->tx_paths > 1) {3241 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);3242 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);3243 }3244 3245 /* MAC settings */3246 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);3247 3248 /* Page B init */3249 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);3250 3251 if (priv->tx_paths > 1)3252 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);3253 3254 /* IQ calibration setting */3255 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);3256 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);3257 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);3258 3259 for (i = 0; i < retry; i++) {3260 path_a_ok = rtl8xxxu_iqk_path_a(priv);3261 if (path_a_ok == 0x03) {3262 val32 = rtl8xxxu_read32(priv,3263 REG_TX_POWER_BEFORE_IQK_A);3264 result[t][0] = (val32 >> 16) & 0x3ff;3265 val32 = rtl8xxxu_read32(priv,3266 REG_TX_POWER_AFTER_IQK_A);3267 result[t][1] = (val32 >> 16) & 0x3ff;3268 val32 = rtl8xxxu_read32(priv,3269 REG_RX_POWER_BEFORE_IQK_A_2);3270 result[t][2] = (val32 >> 16) & 0x3ff;3271 val32 = rtl8xxxu_read32(priv,3272 REG_RX_POWER_AFTER_IQK_A_2);3273 result[t][3] = (val32 >> 16) & 0x3ff;3274 break;3275 } else if (i == (retry - 1) && path_a_ok == 0x01) {3276 /* TX IQK OK */3277 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",3278 __func__);3279 3280 val32 = rtl8xxxu_read32(priv,3281 REG_TX_POWER_BEFORE_IQK_A);3282 result[t][0] = (val32 >> 16) & 0x3ff;3283 val32 = rtl8xxxu_read32(priv,3284 REG_TX_POWER_AFTER_IQK_A);3285 result[t][1] = (val32 >> 16) & 0x3ff;3286 }3287 }3288 3289 if (!path_a_ok)3290 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);3291 3292 if (priv->tx_paths > 1) {3293 /*3294 * Path A into standby3295 */3296 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);3297 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);3298 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);3299 3300 /* Turn Path B ADDA on */3301 rtl8xxxu_path_adda_on(priv, adda_regs, false);3302 3303 for (i = 0; i < retry; i++) {3304 path_b_ok = rtl8xxxu_iqk_path_b(priv);3305 if (path_b_ok == 0x03) {3306 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);3307 result[t][4] = (val32 >> 16) & 0x3ff;3308 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);3309 result[t][5] = (val32 >> 16) & 0x3ff;3310 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);3311 result[t][6] = (val32 >> 16) & 0x3ff;3312 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);3313 result[t][7] = (val32 >> 16) & 0x3ff;3314 break;3315 } else if (i == (retry - 1) && path_b_ok == 0x01) {3316 /* TX IQK OK */3317 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);3318 result[t][4] = (val32 >> 16) & 0x3ff;3319 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);3320 result[t][5] = (val32 >> 16) & 0x3ff;3321 }3322 }3323 3324 if (!path_b_ok)3325 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);3326 }3327 3328 /* Back to BB mode, load original value */3329 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);3330 3331 if (t) {3332 if (!priv->pi_enabled) {3333 /*3334 * Switch back BB to SI mode after finishing3335 * IQ Calibration3336 */3337 val32 = 0x01000000;3338 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);3339 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);3340 }3341 3342 /* Reload ADDA power saving parameters */3343 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,3344 RTL8XXXU_ADDA_REGS);3345 3346 /* Reload MAC parameters */3347 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);3348 3349 /* Reload BB parameters */3350 rtl8xxxu_restore_regs(priv, iqk_bb_regs,3351 priv->bb_backup, RTL8XXXU_BB_REGS);3352 3353 /* Restore RX initial gain */3354 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);3355 3356 if (priv->tx_paths > 1) {3357 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,3358 0x00032ed3);3359 }3360 3361 /* Load 0xe30 IQC default value */3362 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);3363 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);3364 }3365}3366 3367void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)3368{3369 struct h2c_cmd h2c;3370 3371 memset(&h2c, 0, sizeof(struct h2c_cmd));3372 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;3373 h2c.bt_wlan_calibration.data = start;3374 3375 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));3376}3377 3378void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)3379{3380 struct device *dev = &priv->udev->dev;3381 int result[4][8]; /* last is final result */3382 int i, candidate;3383 bool path_a_ok, path_b_ok;3384 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;3385 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;3386 s32 reg_tmp = 0;3387 bool simu;3388 3389 memset(result, 0, sizeof(result));3390 candidate = -1;3391 3392 path_a_ok = false;3393 path_b_ok = false;3394 3395 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);3396 3397 for (i = 0; i < 3; i++) {3398 rtl8xxxu_phy_iqcalibrate(priv, result, i);3399 3400 if (i == 1) {3401 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);3402 if (simu) {3403 candidate = 0;3404 break;3405 }3406 }3407 3408 if (i == 2) {3409 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);3410 if (simu) {3411 candidate = 0;3412 break;3413 }3414 3415 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);3416 if (simu) {3417 candidate = 1;3418 } else {3419 for (i = 0; i < 8; i++)3420 reg_tmp += result[3][i];3421 3422 if (reg_tmp)3423 candidate = 3;3424 else3425 candidate = -1;3426 }3427 }3428 }3429 3430 for (i = 0; i < 4; i++) {3431 reg_e94 = result[i][0];3432 reg_e9c = result[i][1];3433 reg_ea4 = result[i][2];3434 reg_eac = result[i][3];3435 reg_eb4 = result[i][4];3436 reg_ebc = result[i][5];3437 reg_ec4 = result[i][6];3438 reg_ecc = result[i][7];3439 }3440 3441 if (candidate >= 0) {3442 reg_e94 = result[candidate][0];3443 priv->rege94 = reg_e94;3444 reg_e9c = result[candidate][1];3445 priv->rege9c = reg_e9c;3446 reg_ea4 = result[candidate][2];3447 reg_eac = result[candidate][3];3448 reg_eb4 = result[candidate][4];3449 priv->regeb4 = reg_eb4;3450 reg_ebc = result[candidate][5];3451 priv->regebc = reg_ebc;3452 reg_ec4 = result[candidate][6];3453 reg_ecc = result[candidate][7];3454 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);3455 dev_dbg(dev,3456 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",3457 __func__, reg_e94, reg_e9c,3458 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);3459 path_a_ok = true;3460 path_b_ok = true;3461 } else {3462 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;3463 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;3464 }3465 3466 if (reg_e94 && candidate >= 0)3467 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,3468 candidate, (reg_ea4 == 0));3469 3470 if (priv->tx_paths > 1 && reg_eb4)3471 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,3472 candidate, (reg_ec4 == 0));3473 3474 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,3475 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);3476}3477 3478void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)3479{3480 u32 val32;3481 u32 rf_amode, rf_bmode = 0, lstf;3482 3483 /* Check continuous TX and Packet TX */3484 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);3485 3486 if (lstf & OFDM_LSTF_MASK) {3487 /* Disable all continuous TX */3488 val32 = lstf & ~OFDM_LSTF_MASK;3489 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);3490 3491 /* Read original RF mode Path A */3492 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);3493 3494 /* Set RF mode to standby Path A */3495 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,3496 (rf_amode & 0x8ffff) | 0x10000);3497 3498 /* Path-B */3499 if (priv->tx_paths > 1) {3500 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,3501 RF6052_REG_AC);3502 3503 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,3504 (rf_bmode & 0x8ffff) | 0x10000);3505 }3506 } else {3507 /* Deal with Packet TX case */3508 /* block all queues */3509 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);3510 }3511 3512 /* Start LC calibration */3513 if (priv->fops->has_s0s1)3514 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);3515 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);3516 val32 |= 0x08000;3517 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);3518 3519 msleep(100);3520 3521 if (priv->fops->has_s0s1)3522 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);3523 3524 /* Restore original parameters */3525 if (lstf & OFDM_LSTF_MASK) {3526 /* Path-A */3527 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);3528 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);3529 3530 /* Path-B */3531 if (priv->tx_paths > 1)3532 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,3533 rf_bmode);3534 } else /* Deal with Packet TX case */3535 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);3536}3537 3538static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv, int port_num)3539{3540 int i;3541 u16 reg;3542 3543 switch (port_num) {3544 case 0:3545 reg = REG_MACID;3546 break;3547 case 1:3548 reg = REG_MACID1;3549 break;3550 default:3551 WARN_ONCE(1, "%s: invalid port_num\n", __func__);3552 return -EINVAL;3553 }3554 3555 for (i = 0; i < ETH_ALEN; i++)3556 rtl8xxxu_write8(priv, reg + i, priv->vifs[port_num]->addr[i]);3557 3558 return 0;3559}3560 3561static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid, int port_num)3562{3563 int i;3564 u16 reg;3565 3566 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);3567 3568 switch (port_num) {3569 case 0:3570 reg = REG_BSSID;3571 break;3572 case 1:3573 reg = REG_BSSID1;3574 break;3575 default:3576 WARN_ONCE(1, "%s: invalid port_num\n", __func__);3577 return -EINVAL;3578 }3579 3580 for (i = 0; i < ETH_ALEN; i++)3581 rtl8xxxu_write8(priv, reg + i, bssid[i]);3582 3583 return 0;3584}3585 3586static void3587rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)3588{3589 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };3590 u8 max_agg = 0xf;3591 int i;3592 3593 ampdu_factor = 1 << (ampdu_factor + 2);3594 if (ampdu_factor > max_agg)3595 ampdu_factor = max_agg;3596 3597 for (i = 0; i < 4; i++) {3598 if ((vals[i] & 0xf0) > (ampdu_factor << 4))3599 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);3600 3601 if ((vals[i] & 0x0f) > ampdu_factor)3602 vals[i] = (vals[i] & 0xf0) | ampdu_factor;3603 3604 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);3605 }3606}3607 3608static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)3609{3610 u8 val8;3611 3612 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);3613 val8 &= 0xf8;3614 val8 |= density;3615 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);3616}3617 3618static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)3619{3620 u8 val8;3621 int count, ret = 0;3622 3623 /* Start of rtl8723AU_card_enable_flow */3624 /* Act to Cardemu sequence*/3625 /* Turn off RF */3626 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);3627 3628 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */3629 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);3630 val8 &= ~LEDCFG2_DPDT_SELECT;3631 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);3632 3633 /* 0x0005[1] = 1 turn off MAC by HW state machine*/3634 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);3635 val8 |= BIT(1);3636 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);3637 3638 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {3639 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);3640 if ((val8 & BIT(1)) == 0)3641 break;3642 udelay(10);3643 }3644 3645 if (!count) {3646 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",3647 __func__);3648 ret = -EBUSY;3649 goto exit;3650 }3651 3652 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */3653 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);3654 val8 |= SYS_ISO_ANALOG_IPS;3655 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);3656 3657 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/3658 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);3659 val8 &= ~LDOA15_ENABLE;3660 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);3661 3662exit:3663 return ret;3664}3665 3666int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)3667{3668 u8 val8;3669 u8 val32;3670 int count, ret = 0;3671 3672 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);3673 3674 /*3675 * Poll - wait for RX packet to complete3676 */3677 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {3678 val32 = rtl8xxxu_read32(priv, 0x5f8);3679 if (!val32)3680 break;3681 udelay(10);3682 }3683 3684 if (!count) {3685 dev_warn(&priv->udev->dev,3686 "%s: RX poll timed out (0x05f8)\n", __func__);3687 ret = -EBUSY;3688 goto exit;3689 }3690 3691 /* Disable CCK and OFDM, clock gated */3692 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);3693 val8 &= ~SYS_FUNC_BBRSTB;3694 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);3695 3696 udelay(2);3697 3698 /* Reset baseband */3699 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);3700 val8 &= ~SYS_FUNC_BB_GLB_RSTN;3701 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);3702 3703 /* Reset MAC TRX */3704 val8 = rtl8xxxu_read8(priv, REG_CR);3705 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;3706 rtl8xxxu_write8(priv, REG_CR, val8);3707 3708 /* Reset MAC TRX */3709 val8 = rtl8xxxu_read8(priv, REG_CR + 1);3710 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */3711 rtl8xxxu_write8(priv, REG_CR + 1, val8);3712 3713 /* Respond TX OK to scheduler */3714 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);3715 val8 |= DUAL_TSF_TX_OK;3716 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);3717 3718exit:3719 return ret;3720}3721 3722void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)3723{3724 u8 val8;3725 3726 /* Clear suspend enable and power down enable*/3727 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);3728 val8 &= ~(BIT(3) | BIT(7));3729 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);3730 3731 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/3732 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);3733 val8 &= ~BIT(0);3734 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);3735 3736 /* 0x04[12:11] = 11 enable WL suspend*/3737 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);3738 val8 &= ~(BIT(3) | BIT(4));3739 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);3740}3741 3742static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)3743{3744 u8 val8;3745 3746 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */3747 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);3748 3749 /* 0x04[12:11] = 01 enable WL suspend */3750 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);3751 val8 &= ~BIT(4);3752 val8 |= BIT(3);3753 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);3754 3755 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);3756 val8 |= BIT(7);3757 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);3758 3759 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */3760 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);3761 val8 |= BIT(0);3762 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);3763 3764 return 0;3765}3766 3767int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)3768{3769 struct device *dev = &priv->udev->dev;3770 u32 val32;3771 int retry, retval;3772 3773 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);3774 3775 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);3776 val32 |= RXPKT_NUM_RW_RELEASE_EN;3777 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);3778 3779 retry = 100;3780 retval = -EBUSY;3781 3782 do {3783 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);3784 if (val32 & RXPKT_NUM_RXDMA_IDLE) {3785 retval = 0;3786 break;3787 }3788 } while (retry--);3789 3790 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);3791 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);3792 mdelay(2);3793 3794 if (!retry)3795 dev_warn(dev, "Failed to flush FIFO\n");3796 3797 return retval;3798}3799 3800void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)3801{3802 /* Fix USB interface interference issue */3803 rtl8xxxu_write8(priv, 0xfe40, 0xe0);3804 rtl8xxxu_write8(priv, 0xfe41, 0x8d);3805 rtl8xxxu_write8(priv, 0xfe42, 0x80);3806 /*3807 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits3808 * 8 and 5, for which I have found no documentation.3809 */3810 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);3811 3812 /*3813 * Solve too many protocol error on USB bus.3814 * Can't do this for 8188/8192 UMC A cut parts3815 */3816 if (!(!priv->chip_cut && priv->vendor_umc)) {3817 rtl8xxxu_write8(priv, 0xfe40, 0xe6);3818 rtl8xxxu_write8(priv, 0xfe41, 0x94);3819 rtl8xxxu_write8(priv, 0xfe42, 0x80);3820 3821 rtl8xxxu_write8(priv, 0xfe40, 0xe0);3822 rtl8xxxu_write8(priv, 0xfe41, 0x19);3823 rtl8xxxu_write8(priv, 0xfe42, 0x80);3824 3825 rtl8xxxu_write8(priv, 0xfe40, 0xe5);3826 rtl8xxxu_write8(priv, 0xfe41, 0x91);3827 rtl8xxxu_write8(priv, 0xfe42, 0x80);3828 3829 rtl8xxxu_write8(priv, 0xfe40, 0xe2);3830 rtl8xxxu_write8(priv, 0xfe41, 0x81);3831 rtl8xxxu_write8(priv, 0xfe42, 0x80);3832 }3833}3834 3835void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)3836{3837 u32 val32;3838 3839 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);3840 val32 |= TXDMA_OFFSET_DROP_DATA_EN;3841 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);3842}3843 3844void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)3845{3846 u8 val8;3847 u16 val16;3848 u32 val32;3849 3850 /*3851 * Workaround for 8188RU LNA power leakage problem.3852 */3853 if (priv->rtl_chip == RTL8188R) {3854 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);3855 val32 |= BIT(1);3856 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);3857 }3858 3859 rtl8xxxu_flush_fifo(priv);3860 3861 rtl8xxxu_active_to_lps(priv);3862 3863 /* Turn off RF */3864 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);3865 3866 /* Reset Firmware if running in RAM */3867 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)3868 rtl8xxxu_firmware_self_reset(priv);3869 3870 /* Reset MCU */3871 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);3872 val16 &= ~SYS_FUNC_CPU_ENABLE;3873 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);3874 3875 /* Reset MCU ready status */3876 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);3877 3878 rtl8xxxu_active_to_emu(priv);3879 rtl8xxxu_emu_to_disabled(priv);3880 3881 /* Reset MCU IO Wrapper */3882 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);3883 val8 &= ~BIT(0);3884 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);3885 3886 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);3887 val8 |= BIT(0);3888 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);3889 3890 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */3891 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);3892}3893 3894void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,3895 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)3896{3897 struct h2c_cmd h2c;3898 3899 memset(&h2c, 0, sizeof(struct h2c_cmd));3900 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;3901 h2c.b_type_dma.data1 = arg1;3902 h2c.b_type_dma.data2 = arg2;3903 h2c.b_type_dma.data3 = arg3;3904 h2c.b_type_dma.data4 = arg4;3905 h2c.b_type_dma.data5 = arg5;3906 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));3907}3908 3909void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)3910{3911 u32 val32;3912 3913 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);3914 val32 &= ~(BIT(22) | BIT(23));3915 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);3916}3917 3918static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)3919{3920 struct rtl8xxxu_fileops *fops = priv->fops;3921 u32 hq, lq, nq, eq, pubq;3922 u32 val32;3923 3924 hq = 0;3925 lq = 0;3926 nq = 0;3927 eq = 0;3928 pubq = 0;3929 3930 if (priv->ep_tx_high_queue)3931 hq = fops->page_num_hi;3932 if (priv->ep_tx_low_queue)3933 lq = fops->page_num_lo;3934 if (priv->ep_tx_normal_queue)3935 nq = fops->page_num_norm;3936 3937 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);3938 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);3939 3940 pubq = fops->total_page_num - hq - lq - nq - 1;3941 3942 val32 = RQPN_LOAD;3943 val32 |= (hq << RQPN_HI_PQ_SHIFT);3944 val32 |= (lq << RQPN_LO_PQ_SHIFT);3945 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);3946 3947 rtl8xxxu_write32(priv, REG_RQPN, val32);3948}3949 3950void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)3951{3952 u8 val8;3953 3954 /*3955 * For USB high speed set 512B packets3956 */3957 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);3958 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE);3959 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT);3960 val8 |= RXDMA_PRO_DMA_MODE;3961 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);3962 3963 /*3964 * Enable single packet AMPDU3965 */3966 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);3967 val8 |= HT_SINGLE_AMPDU_ENABLE;3968 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);3969 3970 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num);3971 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B,3972 priv->fops->ampdu_max_time);3973 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);3974 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);3975 rtl8xxxu_write8(priv, REG_PIFS, 0x00);3976 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B ||3977 priv->rtl_chip == RTL8192F) {3978 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);3979 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);3980 }3981 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca);3982 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca);3983 3984 /* to prevent mac is reseted by bus. */3985 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);3986 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST;3987 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);3988}3989 3990static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv)3991{3992 u8 macid;3993 3994 macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);3995 if (macid < RTL8XXXU_MAX_MAC_ID_NUM)3996 set_bit(macid, priv->mac_id_map);3997 3998 return macid;3999}4000 4001static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid)4002{4003 clear_bit(macid, priv->mac_id_map);4004}4005 4006static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv,4007 struct ieee80211_sta *sta)4008{4009 struct rtl8xxxu_sta_info *sta_info;4010 4011 if (!sta)4012 return 0;4013 4014 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;4015 if (!sta_info)4016 return 0;4017 4018 return sta_info->macid;4019}4020 4021static int rtl8xxxu_init_device(struct ieee80211_hw *hw)4022{4023 struct rtl8xxxu_priv *priv = hw->priv;4024 struct device *dev = &priv->udev->dev;4025 struct rtl8xxxu_fileops *fops = priv->fops;4026 bool macpower;4027 int ret;4028 u8 val8;4029 u16 val16;4030 u32 val32;4031 4032 /* Check if MAC is already powered on */4033 val8 = rtl8xxxu_read8(priv, REG_CR);4034 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);4035 4036 /*4037 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not4038 * initialized. First MAC returns 0xea, second MAC returns 0x004039 */4040 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))4041 macpower = false;4042 else4043 macpower = true;4044 4045 if (fops->needs_full_init)4046 macpower = false;4047 4048 ret = fops->power_on(priv);4049 if (ret < 0) {4050 dev_warn(dev, "%s: Failed power on\n", __func__);4051 goto exit;4052 }4053 4054 if (!macpower)4055 rtl8xxxu_init_queue_reserved_page(priv);4056 4057 ret = rtl8xxxu_init_queue_priority(priv);4058 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);4059 if (ret)4060 goto exit;4061 4062 /*4063 * Set RX page boundary4064 */4065 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);4066 4067 ret = rtl8xxxu_download_firmware(priv);4068 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);4069 if (ret)4070 goto exit;4071 ret = rtl8xxxu_start_firmware(priv);4072 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);4073 if (ret)4074 goto exit;4075 4076 if (fops->phy_init_antenna_selection)4077 fops->phy_init_antenna_selection(priv);4078 4079 ret = rtl8xxxu_init_mac(priv);4080 4081 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);4082 if (ret)4083 goto exit;4084 4085 ret = rtl8xxxu_init_phy_bb(priv);4086 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);4087 if (ret)4088 goto exit;4089 4090 ret = fops->init_phy_rf(priv);4091 if (ret)4092 goto exit;4093 4094 /* Mac APLL Setting */4095 if (priv->rtl_chip == RTL8192F)4096 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15));4097 4098 /* RFSW Control - clear bit 14 ?? */4099 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E &&4100 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B &&4101 priv->rtl_chip != RTL8192F)4102 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);4103 4104 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |4105 FPGA0_RF_ANTSWB |4106 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);4107 if (!priv->no_pape) {4108 val32 |= (FPGA0_RF_PAPE |4109 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));4110 }4111 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);4112 4113 /* 0x860[6:5]= 00 - why? - this sets antenna B */4114 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E &&4115 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)4116 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);4117 4118 if (!macpower) {4119 /*4120 * Set TX buffer boundary4121 */4122 val8 = fops->total_page_num + 1;4123 4124 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);4125 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);4126 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);4127 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);4128 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);4129 }4130 4131 /*4132 * The vendor drivers set PBP for all devices, except 8192e.4133 * There is no explanation for this in any of the sources.4134 */4135 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |4136 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);4137 if (priv->rtl_chip != RTL8192E)4138 rtl8xxxu_write8(priv, REG_PBP, val8);4139 4140 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);4141 if (!macpower) {4142 ret = fops->llt_init(priv);4143 if (ret) {4144 dev_warn(dev, "%s: LLT table init failed\n", __func__);4145 goto exit;4146 }4147 4148 /*4149 * Chip specific quirks4150 */4151 fops->usb_quirks(priv);4152 4153 /*4154 * Enable TX report and TX report timer for 8723bu/8188eu/...4155 */4156 if (fops->has_tx_report) {4157 /*4158 * The RTL8188EU has two types of TX reports:4159 * rpt_sel=1:4160 * One report for one frame. We can use this for frames4161 * with IEEE80211_TX_CTL_REQ_TX_STATUS.4162 * rpt_sel=2:4163 * One report for many frames transmitted over a period4164 * of time. (This is what REG_TX_REPORT_TIME is for.) The4165 * report includes the number of frames transmitted4166 * successfully, and the number of unsuccessful4167 * transmissions. We use this for software rate control.4168 *4169 * Bit 0 of REG_TX_REPORT_CTRL is required for both types.4170 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for4171 * type 2.4172 */4173 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);4174 if (priv->rtl_chip == RTL8188E)4175 val8 |= BIT(0);4176 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;4177 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);4178 /* Set MAX RPT MACID */4179 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);4180 /* TX report Timer. Unit: 32us */4181 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);4182 4183 /* tmp ps ? */4184 val8 = rtl8xxxu_read8(priv, 0xa3);4185 val8 &= 0xf8;4186 rtl8xxxu_write8(priv, 0xa3, val8);4187 }4188 4189 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)4190 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0);4191 }4192 4193 /*4194 * Unit in 8 bytes.4195 * Get Rx PHY status in order to report RSSI and others.4196 */4197 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);4198 4199 if (priv->rtl_chip == RTL8192E) {4200 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);4201 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);4202 } else if (priv->rtl_chip == RTL8188F) {4203 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);4204 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff);4205 } else if (priv->rtl_chip == RTL8188E) {4206 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);4207 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2;4208 rtl8xxxu_write32(priv, REG_HIMR0, val32);4209 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW;4210 rtl8xxxu_write32(priv, REG_HIMR1, val32);4211 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);4212 val8 |= USB_SPEC_INT_BULK_SELECT;4213 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8);4214 } else if (priv->rtl_chip == RTL8710B) {4215 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0);4216 } else if (priv->rtl_chip != RTL8192F) {4217 /*4218 * Enable all interrupts - not obvious USB needs to do this4219 */4220 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);4221 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);4222 }4223 4224 /*4225 * Configure initial WMAC settings4226 */4227 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |4228 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |4229 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;4230 rtl8xxxu_write32(priv, REG_RCR, val32);4231 priv->regrcr = val32;4232 4233 if (fops->init_reg_rxfltmap) {4234 /* Accept all data frames */4235 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);4236 4237 /*4238 * Since ADF is removed from RCR, ps-poll will not be indicate to driver,4239 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.4240 */4241 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400);4242 4243 /* Accept all management frames */4244 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);4245 } else {4246 /*4247 * Accept all multicast4248 */4249 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);4250 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);4251 }4252 4253 /*4254 * Init adaptive controls4255 */4256 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);4257 val32 &= ~RESPONSE_RATE_BITMAP_ALL;4258 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;4259 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);4260 4261 /* CCK = 0x0a, OFDM = 0x10 */4262 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);4263 rtl8xxxu_set_retry(priv, 0x30, 0x30);4264 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);4265 4266 /*4267 * Init EDCA4268 */4269 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);4270 4271 /* Set CCK SIFS */4272 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);4273 4274 /* Set OFDM SIFS */4275 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);4276 4277 /* TXOP */4278 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);4279 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);4280 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);4281 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);4282 4283 /* Set data auto rate fallback retry count */4284 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);4285 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);4286 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);4287 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);4288 4289 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);4290 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;4291 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);4292 4293 /* Set ACK timeout */4294 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);4295 4296 /*4297 * Initialize beacon parameters4298 */4299 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);4300 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);4301 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);4302 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B &&4303 priv->rtl_chip != RTL8192F)4304 /* Firmware will control REG_DRVERLYINT when power saving is enable, */4305 /* so don't set this register on STA mode. */4306 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);4307 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);4308 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);4309 4310 /*4311 * Initialize burst parameters4312 */4313 if (priv->fops->init_burst)4314 priv->fops->init_burst(priv);4315 4316 if (fops->init_aggregation)4317 fops->init_aggregation(priv);4318 4319 if (fops->init_reg_pkt_life_time) {4320 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */4321 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */4322 }4323 4324 /*4325 * Enable CCK and OFDM block4326 */4327 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);4328 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);4329 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);4330 4331 /*4332 * Invalidate all CAM entries - bit 30 is undocumented4333 */4334 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));4335 4336 /*4337 * Start out with default power levels for channel 6, 20MHz4338 */4339 fops->set_tx_power(priv, 1, false);4340 4341 /* Let the 8051 take control of antenna setting */4342 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F &&4343 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192C) {4344 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);4345 val8 |= LEDCFG2_DPDT_SELECT;4346 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);4347 }4348 4349 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);4350 4351 /* Disable BAR - not sure if this has any effect on USB */4352 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);4353 4354 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E &&4355 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)4356 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);4357 4358 if (fops->init_statistics)4359 fops->init_statistics(priv);4360 4361 if (priv->rtl_chip == RTL8192E) {4362 /*4363 * 0x4c6[3] 1: RTS BW = Data BW4364 * 0: RTS BW depends on CCA / secondary CCA result.4365 */4366 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);4367 val8 &= ~BIT(3);4368 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);4369 /*4370 * Reset USB mode switch setting4371 */4372 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);4373 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E ||4374 priv->rtl_chip == RTL8192F) {4375 /*4376 * Init GPIO settings for 8188f, 8188e, 8192f4377 */4378 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);4379 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;4380 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);4381 }4382 4383 if (priv->rtl_chip == RTL8188F)4384 /* CCK PD */4385 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH);4386 4387 fops->phy_lc_calibrate(priv);4388 4389 fops->phy_iq_calibrate(priv);4390 4391 /*4392 * This should enable thermal meter4393 */4394 if (fops->gen2_thermal_meter) {4395 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) {4396 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B);4397 val32 |= 0x30000;4398 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32);4399 } else {4400 rtl8xxxu_write_rfreg(priv,4401 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);4402 }4403 } else {4404 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);4405 }4406 4407 /* Set NAV_UPPER to 30000us */4408 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);4409 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);4410 4411 if (priv->rtl_chip == RTL8723A) {4412 /*4413 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,4414 * but we need to find root cause.4415 * This is 8723au only.4416 */4417 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);4418 if ((val32 & 0xff000000) != 0x83000000) {4419 val32 |= FPGA_RF_MODE_CCK;4420 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);4421 }4422 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) {4423 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);4424 }4425 4426 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);4427 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;4428 /* ack for xmit mgmt frames. */4429 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);4430 4431 if (priv->rtl_chip == RTL8192E) {4432 /*4433 * Fix LDPC rx hang issue.4434 */4435 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);4436 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);4437 val32 &= 0xfff00fff;4438 val32 |= 0x0007e000;4439 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);4440 4441 /*4442 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting4443 * should be equal or CCK RSSI report may be incorrect4444 */4445 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);4446 priv->cck_agc_report_type =4447 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR);4448 4449 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2);4450 if (priv->cck_agc_report_type !=4451 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) {4452 if (priv->cck_agc_report_type)4453 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR;4454 else4455 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR;4456 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32);4457 }4458 4459 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT);4460 if (priv->cck_agc_report_type)4461 val32 |= AGC_RPT_CCK;4462 else4463 val32 &= ~AGC_RPT_CCK;4464 rtl8xxxu_write32(priv, REG_AGC_RPT, val32);4465 }4466 4467 if (priv->rtl_chip == RTL8710B) {4468 /*4469 * 0x76D[5:4] is Port0,Port1 Enable Bit.4470 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver4471 */4472 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B);4473 val8 |= BIT(5) | BIT(4);4474 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8);4475 4476 /* Set 0x5c[8] and [2:0] = 1, LDO mode */4477 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B);4478 val32 |= 0x107;4479 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32);4480 }4481 4482 val32 = rtl8xxxu_read32(priv, 0xa9c);4483 priv->cck_new_agc = u32_get_bits(val32, BIT(17));4484 4485 /* Initialise the center frequency offset tracking */4486 if (priv->fops->set_crystal_cap) {4487 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);4488 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS;4489 priv->cfo_tracking.adjust = true;4490 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap;4491 }4492 4493 if (priv->rtl_chip == RTL8188E)4494 rtl8188e_ra_info_init_all(&priv->ra_info);4495 4496 set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map);4497 set_bit(RTL8XXXU_BC_MC_MACID1, priv->mac_id_map);4498 4499exit:4500 return ret;4501}4502 4503static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,4504 struct ieee80211_key_conf *key, const u8 *mac)4505{4506 u32 cmd, val32, addr, ctrl;4507 int j, i, tmp_debug;4508 4509 tmp_debug = rtl8xxxu_debug;4510 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)4511 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;4512 4513 /*4514 * This is a bit of a hack - the lower bits of the cipher4515 * suite selector happens to match the cipher index in the CAM4516 */4517 addr = key->hw_key_idx << CAM_CMD_KEY_SHIFT;4518 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;4519 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))4520 ctrl |= BIT(6);4521 4522 for (j = 5; j >= 0; j--) {4523 switch (j) {4524 case 0:4525 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);4526 break;4527 case 1:4528 val32 = mac[2] | (mac[3] << 8) |4529 (mac[4] << 16) | (mac[5] << 24);4530 break;4531 default:4532 i = (j - 2) << 2;4533 val32 = key->key[i] | (key->key[i + 1] << 8) |4534 key->key[i + 2] << 16 | key->key[i + 3] << 24;4535 break;4536 }4537 4538 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);4539 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);4540 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);4541 udelay(100);4542 }4543 4544 rtl8xxxu_debug = tmp_debug;4545}4546 4547static4548int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)4549{4550 struct rtl8xxxu_priv *priv = hw->priv;4551 4552 *tx_ant = BIT(priv->tx_paths) - 1;4553 *rx_ant = BIT(priv->rx_paths) - 1;4554 4555 return 0;4556}4557 4558static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,4559 bool set)4560{4561 struct rtl8xxxu_priv *priv = hw->priv;4562 4563 schedule_delayed_work(&priv->update_beacon_work, 0);4564 4565 return 0;4566}4567 4568static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,4569 struct ieee80211_vif *vif, const u8 *mac)4570{4571 struct rtl8xxxu_priv *priv = hw->priv;4572 u8 val8;4573 4574 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);4575 val8 |= BEACON_DISABLE_TSF_UPDATE;4576 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);4577}4578 4579static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,4580 struct ieee80211_vif *vif)4581{4582 struct rtl8xxxu_priv *priv = hw->priv;4583 u8 val8;4584 4585 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);4586 val8 &= ~BEACON_DISABLE_TSF_UPDATE;4587 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);4588}4589 4590void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,4591 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,4592 u8 macid)4593{4594 struct h2c_cmd h2c;4595 4596 memset(&h2c, 0, sizeof(struct h2c_cmd));4597 4598 h2c.ramask.cmd = H2C_SET_RATE_MASK;4599 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);4600 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);4601 4602 h2c.ramask.arg = 0x80;4603 if (sgi)4604 h2c.ramask.arg |= 0x20;4605 4606 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",4607 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));4608 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));4609}4610 4611void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,4612 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,4613 u8 macid)4614{4615 struct h2c_cmd h2c;4616 u8 bw;4617 4618 if (txbw_40mhz)4619 bw = RTL8XXXU_CHANNEL_WIDTH_40;4620 else4621 bw = RTL8XXXU_CHANNEL_WIDTH_20;4622 4623 memset(&h2c, 0, sizeof(struct h2c_cmd));4624 4625 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;4626 h2c.b_macid_cfg.ramask0 = ramask & 0xff;4627 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;4628 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;4629 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;4630 h2c.b_macid_cfg.macid = macid;4631 4632 h2c.b_macid_cfg.data1 = rateid;4633 if (sgi)4634 h2c.b_macid_cfg.data1 |= BIT(7);4635 4636 h2c.b_macid_cfg.data2 = bw;4637 4638 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n",4639 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg));4640 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));4641}4642 4643void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,4644 u8 macid, u8 role, bool connect)4645{4646 struct h2c_cmd h2c;4647 4648 memset(&h2c, 0, sizeof(struct h2c_cmd));4649 4650 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;4651 4652 if (connect)4653 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;4654 else4655 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;4656 4657 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));4658}4659 4660void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,4661 u8 macid, u8 role, bool connect)4662{4663 /*4664 * The firmware turns on the rate control when it knows it's4665 * connected to a network.4666 */4667 struct h2c_cmd h2c;4668 4669 memset(&h2c, 0, sizeof(struct h2c_cmd));4670 4671 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;4672 if (connect)4673 h2c.media_status_rpt.parm |= BIT(0);4674 else4675 h2c.media_status_rpt.parm &= ~BIT(0);4676 4677 h2c.media_status_rpt.parm |= ((role << 4) & 0xf0);4678 h2c.media_status_rpt.macid = macid;4679 4680 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));4681}4682 4683void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)4684{4685 struct h2c_cmd h2c;4686 const int h2c_size = 4;4687 4688 memset(&h2c, 0, sizeof(struct h2c_cmd));4689 4690 h2c.rssi_report.cmd = H2C_SET_RSSI;4691 h2c.rssi_report.macid = macid;4692 h2c.rssi_report.rssi = rssi;4693 4694 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size);4695}4696 4697void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)4698{4699 struct h2c_cmd h2c;4700 int h2c_size = sizeof(h2c.rssi_report);4701 4702 if (priv->rtl_chip == RTL8723B)4703 h2c_size = 4;4704 4705 memset(&h2c, 0, sizeof(struct h2c_cmd));4706 4707 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING;4708 h2c.rssi_report.macid = macid;4709 h2c.rssi_report.rssi = rssi;4710 4711 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size);4712}4713 4714void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)4715{4716 u8 agg_ctrl, usb_spec, page_thresh, timeout;4717 4718 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);4719 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;4720 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);4721 4722 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);4723 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;4724 4725 if (!rtl8xxxu_dma_aggregation) {4726 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);4727 return;4728 }4729 4730 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;4731 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);4732 4733 /*4734 * The number of packets we can take looks to be buffer size / 5124735 * which matches the 512 byte rounding we have to do when de-muxing4736 * the packets.4737 *4738 * Sample numbers from the vendor driver:4739 * USB High-Speed mode values:4740 * RxAggBlockCount = 8 : 512 byte unit4741 * RxAggBlockTimeout = 64742 * RxAggPageCount = 48 : 128 byte unit4743 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))4744 */4745 4746 page_thresh = (priv->fops->rx_agg_buf_size / 512);4747 if (rtl8xxxu_dma_agg_pages >= 0) {4748 if (rtl8xxxu_dma_agg_pages <= page_thresh)4749 timeout = page_thresh;4750 else if (rtl8xxxu_dma_agg_pages <= 6)4751 dev_err(&priv->udev->dev,4752 "%s: dma_agg_pages=%i too small, minimum is 6\n",4753 __func__, rtl8xxxu_dma_agg_pages);4754 else4755 dev_err(&priv->udev->dev,4756 "%s: dma_agg_pages=%i larger than limit %i\n",4757 __func__, rtl8xxxu_dma_agg_pages, page_thresh);4758 }4759 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);4760 /*4761 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on4762 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we4763 * don't set it, so better set both.4764 */4765 timeout = 4;4766 4767 if (rtl8xxxu_dma_agg_timeout >= 0) {4768 if (rtl8xxxu_dma_agg_timeout <= 127)4769 timeout = rtl8xxxu_dma_agg_timeout;4770 else4771 dev_err(&priv->udev->dev,4772 "%s: Invalid dma_agg_timeout: %i\n",4773 __func__, rtl8xxxu_dma_agg_timeout);4774 }4775 4776 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);4777 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);4778 priv->rx_buf_aggregation = 1;4779}4780 4781static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = {4782 {.bitrate = 10, .hw_value = 0x00,},4783 {.bitrate = 20, .hw_value = 0x01,},4784 {.bitrate = 55, .hw_value = 0x02,},4785 {.bitrate = 110, .hw_value = 0x03,},4786 {.bitrate = 60, .hw_value = 0x04,},4787 {.bitrate = 90, .hw_value = 0x05,},4788 {.bitrate = 120, .hw_value = 0x06,},4789 {.bitrate = 180, .hw_value = 0x07,},4790 {.bitrate = 240, .hw_value = 0x08,},4791 {.bitrate = 360, .hw_value = 0x09,},4792 {.bitrate = 480, .hw_value = 0x0a,},4793 {.bitrate = 540, .hw_value = 0x0b,},4794};4795 4796static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)4797{4798 if (rate <= DESC_RATE_54M)4799 return;4800 4801 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {4802 if (rate < DESC_RATE_MCS8)4803 *nss = 1;4804 else4805 *nss = 2;4806 *mcs = rate - DESC_RATE_MCS0;4807 }4808}4809 4810static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)4811{4812 struct ieee80211_hw *hw = priv->hw;4813 u32 val32;4814 u8 rate_idx = 0;4815 4816 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;4817 4818 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);4819 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ)4820 val32 &= RESPONSE_RATE_RRSR_INIT_5G;4821 else4822 val32 &= RESPONSE_RATE_RRSR_INIT_2G;4823 val32 |= rate_cfg;4824 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);4825 4826 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);4827 4828 if (rate_cfg)4829 rate_idx = __fls(rate_cfg);4830 4831 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);4832}4833 4834static u164835rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta)4836{4837 u16 network_type = WIRELESS_MODE_UNKNOWN;4838 4839 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) {4840 if (sta->deflink.vht_cap.vht_supported)4841 network_type = WIRELESS_MODE_AC;4842 else if (sta->deflink.ht_cap.ht_supported)4843 network_type = WIRELESS_MODE_N_5G;4844 4845 network_type |= WIRELESS_MODE_A;4846 } else {4847 if (sta->deflink.vht_cap.vht_supported)4848 network_type = WIRELESS_MODE_AC;4849 else if (sta->deflink.ht_cap.ht_supported)4850 network_type = WIRELESS_MODE_N_24G;4851 4852 if (sta->deflink.supp_rates[0] <= 0xf)4853 network_type |= WIRELESS_MODE_B;4854 else if (sta->deflink.supp_rates[0] & 0xf)4855 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G);4856 else4857 network_type |= WIRELESS_MODE_G;4858 }4859 4860 return network_type;4861}4862 4863static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time)4864{4865 u32 reg_edca_param[IEEE80211_NUM_ACS] = {4866 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM,4867 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM,4868 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM,4869 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM,4870 };4871 u32 val32;4872 u16 wireless_mode = 0;4873 u8 aifs, aifsn, sifs;4874 int i;4875 4876 for (i = 0; i < ARRAY_SIZE(priv->vifs); i++) {4877 struct ieee80211_sta *sta;4878 4879 if (!priv->vifs[i])4880 continue;4881 4882 rcu_read_lock();4883 sta = ieee80211_find_sta(priv->vifs[i], priv->vifs[i]->bss_conf.bssid);4884 if (sta)4885 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta);4886 rcu_read_unlock();4887 4888 if (wireless_mode)4889 break;4890 }4891 4892 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ ||4893 (wireless_mode & WIRELESS_MODE_N_24G))4894 sifs = 16;4895 else4896 sifs = 10;4897 4898 for (i = 0; i < IEEE80211_NUM_ACS; i++) {4899 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]);4900 4901 /* It was set in conf_tx. */4902 aifsn = val32 & 0xff;4903 4904 /* aifsn not set yet or already fixed */4905 if (aifsn < 2 || aifsn > 15)4906 continue;4907 4908 aifs = aifsn * slot_time + sifs;4909 4910 val32 &= ~0xff;4911 val32 |= aifs;4912 rtl8xxxu_write32(priv, reg_edca_param[i], val32);4913 }4914}4915 4916void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,4917 u8 rate, u8 sgi, u8 bw)4918{4919 u8 mcs, nss;4920 4921 rarpt->txrate.flags = 0;4922 4923 if (rate <= DESC_RATE_54M) {4924 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate;4925 } else {4926 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);4927 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;4928 4929 rarpt->txrate.mcs = mcs;4930 rarpt->txrate.nss = nss;4931 4932 if (sgi)4933 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;4934 4935 rarpt->txrate.bw = bw;4936 }4937 4938 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);4939 rarpt->desc_rate = rate;4940}4941 4942static void4943rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,4944 struct ieee80211_bss_conf *bss_conf, u64 changed)4945{4946 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;4947 struct rtl8xxxu_priv *priv = hw->priv;4948 struct device *dev = &priv->udev->dev;4949 struct rtl8xxxu_sta_info *sta_info;4950 struct ieee80211_sta *sta;4951 struct rtl8xxxu_ra_report *rarpt;4952 u8 val8, macid;4953 u32 val32;4954 4955 rarpt = &priv->ra_report;4956 4957 if (changed & BSS_CHANGED_ASSOC) {4958 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc);4959 4960 rtl8xxxu_set_linktype(priv, vif->type, rtlvif->port_num);4961 4962 if (vif->cfg.assoc) {4963 u32 ramask;4964 int sgi = 0;4965 u8 highest_rate;4966 u8 bw;4967 4968 rcu_read_lock();4969 sta = ieee80211_find_sta(vif, bss_conf->bssid);4970 if (!sta) {4971 dev_info(dev, "%s: ASSOC no sta found\n",4972 __func__);4973 rcu_read_unlock();4974 goto error;4975 }4976 macid = rtl8xxxu_get_macid(priv, sta);4977 4978 if (sta->deflink.ht_cap.ht_supported)4979 dev_info(dev, "%s: HT supported\n", __func__);4980 if (sta->deflink.vht_cap.vht_supported)4981 dev_info(dev, "%s: VHT supported\n", __func__);4982 4983 /* TODO: Set bits 28-31 for rate adaptive id */4984 ramask = (sta->deflink.supp_rates[0] & 0xfff) |4985 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 |4986 sta->deflink.ht_cap.mcs.rx_mask[1] << 20;4987 if (sta->deflink.ht_cap.cap &4988 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))4989 sgi = 1;4990 4991 highest_rate = fls(ramask) - 1;4992 if (rtl8xxxu_ht40_2g &&4993 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))4994 bw = RATE_INFO_BW_40;4995 else4996 bw = RATE_INFO_BW_20;4997 4998 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;4999 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT;5000 rcu_read_unlock();5001 5002 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw);5003 5004 priv->fops->update_rate_mask(priv, ramask, 0, sgi,5005 bw == RATE_INFO_BW_40, macid);5006 5007 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);5008 5009 if (rtlvif->port_num == 0)5010 rtl8xxxu_stop_tx_beacon(priv);5011 5012 /* joinbss sequence */5013 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,5014 0xc000 | vif->cfg.aid);5015 5016 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true);5017 } else {5018 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);5019 val8 |= BEACON_DISABLE_TSF_UPDATE;5020 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);5021 5022 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false);5023 }5024 }5025 5026 if (changed & BSS_CHANGED_ERP_PREAMBLE) {5027 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",5028 bss_conf->use_short_preamble);5029 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);5030 if (bss_conf->use_short_preamble)5031 val32 |= RSR_ACK_SHORT_PREAMBLE;5032 else5033 val32 &= ~RSR_ACK_SHORT_PREAMBLE;5034 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);5035 }5036 5037 if (changed & BSS_CHANGED_ERP_SLOT) {5038 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",5039 bss_conf->use_short_slot);5040 5041 if (bss_conf->use_short_slot)5042 val8 = 9;5043 else5044 val8 = 20;5045 rtl8xxxu_write8(priv, REG_SLOT, val8);5046 5047 rtl8xxxu_set_aifs(priv, val8);5048 }5049 5050 if (changed & BSS_CHANGED_BSSID) {5051 dev_dbg(dev, "Changed BSSID!\n");5052 rtl8xxxu_set_bssid(priv, bss_conf->bssid, rtlvif->port_num);5053 }5054 5055 if (changed & BSS_CHANGED_BASIC_RATES) {5056 dev_dbg(dev, "Changed BASIC_RATES!\n");5057 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);5058 }5059 5060 if (changed & BSS_CHANGED_BEACON_ENABLED) {5061 if (bss_conf->enable_beacon)5062 rtl8xxxu_start_tx_beacon(priv);5063 else5064 rtl8xxxu_stop_tx_beacon(priv);5065 }5066 5067 if (changed & BSS_CHANGED_BEACON)5068 schedule_delayed_work(&priv->update_beacon_work, 0);5069 5070error:5071 return;5072}5073 5074static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,5075 struct ieee80211_bss_conf *link_conf)5076{5077 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;5078 struct rtl8xxxu_priv *priv = hw->priv;5079 struct device *dev = &priv->udev->dev;5080 5081 dev_dbg(dev, "Start AP mode\n");5082 rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid, rtlvif->port_num);5083 rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int);5084 priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true);5085 5086 return 0;5087}5088 5089static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)5090{5091 u32 rtlqueue;5092 5093 switch (queue) {5094 case IEEE80211_AC_VO:5095 rtlqueue = TXDESC_QUEUE_VO;5096 break;5097 case IEEE80211_AC_VI:5098 rtlqueue = TXDESC_QUEUE_VI;5099 break;5100 case IEEE80211_AC_BE:5101 rtlqueue = TXDESC_QUEUE_BE;5102 break;5103 case IEEE80211_AC_BK:5104 rtlqueue = TXDESC_QUEUE_BK;5105 break;5106 default:5107 rtlqueue = TXDESC_QUEUE_BE;5108 }5109 5110 return rtlqueue;5111}5112 5113static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb)5114{5115 u32 queue;5116 5117 if (unlikely(ieee80211_is_beacon(hdr->frame_control)))5118 queue = TXDESC_QUEUE_BEACON;5119 else if (ieee80211_is_mgmt(hdr->frame_control))5120 queue = TXDESC_QUEUE_MGNT;5121 else5122 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));5123 5124 return queue;5125}5126 5127/*5128 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor5129 * format. The descriptor checksum is still only calculated over the5130 * initial 32 bytes of the descriptor!5131 */5132static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)5133{5134 __le16 *ptr = (__le16 *)tx_desc;5135 u16 csum = 0;5136 int i;5137 5138 /*5139 * Clear csum field before calculation, as the csum field is5140 * in the middle of the struct.5141 */5142 tx_desc->csum = cpu_to_le16(0);5143 5144 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)5145 csum = csum ^ le16_to_cpu(ptr[i]);5146 5147 tx_desc->csum |= cpu_to_le16(csum);5148}5149 5150static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)5151{5152 struct rtl8xxxu_tx_urb *tx_urb, *tmp;5153 unsigned long flags;5154 5155 spin_lock_irqsave(&priv->tx_urb_lock, flags);5156 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {5157 list_del(&tx_urb->list);5158 priv->tx_urb_free_count--;5159 usb_free_urb(&tx_urb->urb);5160 }5161 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);5162}5163 5164static struct rtl8xxxu_tx_urb *5165rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)5166{5167 struct rtl8xxxu_tx_urb *tx_urb;5168 unsigned long flags;5169 5170 spin_lock_irqsave(&priv->tx_urb_lock, flags);5171 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,5172 struct rtl8xxxu_tx_urb, list);5173 if (tx_urb) {5174 list_del(&tx_urb->list);5175 priv->tx_urb_free_count--;5176 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&5177 !priv->tx_stopped) {5178 priv->tx_stopped = true;5179 ieee80211_stop_queues(priv->hw);5180 }5181 }5182 5183 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);5184 5185 return tx_urb;5186}5187 5188static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,5189 struct rtl8xxxu_tx_urb *tx_urb)5190{5191 unsigned long flags;5192 5193 INIT_LIST_HEAD(&tx_urb->list);5194 5195 spin_lock_irqsave(&priv->tx_urb_lock, flags);5196 5197 list_add(&tx_urb->list, &priv->tx_urb_free_list);5198 priv->tx_urb_free_count++;5199 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&5200 priv->tx_stopped) {5201 priv->tx_stopped = false;5202 ieee80211_wake_queues(priv->hw);5203 }5204 5205 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);5206}5207 5208static void rtl8xxxu_tx_complete(struct urb *urb)5209{5210 struct sk_buff *skb = (struct sk_buff *)urb->context;5211 struct ieee80211_tx_info *tx_info;5212 struct ieee80211_hw *hw;5213 struct rtl8xxxu_priv *priv;5214 struct rtl8xxxu_tx_urb *tx_urb =5215 container_of(urb, struct rtl8xxxu_tx_urb, urb);5216 5217 tx_info = IEEE80211_SKB_CB(skb);5218 hw = tx_info->rate_driver_data[0];5219 priv = hw->priv;5220 5221 skb_pull(skb, priv->fops->tx_desc_size);5222 5223 ieee80211_tx_info_clear_status(tx_info);5224 tx_info->status.rates[0].idx = -1;5225 tx_info->status.rates[0].count = 0;5226 5227 if (!urb->status)5228 tx_info->flags |= IEEE80211_TX_STAT_ACK;5229 5230 ieee80211_tx_status_irqsafe(hw, skb);5231 5232 rtl8xxxu_free_tx_urb(priv, tx_urb);5233}5234 5235static void rtl8xxxu_dump_action(struct device *dev,5236 struct ieee80211_hdr *hdr)5237{5238 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;5239 u16 cap, timeout;5240 5241 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))5242 return;5243 5244 switch (mgmt->u.action.u.addba_resp.action_code) {5245 case WLAN_ACTION_ADDBA_RESP:5246 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);5247 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);5248 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "5249 "timeout %i, tid %02x, buf_size %02x, policy %02x, "5250 "status %02x\n",5251 timeout,5252 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,5253 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,5254 (cap >> 1) & 0x1,5255 le16_to_cpu(mgmt->u.action.u.addba_resp.status));5256 break;5257 case WLAN_ACTION_ADDBA_REQ:5258 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);5259 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);5260 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "5261 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",5262 timeout,5263 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,5264 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,5265 (cap >> 1) & 0x1);5266 break;5267 default:5268 dev_info(dev, "action frame %02x\n",5269 mgmt->u.action.u.addba_resp.action_code);5270 break;5271 }5272}5273 5274/*5275 * Fill in v1 (gen1) specific TX descriptor bits.5276 * This format is used on 8188cu/8192cu/8723au5277 */5278void5279rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,5280 struct ieee80211_tx_info *tx_info,5281 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,5282 bool short_preamble, bool ampdu_enable, u32 rts_rate,5283 u8 macid)5284{5285 struct rtl8xxxu_priv *priv = hw->priv;5286 struct device *dev = &priv->udev->dev;5287 u8 *qc = ieee80211_get_qos_ctl(hdr);5288 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;5289 u32 rate = 0;5290 u16 seq_number;5291 5292 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)5293 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",5294 __func__, rate, le16_to_cpu(tx_desc->pkt_size));5295 5296 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));5297 5298 tx_desc->txdw5 = cpu_to_le32(rate);5299 5300 if (ieee80211_is_data(hdr->frame_control))5301 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);5302 5303 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);5304 5305 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))5306 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);5307 else5308 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);5309 5310 if (ieee80211_is_mgmt(hdr->frame_control)) {5311 tx_desc->txdw5 = cpu_to_le32(rate);5312 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);5313 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);5314 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);5315 }5316 5317 if (ieee80211_is_data_qos(hdr->frame_control))5318 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);5319 5320 if (short_preamble)5321 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);5322 5323 if (sgi)5324 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);5325 5326 /*5327 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled5328 */5329 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);5330 if (ampdu_enable || tx_info->control.use_rts) {5331 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);5332 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);5333 } else if (tx_info->control.use_cts_prot) {5334 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);5335 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);5336 }5337}5338 5339/*5340 * Fill in v2 (gen2) specific TX descriptor bits.5341 * This format is used on 8192eu/8723bu5342 */5343void5344rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,5345 struct ieee80211_tx_info *tx_info,5346 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,5347 bool short_preamble, bool ampdu_enable, u32 rts_rate,5348 u8 macid)5349{5350 struct rtl8xxxu_priv *priv = hw->priv;5351 struct device *dev = &priv->udev->dev;5352 struct rtl8xxxu_txdesc40 *tx_desc40;5353 u8 *qc = ieee80211_get_qos_ctl(hdr);5354 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;5355 u32 rate = 0;5356 u16 seq_number;5357 5358 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;5359 5360 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)5361 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",5362 __func__, rate, le16_to_cpu(tx_desc40->pkt_size));5363 5364 tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT);5365 5366 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));5367 5368 tx_desc40->txdw4 = cpu_to_le32(rate);5369 if (ieee80211_is_data(hdr->frame_control)) {5370 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<5371 TXDESC40_DATA_RATE_FB_SHIFT);5372 }5373 5374 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);5375 5376 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))5377 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);5378 else5379 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);5380 5381 if (ieee80211_is_mgmt(hdr->frame_control)) {5382 tx_desc40->txdw4 = cpu_to_le32(rate);5383 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);5384 tx_desc40->txdw4 |=5385 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);5386 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);5387 }5388 5389 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)5390 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE);5391 5392 if (short_preamble)5393 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);5394 5395 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);5396 5397 /*5398 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled5399 */5400 if (ampdu_enable || tx_info->control.use_rts) {5401 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);5402 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);5403 } else if (tx_info->control.use_cts_prot) {5404 /*5405 * For some reason the vendor driver doesn't set5406 * TXDESC40_HW_RTS_ENABLE for CTS to SELF5407 */5408 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);5409 }5410}5411 5412/*5413 * Fill in v3 (gen1) specific TX descriptor bits.5414 * This format is a hybrid between the v1 and v2 formats, only seen5415 * on 8188eu devices so far.5416 */5417void5418rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,5419 struct ieee80211_tx_info *tx_info,5420 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,5421 bool short_preamble, bool ampdu_enable, u32 rts_rate,5422 u8 macid)5423{5424 struct rtl8xxxu_priv *priv = hw->priv;5425 struct device *dev = &priv->udev->dev;5426 struct rtl8xxxu_ra_info *ra = &priv->ra_info;5427 u8 *qc = ieee80211_get_qos_ctl(hdr);5428 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;5429 u32 rate = 0;5430 u16 seq_number;5431 5432 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));5433 5434 if (ieee80211_is_data(hdr->frame_control)) {5435 rate = ra->decision_rate;5436 tx_desc->txdw5 = cpu_to_le32(rate);5437 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);5438 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK);5439 /* Data/RTS rate FB limit */5440 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);5441 }5442 5443 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)5444 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",5445 __func__, rate, le16_to_cpu(tx_desc->pkt_size));5446 5447 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);5448 5449 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))5450 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);5451 else5452 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);5453 5454 if (ieee80211_is_mgmt(hdr->frame_control)) {5455 tx_desc->txdw5 = cpu_to_le32(rate);5456 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);5457 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);5458 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);5459 }5460 5461 if (ieee80211_is_data_qos(hdr->frame_control)) {5462 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);5463 5464 if (conf_is_ht40(&hw->conf)) {5465 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW);5466 5467 if (conf_is_ht40_minus(&hw->conf))5468 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER);5469 else5470 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER);5471 }5472 }5473 5474 if (short_preamble)5475 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);5476 5477 if (sgi && ra->rate_sgi)5478 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);5479 5480 /*5481 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled5482 */5483 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);5484 if (ampdu_enable || tx_info->control.use_rts) {5485 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);5486 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);5487 } else if (tx_info->control.use_cts_prot) {5488 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);5489 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);5490 }5491 5492 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A |5493 TXDESC_ANTENNA_SELECT_B);5494 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16);5495}5496 5497static void rtl8xxxu_tx(struct ieee80211_hw *hw,5498 struct ieee80211_tx_control *control,5499 struct sk_buff *skb)5500{5501 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;5502 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);5503 struct rtl8xxxu_priv *priv = hw->priv;5504 struct rtl8xxxu_txdesc32 *tx_desc;5505 struct rtl8xxxu_tx_urb *tx_urb;5506 struct ieee80211_sta *sta = NULL;5507 struct ieee80211_vif *vif = tx_info->control.vif;5508 struct rtl8xxxu_vif *rtlvif = vif ? (struct rtl8xxxu_vif *)vif->drv_priv : NULL;5509 struct device *dev = &priv->udev->dev;5510 u32 queue, rts_rate;5511 u16 pktlen = skb->len;5512 int tx_desc_size = priv->fops->tx_desc_size;5513 u8 macid;5514 int ret;5515 bool ampdu_enable, sgi = false, short_preamble = false, bmc = false;5516 5517 if (skb_headroom(skb) < tx_desc_size) {5518 dev_warn(dev,5519 "%s: Not enough headroom (%i) for tx descriptor\n",5520 __func__, skb_headroom(skb));5521 goto error;5522 }5523 5524 if (unlikely(skb->len > (65535 - tx_desc_size))) {5525 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",5526 __func__, skb->len);5527 goto error;5528 }5529 5530 tx_urb = rtl8xxxu_alloc_tx_urb(priv);5531 if (!tx_urb) {5532 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);5533 goto error;5534 }5535 5536 if (ieee80211_is_action(hdr->frame_control))5537 rtl8xxxu_dump_action(dev, hdr);5538 5539 tx_info->rate_driver_data[0] = hw;5540 5541 if (control && control->sta)5542 sta = control->sta;5543 5544 queue = rtl8xxxu_queue_select(hdr, skb);5545 5546 tx_desc = skb_push(skb, tx_desc_size);5547 5548 memset(tx_desc, 0, tx_desc_size);5549 tx_desc->pkt_size = cpu_to_le16(pktlen);5550 tx_desc->pkt_offset = tx_desc_size;5551 5552 /* These bits mean different things to the RTL8192F. */5553 if (priv->rtl_chip != RTL8192F)5554 tx_desc->txdw0 =5555 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;5556 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||5557 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {5558 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;5559 bmc = true;5560 }5561 5562 5563 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);5564 macid = rtl8xxxu_get_macid(priv, sta);5565 5566 if (tx_info->control.hw_key) {5567 switch (tx_info->control.hw_key->cipher) {5568 case WLAN_CIPHER_SUITE_WEP40:5569 case WLAN_CIPHER_SUITE_WEP104:5570 case WLAN_CIPHER_SUITE_TKIP:5571 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);5572 break;5573 case WLAN_CIPHER_SUITE_CCMP:5574 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);5575 break;5576 default:5577 break;5578 }5579 if (bmc && rtlvif && rtlvif->hw_key_idx != 0xff) {5580 tx_desc->txdw1 |= cpu_to_le32(TXDESC_EN_DESC_ID);5581 macid = rtlvif->hw_key_idx;5582 }5583 }5584 5585 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */5586 ampdu_enable = false;5587 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {5588 if (sta->deflink.ht_cap.ht_supported) {5589 u32 ampdu, val32;5590 u8 *qc = ieee80211_get_qos_ctl(hdr);5591 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;5592 5593 ampdu = (u32)sta->deflink.ht_cap.ampdu_density;5594 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;5595 tx_desc->txdw2 |= cpu_to_le32(val32);5596 5597 ampdu_enable = true;5598 5599 if (!test_bit(tid, priv->tx_aggr_started) &&5600 !(skb->protocol == cpu_to_be16(ETH_P_PAE)))5601 if (!ieee80211_start_tx_ba_session(sta, tid, 0))5602 set_bit(tid, priv->tx_aggr_started);5603 }5604 }5605 5606 if (ieee80211_is_data_qos(hdr->frame_control) &&5607 sta && sta->deflink.ht_cap.cap &5608 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))5609 sgi = true;5610 5611 if (sta && vif && vif->bss_conf.use_short_preamble)5612 short_preamble = true;5613 5614 if (skb->len > hw->wiphy->rts_threshold)5615 tx_info->control.use_rts = true;5616 5617 if (sta && vif && vif->bss_conf.use_cts_prot)5618 tx_info->control.use_cts_prot = true;5619 5620 if (ampdu_enable || tx_info->control.use_rts ||5621 tx_info->control.use_cts_prot)5622 rts_rate = DESC_RATE_24M;5623 else5624 rts_rate = 0;5625 5626 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,5627 ampdu_enable, rts_rate, macid);5628 5629 rtl8xxxu_calc_tx_desc_csum(tx_desc);5630 5631 /* avoid zero checksum make tx hang */5632 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)5633 tx_desc->csum = ~tx_desc->csum;5634 5635 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],5636 skb->data, skb->len, rtl8xxxu_tx_complete, skb);5637 5638 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);5639 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);5640 if (ret) {5641 usb_unanchor_urb(&tx_urb->urb);5642 rtl8xxxu_free_tx_urb(priv, tx_urb);5643 goto error;5644 }5645 return;5646error:5647 dev_kfree_skb(skb);5648}5649 5650static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw,5651 struct ieee80211_vif *vif)5652{5653 struct rtl8xxxu_priv *priv = hw->priv;5654 struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);5655 struct device *dev = &priv->udev->dev;5656 int retry;5657 u8 val8;5658 5659 /* BCN_VALID, write 1 to clear, cleared by SW */5660 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);5661 val8 |= BIT_BCN_VALID >> 16;5662 rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8);5663 5664 /* SW_BCN_SEL - Port0 */5665 val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2);5666 val8 &= ~(BIT_SW_BCN_SEL >> 16);5667 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8);5668 5669 if (skb)5670 rtl8xxxu_tx(hw, NULL, skb);5671 5672 retry = 100;5673 do {5674 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);5675 if (val8 & (BIT_BCN_VALID >> 16))5676 break;5677 usleep_range(10, 20);5678 } while (--retry);5679 5680 if (!retry)5681 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__);5682}5683 5684static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work)5685{5686 struct rtl8xxxu_priv *priv =5687 container_of(work, struct rtl8xxxu_priv, update_beacon_work.work);5688 struct ieee80211_hw *hw = priv->hw;5689 struct ieee80211_vif *vif = priv->vifs[0];5690 5691 if (!vif) {5692 WARN_ONCE(true, "no vif to update beacon\n");5693 return;5694 }5695 5696 if (vif->bss_conf.csa_active) {5697 if (ieee80211_beacon_cntdwn_is_complete(vif, 0)) {5698 ieee80211_csa_finish(vif, 0);5699 return;5700 }5701 schedule_delayed_work(&priv->update_beacon_work,5702 msecs_to_jiffies(vif->bss_conf.beacon_int));5703 }5704 rtl8xxxu_send_beacon_frame(hw, vif);5705}5706 5707static inline bool rtl8xxxu_is_packet_match_bssid(struct rtl8xxxu_priv *priv,5708 struct ieee80211_hdr *hdr,5709 int port_num)5710{5711 return priv->vifs[port_num] &&5712 priv->vifs[port_num]->type == NL80211_IFTYPE_STATION &&5713 priv->vifs[port_num]->cfg.assoc &&5714 ether_addr_equal(priv->vifs[port_num]->bss_conf.bssid, hdr->addr2);5715}5716 5717static inline bool rtl8xxxu_is_sta_sta(struct rtl8xxxu_priv *priv)5718{5719 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc &&5720 priv->vifs[0]->type == NL80211_IFTYPE_STATION) &&5721 (priv->vifs[1] && priv->vifs[1]->cfg.assoc &&5722 priv->vifs[1]->type == NL80211_IFTYPE_STATION);5723}5724 5725void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv,5726 struct ieee80211_rx_status *rx_status,5727 struct rtl8723au_phy_stats *phy_stats,5728 u32 rxmcs, struct ieee80211_hdr *hdr,5729 bool crc_icv_err)5730{5731 if (phy_stats->sgi_en)5732 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;5733 5734 if (rxmcs < DESC_RATE_6M) {5735 /*5736 * Handle PHY stats for CCK rates5737 */5738 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats);5739 } else {5740 bool parse_cfo = priv->fops->set_crystal_cap &&5741 !crc_icv_err &&5742 !ieee80211_is_ctl(hdr->frame_control) &&5743 !rtl8xxxu_is_sta_sta(priv) &&5744 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) ||5745 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1));5746 5747 if (parse_cfo) {5748 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0];5749 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1];5750 5751 priv->cfo_tracking.packet_count++;5752 }5753 5754 rx_status->signal =5755 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;5756 }5757}5758 5759static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv,5760 struct ieee80211_rx_status *rx_status,5761 struct jaguar2_phy_stats_type0 *phy_stats0,5762 u32 rxmcs, struct ieee80211_hdr *hdr,5763 bool crc_icv_err)5764{5765 s8 rx_power = phy_stats0->pwdb - 110;5766 5767 if (!priv->cck_new_agc)5768 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0);5769 5770 rx_status->signal = rx_power;5771}5772 5773static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv,5774 struct ieee80211_rx_status *rx_status,5775 struct jaguar2_phy_stats_type1 *phy_stats1,5776 u32 rxmcs, struct ieee80211_hdr *hdr,5777 bool crc_icv_err)5778{5779 bool parse_cfo = priv->fops->set_crystal_cap &&5780 !crc_icv_err &&5781 !ieee80211_is_ctl(hdr->frame_control) &&5782 !rtl8xxxu_is_sta_sta(priv) &&5783 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) ||5784 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1));5785 u8 pwdb_max = 0;5786 int rx_path;5787 5788 if (parse_cfo) {5789 /* Only path-A and path-B have CFO tail and short CFO */5790 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A];5791 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B];5792 5793 priv->cfo_tracking.packet_count++;5794 }5795 5796 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)5797 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]);5798 5799 rx_status->signal = pwdb_max - 110;5800}5801 5802static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv,5803 struct ieee80211_rx_status *rx_status,5804 struct jaguar2_phy_stats_type2 *phy_stats2,5805 u32 rxmcs, struct ieee80211_hdr *hdr,5806 bool crc_icv_err)5807{5808 u8 pwdb_max = 0;5809 int rx_path;5810 5811 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)5812 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]);5813 5814 rx_status->signal = pwdb_max - 110;5815}5816 5817void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv,5818 struct ieee80211_rx_status *rx_status,5819 struct rtl8723au_phy_stats *phy_stats,5820 u32 rxmcs, struct ieee80211_hdr *hdr,5821 bool crc_icv_err)5822{5823 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;5824 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats;5825 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats;5826 5827 switch (phy_stats0->page_num) {5828 case 0:5829 /* CCK */5830 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0,5831 rxmcs, hdr, crc_icv_err);5832 break;5833 case 1:5834 /* OFDM */5835 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1,5836 rxmcs, hdr, crc_icv_err);5837 break;5838 case 2:5839 /* Also OFDM but different (how?) */5840 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2,5841 rxmcs, hdr, crc_icv_err);5842 break;5843 default:5844 return;5845 }5846}5847 5848static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)5849{5850 struct rtl8xxxu_rx_urb *rx_urb, *tmp;5851 unsigned long flags;5852 5853 spin_lock_irqsave(&priv->rx_urb_lock, flags);5854 5855 list_for_each_entry_safe(rx_urb, tmp,5856 &priv->rx_urb_pending_list, list) {5857 list_del(&rx_urb->list);5858 priv->rx_urb_pending_count--;5859 usb_free_urb(&rx_urb->urb);5860 }5861 5862 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);5863}5864 5865static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,5866 struct rtl8xxxu_rx_urb *rx_urb)5867{5868 struct sk_buff *skb;5869 unsigned long flags;5870 int pending = 0;5871 5872 spin_lock_irqsave(&priv->rx_urb_lock, flags);5873 5874 if (!priv->shutdown) {5875 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);5876 priv->rx_urb_pending_count++;5877 pending = priv->rx_urb_pending_count;5878 } else {5879 skb = (struct sk_buff *)rx_urb->urb.context;5880 dev_kfree_skb_irq(skb);5881 usb_free_urb(&rx_urb->urb);5882 }5883 5884 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);5885 5886 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)5887 schedule_work(&priv->rx_urb_wq);5888}5889 5890static void rtl8xxxu_rx_urb_work(struct work_struct *work)5891{5892 struct rtl8xxxu_priv *priv;5893 struct rtl8xxxu_rx_urb *rx_urb, *tmp;5894 struct list_head local;5895 struct sk_buff *skb;5896 unsigned long flags;5897 int ret;5898 5899 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);5900 INIT_LIST_HEAD(&local);5901 5902 spin_lock_irqsave(&priv->rx_urb_lock, flags);5903 5904 list_splice_init(&priv->rx_urb_pending_list, &local);5905 priv->rx_urb_pending_count = 0;5906 5907 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);5908 5909 list_for_each_entry_safe(rx_urb, tmp, &local, list) {5910 list_del_init(&rx_urb->list);5911 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);5912 /*5913 * If out of memory or temporary error, put it back on the5914 * queue and try again. Otherwise the device is dead/gone5915 * and we should drop it.5916 */5917 switch (ret) {5918 case 0:5919 break;5920 case -ENOMEM:5921 case -EAGAIN:5922 rtl8xxxu_queue_rx_urb(priv, rx_urb);5923 break;5924 default:5925 dev_warn(&priv->udev->dev,5926 "failed to requeue urb with error %i\n", ret);5927 skb = (struct sk_buff *)rx_urb->urb.context;5928 dev_kfree_skb(skb);5929 usb_free_urb(&rx_urb->urb);5930 }5931 }5932}5933 5934/*5935 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type5936 * 0-7 to represent writing different combinations of register values5937 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use5938 * cases which Realtek doesn't provide detail for these settings. Keep5939 * this aligned with vendor driver for easier maintenance.5940 */5941static5942void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type)5943{5944 switch (type) {5945 case 0:5946 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);5947 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);5948 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);5949 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);5950 break;5951 case 1:5952 case 3:5953 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);5954 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);5955 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);5956 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);5957 break;5958 case 2:5959 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);5960 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);5961 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);5962 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);5963 break;5964 case 4:5965 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);5966 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a);5967 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);5968 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);5969 break;5970 case 5:5971 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);5972 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a);5973 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);5974 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);5975 break;5976 case 6:5977 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);5978 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);5979 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);5980 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);5981 break;5982 case 7:5983 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa);5984 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);5985 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);5986 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);5987 break;5988 default:5989 break;5990 }5991}5992 5993static5994void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info)5995{5996 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex;5997 5998 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)5999 btcoex->c2h_bt_inquiry = true;6000 else6001 btcoex->c2h_bt_inquiry = false;6002 6003 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {6004 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE;6005 btcoex->has_sco = false;6006 btcoex->has_hid = false;6007 btcoex->has_pan = false;6008 btcoex->has_a2dp = false;6009 } else {6010 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION)6011 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE;6012 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||6013 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))6014 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY;6015 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY)6016 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY;6017 else6018 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX;6019 6020 if (bt_info & BT_INFO_8723B_1ANT_B_FTP)6021 btcoex->has_pan = true;6022 else6023 btcoex->has_pan = false;6024 6025 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP)6026 btcoex->has_a2dp = true;6027 else6028 btcoex->has_a2dp = false;6029 6030 if (bt_info & BT_INFO_8723B_1ANT_B_HID)6031 btcoex->has_hid = true;6032 else6033 btcoex->has_hid = false;6034 6035 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO)6036 btcoex->has_sco = true;6037 else6038 btcoex->has_sco = false;6039 }6040 6041 if (!btcoex->has_a2dp && !btcoex->has_sco &&6042 !btcoex->has_pan && btcoex->has_hid)6043 btcoex->hid_only = true;6044 else6045 btcoex->hid_only = false;6046 6047 if (!btcoex->has_sco && !btcoex->has_pan &&6048 !btcoex->has_hid && btcoex->has_a2dp)6049 btcoex->has_a2dp = true;6050 else6051 btcoex->has_a2dp = false;6052 6053 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY ||6054 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY)6055 btcoex->bt_busy = true;6056 else6057 btcoex->bt_busy = false;6058}6059 6060static inline bool rtl8xxxu_is_assoc(struct rtl8xxxu_priv *priv)6061{6062 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc) ||6063 (priv->vifs[1] && priv->vifs[1]->cfg.assoc);6064}6065 6066static6067void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv)6068{6069 struct rtl8xxxu_btcoex *btcoex;6070 6071 btcoex = &priv->bt_coex;6072 6073 if (!rtl8xxxu_is_assoc(priv)) {6074 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);6075 rtl8723bu_set_coex_with_type(priv, 0);6076 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) {6077 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11);6078 rtl8723bu_set_coex_with_type(priv, 4);6079 } else if (btcoex->has_pan) {6080 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11);6081 rtl8723bu_set_coex_with_type(priv, 4);6082 } else {6083 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);6084 rtl8723bu_set_coex_with_type(priv, 7);6085 }6086}6087 6088static6089void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv)6090{6091 struct rtl8xxxu_btcoex *btcoex;6092 6093 btcoex = &priv->bt_coex;6094 6095 if (rtl8xxxu_is_assoc(priv)) {6096 u32 val32 = 0;6097 u32 high_prio_tx = 0, high_prio_rx = 0;6098 6099 val32 = rtl8xxxu_read32(priv, 0x770);6100 high_prio_tx = val32 & 0x0000ffff;6101 high_prio_rx = (val32 & 0xffff0000) >> 16;6102 6103 if (btcoex->bt_busy) {6104 if (btcoex->hid_only) {6105 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20,6106 0x3, 0x11, 0x11);6107 rtl8723bu_set_coex_with_type(priv, 5);6108 } else if (btcoex->a2dp_only) {6109 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,6110 0x3, 0x11, 0x11);6111 rtl8723bu_set_coex_with_type(priv, 4);6112 } else if ((btcoex->has_a2dp && btcoex->has_pan) ||6113 (btcoex->has_hid && btcoex->has_a2dp &&6114 btcoex->has_pan)) {6115 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,6116 0x3, 0x10, 0x10);6117 rtl8723bu_set_coex_with_type(priv, 4);6118 } else if (btcoex->has_hid && btcoex->has_a2dp) {6119 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,6120 0x3, 0x10, 0x10);6121 rtl8723bu_set_coex_with_type(priv, 3);6122 } else {6123 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,6124 0x3, 0x11, 0x11);6125 rtl8723bu_set_coex_with_type(priv, 4);6126 }6127 } else {6128 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);6129 if (high_prio_tx + high_prio_rx <= 60)6130 rtl8723bu_set_coex_with_type(priv, 2);6131 else6132 rtl8723bu_set_coex_with_type(priv, 7);6133 }6134 } else {6135 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);6136 rtl8723bu_set_coex_with_type(priv, 0);6137 }6138}6139 6140static void rtl8xxxu_c2hcmd_callback(struct work_struct *work)6141{6142 struct rtl8xxxu_priv *priv;6143 struct rtl8723bu_c2h *c2h;6144 struct sk_buff *skb = NULL;6145 u8 bt_info = 0;6146 struct rtl8xxxu_btcoex *btcoex;6147 struct rtl8xxxu_ra_report *rarpt;6148 u8 bw;6149 6150 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);6151 btcoex = &priv->bt_coex;6152 rarpt = &priv->ra_report;6153 6154 while (!skb_queue_empty(&priv->c2hcmd_queue)) {6155 skb = skb_dequeue(&priv->c2hcmd_queue);6156 6157 c2h = (struct rtl8723bu_c2h *)skb->data;6158 6159 switch (c2h->id) {6160 case C2H_8723B_BT_INFO:6161 bt_info = c2h->bt_info.bt_info;6162 6163 rtl8723bu_update_bt_link_info(priv, bt_info);6164 if (btcoex->c2h_bt_inquiry) {6165 rtl8723bu_handle_bt_inquiry(priv);6166 break;6167 }6168 rtl8723bu_handle_bt_info(priv);6169 break;6170 case C2H_8723B_RA_REPORT:6171 bw = rarpt->txrate.bw;6172 6173 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) {6174 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40)6175 bw = RATE_INFO_BW_40;6176 else6177 bw = RATE_INFO_BW_20;6178 }6179 6180 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate,6181 c2h->ra_report.sgi, bw);6182 break;6183 default:6184 break;6185 }6186 6187 dev_kfree_skb(skb);6188 }6189}6190 6191static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,6192 struct sk_buff *skb)6193{6194 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;6195 struct device *dev = &priv->udev->dev;6196 int len;6197 6198 len = skb->len - 2;6199 6200 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",6201 c2h->id, c2h->seq, len, c2h->bt_info.response_source);6202 6203 switch(c2h->id) {6204 case C2H_8723B_BT_INFO:6205 if (c2h->bt_info.response_source >6206 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)6207 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");6208 else6209 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");6210 6211 if (c2h->bt_info.bt_has_reset)6212 dev_dbg(dev, "BT has been reset\n");6213 if (c2h->bt_info.tx_rx_mask)6214 dev_dbg(dev, "BT TRx mask\n");6215 6216 break;6217 case C2H_8723B_BT_MP_INFO:6218 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",6219 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);6220 break;6221 case C2H_8723B_RA_REPORT:6222 dev_dbg(dev,6223 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",6224 c2h->ra_report.rate, c2h->ra_report.sgi,6225 c2h->ra_report.macid, c2h->ra_report.noisy_state);6226 break;6227 default:6228 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",6229 c2h->id, c2h->seq);6230 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,6231 16, 1, c2h->raw.payload, len, false);6232 break;6233 }6234 6235 skb_queue_tail(&priv->c2hcmd_queue, skb);6236 6237 schedule_work(&priv->c2hcmd_work);6238}6239 6240static void rtl8188e_c2hcmd_callback(struct work_struct *work)6241{6242 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);6243 struct device *dev = &priv->udev->dev;6244 struct sk_buff *skb = NULL;6245 struct rtl8xxxu_rxdesc16 *rx_desc;6246 6247 while (!skb_queue_empty(&priv->c2hcmd_queue)) {6248 skb = skb_dequeue(&priv->c2hcmd_queue);6249 6250 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16));6251 6252 switch (rx_desc->rpt_sel) {6253 case 1:6254 dev_dbg(dev, "C2H TX report type 1\n");6255 6256 break;6257 case 2:6258 dev_dbg(dev, "C2H TX report type 2\n");6259 6260 rtl8188e_handle_ra_tx_report2(priv, skb);6261 6262 break;6263 case 3:6264 dev_dbg(dev, "C2H USB interrupt report\n");6265 6266 break;6267 default:6268 dev_warn(dev, "%s: rpt_sel should not be %d\n",6269 __func__, rx_desc->rpt_sel);6270 6271 break;6272 }6273 6274 dev_kfree_skb(skb);6275 }6276}6277 6278#define rtl8xxxu_iterate_vifs_atomic(priv, iterator, data) \6279 ieee80211_iterate_active_interfaces_atomic((priv)->hw, \6280 IEEE80211_IFACE_ITER_NORMAL, iterator, data)6281 6282struct rtl8xxxu_rx_update_rssi_data {6283 struct rtl8xxxu_priv *priv;6284 struct ieee80211_hdr *hdr;6285 struct ieee80211_rx_status *rx_status;6286 u8 *bssid;6287};6288 6289static void rtl8xxxu_rx_update_rssi_iter(void *data, u8 *mac,6290 struct ieee80211_vif *vif)6291{6292 struct rtl8xxxu_rx_update_rssi_data *iter_data = data;6293 struct ieee80211_sta *sta;6294 struct ieee80211_hdr *hdr = iter_data->hdr;6295 struct rtl8xxxu_priv *priv = iter_data->priv;6296 struct rtl8xxxu_sta_info *sta_info;6297 struct ieee80211_rx_status *rx_status = iter_data->rx_status;6298 u8 *bssid = iter_data->bssid;6299 6300 if (!ether_addr_equal(vif->bss_conf.bssid, bssid))6301 return;6302 6303 if (!(ether_addr_equal(vif->addr, hdr->addr1) ||6304 ieee80211_is_beacon(hdr->frame_control)))6305 return;6306 6307 sta = ieee80211_find_sta_by_ifaddr(priv->hw, hdr->addr2,6308 vif->addr);6309 if (!sta)6310 return;6311 6312 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;6313 ewma_rssi_add(&sta_info->avg_rssi, -rx_status->signal);6314}6315 6316static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)6317{6318 __le16 fc = hdr->frame_control;6319 u8 *bssid;6320 6321 if (ieee80211_has_tods(fc))6322 bssid = hdr->addr1;6323 else if (ieee80211_has_fromds(fc))6324 bssid = hdr->addr2;6325 else6326 bssid = hdr->addr3;6327 6328 return bssid;6329}6330 6331static void rtl8xxxu_rx_update_rssi(struct rtl8xxxu_priv *priv,6332 struct ieee80211_rx_status *rx_status,6333 struct ieee80211_hdr *hdr)6334{6335 struct rtl8xxxu_rx_update_rssi_data data = {};6336 6337 if (ieee80211_is_ctl(hdr->frame_control))6338 return;6339 6340 data.priv = priv;6341 data.hdr = hdr;6342 data.rx_status = rx_status;6343 data.bssid = get_hdr_bssid(hdr);6344 6345 rtl8xxxu_iterate_vifs_atomic(priv, rtl8xxxu_rx_update_rssi_iter, &data);6346}6347 6348int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)6349{6350 struct ieee80211_hw *hw = priv->hw;6351 struct ieee80211_rx_status *rx_status;6352 struct rtl8xxxu_rxdesc16 *rx_desc;6353 struct rtl8723au_phy_stats *phy_stats;6354 struct sk_buff *next_skb = NULL;6355 __le32 *_rx_desc_le;6356 u32 *_rx_desc;6357 int drvinfo_sz, desc_shift;6358 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;6359 6360 urb_len = skb->len;6361 pkt_cnt = 0;6362 6363 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) {6364 kfree_skb(skb);6365 return RX_TYPE_ERROR;6366 }6367 6368 do {6369 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;6370 _rx_desc_le = (__le32 *)skb->data;6371 _rx_desc = (u32 *)skb->data;6372 6373 for (i = 0;6374 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)6375 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);6376 6377 /*6378 * Only read pkt_cnt from the header if we're parsing the6379 * first packet6380 */6381 if (!pkt_cnt)6382 pkt_cnt = rx_desc->pkt_cnt;6383 pkt_len = rx_desc->pktlen;6384 6385 drvinfo_sz = rx_desc->drvinfo_sz * 8;6386 desc_shift = rx_desc->shift;6387 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +6388 sizeof(struct rtl8xxxu_rxdesc16), 128);6389 6390 /*6391 * Only clone the skb if there's enough data at the end to6392 * at least cover the rx descriptor6393 */6394 if (pkt_cnt > 1 &&6395 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))6396 next_skb = skb_clone(skb, GFP_ATOMIC);6397 6398 rx_status = IEEE80211_SKB_RXCB(skb);6399 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));6400 6401 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));6402 6403 if (rx_desc->rpt_sel) {6404 skb_queue_tail(&priv->c2hcmd_queue, skb);6405 schedule_work(&priv->c2hcmd_work);6406 } else {6407 struct ieee80211_hdr *hdr;6408 6409 phy_stats = (struct rtl8723au_phy_stats *)skb->data;6410 6411 skb_pull(skb, drvinfo_sz + desc_shift);6412 6413 skb_trim(skb, pkt_len);6414 6415 hdr = (struct ieee80211_hdr *)skb->data;6416 if (rx_desc->phy_stats) {6417 priv->fops->parse_phystats(6418 priv, rx_status, phy_stats,6419 rx_desc->rxmcs,6420 hdr,6421 rx_desc->crc32 || rx_desc->icverr);6422 if (!rx_desc->crc32 && !rx_desc->icverr)6423 rtl8xxxu_rx_update_rssi(priv,6424 rx_status,6425 hdr);6426 }6427 6428 rx_status->mactime = rx_desc->tsfl;6429 rx_status->flag |= RX_FLAG_MACTIME_START;6430 6431 if (!rx_desc->swdec &&6432 rx_desc->security != RX_DESC_ENC_NONE)6433 rx_status->flag |= RX_FLAG_DECRYPTED;6434 if (rx_desc->crc32)6435 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;6436 if (rx_desc->bw)6437 rx_status->bw = RATE_INFO_BW_40;6438 6439 if (rx_desc->rxht) {6440 rx_status->encoding = RX_ENC_HT;6441 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;6442 } else {6443 rx_status->rate_idx = rx_desc->rxmcs;6444 }6445 6446 rx_status->freq = hw->conf.chandef.chan->center_freq;6447 rx_status->band = hw->conf.chandef.chan->band;6448 6449 ieee80211_rx_irqsafe(hw, skb);6450 }6451 6452 skb = next_skb;6453 if (skb)6454 skb_pull(next_skb, pkt_offset);6455 6456 pkt_cnt--;6457 urb_len -= pkt_offset;6458 next_skb = NULL;6459 } while (skb && pkt_cnt > 0 &&6460 urb_len >= sizeof(struct rtl8xxxu_rxdesc16));6461 6462 return RX_TYPE_DATA_PKT;6463}6464 6465int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)6466{6467 struct ieee80211_hw *hw = priv->hw;6468 struct ieee80211_rx_status *rx_status;6469 struct rtl8xxxu_rxdesc24 *rx_desc;6470 struct rtl8723au_phy_stats *phy_stats;6471 struct sk_buff *next_skb = NULL;6472 __le32 *_rx_desc_le;6473 u32 *_rx_desc;6474 int drvinfo_sz, desc_shift;6475 int i, pkt_len, urb_len, pkt_offset;6476 6477 urb_len = skb->len;6478 6479 if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) {6480 kfree_skb(skb);6481 return RX_TYPE_ERROR;6482 }6483 6484 do {6485 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data;6486 _rx_desc_le = (__le32 *)skb->data;6487 _rx_desc = (u32 *)skb->data;6488 6489 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)6490 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);6491 6492 pkt_len = rx_desc->pktlen;6493 6494 drvinfo_sz = rx_desc->drvinfo_sz * 8;6495 desc_shift = rx_desc->shift;6496 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +6497 sizeof(struct rtl8xxxu_rxdesc24), 8);6498 6499 /*6500 * Only clone the skb if there's enough data at the end to6501 * at least cover the rx descriptor6502 */6503 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24)))6504 next_skb = skb_clone(skb, GFP_ATOMIC);6505 6506 rx_status = IEEE80211_SKB_RXCB(skb);6507 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));6508 6509 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));6510 6511 phy_stats = (struct rtl8723au_phy_stats *)skb->data;6512 6513 skb_pull(skb, drvinfo_sz + desc_shift);6514 6515 skb_trim(skb, pkt_len);6516 6517 if (rx_desc->rpt_sel) {6518 struct device *dev = &priv->udev->dev;6519 dev_dbg(dev, "%s: C2H packet\n", __func__);6520 rtl8723bu_handle_c2h(priv, skb);6521 } else {6522 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;6523 6524 if (rx_desc->phy_stats) {6525 priv->fops->parse_phystats(priv, rx_status, phy_stats,6526 rx_desc->rxmcs, hdr,6527 rx_desc->crc32 || rx_desc->icverr);6528 if (!rx_desc->crc32 && !rx_desc->icverr)6529 rtl8xxxu_rx_update_rssi(priv,6530 rx_status,6531 hdr);6532 }6533 6534 rx_status->mactime = rx_desc->tsfl;6535 rx_status->flag |= RX_FLAG_MACTIME_START;6536 6537 if (!rx_desc->swdec &&6538 rx_desc->security != RX_DESC_ENC_NONE)6539 rx_status->flag |= RX_FLAG_DECRYPTED;6540 if (rx_desc->crc32)6541 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;6542 if (rx_desc->bw)6543 rx_status->bw = RATE_INFO_BW_40;6544 6545 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {6546 rx_status->encoding = RX_ENC_HT;6547 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;6548 } else {6549 rx_status->rate_idx = rx_desc->rxmcs;6550 }6551 6552 rx_status->freq = hw->conf.chandef.chan->center_freq;6553 rx_status->band = hw->conf.chandef.chan->band;6554 6555 ieee80211_rx_irqsafe(hw, skb);6556 }6557 6558 skb = next_skb;6559 if (skb)6560 skb_pull(next_skb, pkt_offset);6561 6562 urb_len -= pkt_offset;6563 next_skb = NULL;6564 } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24));6565 6566 return RX_TYPE_DATA_PKT;6567}6568 6569static void rtl8xxxu_rx_complete(struct urb *urb)6570{6571 struct rtl8xxxu_rx_urb *rx_urb =6572 container_of(urb, struct rtl8xxxu_rx_urb, urb);6573 struct ieee80211_hw *hw = rx_urb->hw;6574 struct rtl8xxxu_priv *priv = hw->priv;6575 struct sk_buff *skb = (struct sk_buff *)urb->context;6576 struct device *dev = &priv->udev->dev;6577 6578 skb_put(skb, urb->actual_length);6579 6580 if (urb->status == 0) {6581 priv->fops->parse_rx_desc(priv, skb);6582 6583 skb = NULL;6584 rx_urb->urb.context = NULL;6585 rtl8xxxu_queue_rx_urb(priv, rx_urb);6586 } else {6587 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);6588 goto cleanup;6589 }6590 return;6591 6592cleanup:6593 usb_free_urb(urb);6594 dev_kfree_skb(skb);6595}6596 6597static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,6598 struct rtl8xxxu_rx_urb *rx_urb)6599{6600 struct rtl8xxxu_fileops *fops = priv->fops;6601 struct sk_buff *skb;6602 int skb_size;6603 int ret, rx_desc_sz;6604 6605 rx_desc_sz = fops->rx_desc_size;6606 6607 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {6608 skb_size = fops->rx_agg_buf_size;6609 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));6610 } else {6611 skb_size = IEEE80211_MAX_FRAME_LEN;6612 }6613 6614 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);6615 if (!skb)6616 return -ENOMEM;6617 6618 memset(skb->data, 0, rx_desc_sz);6619 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,6620 skb_size, rtl8xxxu_rx_complete, skb);6621 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);6622 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);6623 if (ret)6624 usb_unanchor_urb(&rx_urb->urb);6625 return ret;6626}6627 6628static void rtl8xxxu_int_complete(struct urb *urb)6629{6630 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;6631 struct device *dev = &priv->udev->dev;6632 int ret;6633 6634 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)6635 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);6636 if (urb->status == 0) {6637 usb_anchor_urb(urb, &priv->int_anchor);6638 ret = usb_submit_urb(urb, GFP_ATOMIC);6639 if (ret)6640 usb_unanchor_urb(urb);6641 } else {6642 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);6643 }6644}6645 6646 6647static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)6648{6649 struct rtl8xxxu_priv *priv = hw->priv;6650 struct urb *urb;6651 u32 val32;6652 int ret;6653 6654 urb = usb_alloc_urb(0, GFP_KERNEL);6655 if (!urb)6656 return -ENOMEM;6657 6658 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,6659 priv->int_buf, USB_INTR_CONTENT_LENGTH,6660 rtl8xxxu_int_complete, priv, 1);6661 usb_anchor_urb(urb, &priv->int_anchor);6662 ret = usb_submit_urb(urb, GFP_KERNEL);6663 if (ret) {6664 usb_unanchor_urb(urb);6665 goto error;6666 }6667 6668 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);6669 val32 |= USB_HIMR_CPWM;6670 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);6671 6672error:6673 usb_free_urb(urb);6674 return ret;6675}6676 6677static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv)6678{6679 u8 macid[ETH_ALEN], bssid[ETH_ALEN], macid_1[ETH_ALEN], bssid_1[ETH_ALEN];6680 u8 msr, bcn_ctrl, bcn_ctrl_1, atimwnd[2], atimwnd_1[2];6681 struct rtl8xxxu_vif *rtlvif;6682 u8 tsftr[8], tsftr_1[8];6683 int i;6684 6685 msr = rtl8xxxu_read8(priv, REG_MSR);6686 bcn_ctrl = rtl8xxxu_read8(priv, REG_BEACON_CTRL);6687 bcn_ctrl_1 = rtl8xxxu_read8(priv, REG_BEACON_CTRL_1);6688 6689 for (i = 0; i < ARRAY_SIZE(atimwnd); i++)6690 atimwnd[i] = rtl8xxxu_read8(priv, REG_ATIMWND + i);6691 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++)6692 atimwnd_1[i] = rtl8xxxu_read8(priv, REG_ATIMWND_1 + i);6693 6694 for (i = 0; i < ARRAY_SIZE(tsftr); i++)6695 tsftr[i] = rtl8xxxu_read8(priv, REG_TSFTR + i);6696 for (i = 0; i < ARRAY_SIZE(tsftr); i++)6697 tsftr_1[i] = rtl8xxxu_read8(priv, REG_TSFTR1 + i);6698 6699 for (i = 0; i < ARRAY_SIZE(macid); i++)6700 macid[i] = rtl8xxxu_read8(priv, REG_MACID + i);6701 6702 for (i = 0; i < ARRAY_SIZE(bssid); i++)6703 bssid[i] = rtl8xxxu_read8(priv, REG_BSSID + i);6704 6705 for (i = 0; i < ARRAY_SIZE(macid_1); i++)6706 macid_1[i] = rtl8xxxu_read8(priv, REG_MACID1 + i);6707 6708 for (i = 0; i < ARRAY_SIZE(bssid_1); i++)6709 bssid_1[i] = rtl8xxxu_read8(priv, REG_BSSID1 + i);6710 6711 /* disable bcn function, disable update TSF */6712 rtl8xxxu_write8(priv, REG_BEACON_CTRL, (bcn_ctrl &6713 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE);6714 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, (bcn_ctrl_1 &6715 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE);6716 6717 /* switch msr */6718 msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2);6719 rtl8xxxu_write8(priv, REG_MSR, msr);6720 6721 /* write port0 */6722 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1 & ~BEACON_FUNCTION_ENABLE);6723 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++)6724 rtl8xxxu_write8(priv, REG_ATIMWND + i, atimwnd_1[i]);6725 for (i = 0; i < ARRAY_SIZE(tsftr_1); i++)6726 rtl8xxxu_write8(priv, REG_TSFTR + i, tsftr_1[i]);6727 for (i = 0; i < ARRAY_SIZE(macid_1); i++)6728 rtl8xxxu_write8(priv, REG_MACID + i, macid_1[i]);6729 for (i = 0; i < ARRAY_SIZE(bssid_1); i++)6730 rtl8xxxu_write8(priv, REG_BSSID + i, bssid_1[i]);6731 6732 /* write port1 */6733 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl & ~BEACON_FUNCTION_ENABLE);6734 for (i = 0; i < ARRAY_SIZE(atimwnd); i++)6735 rtl8xxxu_write8(priv, REG_ATIMWND_1 + i, atimwnd[i]);6736 for (i = 0; i < ARRAY_SIZE(tsftr); i++)6737 rtl8xxxu_write8(priv, REG_TSFTR1 + i, tsftr[i]);6738 for (i = 0; i < ARRAY_SIZE(macid); i++)6739 rtl8xxxu_write8(priv, REG_MACID1 + i, macid[i]);6740 for (i = 0; i < ARRAY_SIZE(bssid); i++)6741 rtl8xxxu_write8(priv, REG_BSSID1 + i, bssid[i]);6742 6743 /* write bcn ctl */6744 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1);6745 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl);6746 swap(priv->vifs[0], priv->vifs[1]);6747 6748 /* priv->vifs[0] is NULL here, based on how this function is currently6749 * called from rtl8xxxu_add_interface().6750 * When this function will be used in the future for a different6751 * scenario, please check whether vifs[0] or vifs[1] can be NULL and if6752 * necessary add code to set port_num = 1.6753 */6754 rtlvif = (struct rtl8xxxu_vif *)priv->vifs[1]->drv_priv;6755 rtlvif->port_num = 1;6756}6757 6758static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,6759 struct ieee80211_vif *vif)6760{6761 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;6762 struct rtl8xxxu_priv *priv = hw->priv;6763 int port_num;6764 u8 val8;6765 6766 if (!priv->vifs[0])6767 port_num = 0;6768 else if (!priv->vifs[1])6769 port_num = 1;6770 else6771 return -EOPNOTSUPP;6772 6773 switch (vif->type) {6774 case NL80211_IFTYPE_STATION:6775 if (port_num == 0) {6776 rtl8xxxu_stop_tx_beacon(priv);6777 6778 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);6779 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |6780 BEACON_DISABLE_TSF_UPDATE;6781 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);6782 }6783 break;6784 case NL80211_IFTYPE_AP:6785 if (port_num == 1) {6786 rtl8xxxu_switch_ports(priv);6787 port_num = 0;6788 }6789 6790 rtl8xxxu_write8(priv, REG_BEACON_CTRL,6791 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID);6792 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */6793 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */6794 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0);6795 6796 /* enable BCN0 function */6797 rtl8xxxu_write8(priv, REG_BEACON_CTRL,6798 BEACON_DISABLE_TSF_UPDATE |6799 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID |6800 BEACON_CTRL_TX_BEACON_RPT);6801 6802 /* select BCN on port 0 */6803 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK);6804 val8 &= ~BIT_BCN_PORT_SEL;6805 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8);6806 break;6807 default:6808 return -EOPNOTSUPP;6809 }6810 6811 priv->vifs[port_num] = vif;6812 rtlvif->port_num = port_num;6813 rtlvif->hw_key_idx = 0xff;6814 6815 rtl8xxxu_set_linktype(priv, vif->type, port_num);6816 ether_addr_copy(priv->mac_addr, vif->addr);6817 rtl8xxxu_set_mac(priv, port_num);6818 6819 return 0;6820}6821 6822static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,6823 struct ieee80211_vif *vif)6824{6825 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;6826 struct rtl8xxxu_priv *priv = hw->priv;6827 6828 dev_dbg(&priv->udev->dev, "%s\n", __func__);6829 6830 priv->vifs[rtlvif->port_num] = NULL;6831}6832 6833static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)6834{6835 struct rtl8xxxu_priv *priv = hw->priv;6836 struct device *dev = &priv->udev->dev;6837 int ret = 0, channel;6838 bool ht40;6839 6840 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)6841 dev_info(dev,6842 "%s: channel: %i (changed %08x chandef.width %02x)\n",6843 __func__, hw->conf.chandef.chan->hw_value,6844 changed, hw->conf.chandef.width);6845 6846 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {6847 switch (hw->conf.chandef.width) {6848 case NL80211_CHAN_WIDTH_20_NOHT:6849 case NL80211_CHAN_WIDTH_20:6850 ht40 = false;6851 break;6852 case NL80211_CHAN_WIDTH_40:6853 ht40 = true;6854 break;6855 default:6856 ret = -ENOTSUPP;6857 goto exit;6858 }6859 6860 channel = hw->conf.chandef.chan->hw_value;6861 6862 priv->fops->set_tx_power(priv, channel, ht40);6863 6864 priv->fops->config_channel(hw);6865 }6866 6867exit:6868 return ret;6869}6870 6871static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,6872 struct ieee80211_vif *vif,6873 unsigned int link_id, u16 queue,6874 const struct ieee80211_tx_queue_params *param)6875{6876 struct rtl8xxxu_priv *priv = hw->priv;6877 struct device *dev = &priv->udev->dev;6878 u32 val32;6879 u8 aifs, acm_ctrl, acm_bit;6880 6881 aifs = param->aifs;6882 6883 val32 = aifs |6884 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |6885 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |6886 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;6887 6888 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);6889 dev_dbg(dev,6890 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",6891 __func__, queue, val32, param->acm, acm_ctrl);6892 6893 switch (queue) {6894 case IEEE80211_AC_VO:6895 acm_bit = ACM_HW_CTRL_VO;6896 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);6897 break;6898 case IEEE80211_AC_VI:6899 acm_bit = ACM_HW_CTRL_VI;6900 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);6901 break;6902 case IEEE80211_AC_BE:6903 acm_bit = ACM_HW_CTRL_BE;6904 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);6905 break;6906 case IEEE80211_AC_BK:6907 acm_bit = ACM_HW_CTRL_BK;6908 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);6909 break;6910 default:6911 acm_bit = 0;6912 break;6913 }6914 6915 if (param->acm)6916 acm_ctrl |= acm_bit;6917 else6918 acm_ctrl &= ~acm_bit;6919 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);6920 6921 return 0;6922}6923 6924static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,6925 unsigned int changed_flags,6926 unsigned int *total_flags, u64 multicast)6927{6928 struct rtl8xxxu_priv *priv = hw->priv;6929 u32 rcr = priv->regrcr;6930 6931 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",6932 __func__, changed_flags, *total_flags);6933 6934 /*6935 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)6936 */6937 6938 if (*total_flags & FIF_FCSFAIL)6939 rcr |= RCR_ACCEPT_CRC32;6940 else6941 rcr &= ~RCR_ACCEPT_CRC32;6942 6943 /*6944 * FIF_PLCPFAIL not supported?6945 */6946 6947 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)6948 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH);6949 else6950 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH;6951 6952 if (priv->vifs[0] && priv->vifs[0]->type == NL80211_IFTYPE_AP)6953 rcr &= ~(RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON);6954 6955 if (*total_flags & FIF_CONTROL)6956 rcr |= RCR_ACCEPT_CTRL_FRAME;6957 else6958 rcr &= ~RCR_ACCEPT_CTRL_FRAME;6959 6960 if (*total_flags & FIF_OTHER_BSS)6961 rcr |= RCR_ACCEPT_AP;6962 else6963 rcr &= ~RCR_ACCEPT_AP;6964 6965 if (*total_flags & FIF_PSPOLL)6966 rcr |= RCR_ACCEPT_PM;6967 else6968 rcr &= ~RCR_ACCEPT_PM;6969 6970 /*6971 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted6972 */6973 6974 rtl8xxxu_write32(priv, REG_RCR, rcr);6975 priv->regrcr = rcr;6976 6977 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |6978 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |6979 FIF_PROBE_REQ);6980}6981 6982static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)6983{6984 if (rts > 2347 && rts != (u32)-1)6985 return -EINVAL;6986 6987 return 0;6988}6989 6990static int rtl8xxxu_get_free_sec_cam(struct ieee80211_hw *hw)6991{6992 struct rtl8xxxu_priv *priv = hw->priv;6993 6994 return find_first_zero_bit(priv->cam_map, priv->fops->max_sec_cam_num);6995}6996 6997static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,6998 struct ieee80211_vif *vif,6999 struct ieee80211_sta *sta,7000 struct ieee80211_key_conf *key)7001{7002 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;7003 struct rtl8xxxu_priv *priv = hw->priv;7004 struct device *dev = &priv->udev->dev;7005 u8 mac_addr[ETH_ALEN];7006 u8 val8;7007 u16 val16;7008 u32 val32;7009 int retval = -EOPNOTSUPP;7010 7011 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",7012 __func__, cmd, key->cipher, key->keyidx);7013 7014 if (key->keyidx > 3)7015 return -EOPNOTSUPP;7016 7017 switch (key->cipher) {7018 case WLAN_CIPHER_SUITE_WEP40:7019 case WLAN_CIPHER_SUITE_WEP104:7020 7021 break;7022 case WLAN_CIPHER_SUITE_CCMP:7023 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;7024 break;7025 case WLAN_CIPHER_SUITE_TKIP:7026 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;7027 break;7028 default:7029 return -EOPNOTSUPP;7030 }7031 7032 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {7033 dev_dbg(dev, "%s: pairwise key\n", __func__);7034 ether_addr_copy(mac_addr, sta->addr);7035 } else {7036 dev_dbg(dev, "%s: group key\n", __func__);7037 ether_addr_copy(mac_addr, vif->bss_conf.bssid);7038 }7039 7040 val16 = rtl8xxxu_read16(priv, REG_CR);7041 val16 |= CR_SECURITY_ENABLE;7042 rtl8xxxu_write16(priv, REG_CR, val16);7043 7044 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |7045 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;7046 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;7047 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);7048 7049 switch (cmd) {7050 case SET_KEY:7051 7052 retval = rtl8xxxu_get_free_sec_cam(hw);7053 if (retval < 0)7054 return -EOPNOTSUPP;7055 7056 key->hw_key_idx = retval;7057 7058 if (vif->type == NL80211_IFTYPE_AP && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))7059 rtlvif->hw_key_idx = key->hw_key_idx;7060 7061 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;7062 rtl8xxxu_cam_write(priv, key, mac_addr);7063 set_bit(key->hw_key_idx, priv->cam_map);7064 retval = 0;7065 break;7066 case DISABLE_KEY:7067 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);7068 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |7069 key->hw_key_idx << CAM_CMD_KEY_SHIFT;7070 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);7071 rtlvif->hw_key_idx = 0xff;7072 clear_bit(key->hw_key_idx, priv->cam_map);7073 retval = 0;7074 break;7075 default:7076 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);7077 }7078 7079 return retval;7080}7081 7082static int7083rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,7084 struct ieee80211_ampdu_params *params)7085{7086 struct rtl8xxxu_priv *priv = hw->priv;7087 struct device *dev = &priv->udev->dev;7088 u8 ampdu_factor, ampdu_density;7089 struct ieee80211_sta *sta = params->sta;7090 u16 tid = params->tid;7091 enum ieee80211_ampdu_mlme_action action = params->action;7092 7093 switch (action) {7094 case IEEE80211_AMPDU_TX_START:7095 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);7096 ampdu_factor = sta->deflink.ht_cap.ampdu_factor;7097 ampdu_density = sta->deflink.ht_cap.ampdu_density;7098 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);7099 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);7100 dev_dbg(dev,7101 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",7102 ampdu_factor, ampdu_density);7103 return IEEE80211_AMPDU_TX_START_IMMEDIATE;7104 case IEEE80211_AMPDU_TX_STOP_CONT:7105 case IEEE80211_AMPDU_TX_STOP_FLUSH:7106 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:7107 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__);7108 rtl8xxxu_set_ampdu_factor(priv, 0);7109 rtl8xxxu_set_ampdu_min_space(priv, 0);7110 clear_bit(tid, priv->tx_aggr_started);7111 clear_bit(tid, priv->tid_tx_operational);7112 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);7113 break;7114 case IEEE80211_AMPDU_TX_OPERATIONAL:7115 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__);7116 set_bit(tid, priv->tid_tx_operational);7117 break;7118 case IEEE80211_AMPDU_RX_START:7119 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);7120 break;7121 case IEEE80211_AMPDU_RX_STOP:7122 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);7123 break;7124 default:7125 break;7126 }7127 return 0;7128}7129 7130static void7131rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif,7132 struct ieee80211_sta *sta, struct station_info *sinfo)7133{7134 struct rtl8xxxu_priv *priv = hw->priv;7135 7136 sinfo->txrate = priv->ra_report.txrate;7137 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);7138}7139 7140static u8 rtl8xxxu_signal_to_snr(int signal)7141{7142 if (signal < RTL8XXXU_NOISE_FLOOR_MIN)7143 signal = RTL8XXXU_NOISE_FLOOR_MIN;7144 else if (signal > 0)7145 signal = 0;7146 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN);7147}7148 7149static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,7150 int signal, struct ieee80211_sta *sta,7151 bool force)7152{7153 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;7154 struct ieee80211_hw *hw = priv->hw;7155 u16 wireless_mode;7156 u8 rssi_level, ratr_idx;7157 u8 txbw_40mhz;7158 u8 snr, snr_thresh_high, snr_thresh_low;7159 u8 go_up_gap = 5;7160 u8 macid = rtl8xxxu_get_macid(priv, sta);7161 7162 rssi_level = sta_info->rssi_level;7163 snr = rtl8xxxu_signal_to_snr(signal);7164 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH;7165 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW;7166 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0;7167 7168 switch (rssi_level) {7169 case RTL8XXXU_RATR_STA_MID:7170 snr_thresh_high += go_up_gap;7171 break;7172 case RTL8XXXU_RATR_STA_LOW:7173 snr_thresh_high += go_up_gap;7174 snr_thresh_low += go_up_gap;7175 break;7176 default:7177 break;7178 }7179 7180 if (snr > snr_thresh_high)7181 rssi_level = RTL8XXXU_RATR_STA_HIGH;7182 else if (snr > snr_thresh_low)7183 rssi_level = RTL8XXXU_RATR_STA_MID;7184 else7185 rssi_level = RTL8XXXU_RATR_STA_LOW;7186 7187 if (rssi_level != sta_info->rssi_level || force) {7188 int sgi = 0;7189 u32 rate_bitmap = 0;7190 7191 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) |7192 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) |7193 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20);7194 if (sta->deflink.ht_cap.cap &7195 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))7196 sgi = 1;7197 7198 wireless_mode = rtl8xxxu_wireless_mode(hw, sta);7199 switch (wireless_mode) {7200 case WIRELESS_MODE_B:7201 ratr_idx = RATEID_IDX_B;7202 if (rate_bitmap & 0x0000000c)7203 rate_bitmap &= 0x0000000d;7204 else7205 rate_bitmap &= 0x0000000f;7206 break;7207 case WIRELESS_MODE_A:7208 case WIRELESS_MODE_G:7209 ratr_idx = RATEID_IDX_G;7210 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)7211 rate_bitmap &= 0x00000f00;7212 else7213 rate_bitmap &= 0x00000ff0;7214 break;7215 case (WIRELESS_MODE_B | WIRELESS_MODE_G):7216 ratr_idx = RATEID_IDX_BG;7217 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)7218 rate_bitmap &= 0x00000f00;7219 else if (rssi_level == RTL8XXXU_RATR_STA_MID)7220 rate_bitmap &= 0x00000ff0;7221 else7222 rate_bitmap &= 0x00000ff5;7223 break;7224 case WIRELESS_MODE_N_24G:7225 case WIRELESS_MODE_N_5G:7226 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G):7227 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G):7228 if (priv->tx_paths == 2 && priv->rx_paths == 2)7229 ratr_idx = RATEID_IDX_GN_N2SS;7230 else7231 ratr_idx = RATEID_IDX_GN_N1SS;7232 break;7233 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G):7234 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G):7235 if (txbw_40mhz) {7236 if (priv->tx_paths == 2 && priv->rx_paths == 2)7237 ratr_idx = RATEID_IDX_BGN_40M_2SS;7238 else7239 ratr_idx = RATEID_IDX_BGN_40M_1SS;7240 } else {7241 if (priv->tx_paths == 2 && priv->rx_paths == 2)7242 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN;7243 else7244 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN;7245 }7246 7247 if (priv->tx_paths == 2 && priv->rx_paths == 2) {7248 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {7249 rate_bitmap &= 0x0f8f0000;7250 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {7251 rate_bitmap &= 0x0f8ff000;7252 } else {7253 if (txbw_40mhz)7254 rate_bitmap &= 0x0f8ff015;7255 else7256 rate_bitmap &= 0x0f8ff005;7257 }7258 } else {7259 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {7260 rate_bitmap &= 0x000f0000;7261 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {7262 rate_bitmap &= 0x000ff000;7263 } else {7264 if (txbw_40mhz)7265 rate_bitmap &= 0x000ff015;7266 else7267 rate_bitmap &= 0x000ff005;7268 }7269 }7270 break;7271 default:7272 ratr_idx = RATEID_IDX_BGN_40M_2SS;7273 rate_bitmap &= 0x0fffffff;7274 break;7275 }7276 7277 sta_info->rssi_level = rssi_level;7278 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid);7279 }7280}7281 7282static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status)7283{7284 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;7285 u32 val32;7286 7287 if (atc_status == cfo->atc_status)7288 return;7289 7290 cfo->atc_status = atc_status;7291 7292 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);7293 if (atc_status)7294 val32 |= CFO_TRACKING_ATC_STATUS;7295 else7296 val32 &= ~CFO_TRACKING_ATC_STATUS;7297 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32);7298}7299 7300/* Central frequency offset correction */7301static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv)7302{7303 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;7304 int cfo_khz_a, cfo_khz_b, cfo_average;7305 int crystal_cap;7306 7307 if (!rtl8xxxu_is_assoc(priv)) {7308 /* Reset */7309 cfo->adjust = true;7310 7311 if (cfo->crystal_cap > priv->default_crystal_cap)7312 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1);7313 else if (cfo->crystal_cap < priv->default_crystal_cap)7314 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1);7315 7316 rtl8xxxu_set_atc_status(priv, true);7317 7318 return;7319 }7320 7321 if (cfo->packet_count == cfo->packet_count_pre)7322 /* No new information. */7323 return;7324 7325 cfo->packet_count_pre = cfo->packet_count;7326 7327 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */7328 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7;7329 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7;7330 7331 if (priv->tx_paths == 1)7332 cfo_average = cfo_khz_a;7333 else7334 cfo_average = (cfo_khz_a + cfo_khz_b) / 2;7335 7336 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average);7337 7338 if (cfo->adjust) {7339 if (abs(cfo_average) < CFO_TH_XTAL_LOW)7340 cfo->adjust = false;7341 } else {7342 if (abs(cfo_average) > CFO_TH_XTAL_HIGH)7343 cfo->adjust = true;7344 }7345 7346 /*7347 * TODO: We should return here only if bluetooth is enabled.7348 * See the vendor drivers for how to determine that.7349 */7350 if (priv->has_bluetooth)7351 return;7352 7353 if (!cfo->adjust)7354 return;7355 7356 crystal_cap = cfo->crystal_cap;7357 7358 if (cfo_average > CFO_TH_XTAL_LOW)7359 crystal_cap++;7360 else if (cfo_average < -CFO_TH_XTAL_LOW)7361 crystal_cap--;7362 7363 crystal_cap = clamp(crystal_cap, 0, 0x3f);7364 7365 priv->fops->set_crystal_cap(priv, crystal_cap);7366 7367 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC);7368}7369 7370static void rtl8xxxu_ra_iter(void *data, struct ieee80211_sta *sta)7371{7372 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;7373 struct rtl8xxxu_priv *priv = data;7374 int signal = -ewma_rssi_read(&sta_info->avg_rssi);7375 7376 priv->fops->report_rssi(priv, rtl8xxxu_get_macid(priv, sta),7377 rtl8xxxu_signal_to_snr(signal));7378 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false);7379}7380 7381struct rtl8xxxu_stas_entry {7382 struct list_head list;7383 struct ieee80211_sta *sta;7384};7385 7386struct rtl8xxxu_iter_stas_data {7387 struct rtl8xxxu_priv *priv;7388 struct list_head list;7389};7390 7391static void rtl8xxxu_collect_sta_iter(void *data, struct ieee80211_sta *sta)7392{7393 struct rtl8xxxu_iter_stas_data *iter_stas = data;7394 struct rtl8xxxu_stas_entry *stas_entry;7395 7396 stas_entry = kmalloc(sizeof(*stas_entry), GFP_ATOMIC);7397 if (!stas_entry)7398 return;7399 7400 stas_entry->sta = sta;7401 list_add_tail(&stas_entry->list, &iter_stas->list);7402}7403 7404static void rtl8xxxu_watchdog_callback(struct work_struct *work)7405{7406 7407 struct rtl8xxxu_iter_stas_data iter_data;7408 struct rtl8xxxu_stas_entry *sta_entry, *tmp;7409 struct rtl8xxxu_priv *priv;7410 7411 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work);7412 iter_data.priv = priv;7413 INIT_LIST_HEAD(&iter_data.list);7414 7415 mutex_lock(&priv->sta_mutex);7416 ieee80211_iterate_stations_atomic(priv->hw, rtl8xxxu_collect_sta_iter,7417 &iter_data);7418 list_for_each_entry_safe(sta_entry, tmp, &iter_data.list, list) {7419 list_del_init(&sta_entry->list);7420 rtl8xxxu_ra_iter(priv, sta_entry->sta);7421 kfree(sta_entry);7422 }7423 mutex_unlock(&priv->sta_mutex);7424 7425 if (priv->fops->set_crystal_cap)7426 rtl8xxxu_track_cfo(priv);7427 7428 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);7429}7430 7431static int rtl8xxxu_start(struct ieee80211_hw *hw)7432{7433 struct rtl8xxxu_priv *priv = hw->priv;7434 struct rtl8xxxu_rx_urb *rx_urb;7435 struct rtl8xxxu_tx_urb *tx_urb;7436 struct sk_buff *skb;7437 unsigned long flags;7438 int ret, i;7439 7440 ret = 0;7441 7442 init_usb_anchor(&priv->rx_anchor);7443 init_usb_anchor(&priv->tx_anchor);7444 init_usb_anchor(&priv->int_anchor);7445 7446 priv->fops->enable_rf(priv);7447 if (priv->usb_interrupts) {7448 ret = rtl8xxxu_submit_int_urb(hw);7449 if (ret)7450 goto exit;7451 }7452 7453 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {7454 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);7455 if (!tx_urb) {7456 if (!i)7457 ret = -ENOMEM;7458 7459 goto error_out;7460 }7461 usb_init_urb(&tx_urb->urb);7462 INIT_LIST_HEAD(&tx_urb->list);7463 tx_urb->hw = hw;7464 list_add(&tx_urb->list, &priv->tx_urb_free_list);7465 priv->tx_urb_free_count++;7466 }7467 7468 priv->tx_stopped = false;7469 7470 spin_lock_irqsave(&priv->rx_urb_lock, flags);7471 priv->shutdown = false;7472 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);7473 7474 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {7475 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);7476 if (!rx_urb) {7477 if (!i)7478 ret = -ENOMEM;7479 7480 goto error_out;7481 }7482 usb_init_urb(&rx_urb->urb);7483 INIT_LIST_HEAD(&rx_urb->list);7484 rx_urb->hw = hw;7485 7486 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);7487 if (ret) {7488 if (ret != -ENOMEM) {7489 skb = (struct sk_buff *)rx_urb->urb.context;7490 dev_kfree_skb(skb);7491 }7492 rtl8xxxu_queue_rx_urb(priv, rx_urb);7493 }7494 }7495 7496 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);7497exit:7498 /*7499 * Accept all data and mgmt frames7500 */7501 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);7502 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);7503 7504 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1,7505 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e);7506 7507 return ret;7508 7509error_out:7510 rtl8xxxu_free_tx_resources(priv);7511 /*7512 * Disable all data and mgmt frames7513 */7514 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);7515 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);7516 7517 return ret;7518}7519 7520static void rtl8xxxu_stop(struct ieee80211_hw *hw, bool suspend)7521{7522 struct rtl8xxxu_priv *priv = hw->priv;7523 unsigned long flags;7524 7525 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);7526 7527 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);7528 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);7529 7530 spin_lock_irqsave(&priv->rx_urb_lock, flags);7531 priv->shutdown = true;7532 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);7533 7534 usb_kill_anchored_urbs(&priv->rx_anchor);7535 usb_kill_anchored_urbs(&priv->tx_anchor);7536 if (priv->usb_interrupts)7537 usb_kill_anchored_urbs(&priv->int_anchor);7538 7539 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);7540 7541 priv->fops->disable_rf(priv);7542 7543 /*7544 * Disable interrupts7545 */7546 if (priv->usb_interrupts)7547 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);7548 7549 cancel_work_sync(&priv->c2hcmd_work);7550 cancel_delayed_work_sync(&priv->ra_watchdog);7551 cancel_delayed_work_sync(&priv->update_beacon_work);7552 7553 rtl8xxxu_free_rx_resources(priv);7554 rtl8xxxu_free_tx_resources(priv);7555}7556 7557static int rtl8xxxu_sta_add(struct ieee80211_hw *hw,7558 struct ieee80211_vif *vif,7559 struct ieee80211_sta *sta)7560{7561 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;7562 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;7563 struct rtl8xxxu_priv *priv = hw->priv;7564 7565 mutex_lock(&priv->sta_mutex);7566 ewma_rssi_init(&sta_info->avg_rssi);7567 if (vif->type == NL80211_IFTYPE_AP) {7568 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT;7569 sta_info->macid = rtl8xxxu_acquire_macid(priv);7570 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM) {7571 mutex_unlock(&priv->sta_mutex);7572 return -ENOSPC;7573 }7574 7575 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true);7576 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true);7577 } else {7578 switch (rtlvif->port_num) {7579 case 0:7580 sta_info->macid = RTL8XXXU_BC_MC_MACID;7581 break;7582 case 1:7583 sta_info->macid = RTL8XXXU_BC_MC_MACID1;7584 break;7585 default:7586 break;7587 }7588 }7589 mutex_unlock(&priv->sta_mutex);7590 7591 return 0;7592}7593 7594static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw,7595 struct ieee80211_vif *vif,7596 struct ieee80211_sta *sta)7597{7598 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;7599 struct rtl8xxxu_priv *priv = hw->priv;7600 7601 mutex_lock(&priv->sta_mutex);7602 if (vif->type == NL80211_IFTYPE_AP)7603 rtl8xxxu_release_macid(priv, sta_info->macid);7604 mutex_unlock(&priv->sta_mutex);7605 7606 return 0;7607}7608 7609static const struct ieee80211_ops rtl8xxxu_ops = {7610 .add_chanctx = ieee80211_emulate_add_chanctx,7611 .remove_chanctx = ieee80211_emulate_remove_chanctx,7612 .change_chanctx = ieee80211_emulate_change_chanctx,7613 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx,7614 .tx = rtl8xxxu_tx,7615 .wake_tx_queue = ieee80211_handle_wake_tx_queue,7616 .add_interface = rtl8xxxu_add_interface,7617 .remove_interface = rtl8xxxu_remove_interface,7618 .config = rtl8xxxu_config,7619 .conf_tx = rtl8xxxu_conf_tx,7620 .bss_info_changed = rtl8xxxu_bss_info_changed,7621 .start_ap = rtl8xxxu_start_ap,7622 .configure_filter = rtl8xxxu_configure_filter,7623 .set_rts_threshold = rtl8xxxu_set_rts_threshold,7624 .start = rtl8xxxu_start,7625 .stop = rtl8xxxu_stop,7626 .sw_scan_start = rtl8xxxu_sw_scan_start,7627 .sw_scan_complete = rtl8xxxu_sw_scan_complete,7628 .set_key = rtl8xxxu_set_key,7629 .ampdu_action = rtl8xxxu_ampdu_action,7630 .sta_statistics = rtl8xxxu_sta_statistics,7631 .get_antenna = rtl8xxxu_get_antenna,7632 .set_tim = rtl8xxxu_set_tim,7633 .sta_add = rtl8xxxu_sta_add,7634 .sta_remove = rtl8xxxu_sta_remove,7635};7636 7637static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,7638 struct usb_interface *interface)7639{7640 struct usb_interface_descriptor *interface_desc;7641 struct usb_host_interface *host_interface;7642 struct usb_endpoint_descriptor *endpoint;7643 struct device *dev = &priv->udev->dev;7644 int i, j = 0, endpoints;7645 u8 dir, xtype, num;7646 int ret = 0;7647 7648 host_interface = interface->cur_altsetting;7649 interface_desc = &host_interface->desc;7650 endpoints = interface_desc->bNumEndpoints;7651 7652 for (i = 0; i < endpoints; i++) {7653 endpoint = &host_interface->endpoint[i].desc;7654 7655 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;7656 num = usb_endpoint_num(endpoint);7657 xtype = usb_endpoint_type(endpoint);7658 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)7659 dev_dbg(dev,7660 "%s: endpoint: dir %02x, # %02x, type %02x\n",7661 __func__, dir, num, xtype);7662 if (usb_endpoint_dir_in(endpoint) &&7663 usb_endpoint_xfer_bulk(endpoint)) {7664 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)7665 dev_dbg(dev, "%s: in endpoint num %i\n",7666 __func__, num);7667 7668 if (priv->pipe_in) {7669 dev_warn(dev,7670 "%s: Too many IN pipes\n", __func__);7671 ret = -EINVAL;7672 goto exit;7673 }7674 7675 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);7676 }7677 7678 if (usb_endpoint_dir_in(endpoint) &&7679 usb_endpoint_xfer_int(endpoint)) {7680 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)7681 dev_dbg(dev, "%s: interrupt endpoint num %i\n",7682 __func__, num);7683 7684 if (priv->pipe_interrupt) {7685 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",7686 __func__);7687 ret = -EINVAL;7688 goto exit;7689 }7690 7691 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);7692 }7693 7694 if (usb_endpoint_dir_out(endpoint) &&7695 usb_endpoint_xfer_bulk(endpoint)) {7696 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)7697 dev_dbg(dev, "%s: out endpoint num %i\n",7698 __func__, num);7699 if (j >= RTL8XXXU_OUT_ENDPOINTS) {7700 dev_warn(dev,7701 "%s: Too many OUT pipes\n", __func__);7702 ret = -EINVAL;7703 goto exit;7704 }7705 priv->out_ep[j++] = num;7706 }7707 }7708exit:7709 priv->nr_out_eps = j;7710 return ret;7711}7712 7713static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv)7714{7715 struct led_classdev *led = &priv->led_cdev;7716 7717 if (!priv->fops->led_classdev_brightness_set)7718 return;7719 7720 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set;7721 7722 snprintf(priv->led_name, sizeof(priv->led_name),7723 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev));7724 led->name = priv->led_name;7725 led->max_brightness = RTL8XXXU_HW_LED_CONTROL;7726 7727 if (led_classdev_register(&priv->udev->dev, led))7728 return;7729 7730 priv->led_registered = true;7731 7732 led->brightness = led->max_brightness;7733 priv->fops->led_classdev_brightness_set(led, led->brightness);7734}7735 7736static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv)7737{7738 struct led_classdev *led = &priv->led_cdev;7739 7740 if (!priv->led_registered)7741 return;7742 7743 priv->fops->led_classdev_brightness_set(led, LED_OFF);7744 led_classdev_unregister(led);7745}7746 7747static const struct ieee80211_iface_limit rtl8xxxu_limits[] = {7748 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION), },7749 { .max = 1, .types = BIT(NL80211_IFTYPE_AP), },7750};7751 7752static const struct ieee80211_iface_combination rtl8xxxu_combinations[] = {7753 {7754 .limits = rtl8xxxu_limits,7755 .n_limits = ARRAY_SIZE(rtl8xxxu_limits),7756 .max_interfaces = 2,7757 .num_different_channels = 1,7758 },7759};7760 7761static int rtl8xxxu_probe(struct usb_interface *interface,7762 const struct usb_device_id *id)7763{7764 struct rtl8xxxu_priv *priv;7765 struct ieee80211_hw *hw;7766 struct usb_device *udev;7767 struct ieee80211_supported_band *sband;7768 int ret;7769 int untested = 1;7770 7771 udev = usb_get_dev(interface_to_usbdev(interface));7772 7773 switch (id->idVendor) {7774 case USB_VENDOR_ID_REALTEK:7775 switch(id->idProduct) {7776 case 0x1724:7777 case 0x8176:7778 case 0x8178:7779 case 0x817f:7780 case 0x818b:7781 case 0xf179:7782 case 0x8179:7783 case 0xb711:7784 case 0xf192:7785 case 0x2005:7786 untested = 0;7787 break;7788 }7789 break;7790 case 0x7392:7791 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811)7792 untested = 0;7793 break;7794 case 0x050d:7795 if (id->idProduct == 0x1004)7796 untested = 0;7797 break;7798 case 0x20f4:7799 if (id->idProduct == 0x648b)7800 untested = 0;7801 break;7802 case 0x2001:7803 if (id->idProduct == 0x3308)7804 untested = 0;7805 break;7806 case 0x2357:7807 if (id->idProduct == 0x0109 || id->idProduct == 0x0135)7808 untested = 0;7809 break;7810 case 0x0b05:7811 if (id->idProduct == 0x18f1)7812 untested = 0;7813 break;7814 default:7815 break;7816 }7817 7818 if (untested) {7819 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;7820 dev_info(&udev->dev,7821 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",7822 id->idVendor, id->idProduct);7823 dev_info(&udev->dev,7824 "Please report results to Jes.Sorensen@gmail.com\n");7825 }7826 7827 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);7828 if (!hw) {7829 ret = -ENOMEM;7830 goto err_put_dev;7831 }7832 7833 priv = hw->priv;7834 priv->hw = hw;7835 priv->udev = udev;7836 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;7837 mutex_init(&priv->usb_buf_mutex);7838 mutex_init(&priv->syson_indirect_access_mutex);7839 mutex_init(&priv->h2c_mutex);7840 mutex_init(&priv->sta_mutex);7841 INIT_LIST_HEAD(&priv->tx_urb_free_list);7842 spin_lock_init(&priv->tx_urb_lock);7843 INIT_LIST_HEAD(&priv->rx_urb_pending_list);7844 spin_lock_init(&priv->rx_urb_lock);7845 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);7846 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback);7847 INIT_DELAYED_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback);7848 skb_queue_head_init(&priv->c2hcmd_queue);7849 7850 usb_set_intfdata(interface, hw);7851 7852 ret = rtl8xxxu_parse_usb(priv, interface);7853 if (ret)7854 goto err_set_intfdata;7855 7856 ret = priv->fops->identify_chip(priv);7857 if (ret) {7858 dev_err(&udev->dev, "Fatal - failed to identify chip\n");7859 goto err_set_intfdata;7860 }7861 7862 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;7863 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;7864 7865 if (priv->rtl_chip == RTL8188E)7866 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback);7867 else7868 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback);7869 7870 ret = priv->fops->read_efuse(priv);7871 if (ret) {7872 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");7873 goto err_set_intfdata;7874 }7875 7876 ret = priv->fops->parse_efuse(priv);7877 if (ret) {7878 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");7879 goto err_set_intfdata;7880 }7881 7882 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE)7883 rtl8xxxu_dump_efuse(priv);7884 7885 rtl8xxxu_print_chipinfo(priv);7886 7887 ret = priv->fops->load_firmware(priv);7888 if (ret) {7889 dev_err(&udev->dev, "Fatal - failed to load firmware\n");7890 goto err_set_intfdata;7891 }7892 7893 ret = rtl8xxxu_init_device(hw);7894 if (ret)7895 goto err_set_intfdata;7896 7897 hw->vif_data_size = sizeof(struct rtl8xxxu_vif);7898 7899 hw->wiphy->max_scan_ssids = 1;7900 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;7901 if (priv->fops->max_macid_num)7902 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1;7903 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);7904 if (priv->fops->supports_ap)7905 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);7906 hw->queues = 4;7907 7908 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;7909 7910 if (priv->fops->supports_concurrent) {7911 hw->wiphy->iface_combinations = rtl8xxxu_combinations;7912 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtl8xxxu_combinations);7913 }7914 7915 sband = &rtl8xxxu_supported_band;7916 sband->ht_cap.ht_supported = true;7917 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;7918 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;7919 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;7920 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));7921 sband->ht_cap.mcs.rx_mask[0] = 0xff;7922 sband->ht_cap.mcs.rx_mask[4] = 0x01;7923 if (priv->rf_paths > 1) {7924 sband->ht_cap.mcs.rx_mask[1] = 0xff;7925 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;7926 }7927 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;7928 /*7929 * Some APs will negotiate HT20_40 in a noisy environment leading7930 * to miserable performance. Rather than defaulting to this, only7931 * enable it if explicitly requested at module load time.7932 */7933 if (rtl8xxxu_ht40_2g) {7934 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");7935 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;7936 }7937 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;7938 7939 hw->wiphy->rts_threshold = 2347;7940 7941 SET_IEEE80211_DEV(priv->hw, &interface->dev);7942 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);7943 7944 hw->extra_tx_headroom = priv->fops->tx_desc_size;7945 ieee80211_hw_set(hw, SIGNAL_DBM);7946 7947 /*7948 * The firmware handles rate control, except for RTL8188EU,7949 * where we handle the rate control in the driver.7950 */7951 ieee80211_hw_set(hw, HAS_RATE_CONTROL);7952 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);7953 ieee80211_hw_set(hw, AMPDU_AGGREGATION);7954 ieee80211_hw_set(hw, MFP_CAPABLE);7955 7956 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);7957 7958 ret = ieee80211_register_hw(priv->hw);7959 if (ret) {7960 dev_err(&udev->dev, "%s: Failed to register: %i\n",7961 __func__, ret);7962 goto err_set_intfdata;7963 }7964 7965 rtl8xxxu_init_led(priv);7966 7967 return 0;7968 7969err_set_intfdata:7970 usb_set_intfdata(interface, NULL);7971 7972 kfree(priv->fw_data);7973 mutex_destroy(&priv->usb_buf_mutex);7974 mutex_destroy(&priv->syson_indirect_access_mutex);7975 mutex_destroy(&priv->h2c_mutex);7976 7977 ieee80211_free_hw(hw);7978err_put_dev:7979 usb_put_dev(udev);7980 7981 return ret;7982}7983 7984static void rtl8xxxu_disconnect(struct usb_interface *interface)7985{7986 struct rtl8xxxu_priv *priv;7987 struct ieee80211_hw *hw;7988 7989 hw = usb_get_intfdata(interface);7990 priv = hw->priv;7991 7992 rtl8xxxu_deinit_led(priv);7993 7994 ieee80211_unregister_hw(hw);7995 7996 priv->fops->power_off(priv);7997 7998 usb_set_intfdata(interface, NULL);7999 8000 dev_info(&priv->udev->dev, "disconnecting\n");8001 8002 kfree(priv->fw_data);8003 mutex_destroy(&priv->usb_buf_mutex);8004 mutex_destroy(&priv->syson_indirect_access_mutex);8005 mutex_destroy(&priv->h2c_mutex);8006 8007 if (priv->udev->state != USB_STATE_NOTATTACHED) {8008 dev_info(&priv->udev->dev,8009 "Device still attached, trying to reset\n");8010 usb_reset_device(priv->udev);8011 }8012 usb_put_dev(priv->udev);8013 ieee80211_free_hw(hw);8014}8015 8016static const struct usb_device_id dev_table[] = {8017{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),8018 .driver_info = (unsigned long)&rtl8723au_fops},8019{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),8020 .driver_info = (unsigned long)&rtl8723au_fops},8021{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),8022 .driver_info = (unsigned long)&rtl8723au_fops},8023{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),8024 .driver_info = (unsigned long)&rtl8192eu_fops},8025/* TP-Link TL-WN822N v4 */8026{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),8027 .driver_info = (unsigned long)&rtl8192eu_fops},8028/* D-Link DWA-131 rev E1, tested by David Patiño */8029{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),8030 .driver_info = (unsigned long)&rtl8192eu_fops},8031/* Tested by Myckel Habets */8032{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),8033 .driver_info = (unsigned long)&rtl8192eu_fops},8034{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),8035 .driver_info = (unsigned long)&rtl8723bu_fops},8036{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),8037 .driver_info = (unsigned long)&rtl8723bu_fops},8038/* RTL8188FU */8039{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff),8040 .driver_info = (unsigned long)&rtl8188fu_fops},8041{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff),8042 .driver_info = (unsigned long)&rtl8188eu_fops},8043/* Tested by Hans de Goede - rtl8188etv */8044{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff),8045 .driver_info = (unsigned long)&rtl8188eu_fops},8046/* Sitecom rtl8188eus */8047{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff),8048 .driver_info = (unsigned long)&rtl8188eu_fops},8049/* D-Link USB-GO-N150 */8050{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff),8051 .driver_info = (unsigned long)&rtl8188eu_fops},8052/* D-Link DWA-125 REV D1 */8053{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff),8054 .driver_info = (unsigned long)&rtl8188eu_fops},8055/* D-Link DWA-123 REV D1 */8056{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff),8057 .driver_info = (unsigned long)&rtl8188eu_fops},8058/* D-Link DWA-121 rev B1 */8059{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff),8060 .driver_info = (unsigned long)&rtl8188eu_fops},8061/* Abocom - Abocom */8062{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff),8063 .driver_info = (unsigned long)&rtl8188eu_fops},8064/* Elecom WDC-150SU2M */8065{USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff),8066 .driver_info = (unsigned long)&rtl8188eu_fops},8067/* TP-Link TL-WN722N v2 */8068{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff),8069 .driver_info = (unsigned long)&rtl8188eu_fops},8070/* TP-Link TL-WN727N v5.21 */8071{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff),8072 .driver_info = (unsigned long)&rtl8188eu_fops},8073/* MERCUSYS MW150US v2 */8074{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff),8075 .driver_info = (unsigned long)&rtl8188eu_fops},8076/* ASUS USB-N10 Nano B1 */8077{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff),8078 .driver_info = (unsigned long)&rtl8188eu_fops},8079 /* Edimax EW-7811Un V2 */8080{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff),8081 .driver_info = (unsigned long)&rtl8188eu_fops},8082/* Rosewill USB-N150 Nano */8083{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff),8084 .driver_info = (unsigned long)&rtl8188eu_fops},8085/* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */8086{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff),8087 .driver_info = (unsigned long)&rtl8710bu_fops},8088/* TOTOLINK N150UA V5 / N150UA-B */8089{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff),8090 .driver_info = (unsigned long)&rtl8710bu_fops},8091/* Comfast CF-826F */8092{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff),8093 .driver_info = (unsigned long)&rtl8192fu_fops},8094/* Asus USB-N13 rev C1 */8095{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff),8096 .driver_info = (unsigned long)&rtl8192fu_fops},8097/* EDIMAX EW-7722UTn V3 */8098{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff),8099 .driver_info = (unsigned long)&rtl8192fu_fops},8100{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff),8101 .driver_info = (unsigned long)&rtl8192fu_fops},8102/* TP-Link TL-WN823N V2 */8103{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0135, 0xff, 0xff, 0xff),8104 .driver_info = (unsigned long)&rtl8192fu_fops},8105#ifdef CONFIG_RTL8XXXU_UNTESTED8106/* Still supported by rtlwifi */8107{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),8108 .driver_info = (unsigned long)&rtl8192cu_fops},8109{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),8110 .driver_info = (unsigned long)&rtl8192cu_fops},8111{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),8112 .driver_info = (unsigned long)&rtl8192cu_fops},8113{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x819a, 0xff, 0xff, 0xff),8114 .driver_info = (unsigned long)&rtl8192cu_fops},8115{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8754, 0xff, 0xff, 0xff),8116 .driver_info = (unsigned long)&rtl8192cu_fops},8117{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817c, 0xff, 0xff, 0xff),8118 .driver_info = (unsigned long)&rtl8192cu_fops},8119/* Tested by Larry Finger */8120{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),8121 .driver_info = (unsigned long)&rtl8192cu_fops},8122/* Tested by Andrea Merello */8123{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),8124 .driver_info = (unsigned long)&rtl8192cu_fops},8125/* Tested by Jocelyn Mayer */8126{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),8127 .driver_info = (unsigned long)&rtl8192cu_fops},8128/* Tested by Stefano Bravi */8129{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),8130 .driver_info = (unsigned long)&rtl8192cu_fops},8131/* Currently untested 8188 series devices */8132{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff),8133 .driver_info = (unsigned long)&rtl8192cu_fops},8134{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),8135 .driver_info = (unsigned long)&rtl8192cu_fops},8136{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),8137 .driver_info = (unsigned long)&rtl8192cu_fops},8138{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),8139 .driver_info = (unsigned long)&rtl8192cu_fops},8140{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),8141 .driver_info = (unsigned long)&rtl8192cu_fops},8142{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),8143 .driver_info = (unsigned long)&rtl8192cu_fops},8144{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),8145 .driver_info = (unsigned long)&rtl8192cu_fops},8146{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),8147 .driver_info = (unsigned long)&rtl8192cu_fops},8148{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),8149 .driver_info = (unsigned long)&rtl8192cu_fops},8150{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),8151 .driver_info = (unsigned long)&rtl8192cu_fops},8152{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),8153 .driver_info = (unsigned long)&rtl8192cu_fops},8154{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),8155 .driver_info = (unsigned long)&rtl8192cu_fops},8156{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),8157 .driver_info = (unsigned long)&rtl8192cu_fops},8158{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),8159 .driver_info = (unsigned long)&rtl8192cu_fops},8160{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),8161 .driver_info = (unsigned long)&rtl8192cu_fops},8162{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),8163 .driver_info = (unsigned long)&rtl8192cu_fops},8164{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),8165 .driver_info = (unsigned long)&rtl8192cu_fops},8166{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),8167 .driver_info = (unsigned long)&rtl8192cu_fops},8168{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),8169 .driver_info = (unsigned long)&rtl8192cu_fops},8170{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),8171 .driver_info = (unsigned long)&rtl8192cu_fops},8172{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),8173 .driver_info = (unsigned long)&rtl8192cu_fops},8174{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),8175 .driver_info = (unsigned long)&rtl8192cu_fops},8176{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),8177 .driver_info = (unsigned long)&rtl8192cu_fops},8178{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),8179 .driver_info = (unsigned long)&rtl8192cu_fops},8180{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),8181 .driver_info = (unsigned long)&rtl8192cu_fops},8182{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),8183 .driver_info = (unsigned long)&rtl8192cu_fops},8184{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),8185 .driver_info = (unsigned long)&rtl8192cu_fops},8186{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),8187 .driver_info = (unsigned long)&rtl8192cu_fops},8188{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),8189 .driver_info = (unsigned long)&rtl8192cu_fops},8190{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),8191 .driver_info = (unsigned long)&rtl8192cu_fops},8192{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),8193 .driver_info = (unsigned long)&rtl8192cu_fops},8194{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),8195 .driver_info = (unsigned long)&rtl8192cu_fops},8196{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),8197 .driver_info = (unsigned long)&rtl8192cu_fops},8198{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),8199 .driver_info = (unsigned long)&rtl8192cu_fops},8200{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),8201 .driver_info = (unsigned long)&rtl8192cu_fops},8202{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),8203 .driver_info = (unsigned long)&rtl8192cu_fops},8204{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),8205 .driver_info = (unsigned long)&rtl8192cu_fops},8206{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),8207 .driver_info = (unsigned long)&rtl8192cu_fops},8208{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),8209 .driver_info = (unsigned long)&rtl8192cu_fops},8210/* Currently untested 8192 series devices */8211{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),8212 .driver_info = (unsigned long)&rtl8192cu_fops},8213{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),8214 .driver_info = (unsigned long)&rtl8192cu_fops},8215{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),8216 .driver_info = (unsigned long)&rtl8192cu_fops},8217{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),8218 .driver_info = (unsigned long)&rtl8192cu_fops},8219{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),8220 .driver_info = (unsigned long)&rtl8192cu_fops},8221{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),8222 .driver_info = (unsigned long)&rtl8192cu_fops},8223{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),8224 .driver_info = (unsigned long)&rtl8192cu_fops},8225{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),8226 .driver_info = (unsigned long)&rtl8192cu_fops},8227{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),8228 .driver_info = (unsigned long)&rtl8192cu_fops},8229{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),8230 .driver_info = (unsigned long)&rtl8192cu_fops},8231{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),8232 .driver_info = (unsigned long)&rtl8192cu_fops},8233{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),8234 .driver_info = (unsigned long)&rtl8192cu_fops},8235{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),8236 .driver_info = (unsigned long)&rtl8192cu_fops},8237{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),8238 .driver_info = (unsigned long)&rtl8192cu_fops},8239{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),8240 .driver_info = (unsigned long)&rtl8192cu_fops},8241{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),8242 .driver_info = (unsigned long)&rtl8192cu_fops},8243{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),8244 .driver_info = (unsigned long)&rtl8192cu_fops},8245{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),8246 .driver_info = (unsigned long)&rtl8192cu_fops},8247{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),8248 .driver_info = (unsigned long)&rtl8192cu_fops},8249{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),8250 .driver_info = (unsigned long)&rtl8192cu_fops},8251{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),8252 .driver_info = (unsigned long)&rtl8192cu_fops},8253{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),8254 .driver_info = (unsigned long)&rtl8192cu_fops},8255{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),8256 .driver_info = (unsigned long)&rtl8192cu_fops},8257{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),8258 .driver_info = (unsigned long)&rtl8192cu_fops},8259/* found in rtl8192eu vendor driver */8260{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),8261 .driver_info = (unsigned long)&rtl8192eu_fops},8262{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),8263 .driver_info = (unsigned long)&rtl8192eu_fops},8264{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),8265 .driver_info = (unsigned long)&rtl8192eu_fops},8266/* D-Link DWA-131 rev C1 */8267{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff),8268 .driver_info = (unsigned long)&rtl8192eu_fops},8269/* TP-Link TL-WN8200ND V2 */8270{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff),8271 .driver_info = (unsigned long)&rtl8192eu_fops},8272/* Mercusys MW300UM */8273{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff),8274 .driver_info = (unsigned long)&rtl8192eu_fops},8275/* Mercusys MW300UH */8276{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff),8277 .driver_info = (unsigned long)&rtl8192eu_fops},8278#endif8279{ }8280};8281 8282static struct usb_driver rtl8xxxu_driver = {8283 .name = DRIVER_NAME,8284 .probe = rtl8xxxu_probe,8285 .disconnect = rtl8xxxu_disconnect,8286 .id_table = dev_table,8287 .no_dynamic_id = 1,8288 .disable_hub_initiated_lpm = 1,8289};8290 8291MODULE_DEVICE_TABLE(usb, dev_table);8292 8293module_usb_driver(rtl8xxxu_driver);8294