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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2013 Realtek Corporation.*/3 4#ifndef __RTL88E_DM_H__5#define __RTL88E_DM_H__6 7#define MAIN_ANT 08#define AUX_ANT 19#define MAIN_ANT_CG_TRX 110#define AUX_ANT_CG_TRX 011#define MAIN_ANT_CGCS_RX 012#define AUX_ANT_CGCS_RX 113 14/*RF REG LIST*/15#define DM_REG_RF_MODE_11N 0x0016#define DM_REG_RF_0B_11N 0x0B17#define DM_REG_CHNBW_11N 0x1818#define DM_REG_T_METER_11N 0x2419#define DM_REG_RF_25_11N 0x2520#define DM_REG_RF_26_11N 0x2621#define DM_REG_RF_27_11N 0x2722#define DM_REG_RF_2B_11N 0x2B23#define DM_REG_RF_2C_11N 0x2C24#define DM_REG_RXRF_A3_11N 0x3C25#define DM_REG_T_METER_92D_11N 0x4226#define DM_REG_T_METER_88E_11N 0x4227 28/*BB REG LIST*/29/*PAGE 8 */30#define DM_REG_BB_CTRL_11N 0x80031#define DM_REG_RF_PIN_11N 0x80432#define DM_REG_PSD_CTRL_11N 0x80833#define DM_REG_TX_ANT_CTRL_11N 0x80C34#define DM_REG_BB_PWR_SAV5_11N 0x81835#define DM_REG_CCK_RPT_FORMAT_11N 0x82436#define DM_REG_RX_DEFAULT_A_11N 0x85837#define DM_REG_RX_DEFAULT_B_11N 0x85A38#define DM_REG_BB_PWR_SAV3_11N 0x85C39#define DM_REG_ANTSEL_CTRL_11N 0x86040#define DM_REG_RX_ANT_CTRL_11N 0x86441#define DM_REG_PIN_CTRL_11N 0x87042#define DM_REG_BB_PWR_SAV1_11N 0x87443#define DM_REG_ANTSEL_PATH_11N 0x87844#define DM_REG_BB_3WIRE_11N 0x88C45#define DM_REG_SC_CNT_11N 0x8C446#define DM_REG_PSD_DATA_11N 0x8B447/*PAGE 9*/48#define DM_REG_ANT_MAPPING1_11N 0x91449#define DM_REG_ANT_MAPPING2_11N 0x91850/*PAGE A*/51#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA0052#define DM_REG_CCK_CCA_11N 0xA0A53#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C54#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA1055#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA1456#define DM_REG_CCK_FILTER_PARA1_11N 0xA2257#define DM_REG_CCK_FILTER_PARA2_11N 0xA2358#define DM_REG_CCK_FILTER_PARA3_11N 0xA2459#define DM_REG_CCK_FILTER_PARA4_11N 0xA2560#define DM_REG_CCK_FILTER_PARA5_11N 0xA2661#define DM_REG_CCK_FILTER_PARA6_11N 0xA2762#define DM_REG_CCK_FILTER_PARA7_11N 0xA2863#define DM_REG_CCK_FILTER_PARA8_11N 0xA2964#define DM_REG_CCK_FA_RST_11N 0xA2C65#define DM_REG_CCK_FA_MSB_11N 0xA5866#define DM_REG_CCK_FA_LSB_11N 0xA5C67#define DM_REG_CCK_CCA_CNT_11N 0xA6068#define DM_REG_BB_PWR_SAV4_11N 0xA7469/*PAGE B */70#define DM_REG_LNA_SWITCH_11N 0xB2C71#define DM_REG_PATH_SWITCH_11N 0xB3072#define DM_REG_RSSI_CTRL_11N 0xB3873#define DM_REG_CONFIG_ANTA_11N 0xB6874#define DM_REG_RSSI_BT_11N 0xB9C75/*PAGE C */76#define DM_REG_OFDM_FA_HOLDC_11N 0xC0077#define DM_REG_RX_PATH_11N 0xC0478#define DM_REG_TRMUX_11N 0xC0879#define DM_REG_OFDM_FA_RSTC_11N 0xC0C80#define DM_REG_RXIQI_MATRIX_11N 0xC1481#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C82#define DM_REG_IGI_A_11N 0xC5083#define DM_REG_ANTDIV_PARA2_11N 0xC5484#define DM_REG_IGI_B_11N 0xC5885#define DM_REG_ANTDIV_PARA3_11N 0xC5C86#define DM_REG_BB_PWR_SAV2_11N 0xC7087#define DM_REG_RX_OFF_11N 0xC7C88#define DM_REG_TXIQK_MATRIXA_11N 0xC8089#define DM_REG_TXIQK_MATRIXB_11N 0xC8890#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC9491#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C92#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA093#define DM_REG_ANTDIV_PARA1_11N 0xCA494#define DM_REG_OFDM_FA_TYPE1_11N 0xCF095/*PAGE D */96#define DM_REG_OFDM_FA_RSTD_11N 0xD0097#define DM_REG_OFDM_FA_TYPE2_11N 0xDA098#define DM_REG_OFDM_FA_TYPE3_11N 0xDA499#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8100/*PAGE E */101#define DM_REG_TXAGC_A_6_18_11N 0xE00102#define DM_REG_TXAGC_A_24_54_11N 0xE04103#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08104#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10105#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14106#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18107#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C108#define DM_REG_FPGA0_IQK_11N 0xE28109#define DM_REG_TXIQK_TONE_A_11N 0xE30110#define DM_REG_RXIQK_TONE_A_11N 0xE34111#define DM_REG_TXIQK_PI_A_11N 0xE38112#define DM_REG_RXIQK_PI_A_11N 0xE3C113#define DM_REG_TXIQK_11N 0xE40114#define DM_REG_RXIQK_11N 0xE44115#define DM_REG_IQK_AGC_PTS_11N 0xE48116#define DM_REG_IQK_AGC_RSP_11N 0xE4C117#define DM_REG_BLUETOOTH_11N 0xE6C118#define DM_REG_RX_WAIT_CCA_11N 0xE70119#define DM_REG_TX_CCK_RFON_11N 0xE74120#define DM_REG_TX_CCK_BBON_11N 0xE78121#define DM_REG_OFDM_RFON_11N 0xE7C122#define DM_REG_OFDM_BBON_11N 0xE80123#define DM_REG_TX2RX_11N 0xE84124#define DM_REG_TX2TX_11N 0xE88125#define DM_REG_RX_CCK_11N 0xE8C126#define DM_REG_RX_OFDM_11N 0xED0127#define DM_REG_RX_WAIT_RIFS_11N 0xED4128#define DM_REG_RX2RX_11N 0xED8129#define DM_REG_STANDBY_11N 0xEDC130#define DM_REG_SLEEP_11N 0xEE0131#define DM_REG_PMPD_ANAEN_11N 0xEEC132 133/*MAC REG LIST*/134#define DM_REG_BB_RST_11N 0x02135#define DM_REG_ANTSEL_PIN_11N 0x4C136#define DM_REG_EARLY_MODE_11N 0x4D0137#define DM_REG_RSSI_MONITOR_11N 0x4FE138#define DM_REG_EDCA_VO_11N 0x500139#define DM_REG_EDCA_VI_11N 0x504140#define DM_REG_EDCA_BE_11N 0x508141#define DM_REG_EDCA_BK_11N 0x50C142#define DM_REG_TXPAUSE_11N 0x522143#define DM_REG_RESP_TX_11N 0x6D8144#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0145#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4146 147 148/*DIG Related*/149#define DM_BIT_IGI_11N 0x0000007F150 151#define HAL_DM_DIG_DISABLE BIT(0)152#define HAL_DM_HIPWR_DISABLE BIT(1)153 154#define OFDM_TABLE_LENGTH 43155#define CCK_TABLE_LENGTH 33156 157#define OFDM_TABLE_SIZE 43158#define CCK_TABLE_SIZE 33159 160#define BW_AUTO_SWITCH_HIGH_LOW 25161#define BW_AUTO_SWITCH_LOW_HIGH 30162 163#define DM_DIG_FA_UPPER 0x3e164#define DM_DIG_FA_LOWER 0x1e165#define DM_DIG_FA_TH0 0x200166#define DM_DIG_FA_TH1 0x300167#define DM_DIG_FA_TH2 0x400168 169#define RXPATHSELECTION_SS_TH_W 30170#define RXPATHSELECTION_DIFF_TH 18171 172#define DM_RATR_STA_INIT 0173#define DM_RATR_STA_HIGH 1174#define DM_RATR_STA_MIDDLE 2175#define DM_RATR_STA_LOW 3176 177#define CTS2SELF_THVAL 30178#define REGC38_TH 20179 180#define WAIOTTHVAL 25181 182#define TXHIGHPWRLEVEL_NORMAL 0183#define TXHIGHPWRLEVEL_LEVEL1 1184#define TXHIGHPWRLEVEL_LEVEL2 2185#define TXHIGHPWRLEVEL_BT1 3186#define TXHIGHPWRLEVEL_BT2 4187 188#define DM_TYPE_BYFW 0189#define DM_TYPE_BYDRIVER 1190 191#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74192#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67193#define TXPWRTRACK_MAX_IDX 6194 195struct swat_t {196 u8 failure_cnt;197 u8 try_flag;198 u8 stop_trying;199 200 long pre_rssi;201 long trying_threshold;202 u8 cur_antenna;203 u8 pre_antenna;204 205};206 207enum FAT_STATE {208 FAT_NORMAL_STATE = 0,209 FAT_TRAINING_STATE = 1,210};211 212enum tag_dynamic_init_gain_operation_type_definition {213 DIG_TYPE_THRESH_HIGH = 0,214 DIG_TYPE_THRESH_LOW = 1,215 DIG_TYPE_BACKOFF = 2,216 DIG_TYPE_RX_GAIN_MIN = 3,217 DIG_TYPE_RX_GAIN_MAX = 4,218 DIG_TYPE_ENABLE = 5,219 DIG_TYPE_DISABLE = 6,220 DIG_OP_TYPE_MAX221};222 223enum dm_1r_cca_e {224 CCA_1R = 0,225 CCA_2R = 1,226 CCA_MAX = 2,227};228 229enum dm_rf_e {230 RF_SAVE = 0,231 RF_NORMAL = 1,232 RF_MAX = 2,233};234 235enum dm_sw_ant_switch_e {236 ANS_ANTENNA_B = 1,237 ANS_ANTENNA_A = 2,238 ANS_ANTENNA_MAX = 3,239};240 241enum pwr_track_control_method {242 BBSWING,243 TXAGC244};245 246void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,247 u8 *pdesc, u32 mac_id);248void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,249 u8 antsel_tr_mux, u32 mac_id,250 u32 rx_pwdb_all);251void rtl88e_dm_fast_antenna_training_callback(struct timer_list *t);252void rtl88e_dm_init(struct ieee80211_hw *hw);253void rtl88e_dm_watchdog(struct ieee80211_hw *hw);254void rtl88e_dm_write_dig(struct ieee80211_hw *hw);255void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw);256void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw);257void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);258void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,259 u8 type, u8 *pdirection, u32 *poutwrite_val);260#endif261