2516 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2013 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../efuse.h"6#include "../base.h"7#include "../regd.h"8#include "../cam.h"9#include "../ps.h"10#include "../pci.h"11#include "../pwrseqcmd.h"12#include "reg.h"13#include "def.h"14#include "phy.h"15#include "dm.h"16#include "fw.h"17#include "led.h"18#include "hw.h"19#include "pwrseq.h"20 21#define LLT_CONFIG 522 23static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,24 u8 set_bits, u8 clear_bits)25{26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));27 struct rtl_priv *rtlpriv = rtl_priv(hw);28 29 rtlpci->reg_bcn_ctrl_val |= set_bits;30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;31 32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);33}34 35static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)36{37 struct rtl_priv *rtlpriv = rtl_priv(hw);38 u8 tmp1byte;39 40 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);43 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);44 tmp1byte &= ~(BIT(0));45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);46}47 48static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)49{50 struct rtl_priv *rtlpriv = rtl_priv(hw);51 u8 tmp1byte;52 53 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);56 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);57 tmp1byte |= BIT(0);58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);59}60 61static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)62{63 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));64}65 66static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)67{68 struct rtl_priv *rtlpriv = rtl_priv(hw);69 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));70 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];71 struct sk_buff_head free_list;72 unsigned long flags;73 74 skb_queue_head_init(&free_list);75 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);76 while (skb_queue_len(&ring->queue)) {77 struct rtl_tx_desc *entry = &ring->desc[ring->idx];78 struct sk_buff *skb = __skb_dequeue(&ring->queue);79 80 dma_unmap_single(&rtlpci->pdev->dev,81 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,82 true, HW_DESC_TXBUFF_ADDR),83 skb->len, DMA_TO_DEVICE);84 __skb_queue_tail(&free_list, skb);85 ring->idx = (ring->idx + 1) % ring->entries;86 }87 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);88 89 __skb_queue_purge(&free_list);90}91 92static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)93{94 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);95}96 97static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,98 u8 rpwm_val, bool b_need_turn_off_ckk)99{100 struct rtl_priv *rtlpriv = rtl_priv(hw);101 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));102 bool b_support_remote_wake_up;103 u32 count = 0, isr_regaddr, content;104 bool schedule_timer = b_need_turn_off_ckk;105 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,106 (u8 *)(&b_support_remote_wake_up));107 108 if (!rtlhal->fw_ready)109 return;110 if (!rtlpriv->psc.fw_current_inpsmode)111 return;112 113 while (1) {114 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);115 if (rtlhal->fw_clk_change_in_progress) {116 while (rtlhal->fw_clk_change_in_progress) {117 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);118 count++;119 udelay(100);120 if (count > 1000)121 return;122 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);123 }124 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);125 } else {126 rtlhal->fw_clk_change_in_progress = false;127 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);128 break;129 }130 }131 132 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {133 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);134 if (FW_PS_IS_ACK(rpwm_val)) {135 isr_regaddr = REG_HISR;136 content = rtl_read_dword(rtlpriv, isr_regaddr);137 while (!(content & IMR_CPWM) && (count < 500)) {138 udelay(50);139 count++;140 content = rtl_read_dword(rtlpriv, isr_regaddr);141 }142 143 if (content & IMR_CPWM) {144 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);145 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;146 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,147 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",148 rtlhal->fw_ps_state);149 }150 }151 152 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);153 rtlhal->fw_clk_change_in_progress = false;154 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);155 if (schedule_timer) {156 mod_timer(&rtlpriv->works.fw_clockoff_timer,157 jiffies + MSECS(10));158 }159 160 } else {161 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);162 rtlhal->fw_clk_change_in_progress = false;163 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);164 }165}166 167static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,168 u8 rpwm_val)169{170 struct rtl_priv *rtlpriv = rtl_priv(hw);171 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));172 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));173 struct rtl8192_tx_ring *ring;174 enum rf_pwrstate rtstate;175 bool schedule_timer = false;176 u8 queue;177 178 if (!rtlhal->fw_ready)179 return;180 if (!rtlpriv->psc.fw_current_inpsmode)181 return;182 if (!rtlhal->allow_sw_to_change_hwclc)183 return;184 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));185 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)186 return;187 188 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {189 ring = &rtlpci->tx_ring[queue];190 if (skb_queue_len(&ring->queue)) {191 schedule_timer = true;192 break;193 }194 }195 196 if (schedule_timer) {197 mod_timer(&rtlpriv->works.fw_clockoff_timer,198 jiffies + MSECS(10));199 return;200 }201 202 if (FW_PS_STATE(rtlhal->fw_ps_state) !=203 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {204 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);205 if (!rtlhal->fw_clk_change_in_progress) {206 rtlhal->fw_clk_change_in_progress = true;207 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);208 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);209 rtl_write_word(rtlpriv, REG_HISR, 0x0100);210 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,211 &rpwm_val);212 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);213 rtlhal->fw_clk_change_in_progress = false;214 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);215 } else {216 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);217 mod_timer(&rtlpriv->works.fw_clockoff_timer,218 jiffies + MSECS(10));219 }220 }221}222 223static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)224{225 u8 rpwm_val = 0;226 227 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);228 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);229}230 231static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)232{233 u8 rpwm_val = 0;234 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;235 _rtl88ee_set_fw_clock_off(hw, rpwm_val);236}237 238void rtl88ee_fw_clk_off_timer_callback(struct timer_list *t)239{240 struct rtl_priv *rtlpriv = from_timer(rtlpriv, t,241 works.fw_clockoff_timer);242 struct ieee80211_hw *hw = rtlpriv->hw;243 244 _rtl88ee_set_fw_ps_rf_off_low_power(hw);245}246 247static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)248{249 struct rtl_priv *rtlpriv = rtl_priv(hw);250 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));251 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));252 bool fw_current_inps = false;253 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;254 255 if (ppsc->low_power_enable) {256 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */257 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);258 rtlhal->allow_sw_to_change_hwclc = false;259 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,260 &fw_pwrmode);261 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,262 (u8 *)(&fw_current_inps));263 } else {264 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);266 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,267 &fw_pwrmode);268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,269 (u8 *)(&fw_current_inps));270 }271}272 273static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)274{275 struct rtl_priv *rtlpriv = rtl_priv(hw);276 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));277 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));278 bool fw_current_inps = true;279 u8 rpwm_val;280 281 if (ppsc->low_power_enable) {282 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */283 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,284 (u8 *)(&fw_current_inps));285 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,286 &ppsc->fwctrl_psmode);287 rtlhal->allow_sw_to_change_hwclc = true;288 _rtl88ee_set_fw_clock_off(hw, rpwm_val);289 } else {290 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,292 (u8 *)(&fw_current_inps));293 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,294 &ppsc->fwctrl_psmode);295 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);296 }297}298 299void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)300{301 struct rtl_priv *rtlpriv = rtl_priv(hw);302 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));303 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));304 305 switch (variable) {306 case HW_VAR_RCR:307 *((u32 *)(val)) = rtlpci->receive_config;308 break;309 case HW_VAR_RF_STATE:310 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;311 break;312 case HW_VAR_FWLPS_RF_ON:{313 enum rf_pwrstate rfstate;314 u32 val_rcr;315 316 rtlpriv->cfg->ops->get_hw_reg(hw,317 HW_VAR_RF_STATE,318 (u8 *)(&rfstate));319 if (rfstate == ERFOFF) {320 *((bool *)(val)) = true;321 } else {322 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);323 val_rcr &= 0x00070000;324 if (val_rcr)325 *((bool *)(val)) = false;326 else327 *((bool *)(val)) = true;328 }329 break; }330 case HW_VAR_FW_PSMODE_STATUS:331 *((bool *)(val)) = ppsc->fw_current_inpsmode;332 break;333 case HW_VAR_CORRECT_TSF:{334 u64 tsf;335 u32 *ptsf_low = (u32 *)&tsf;336 u32 *ptsf_high = ((u32 *)&tsf) + 1;337 338 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));339 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);340 341 *((u64 *)(val)) = tsf;342 break; }343 case HAL_DEF_WOWLAN:344 break;345 default:346 pr_err("switch case %#x not processed\n", variable);347 break;348 }349}350 351void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)352{353 struct rtl_priv *rtlpriv = rtl_priv(hw);354 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));355 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));356 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));357 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));358 u8 idx;359 360 switch (variable) {361 case HW_VAR_ETHER_ADDR:362 for (idx = 0; idx < ETH_ALEN; idx++) {363 rtl_write_byte(rtlpriv, (REG_MACID + idx),364 val[idx]);365 }366 break;367 case HW_VAR_BASIC_RATE:{368 u16 b_rate_cfg = ((u16 *)val)[0];369 u8 rate_index = 0;370 b_rate_cfg = b_rate_cfg & 0x15f;371 b_rate_cfg |= 0x01;372 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);373 rtl_write_byte(rtlpriv, REG_RRSR + 1,374 (b_rate_cfg >> 8) & 0xff);375 while (b_rate_cfg > 0x1) {376 b_rate_cfg = (b_rate_cfg >> 1);377 rate_index++;378 }379 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,380 rate_index);381 break;382 }383 case HW_VAR_BSSID:384 for (idx = 0; idx < ETH_ALEN; idx++) {385 rtl_write_byte(rtlpriv, (REG_BSSID + idx),386 val[idx]);387 }388 break;389 case HW_VAR_SIFS:390 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);391 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);392 393 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);394 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);395 396 if (!mac->ht_enable)397 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,398 0x0e0e);399 else400 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,401 *((u16 *)val));402 break;403 case HW_VAR_SLOT_TIME:{404 u8 e_aci;405 406 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,407 "HW_VAR_SLOT_TIME %x\n", val[0]);408 409 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);410 411 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {412 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,413 &e_aci);414 }415 break;416 }417 case HW_VAR_ACK_PREAMBLE:{418 u8 reg_tmp;419 u8 short_preamble = (bool)*val;420 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);421 if (short_preamble) {422 reg_tmp |= 0x02;423 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +424 2, reg_tmp);425 } else {426 reg_tmp |= 0xFD;427 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +428 2, reg_tmp);429 }430 break; }431 case HW_VAR_WPA_CONFIG:432 rtl_write_byte(rtlpriv, REG_SECCFG, *val);433 break;434 case HW_VAR_AMPDU_MIN_SPACE:{435 u8 min_spacing_to_set;436 437 min_spacing_to_set = *val;438 if (min_spacing_to_set <= 7) {439 440 mac->min_space_cfg = ((mac->min_space_cfg &441 0xf8) |442 min_spacing_to_set);443 444 *val = min_spacing_to_set;445 446 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,447 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",448 mac->min_space_cfg);449 450 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,451 mac->min_space_cfg);452 }453 break; }454 case HW_VAR_SHORTGI_DENSITY:{455 u8 density_to_set;456 457 density_to_set = *val;458 mac->min_space_cfg |= (density_to_set << 3);459 460 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,461 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",462 mac->min_space_cfg);463 464 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,465 mac->min_space_cfg);466 break;467 }468 case HW_VAR_AMPDU_FACTOR:{469 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };470 u8 factor_toset;471 u8 *p_regtoset = NULL;472 u8 index = 0;473 474 p_regtoset = regtoset_normal;475 476 factor_toset = *val;477 if (factor_toset <= 3) {478 factor_toset = (1 << (factor_toset + 2));479 if (factor_toset > 0xf)480 factor_toset = 0xf;481 482 for (index = 0; index < 4; index++) {483 if ((p_regtoset[index] & 0xf0) >484 (factor_toset << 4))485 p_regtoset[index] =486 (p_regtoset[index] & 0x0f) |487 (factor_toset << 4);488 489 if ((p_regtoset[index] & 0x0f) >490 factor_toset)491 p_regtoset[index] =492 (p_regtoset[index] & 0xf0) |493 (factor_toset);494 495 rtl_write_byte(rtlpriv,496 (REG_AGGLEN_LMT + index),497 p_regtoset[index]);498 499 }500 501 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,502 "Set HW_VAR_AMPDU_FACTOR: %#x\n",503 factor_toset);504 }505 break; }506 case HW_VAR_AC_PARAM:{507 u8 e_aci = *val;508 rtl88e_dm_init_edca_turbo(hw);509 510 if (rtlpci->acm_method != EACMWAY2_SW)511 rtlpriv->cfg->ops->set_hw_reg(hw,512 HW_VAR_ACM_CTRL,513 &e_aci);514 break; }515 case HW_VAR_ACM_CTRL:{516 u8 e_aci = *val;517 union aci_aifsn *p_aci_aifsn =518 (union aci_aifsn *)(&(mac->ac[0].aifs));519 u8 acm = p_aci_aifsn->f.acm;520 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);521 522 acm_ctrl = acm_ctrl |523 ((rtlpci->acm_method == 2) ? 0x0 : 0x1);524 525 if (acm) {526 switch (e_aci) {527 case AC0_BE:528 acm_ctrl |= ACMHW_BEQEN;529 break;530 case AC2_VI:531 acm_ctrl |= ACMHW_VIQEN;532 break;533 case AC3_VO:534 acm_ctrl |= ACMHW_VOQEN;535 break;536 default:537 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,538 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",539 acm);540 break;541 }542 } else {543 switch (e_aci) {544 case AC0_BE:545 acm_ctrl &= (~ACMHW_BEQEN);546 break;547 case AC2_VI:548 acm_ctrl &= (~ACMHW_VIQEN);549 break;550 case AC3_VO:551 acm_ctrl &= (~ACMHW_VOQEN);552 break;553 default:554 pr_err("switch case %#x not processed\n",555 e_aci);556 break;557 }558 }559 560 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,561 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",562 acm_ctrl);563 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);564 break; }565 case HW_VAR_RCR:566 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);567 rtlpci->receive_config = ((u32 *)(val))[0];568 break;569 case HW_VAR_RETRY_LIMIT:{570 u8 retry_limit = *val;571 572 rtl_write_word(rtlpriv, REG_RL,573 retry_limit << RETRY_LIMIT_SHORT_SHIFT |574 retry_limit << RETRY_LIMIT_LONG_SHIFT);575 break; }576 case HW_VAR_DUAL_TSF_RST:577 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));578 break;579 case HW_VAR_EFUSE_BYTES:580 rtlefuse->efuse_usedbytes = *((u16 *)val);581 break;582 case HW_VAR_EFUSE_USAGE:583 rtlefuse->efuse_usedpercentage = *val;584 break;585 case HW_VAR_IO_CMD:586 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));587 break;588 case HW_VAR_SET_RPWM:{589 u8 rpwm_val;590 591 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);592 udelay(1);593 594 if (rpwm_val & BIT(7)) {595 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);596 } else {597 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));598 }599 break; }600 case HW_VAR_H2C_FW_PWRMODE:601 rtl88e_set_fw_pwrmode_cmd(hw, *val);602 break;603 case HW_VAR_FW_PSMODE_STATUS:604 ppsc->fw_current_inpsmode = *((bool *)val);605 break;606 case HW_VAR_RESUME_CLK_ON:607 _rtl88ee_set_fw_ps_rf_on(hw);608 break;609 case HW_VAR_FW_LPS_ACTION:{610 bool enter_fwlps = *((bool *)val);611 612 if (enter_fwlps)613 _rtl88ee_fwlps_enter(hw);614 else615 _rtl88ee_fwlps_leave(hw);616 617 break; }618 case HW_VAR_H2C_FW_JOINBSSRPT:{619 u8 mstatus = *val;620 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;621 u8 count = 0, dlbcn_count = 0;622 bool b_recover = false;623 624 if (mstatus == RT_MEDIA_CONNECT) {625 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,626 NULL);627 628 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);629 rtl_write_byte(rtlpriv, REG_CR + 1,630 (tmp_regcr | BIT(0)));631 632 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));633 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);634 635 tmp_reg422 =636 rtl_read_byte(rtlpriv,637 REG_FWHW_TXQ_CTRL + 2);638 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,639 tmp_reg422 & (~BIT(6)));640 if (tmp_reg422 & BIT(6))641 b_recover = true;642 643 do {644 bcnvalid_reg = rtl_read_byte(rtlpriv,645 REG_TDECTRL+2);646 rtl_write_byte(rtlpriv, REG_TDECTRL+2,647 (bcnvalid_reg | BIT(0)));648 _rtl88ee_return_beacon_queue_skb(hw);649 650 rtl88e_set_fw_rsvdpagepkt(hw, 0);651 bcnvalid_reg = rtl_read_byte(rtlpriv,652 REG_TDECTRL+2);653 count = 0;654 while (!(bcnvalid_reg & BIT(0)) && count < 20) {655 count++;656 udelay(10);657 bcnvalid_reg =658 rtl_read_byte(rtlpriv, REG_TDECTRL+2);659 }660 dlbcn_count++;661 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);662 663 if (bcnvalid_reg & BIT(0))664 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));665 666 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);667 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));668 669 if (b_recover) {670 rtl_write_byte(rtlpriv,671 REG_FWHW_TXQ_CTRL + 2,672 tmp_reg422);673 }674 675 rtl_write_byte(rtlpriv, REG_CR + 1,676 (tmp_regcr & ~(BIT(0))));677 }678 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));679 break; }680 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:681 rtl88e_set_p2p_ps_offload_cmd(hw, *val);682 break;683 case HW_VAR_AID:{684 u16 u2btmp;685 686 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);687 u2btmp &= 0xC000;688 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |689 mac->assoc_id));690 break; }691 case HW_VAR_CORRECT_TSF:{692 u8 btype_ibss = *val;693 694 if (btype_ibss)695 _rtl88ee_stop_tx_beacon(hw);696 697 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));698 699 rtl_write_dword(rtlpriv, REG_TSFTR,700 (u32)(mac->tsf & 0xffffffff));701 rtl_write_dword(rtlpriv, REG_TSFTR + 4,702 (u32)((mac->tsf >> 32) & 0xffffffff));703 704 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);705 706 if (btype_ibss)707 _rtl88ee_resume_tx_beacon(hw);708 break; }709 case HW_VAR_KEEP_ALIVE: {710 u8 array[2];711 712 array[0] = 0xff;713 array[1] = *((u8 *)val);714 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,715 2, array);716 break; }717 default:718 pr_err("switch case %#x not processed\n", variable);719 break;720 }721}722 723static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)724{725 struct rtl_priv *rtlpriv = rtl_priv(hw);726 bool status = true;727 long count = 0;728 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |729 _LLT_OP(_LLT_WRITE_ACCESS);730 731 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);732 733 do {734 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);735 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))736 break;737 738 if (count > POLLING_LLT_THRESHOLD) {739 pr_err("Failed to polling write LLT done at address %d!\n",740 address);741 status = false;742 break;743 }744 } while (++count);745 746 return status;747}748 749static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)750{751 struct rtl_priv *rtlpriv = rtl_priv(hw);752 unsigned short i;753 u8 txpktbuf_bndy;754 u8 maxpage;755 bool status;756 757 maxpage = 0xAF;758 txpktbuf_bndy = 0xAB;759 760 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);761 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);762 763 /*0x2600 MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */764 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));765 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);766 767 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);768 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);769 770 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);771 rtl_write_byte(rtlpriv, REG_PBP, 0x11);772 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);773 774 for (i = 0; i < (txpktbuf_bndy - 1); i++) {775 status = _rtl88ee_llt_write(hw, i, i + 1);776 if (!status)777 return status;778 }779 780 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);781 if (!status)782 return status;783 784 for (i = txpktbuf_bndy; i < maxpage; i++) {785 status = _rtl88ee_llt_write(hw, i, (i + 1));786 if (!status)787 return status;788 }789 790 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);791 if (!status)792 return status;793 794 return true;795}796 797static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)798{799 struct rtl_priv *rtlpriv = rtl_priv(hw);800 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));801 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;802 803 if (rtlpriv->rtlhal.up_first_time)804 return;805 806 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)807 rtl88ee_sw_led_on(hw, pin0);808 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)809 rtl88ee_sw_led_on(hw, pin0);810 else811 rtl88ee_sw_led_off(hw, pin0);812}813 814static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)815{816 struct rtl_priv *rtlpriv = rtl_priv(hw);817 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));818 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));819 820 u8 bytetmp;821 u16 wordtmp;822 823 /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */824 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));825 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);826 /*Auto Power Down to CHIP-off State*/827 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));828 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);829 830 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);831 /* HW Power on sequence */832 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,833 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,834 RTL8188EE_NIC_ENABLE_FLOW)) {835 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,836 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");837 return false;838 }839 840 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);841 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);842 843 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);844 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));845 846 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);847 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));848 849 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);850 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));851 852 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);853 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));854 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);855 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);856 857 /*Add for wake up online*/858 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);859 860 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));861 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);862 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));863 rtl_write_byte(rtlpriv, 0x367, 0x80);864 865 rtl_write_word(rtlpriv, REG_CR, 0x2ff);866 rtl_write_byte(rtlpriv, REG_CR+1, 0x06);867 rtl_write_byte(rtlpriv, MSR, 0x00);868 869 if (!rtlhal->mac_func_enable) {870 if (!_rtl88ee_llt_table_init(hw)) {871 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,872 "LLT table init fail\n");873 return false;874 }875 }876 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);877 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);878 879 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);880 wordtmp &= 0xf;881 wordtmp |= 0xE771;882 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);883 884 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);885 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);886 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);887 888 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,889 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &890 DMA_BIT_MASK(32));891 rtl_write_dword(rtlpriv, REG_MGQ_DESA,892 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &893 DMA_BIT_MASK(32));894 rtl_write_dword(rtlpriv, REG_VOQ_DESA,895 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));896 rtl_write_dword(rtlpriv, REG_VIQ_DESA,897 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));898 rtl_write_dword(rtlpriv, REG_BEQ_DESA,899 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));900 rtl_write_dword(rtlpriv, REG_BKQ_DESA,901 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));902 rtl_write_dword(rtlpriv, REG_HQ_DESA,903 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &904 DMA_BIT_MASK(32));905 rtl_write_dword(rtlpriv, REG_RX_DESA,906 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &907 DMA_BIT_MASK(32));908 909 /* if we want to support 64 bit DMA, we should set it here,910 * but now we do not support 64 bit DMA911 */912 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);913 914 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);915 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */916 917 if (rtlhal->earlymode_enable) {/*Early mode enable*/918 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);919 bytetmp |= 0x1f;920 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);921 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);922 }923 _rtl88ee_gen_refresh_led_state(hw);924 return true;925}926 927static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)928{929 struct rtl_priv *rtlpriv = rtl_priv(hw);930 u32 reg_prsr;931 932 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;933 934 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);935 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);936}937 938static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)939{940 struct rtl_priv *rtlpriv = rtl_priv(hw);941 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));942 u8 tmp1byte = 0;943 u32 tmp4byte = 0, count = 0;944 945 rtl_write_word(rtlpriv, 0x354, 0x8104);946 rtl_write_word(rtlpriv, 0x358, 0x24);947 948 rtl_write_word(rtlpriv, 0x350, 0x70c);949 rtl_write_byte(rtlpriv, 0x352, 0x2);950 tmp1byte = rtl_read_byte(rtlpriv, 0x352);951 count = 0;952 while (tmp1byte && count < 20) {953 udelay(10);954 tmp1byte = rtl_read_byte(rtlpriv, 0x352);955 count++;956 }957 if (0 == tmp1byte) {958 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);959 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));960 rtl_write_word(rtlpriv, 0x350, 0xf70c);961 rtl_write_byte(rtlpriv, 0x352, 0x1);962 }963 964 tmp1byte = rtl_read_byte(rtlpriv, 0x352);965 count = 0;966 while (tmp1byte && count < 20) {967 udelay(10);968 tmp1byte = rtl_read_byte(rtlpriv, 0x352);969 count++;970 }971 972 rtl_write_word(rtlpriv, 0x350, 0x718);973 rtl_write_byte(rtlpriv, 0x352, 0x2);974 tmp1byte = rtl_read_byte(rtlpriv, 0x352);975 count = 0;976 while (tmp1byte && count < 20) {977 udelay(10);978 tmp1byte = rtl_read_byte(rtlpriv, 0x352);979 count++;980 }981 982 if (ppsc->support_backdoor || (0 == tmp1byte)) {983 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);984 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));985 rtl_write_word(rtlpriv, 0x350, 0xf718);986 rtl_write_byte(rtlpriv, 0x352, 0x1);987 }988 989 tmp1byte = rtl_read_byte(rtlpriv, 0x352);990 count = 0;991 while (tmp1byte && count < 20) {992 udelay(10);993 tmp1byte = rtl_read_byte(rtlpriv, 0x352);994 count++;995 }996}997 998void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)999{1000 struct rtl_priv *rtlpriv = rtl_priv(hw);1001 u8 sec_reg_value;1002 1003 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,1004 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",1005 rtlpriv->sec.pairwise_enc_algorithm,1006 rtlpriv->sec.group_enc_algorithm);1007 1008 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {1009 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,1010 "not open hw encryption\n");1011 return;1012 }1013 1014 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;1015 1016 if (rtlpriv->sec.use_defaultkey) {1017 sec_reg_value |= SCR_TXUSEDK;1018 sec_reg_value |= SCR_RXUSEDK;1019 }1020 1021 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);1022 1023 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);1024 1025 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,1026 "The SECR-value %x\n", sec_reg_value);1027 1028 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);1029}1030 1031int rtl88ee_hw_init(struct ieee80211_hw *hw)1032{1033 struct rtl_priv *rtlpriv = rtl_priv(hw);1034 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1035 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1036 struct rtl_phy *rtlphy = &(rtlpriv->phy);1037 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1038 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1039 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));1040 bool rtstatus;1041 int err = 0;1042 u8 tmp_u1b, u1byte;1043 unsigned long flags;1044 1045 rtlpriv->rtlhal.being_init_adapter = true;1046 /* As this function can take a very long time (up to 350 ms)1047 * and can be called with irqs disabled, reenable the irqs1048 * to let the other devices continue being serviced.1049 *1050 * It is safe doing so since our own interrupts will only be enabled1051 * in a subsequent step.1052 */1053 local_save_flags(flags);1054 local_irq_enable();1055 rtlhal->fw_ready = false;1056 1057 rtlpriv->intf_ops->disable_aspm(hw);1058 1059 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);1060 u1byte = rtl_read_byte(rtlpriv, REG_CR);1061 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {1062 rtlhal->mac_func_enable = true;1063 } else {1064 rtlhal->mac_func_enable = false;1065 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;1066 }1067 1068 rtstatus = _rtl88ee_init_mac(hw);1069 if (!rtstatus) {1070 pr_info("Init MAC failed\n");1071 err = 1;1072 goto exit;1073 }1074 1075 err = rtl88e_download_fw(hw, false);1076 if (err) {1077 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,1078 "Failed to download FW. Init HW without FW now..\n");1079 err = 1;1080 goto exit;1081 }1082 rtlhal->fw_ready = true;1083 /*fw related variable initialize */1084 rtlhal->last_hmeboxnum = 0;1085 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;1086 rtlhal->fw_clk_change_in_progress = false;1087 rtlhal->allow_sw_to_change_hwclc = false;1088 ppsc->fw_current_inpsmode = false;1089 1090 rtl88e_phy_mac_config(hw);1091 /* because last function modify RCR, so we update1092 * rcr var here, or TP will unstable for receive_config1093 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx1094 * RCR_APP_ICV will cause mac80211 unassoc for cisco 12521095 */1096 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);1097 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);1098 1099 rtl88e_phy_bb_config(hw);1100 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);1101 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);1102 1103 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;1104 rtl88e_phy_rf_config(hw);1105 1106 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,1107 RF_CHNLBW, RFREG_OFFSET_MASK);1108 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;1109 1110 _rtl88ee_hw_configure(hw);1111 rtl_cam_reset_all_entry(hw);1112 rtl88ee_enable_hw_security_config(hw);1113 1114 rtlhal->mac_func_enable = true;1115 ppsc->rfpwr_state = ERFON;1116 1117 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);1118 _rtl88ee_enable_aspm_back_door(hw);1119 rtlpriv->intf_ops->enable_aspm(hw);1120 1121 if (ppsc->rfpwr_state == ERFON) {1122 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||1123 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&1124 (rtlhal->oem_id == RT_CID_819X_HP))) {1125 rtl88e_phy_set_rfpath_switch(hw, true);1126 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;1127 } else {1128 rtl88e_phy_set_rfpath_switch(hw, false);1129 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;1130 }1131 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",1132 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?1133 ("MAIN_ANT") : ("AUX_ANT"));1134 1135 if (rtlphy->iqk_initialized) {1136 rtl88e_phy_iq_calibrate(hw, true);1137 } else {1138 rtl88e_phy_iq_calibrate(hw, false);1139 rtlphy->iqk_initialized = true;1140 }1141 1142 rtl88e_dm_check_txpower_tracking(hw);1143 rtl88e_phy_lc_calibrate(hw);1144 }1145 1146 tmp_u1b = efuse_read_1byte(hw, 0x1FA);1147 if (!(tmp_u1b & BIT(0))) {1148 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);1149 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");1150 }1151 1152 if (!(tmp_u1b & BIT(4))) {1153 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);1154 tmp_u1b &= 0x0F;1155 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);1156 udelay(10);1157 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);1158 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");1159 }1160 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128));1161 rtl88e_dm_init(hw);1162exit:1163 local_irq_restore(flags);1164 rtlpriv->rtlhal.being_init_adapter = false;1165 return err;1166}1167 1168static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)1169{1170 struct rtl_priv *rtlpriv = rtl_priv(hw);1171 struct rtl_phy *rtlphy = &(rtlpriv->phy);1172 enum version_8188e version = VERSION_UNKNOWN;1173 u32 value32;1174 1175 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);1176 if (value32 & TRP_VAUX_EN) {1177 version = (enum version_8188e) VERSION_TEST_CHIP_88E;1178 } else {1179 version = NORMAL_CHIP;1180 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);1181 version = version | ((value32 & VENDOR_ID) ?1182 CHIP_VENDOR_UMC : 0);1183 }1184 1185 rtlphy->rf_type = RF_1T1R;1186 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1187 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?1188 "RF_2T2R" : "RF_1T1R");1189 1190 return version;1191}1192 1193static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,1194 enum nl80211_iftype type)1195{1196 struct rtl_priv *rtlpriv = rtl_priv(hw);1197 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;1198 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;1199 u8 mode = MSR_NOLINK;1200 1201 switch (type) {1202 case NL80211_IFTYPE_UNSPECIFIED:1203 mode = MSR_NOLINK;1204 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1205 "Set Network type to NO LINK!\n");1206 break;1207 case NL80211_IFTYPE_ADHOC:1208 case NL80211_IFTYPE_MESH_POINT:1209 mode = MSR_ADHOC;1210 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1211 "Set Network type to Ad Hoc!\n");1212 break;1213 case NL80211_IFTYPE_STATION:1214 mode = MSR_INFRA;1215 ledaction = LED_CTL_LINK;1216 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1217 "Set Network type to STA!\n");1218 break;1219 case NL80211_IFTYPE_AP:1220 mode = MSR_AP;1221 ledaction = LED_CTL_LINK;1222 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1223 "Set Network type to AP!\n");1224 break;1225 default:1226 pr_err("Network type %d not support!\n", type);1227 return 1;1228 }1229 1230 /* MSR_INFRA == Link in infrastructure network;1231 * MSR_ADHOC == Link in ad hoc network;1232 * Therefore, check link state is necessary.1233 *1234 * MSR_AP == AP mode; link state is not cared here.1235 */1236 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {1237 mode = MSR_NOLINK;1238 ledaction = LED_CTL_NO_LINK;1239 }1240 1241 if (mode == MSR_NOLINK || mode == MSR_INFRA) {1242 _rtl88ee_stop_tx_beacon(hw);1243 _rtl88ee_enable_bcn_sub_func(hw);1244 } else if (mode == MSR_ADHOC || mode == MSR_AP) {1245 _rtl88ee_resume_tx_beacon(hw);1246 _rtl88ee_disable_bcn_sub_func(hw);1247 } else {1248 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,1249 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",1250 mode);1251 }1252 1253 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);1254 rtlpriv->cfg->ops->led_control(hw, ledaction);1255 if (mode == MSR_AP)1256 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);1257 else1258 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);1259 return 0;1260}1261 1262void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)1263{1264 struct rtl_priv *rtlpriv = rtl_priv(hw);1265 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1266 u32 reg_rcr = rtlpci->receive_config;1267 1268 if (rtlpriv->psc.rfpwr_state != ERFON)1269 return;1270 1271 if (check_bssid) {1272 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);1273 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,1274 (u8 *)(®_rcr));1275 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));1276 } else if (!check_bssid) {1277 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));1278 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);1279 rtlpriv->cfg->ops->set_hw_reg(hw,1280 HW_VAR_RCR, (u8 *)(®_rcr));1281 }1282 1283}1284 1285int rtl88ee_set_network_type(struct ieee80211_hw *hw,1286 enum nl80211_iftype type)1287{1288 struct rtl_priv *rtlpriv = rtl_priv(hw);1289 1290 if (_rtl88ee_set_media_status(hw, type))1291 return -EOPNOTSUPP;1292 1293 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {1294 if (type != NL80211_IFTYPE_AP &&1295 type != NL80211_IFTYPE_MESH_POINT)1296 rtl88ee_set_check_bssid(hw, true);1297 } else {1298 rtl88ee_set_check_bssid(hw, false);1299 }1300 1301 return 0;1302}1303 1304/* don't set REG_EDCA_BE_PARAM here1305 * because mac80211 will send pkt when scan1306 */1307void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)1308{1309 struct rtl_priv *rtlpriv = rtl_priv(hw);1310 rtl88e_dm_init_edca_turbo(hw);1311 switch (aci) {1312 case AC1_BK:1313 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);1314 break;1315 case AC0_BE:1316 break;1317 case AC2_VI:1318 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);1319 break;1320 case AC3_VO:1321 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);1322 break;1323 default:1324 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci);1325 break;1326 }1327}1328 1329void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)1330{1331 struct rtl_priv *rtlpriv = rtl_priv(hw);1332 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1333 1334 rtl_write_dword(rtlpriv, REG_HIMR,1335 rtlpci->irq_mask[0] & 0xFFFFFFFF);1336 rtl_write_dword(rtlpriv, REG_HIMRE,1337 rtlpci->irq_mask[1] & 0xFFFFFFFF);1338 rtlpci->irq_enabled = true;1339 /* there are some C2H CMDs have been sent1340 * before system interrupt is enabled, e.g., C2H, CPWM.1341 * So we need to clear all C2H events that FW has notified,1342 * otherwise FW won't schedule any commands anymore.1343 */1344 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);1345 /*enable system interrupt*/1346 rtl_write_dword(rtlpriv, REG_HSIMR,1347 rtlpci->sys_irq_mask & 0xFFFFFFFF);1348}1349 1350void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)1351{1352 struct rtl_priv *rtlpriv = rtl_priv(hw);1353 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1354 1355 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);1356 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);1357 rtlpci->irq_enabled = false;1358 /*synchronize_irq(rtlpci->pdev->irq);*/1359}1360 1361static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)1362{1363 struct rtl_priv *rtlpriv = rtl_priv(hw);1364 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1365 u8 u1b_tmp;1366 u32 count = 0;1367 rtlhal->mac_func_enable = false;1368 rtlpriv->intf_ops->enable_aspm(hw);1369 1370 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");1371 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);1372 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));1373 1374 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);1375 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {1376 udelay(10);1377 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);1378 count++;1379 }1380 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);1381 1382 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,1383 PWR_INTF_PCI_MSK,1384 RTL8188EE_NIC_LPS_ENTER_FLOW);1385 1386 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);1387 1388 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)1389 rtl88e_firmware_selfreset(hw);1390 1391 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);1392 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));1393 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);1394 1395 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);1396 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));1397 1398 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,1399 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);1400 1401 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);1402 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));1403 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);1404 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));1405 1406 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);1407 1408 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);1409 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);1410 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);1411 1412 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);1413 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);1414 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);1415 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);1416 1417 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);1418}1419 1420void rtl88ee_card_disable(struct ieee80211_hw *hw)1421{1422 struct rtl_priv *rtlpriv = rtl_priv(hw);1423 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1424 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1425 enum nl80211_iftype opmode;1426 1427 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");1428 1429 mac->link_state = MAC80211_NOLINK;1430 opmode = NL80211_IFTYPE_UNSPECIFIED;1431 1432 _rtl88ee_set_media_status(hw, opmode);1433 1434 if (rtlpriv->rtlhal.driver_is_goingto_unload ||1435 ppsc->rfoff_reason > RF_CHANGE_BY_PS)1436 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);1437 1438 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);1439 _rtl88ee_poweroff_adapter(hw);1440 1441 /* after power off we should do iqk again */1442 rtlpriv->phy.iqk_initialized = false;1443}1444 1445void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,1446 struct rtl_int *intvec)1447{1448 struct rtl_priv *rtlpriv = rtl_priv(hw);1449 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1450 1451 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];1452 rtl_write_dword(rtlpriv, ISR, intvec->inta);1453 1454 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];1455 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);1456 1457}1458 1459void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)1460{1461 struct rtl_priv *rtlpriv = rtl_priv(hw);1462 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1463 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1464 u16 bcn_interval, atim_window;1465 1466 bcn_interval = mac->beacon_interval;1467 atim_window = 2; /*FIX MERGE */1468 rtl88ee_disable_interrupt(hw);1469 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);1470 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1471 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);1472 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);1473 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);1474 rtl_write_byte(rtlpriv, 0x606, 0x30);1475 rtlpci->reg_bcn_ctrl_val |= BIT(3);1476 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);1477 /*rtl88ee_enable_interrupt(hw);*/1478}1479 1480void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)1481{1482 struct rtl_priv *rtlpriv = rtl_priv(hw);1483 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1484 u16 bcn_interval = mac->beacon_interval;1485 1486 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,1487 "beacon_interval:%d\n", bcn_interval);1488 /*rtl88ee_disable_interrupt(hw);*/1489 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1490 /*rtl88ee_enable_interrupt(hw);*/1491}1492 1493void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,1494 u32 add_msr, u32 rm_msr)1495{1496 struct rtl_priv *rtlpriv = rtl_priv(hw);1497 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1498 1499 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,1500 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);1501 1502 if (add_msr)1503 rtlpci->irq_mask[0] |= add_msr;1504 if (rm_msr)1505 rtlpci->irq_mask[0] &= (~rm_msr);1506 rtl88ee_disable_interrupt(hw);1507 rtl88ee_enable_interrupt(hw);1508}1509 1510static u8 _rtl88e_get_chnl_group(u8 chnl)1511{1512 u8 group = 0;1513 1514 if (chnl < 3)1515 group = 0;1516 else if (chnl < 6)1517 group = 1;1518 else if (chnl < 9)1519 group = 2;1520 else if (chnl < 12)1521 group = 3;1522 else if (chnl < 14)1523 group = 4;1524 else if (chnl == 14)1525 group = 5;1526 1527 return group;1528}1529 1530static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)1531{1532 int group, txcnt;1533 1534 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {1535 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;1536 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;1537 }1538 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {1539 if (txcnt == 0) {1540 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;1541 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;1542 } else {1543 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;1544 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;1545 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;1546 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;1547 }1548 }1549}1550 1551static void read_power_value_fromprom(struct ieee80211_hw *hw,1552 struct txpower_info_2g *pwrinfo24g,1553 struct txpower_info_5g *pwrinfo5g,1554 bool autoload_fail, u8 *hwinfo)1555{1556 struct rtl_priv *rtlpriv = rtl_priv(hw);1557 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;1558 1559 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1560 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",1561 (eeaddr + 1), hwinfo[eeaddr + 1]);1562 if (0xFF == hwinfo[eeaddr+1]) /*YJ,add,120316*/1563 autoload_fail = true;1564 1565 if (autoload_fail) {1566 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1567 "auto load fail : Use Default value!\n");1568 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {1569 /* 2.4G default value */1570 set_24g_base(pwrinfo24g, rfpath);1571 }1572 return;1573 }1574 1575 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {1576 /*2.4G default value*/1577 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {1578 pwrinfo24g->index_cck_base[rfpath][group] =1579 hwinfo[eeaddr++];1580 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)1581 pwrinfo24g->index_cck_base[rfpath][group] =1582 0x2D;1583 }1584 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {1585 pwrinfo24g->index_bw40_base[rfpath][group] =1586 hwinfo[eeaddr++];1587 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)1588 pwrinfo24g->index_bw40_base[rfpath][group] =1589 0x2D;1590 }1591 pwrinfo24g->bw40_diff[rfpath][0] = 0;1592 if (hwinfo[eeaddr] == 0xFF) {1593 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;1594 } else {1595 pwrinfo24g->bw20_diff[rfpath][0] =1596 (hwinfo[eeaddr]&0xf0)>>4;1597 /*bit sign number to 8 bit sign number*/1598 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))1599 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;1600 }1601 1602 if (hwinfo[eeaddr] == 0xFF) {1603 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;1604 } else {1605 pwrinfo24g->ofdm_diff[rfpath][0] =1606 (hwinfo[eeaddr]&0x0f);1607 /*bit sign number to 8 bit sign number*/1608 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))1609 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;1610 }1611 pwrinfo24g->cck_diff[rfpath][0] = 0;1612 eeaddr++;1613 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {1614 if (hwinfo[eeaddr] == 0xFF) {1615 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;1616 } else {1617 pwrinfo24g->bw40_diff[rfpath][txcnt] =1618 (hwinfo[eeaddr]&0xf0)>>4;1619 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &1620 BIT(3))1621 pwrinfo24g->bw40_diff[rfpath][txcnt] |=1622 0xF0;1623 }1624 1625 if (hwinfo[eeaddr] == 0xFF) {1626 pwrinfo24g->bw20_diff[rfpath][txcnt] =1627 0xFE;1628 } else {1629 pwrinfo24g->bw20_diff[rfpath][txcnt] =1630 (hwinfo[eeaddr]&0x0f);1631 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &1632 BIT(3))1633 pwrinfo24g->bw20_diff[rfpath][txcnt] |=1634 0xF0;1635 }1636 eeaddr++;1637 1638 if (hwinfo[eeaddr] == 0xFF) {1639 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;1640 } else {1641 pwrinfo24g->ofdm_diff[rfpath][txcnt] =1642 (hwinfo[eeaddr]&0xf0)>>4;1643 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &1644 BIT(3))1645 pwrinfo24g->ofdm_diff[rfpath][txcnt] |=1646 0xF0;1647 }1648 1649 if (hwinfo[eeaddr] == 0xFF) {1650 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;1651 } else {1652 pwrinfo24g->cck_diff[rfpath][txcnt] =1653 (hwinfo[eeaddr]&0x0f);1654 if (pwrinfo24g->cck_diff[rfpath][txcnt] &1655 BIT(3))1656 pwrinfo24g->cck_diff[rfpath][txcnt] |=1657 0xF0;1658 }1659 eeaddr++;1660 }1661 1662 /*5G default value*/1663 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {1664 pwrinfo5g->index_bw40_base[rfpath][group] =1665 hwinfo[eeaddr++];1666 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)1667 pwrinfo5g->index_bw40_base[rfpath][group] =1668 0xFE;1669 }1670 1671 pwrinfo5g->bw40_diff[rfpath][0] = 0;1672 1673 if (hwinfo[eeaddr] == 0xFF) {1674 pwrinfo5g->bw20_diff[rfpath][0] = 0;1675 } else {1676 pwrinfo5g->bw20_diff[rfpath][0] =1677 (hwinfo[eeaddr]&0xf0)>>4;1678 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))1679 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;1680 }1681 1682 if (hwinfo[eeaddr] == 0xFF) {1683 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;1684 } else {1685 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);1686 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))1687 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;1688 }1689 eeaddr++;1690 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {1691 if (hwinfo[eeaddr] == 0xFF) {1692 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE;1693 } else {1694 pwrinfo5g->bw40_diff[rfpath][txcnt] =1695 (hwinfo[eeaddr]&0xf0)>>4;1696 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &1697 BIT(3))1698 pwrinfo5g->bw40_diff[rfpath][txcnt] |=1699 0xF0;1700 }1701 1702 if (hwinfo[eeaddr] == 0xFF) {1703 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE;1704 } else {1705 pwrinfo5g->bw20_diff[rfpath][txcnt] =1706 (hwinfo[eeaddr]&0x0f);1707 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &1708 BIT(3))1709 pwrinfo5g->bw20_diff[rfpath][txcnt] |=1710 0xF0;1711 }1712 eeaddr++;1713 }1714 1715 if (hwinfo[eeaddr] == 0xFF) {1716 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;1717 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;1718 } else {1719 pwrinfo5g->ofdm_diff[rfpath][1] =1720 (hwinfo[eeaddr]&0xf0)>>4;1721 pwrinfo5g->ofdm_diff[rfpath][2] =1722 (hwinfo[eeaddr]&0x0f);1723 }1724 eeaddr++;1725 1726 if (hwinfo[eeaddr] == 0xFF)1727 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;1728 else1729 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);1730 eeaddr++;1731 1732 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {1733 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)1734 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE;1735 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))1736 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;1737 }1738 }1739}1740 1741static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,1742 bool autoload_fail,1743 u8 *hwinfo)1744{1745 struct rtl_priv *rtlpriv = rtl_priv(hw);1746 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));1747 struct txpower_info_2g pwrinfo24g;1748 struct txpower_info_5g pwrinfo5g;1749 u8 rf_path, index;1750 u8 i;1751 1752 read_power_value_fromprom(hw, &pwrinfo24g,1753 &pwrinfo5g, autoload_fail, hwinfo);1754 1755 for (rf_path = 0; rf_path < 2; rf_path++) {1756 for (i = 0; i < 14; i++) {1757 index = _rtl88e_get_chnl_group(i+1);1758 1759 rtlefuse->txpwrlevel_cck[rf_path][i] =1760 pwrinfo24g.index_cck_base[rf_path][index];1761 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =1762 pwrinfo24g.index_bw40_base[rf_path][index];1763 rtlefuse->txpwr_ht20diff[rf_path][i] =1764 pwrinfo24g.bw20_diff[rf_path][0];1765 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =1766 pwrinfo24g.ofdm_diff[rf_path][0];1767 }1768 1769 for (i = 0; i < 14; i++) {1770 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,1771 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",1772 rf_path, i,1773 rtlefuse->txpwrlevel_cck[rf_path][i],1774 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);1775 }1776 }1777 1778 if (!autoload_fail)1779 rtlefuse->eeprom_thermalmeter =1780 hwinfo[EEPROM_THERMAL_METER_88E];1781 else1782 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;1783 1784 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {1785 rtlefuse->apk_thermalmeterignore = true;1786 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;1787 }1788 1789 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;1790 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,1791 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);1792 1793 if (!autoload_fail) {1794 rtlefuse->eeprom_regulatory =1795 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/1796 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)1797 rtlefuse->eeprom_regulatory = 0;1798 } else {1799 rtlefuse->eeprom_regulatory = 0;1800 }1801 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,1802 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);1803}1804 1805static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)1806{1807 struct rtl_priv *rtlpriv = rtl_priv(hw);1808 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));1809 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1810 int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID,1811 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,1812 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,1813 COUNTRY_CODE_WORLD_WIDE_13};1814 u8 *hwinfo;1815 1816 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);1817 if (!hwinfo)1818 return;1819 1820 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))1821 goto exit;1822 1823 if (rtlefuse->eeprom_oemid == 0xFF)1824 rtlefuse->eeprom_oemid = 0;1825 1826 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1827 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);1828 /* set channel plan from efuse */1829 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;1830 /*tx power*/1831 _rtl88ee_read_txpower_info_from_hwpg(hw,1832 rtlefuse->autoload_failflag,1833 hwinfo);1834 rtlefuse->txpwr_fromeprom = true;1835 1836 rtl8188ee_read_bt_coexist_info_from_hwpg(hw,1837 rtlefuse->autoload_failflag,1838 hwinfo);1839 1840 /*board type*/1841 rtlefuse->board_type =1842 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);1843 rtlhal->board_type = rtlefuse->board_type;1844 /*Wake on wlan*/1845 rtlefuse->wowlan_enable =1846 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);1847 /*parse xtal*/1848 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];1849 if (hwinfo[EEPROM_XTAL_88E])1850 rtlefuse->crystalcap = 0x20;1851 /*antenna diversity*/1852 rtlefuse->antenna_div_cfg =1853 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;1854 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)1855 rtlefuse->antenna_div_cfg = 0;1856 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&1857 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)1858 rtlefuse->antenna_div_cfg = 0;1859 1860 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];1861 if (rtlefuse->antenna_div_type == 0xFF)1862 rtlefuse->antenna_div_type = 0x01;1863 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||1864 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)1865 rtlefuse->antenna_div_cfg = 1;1866 1867 if (rtlhal->oem_id == RT_CID_DEFAULT) {1868 switch (rtlefuse->eeprom_oemid) {1869 case EEPROM_CID_DEFAULT:1870 if (rtlefuse->eeprom_did == 0x8179) {1871 if (rtlefuse->eeprom_svid == 0x1025) {1872 rtlhal->oem_id = RT_CID_819X_ACER;1873 } else if ((rtlefuse->eeprom_svid == 0x10EC &&1874 rtlefuse->eeprom_smid == 0x0179) ||1875 (rtlefuse->eeprom_svid == 0x17AA &&1876 rtlefuse->eeprom_smid == 0x0179)) {1877 rtlhal->oem_id = RT_CID_819X_LENOVO;1878 } else if (rtlefuse->eeprom_svid == 0x103c &&1879 rtlefuse->eeprom_smid == 0x197d) {1880 rtlhal->oem_id = RT_CID_819X_HP;1881 } else {1882 rtlhal->oem_id = RT_CID_DEFAULT;1883 }1884 } else {1885 rtlhal->oem_id = RT_CID_DEFAULT;1886 }1887 break;1888 case EEPROM_CID_TOSHIBA:1889 rtlhal->oem_id = RT_CID_TOSHIBA;1890 break;1891 case EEPROM_CID_QMI:1892 rtlhal->oem_id = RT_CID_819X_QMI;1893 break;1894 case EEPROM_CID_WHQL:1895 default:1896 rtlhal->oem_id = RT_CID_DEFAULT;1897 break;1898 1899 }1900 }1901exit:1902 kfree(hwinfo);1903}1904 1905static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)1906{1907 struct rtl_priv *rtlpriv = rtl_priv(hw);1908 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1909 1910 rtlpriv->ledctl.led_opendrain = true;1911 1912 switch (rtlhal->oem_id) {1913 case RT_CID_819X_HP:1914 rtlpriv->ledctl.led_opendrain = true;1915 break;1916 case RT_CID_819X_LENOVO:1917 case RT_CID_DEFAULT:1918 case RT_CID_TOSHIBA:1919 case RT_CID_CCX:1920 case RT_CID_819X_ACER:1921 case RT_CID_WHQL:1922 default:1923 break;1924 }1925 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,1926 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);1927}1928 1929void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)1930{1931 struct rtl_priv *rtlpriv = rtl_priv(hw);1932 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));1933 struct rtl_phy *rtlphy = &(rtlpriv->phy);1934 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1935 u8 tmp_u1b;1936 1937 rtlhal->version = _rtl88ee_read_chip_version(hw);1938 if (get_rf_type(rtlphy) == RF_1T1R)1939 rtlpriv->dm.rfpath_rxenable[0] = true;1940 else1941 rtlpriv->dm.rfpath_rxenable[0] =1942 rtlpriv->dm.rfpath_rxenable[1] = true;1943 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",1944 rtlhal->version);1945 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);1946 if (tmp_u1b & BIT(4)) {1947 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");1948 rtlefuse->epromtype = EEPROM_93C46;1949 } else {1950 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");1951 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;1952 }1953 if (tmp_u1b & BIT(5)) {1954 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");1955 rtlefuse->autoload_failflag = false;1956 _rtl88ee_read_adapter_info(hw);1957 } else {1958 pr_err("Autoload ERR!!\n");1959 }1960 _rtl88ee_hal_customized_behavior(hw);1961}1962 1963static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,1964 struct ieee80211_sta *sta)1965{1966 struct rtl_priv *rtlpriv = rtl_priv(hw);1967 struct rtl_phy *rtlphy = &(rtlpriv->phy);1968 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1969 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1970 u32 ratr_value;1971 u8 ratr_index = 0;1972 u8 b_nmode = mac->ht_enable;1973 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/1974 u16 shortgi_rate;1975 u32 tmp_ratr_value;1976 u8 curtxbw_40mhz = mac->bw_40;1977 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?1978 1 : 0;1979 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?1980 1 : 0;1981 enum wireless_mode wirelessmode = mac->mode;1982 u32 ratr_mask;1983 1984 if (rtlhal->current_bandtype == BAND_ON_5G)1985 ratr_value = sta->deflink.supp_rates[1] << 4;1986 else1987 ratr_value = sta->deflink.supp_rates[0];1988 if (mac->opmode == NL80211_IFTYPE_ADHOC)1989 ratr_value = 0xfff;1990 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |1991 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);1992 switch (wirelessmode) {1993 case WIRELESS_MODE_B:1994 if (ratr_value & 0x0000000c)1995 ratr_value &= 0x0000000d;1996 else1997 ratr_value &= 0x0000000f;1998 break;1999 case WIRELESS_MODE_G:2000 ratr_value &= 0x00000FF5;2001 break;2002 case WIRELESS_MODE_N_24G:2003 case WIRELESS_MODE_N_5G:2004 b_nmode = 1;2005 if (get_rf_type(rtlphy) == RF_1T2R ||2006 get_rf_type(rtlphy) == RF_1T1R)2007 ratr_mask = 0x000ff005;2008 else2009 ratr_mask = 0x0f0ff005;2010 2011 ratr_value &= ratr_mask;2012 break;2013 default:2014 if (rtlphy->rf_type == RF_1T2R)2015 ratr_value &= 0x000ff0ff;2016 else2017 ratr_value &= 0x0f0ff0ff;2018 2019 break;2020 }2021 2022 if ((rtlpriv->btcoexist.bt_coexistence) &&2023 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&2024 (rtlpriv->btcoexist.bt_cur_state) &&2025 (rtlpriv->btcoexist.bt_ant_isolation) &&2026 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||2027 (rtlpriv->btcoexist.bt_service == BT_BUSY)))2028 ratr_value &= 0x0fffcfc0;2029 else2030 ratr_value &= 0x0FFFFFFF;2031 2032 if (b_nmode &&2033 ((curtxbw_40mhz && curshortgi_40mhz) ||2034 (!curtxbw_40mhz && curshortgi_20mhz))) {2035 ratr_value |= 0x10000000;2036 tmp_ratr_value = (ratr_value >> 12);2037 2038 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {2039 if ((1 << shortgi_rate) & tmp_ratr_value)2040 break;2041 }2042 2043 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |2044 (shortgi_rate << 4) | (shortgi_rate);2045 }2046 2047 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);2048 2049 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,2050 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));2051}2052 2053static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,2054 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)2055{2056 struct rtl_priv *rtlpriv = rtl_priv(hw);2057 struct rtl_phy *rtlphy = &(rtlpriv->phy);2058 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));2059 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));2060 struct rtl_sta_info *sta_entry = NULL;2061 u32 ratr_bitmap;2062 u8 ratr_index;2063 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)2064 ? 1 : 0;2065 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?2066 1 : 0;2067 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?2068 1 : 0;2069 enum wireless_mode wirelessmode = 0;2070 bool b_shortgi = false;2071 u8 rate_mask[5];2072 u8 macid = 0;2073 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/2074 2075 sta_entry = (struct rtl_sta_info *)sta->drv_priv;2076 wirelessmode = sta_entry->wireless_mode;2077 if (mac->opmode == NL80211_IFTYPE_STATION ||2078 mac->opmode == NL80211_IFTYPE_MESH_POINT)2079 curtxbw_40mhz = mac->bw_40;2080 else if (mac->opmode == NL80211_IFTYPE_AP ||2081 mac->opmode == NL80211_IFTYPE_ADHOC)2082 macid = sta->aid + 1;2083 2084 if (rtlhal->current_bandtype == BAND_ON_5G)2085 ratr_bitmap = sta->deflink.supp_rates[1] << 4;2086 else2087 ratr_bitmap = sta->deflink.supp_rates[0];2088 if (mac->opmode == NL80211_IFTYPE_ADHOC)2089 ratr_bitmap = 0xfff;2090 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |2091 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);2092 switch (wirelessmode) {2093 case WIRELESS_MODE_B:2094 ratr_index = RATR_INX_WIRELESS_B;2095 if (ratr_bitmap & 0x0000000c)2096 ratr_bitmap &= 0x0000000d;2097 else2098 ratr_bitmap &= 0x0000000f;2099 break;2100 case WIRELESS_MODE_G:2101 ratr_index = RATR_INX_WIRELESS_GB;2102 2103 if (rssi_level == 1)2104 ratr_bitmap &= 0x00000f00;2105 else if (rssi_level == 2)2106 ratr_bitmap &= 0x00000ff0;2107 else2108 ratr_bitmap &= 0x00000ff5;2109 break;2110 case WIRELESS_MODE_N_24G:2111 case WIRELESS_MODE_N_5G:2112 ratr_index = RATR_INX_WIRELESS_NGB;2113 if (rtlphy->rf_type == RF_1T2R ||2114 rtlphy->rf_type == RF_1T1R) {2115 if (curtxbw_40mhz) {2116 if (rssi_level == 1)2117 ratr_bitmap &= 0x000f0000;2118 else if (rssi_level == 2)2119 ratr_bitmap &= 0x000ff000;2120 else2121 ratr_bitmap &= 0x000ff015;2122 } else {2123 if (rssi_level == 1)2124 ratr_bitmap &= 0x000f0000;2125 else if (rssi_level == 2)2126 ratr_bitmap &= 0x000ff000;2127 else2128 ratr_bitmap &= 0x000ff005;2129 }2130 } else {2131 if (curtxbw_40mhz) {2132 if (rssi_level == 1)2133 ratr_bitmap &= 0x0f8f0000;2134 else if (rssi_level == 2)2135 ratr_bitmap &= 0x0f8ff000;2136 else2137 ratr_bitmap &= 0x0f8ff015;2138 } else {2139 if (rssi_level == 1)2140 ratr_bitmap &= 0x0f8f0000;2141 else if (rssi_level == 2)2142 ratr_bitmap &= 0x0f8ff000;2143 else2144 ratr_bitmap &= 0x0f8ff005;2145 }2146 }2147 /*}*/2148 2149 if ((curtxbw_40mhz && curshortgi_40mhz) ||2150 (!curtxbw_40mhz && curshortgi_20mhz)) {2151 2152 if (macid == 0)2153 b_shortgi = true;2154 else if (macid == 1)2155 b_shortgi = false;2156 }2157 break;2158 default:2159 ratr_index = RATR_INX_WIRELESS_NGB;2160 2161 if (rtlphy->rf_type == RF_1T2R)2162 ratr_bitmap &= 0x000ff0ff;2163 else2164 ratr_bitmap &= 0x0f0ff0ff;2165 break;2166 }2167 sta_entry->ratr_index = ratr_index;2168 2169 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,2170 "ratr_bitmap :%x\n", ratr_bitmap);2171 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |2172 (ratr_index << 28);2173 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;2174 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,2175 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",2176 ratr_index, ratr_bitmap,2177 rate_mask[0], rate_mask[1],2178 rate_mask[2], rate_mask[3],2179 rate_mask[4]);2180 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);2181 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);2182}2183 2184void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,2185 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)2186{2187 struct rtl_priv *rtlpriv = rtl_priv(hw);2188 2189 if (rtlpriv->dm.useramask)2190 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw);2191 else2192 rtl88ee_update_hal_rate_table(hw, sta);2193}2194 2195void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)2196{2197 struct rtl_priv *rtlpriv = rtl_priv(hw);2198 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));2199 u16 sifs_timer;2200 2201 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);2202 if (!mac->ht_enable)2203 sifs_timer = 0x0a0a;2204 else2205 sifs_timer = 0x0e0e;2206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);2207}2208 2209bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)2210{2211 struct rtl_priv *rtlpriv = rtl_priv(hw);2212 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));2213 enum rf_pwrstate e_rfpowerstate_toset;2214 u32 u4tmp;2215 bool b_actuallyset = false;2216 2217 if (rtlpriv->rtlhal.being_init_adapter)2218 return false;2219 2220 if (ppsc->swrf_processing)2221 return false;2222 2223 spin_lock(&rtlpriv->locks.rf_ps_lock);2224 if (ppsc->rfchange_inprogress) {2225 spin_unlock(&rtlpriv->locks.rf_ps_lock);2226 return false;2227 } else {2228 ppsc->rfchange_inprogress = true;2229 spin_unlock(&rtlpriv->locks.rf_ps_lock);2230 }2231 2232 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);2233 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;2234 2235 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {2236 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,2237 "GPIOChangeRF - HW Radio ON, RF ON\n");2238 2239 e_rfpowerstate_toset = ERFON;2240 ppsc->hwradiooff = false;2241 b_actuallyset = true;2242 } else if ((!ppsc->hwradiooff) &&2243 (e_rfpowerstate_toset == ERFOFF)) {2244 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,2245 "GPIOChangeRF - HW Radio OFF, RF OFF\n");2246 2247 e_rfpowerstate_toset = ERFOFF;2248 ppsc->hwradiooff = true;2249 b_actuallyset = true;2250 }2251 2252 if (b_actuallyset) {2253 spin_lock(&rtlpriv->locks.rf_ps_lock);2254 ppsc->rfchange_inprogress = false;2255 spin_unlock(&rtlpriv->locks.rf_ps_lock);2256 } else {2257 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)2258 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);2259 2260 spin_lock(&rtlpriv->locks.rf_ps_lock);2261 ppsc->rfchange_inprogress = false;2262 spin_unlock(&rtlpriv->locks.rf_ps_lock);2263 }2264 2265 *valid = 1;2266 return !ppsc->hwradiooff;2267 2268}2269 2270void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,2271 u8 *p_macaddr, bool is_group, u8 enc_algo,2272 bool is_wepkey, bool clear_all)2273{2274 struct rtl_priv *rtlpriv = rtl_priv(hw);2275 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));2276 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));2277 u8 *macaddr = p_macaddr;2278 u32 entry_id = 0;2279 bool is_pairwise = false;2280 static u8 cam_const_addr[4][6] = {2281 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},2282 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},2283 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},2284 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}2285 };2286 static u8 cam_const_broad[] = {2287 0xff, 0xff, 0xff, 0xff, 0xff, 0xff2288 };2289 2290 if (clear_all) {2291 u8 idx = 0;2292 u8 cam_offset = 0;2293 u8 clear_number = 5;2294 2295 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");2296 2297 for (idx = 0; idx < clear_number; idx++) {2298 rtl_cam_mark_invalid(hw, cam_offset + idx);2299 rtl_cam_empty_entry(hw, cam_offset + idx);2300 2301 if (idx < 5) {2302 memset(rtlpriv->sec.key_buf[idx], 0,2303 MAX_KEY_LEN);2304 rtlpriv->sec.key_len[idx] = 0;2305 }2306 }2307 2308 } else {2309 switch (enc_algo) {2310 case WEP40_ENCRYPTION:2311 enc_algo = CAM_WEP40;2312 break;2313 case WEP104_ENCRYPTION:2314 enc_algo = CAM_WEP104;2315 break;2316 case TKIP_ENCRYPTION:2317 enc_algo = CAM_TKIP;2318 break;2319 case AESCCMP_ENCRYPTION:2320 enc_algo = CAM_AES;2321 break;2322 default:2323 pr_err("switch case %#x not processed\n",2324 enc_algo);2325 enc_algo = CAM_TKIP;2326 break;2327 }2328 2329 if (is_wepkey || rtlpriv->sec.use_defaultkey) {2330 macaddr = cam_const_addr[key_index];2331 entry_id = key_index;2332 } else {2333 if (is_group) {2334 macaddr = cam_const_broad;2335 entry_id = key_index;2336 } else {2337 if (mac->opmode == NL80211_IFTYPE_AP ||2338 mac->opmode == NL80211_IFTYPE_MESH_POINT) {2339 entry_id =2340 rtl_cam_get_free_entry(hw, p_macaddr);2341 if (entry_id >= TOTAL_CAM_ENTRY) {2342 pr_err("Can not find free hw security cam entry\n");2343 return;2344 }2345 } else {2346 entry_id = CAM_PAIRWISE_KEY_POSITION;2347 }2348 key_index = PAIRWISE_KEYIDX;2349 is_pairwise = true;2350 }2351 }2352 2353 if (rtlpriv->sec.key_len[key_index] == 0) {2354 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2355 "delete one entry, entry_id is %d\n",2356 entry_id);2357 if (mac->opmode == NL80211_IFTYPE_AP ||2358 mac->opmode == NL80211_IFTYPE_MESH_POINT)2359 rtl_cam_del_entry(hw, p_macaddr);2360 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);2361 } else {2362 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2363 "add one entry\n");2364 if (is_pairwise) {2365 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2366 "set Pairwise key\n");2367 2368 rtl_cam_add_one_entry(hw, macaddr, key_index,2369 entry_id, enc_algo,2370 CAM_CONFIG_NO_USEDK,2371 rtlpriv->sec.key_buf[key_index]);2372 } else {2373 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2374 "set group key\n");2375 2376 if (mac->opmode == NL80211_IFTYPE_ADHOC) {2377 rtl_cam_add_one_entry(hw,2378 rtlefuse->dev_addr,2379 PAIRWISE_KEYIDX,2380 CAM_PAIRWISE_KEY_POSITION,2381 enc_algo,2382 CAM_CONFIG_NO_USEDK,2383 rtlpriv->sec.key_buf2384 [entry_id]);2385 }2386 2387 rtl_cam_add_one_entry(hw, macaddr, key_index,2388 entry_id, enc_algo,2389 CAM_CONFIG_NO_USEDK,2390 rtlpriv->sec.key_buf[entry_id]);2391 }2392 2393 }2394 }2395}2396 2397static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)2398{2399 struct rtl_priv *rtlpriv = rtl_priv(hw);2400 2401 rtlpriv->btcoexist.bt_coexistence =2402 rtlpriv->btcoexist.eeprom_bt_coexist;2403 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;2404 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;2405 2406 if (rtlpriv->btcoexist.reg_bt_iso == 2)2407 rtlpriv->btcoexist.bt_ant_isolation =2408 rtlpriv->btcoexist.eeprom_bt_ant_isol;2409 else2410 rtlpriv->btcoexist.bt_ant_isolation =2411 rtlpriv->btcoexist.reg_bt_iso;2412 2413 rtlpriv->btcoexist.bt_radio_shared_type =2414 rtlpriv->btcoexist.eeprom_bt_radio_shared;2415 2416 if (rtlpriv->btcoexist.bt_coexistence) {2417 if (rtlpriv->btcoexist.reg_bt_sco == 1)2418 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;2419 else if (rtlpriv->btcoexist.reg_bt_sco == 2)2420 rtlpriv->btcoexist.bt_service = BT_SCO;2421 else if (rtlpriv->btcoexist.reg_bt_sco == 4)2422 rtlpriv->btcoexist.bt_service = BT_BUSY;2423 else if (rtlpriv->btcoexist.reg_bt_sco == 5)2424 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;2425 else2426 rtlpriv->btcoexist.bt_service = BT_IDLE;2427 2428 rtlpriv->btcoexist.bt_edca_ul = 0;2429 rtlpriv->btcoexist.bt_edca_dl = 0;2430 rtlpriv->btcoexist.bt_rssi_state = 0xff;2431 }2432}2433 2434void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,2435 bool auto_load_fail, u8 *hwinfo)2436{2437 struct rtl_priv *rtlpriv = rtl_priv(hw);2438 u8 value;2439 2440 if (!auto_load_fail) {2441 rtlpriv->btcoexist.eeprom_bt_coexist =2442 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);2443 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)2444 rtlpriv->btcoexist.eeprom_bt_coexist = 0;2445 value = hwinfo[EEPROM_RF_BT_SETTING_88E];2446 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);2447 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);2448 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);2449 rtlpriv->btcoexist.eeprom_bt_radio_shared =2450 ((value & 0x20) >> 5);2451 } else {2452 rtlpriv->btcoexist.eeprom_bt_coexist = 0;2453 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;2454 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;2455 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;2456 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;2457 }2458 2459 rtl8188ee_bt_var_init(hw);2460}2461 2462void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)2463{2464 struct rtl_priv *rtlpriv = rtl_priv(hw);2465 2466 /* 0:Low, 1:High, 2:From Efuse. */2467 rtlpriv->btcoexist.reg_bt_iso = 2;2468 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */2469 rtlpriv->btcoexist.reg_bt_sco = 0;2470}2471 2472void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)2473{2474 struct rtl_priv *rtlpriv = rtl_priv(hw);2475 struct rtl_phy *rtlphy = &rtlpriv->phy;2476 u8 u1_tmp;2477 2478 if (rtlpriv->btcoexist.bt_coexistence &&2479 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||2480 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {2481 if (rtlpriv->btcoexist.bt_ant_isolation)2482 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);2483 2484 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0);2485 u1_tmp = u1_tmp |2486 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?2487 0 : BIT((1)) |2488 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?2489 0 : BIT(2)));2490 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);2491 2492 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);2493 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);2494 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);2495 2496 /* Config to 1T1R. */2497 if (rtlphy->rf_type == RF_1T1R) {2498 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);2499 u1_tmp &= ~(BIT(1));2500 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);2501 2502 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);2503 u1_tmp &= ~(BIT(1));2504 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);2505 }2506 }2507}2508 2509void rtl88ee_suspend(struct ieee80211_hw *hw)2510{2511}2512 2513void rtl88ee_resume(struct ieee80211_hw *hw)2514{2515}2516