2250 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2013 Realtek Corporation.*/3 4#ifndef __RTL92C_REG_H__5#define __RTL92C_REG_H__6 7#define TXPKT_BUF_SELECT 0x698#define RXPKT_BUF_SELECT 0xA59#define DISABLE_TRXPKT_BUF_ACCESS 0x010 11#define REG_SYS_ISO_CTRL 0x000012#define REG_SYS_FUNC_EN 0x000213#define REG_APS_FSMCO 0x000414#define REG_SYS_CLKR 0x000815#define REG_9346CR 0x000A16#define REG_EE_VPD 0x000C17#define REG_AFE_MISC 0x001018#define REG_SPS0_CTRL 0x001119#define REG_SPS_OCP_CFG 0x001820#define REG_RSV_CTRL 0x001C21#define REG_RF_CTRL 0x001F22#define REG_LDOA15_CTRL 0x002023#define REG_LDOV12D_CTRL 0x002124#define REG_LDOHCI12_CTRL 0x002225#define REG_LPLDO_CTRL 0x002326#define REG_AFE_XTAL_CTRL 0x002427/* 1.5v for 8188EE test chip, 1.4v for MP chip */28#define REG_AFE_LDO_CTRL 0x002729#define REG_AFE_PLL_CTRL 0x002830#define REG_EFUSE_CTRL 0x003031#define REG_EFUSE_TEST 0x003432#define REG_PWR_DATA 0x003833#define REG_CAL_TIMER 0x003C34#define REG_ACLK_MON 0x003E35#define REG_GPIO_MUXCFG 0x004036#define REG_GPIO_IO_SEL 0x004237#define REG_MAC_PINMUX_CFG 0x004338#define REG_GPIO_PIN_CTRL 0x004439#define REG_GPIO_INTM 0x004840#define REG_LEDCFG0 0x004C41#define REG_LEDCFG1 0x004D42#define REG_LEDCFG2 0x004E43#define REG_LEDCFG3 0x004F44#define REG_FSIMR 0x005045#define REG_FSISR 0x005446#define REG_HSIMR 0x005847#define REG_HSISR 0x005c48#define REG_GPIO_PIN_CTRL_2 0x006049#define REG_GPIO_IO_SEL_2 0x006250#define REG_GPIO_OUTPUT 0x006c51#define REG_AFE_XTAL_CTRL_EXT 0x007852#define REG_XCK_OUT_CTRL 0x007c53#define REG_MCUFWDL 0x008054#define REG_WOL_EVENT 0x008155#define REG_MCUTSTCFG 0x008456 57#define REG_HIMR 0x00B058#define REG_HISR 0x00B459#define REG_HIMRE 0x00B860#define REG_HISRE 0x00BC61 62#define REG_EFUSE_ACCESS 0x00CF63 64#define REG_BIST_SCAN 0x00D065#define REG_BIST_RPT 0x00D466#define REG_BIST_ROM_RPT 0x00D867#define REG_USB_SIE_INTF 0x00E068#define REG_PCIE_MIO_INTF 0x00E469#define REG_PCIE_MIO_INTD 0x00E870#define REG_HPON_FSM 0x00EC71#define REG_SYS_CFG 0x00F072 73#define REG_CR 0x010074#define REG_PBP 0x010475#define REG_PKT_BUFF_ACCESS_CTRL 0x010676#define REG_TRXDMA_CTRL 0x010C77#define REG_TRXFF_BNDY 0x011478#define REG_TRXFF_STATUS 0x011879#define REG_RXFF_PTR 0x011C80 81#define REG_CPWM 0x012F82#define REG_FWIMR 0x013083#define REG_FWISR 0x013484#define REG_PKTBUF_DBG_CTRL 0x014085#define REG_PKTBUF_DBG_DATA_L 0x014486#define REG_PKTBUF_DBG_DATA_H 0x014887#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)88 89#define REG_TC0_CTRL 0x015090#define REG_TC1_CTRL 0x015491#define REG_TC2_CTRL 0x015892#define REG_TC3_CTRL 0x015C93#define REG_TC4_CTRL 0x016094#define REG_TCUNIT_BASE 0x016495#define REG_MBIST_START 0x017496#define REG_MBIST_DONE 0x017897#define REG_MBIST_FAIL 0x017C98#define REG_32K_CTRL 0x019499#define REG_C2HEVT_MSG_NORMAL 0x01A0100#define REG_C2HEVT_CLEAR 0x01AF101#define REG_C2HEVT_MSG_TEST 0x01B8102#define REG_MCUTST_1 0x01c0103#define REG_FMETHR 0x01C8104#define REG_HMETFR 0x01CC105#define REG_HMEBOX_0 0x01D0106#define REG_HMEBOX_1 0x01D4107#define REG_HMEBOX_2 0x01D8108#define REG_HMEBOX_3 0x01DC109 110#define REG_LLT_INIT 0x01E0111#define REG_BB_ACCEESS_CTRL 0x01E8112#define REG_BB_ACCESS_DATA 0x01EC113 114#define REG_HMEBOX_EXT_0 0x01F0115#define REG_HMEBOX_EXT_1 0x01F4116#define REG_HMEBOX_EXT_2 0x01F8117#define REG_HMEBOX_EXT_3 0x01FC118 119#define REG_RQPN 0x0200120#define REG_FIFOPAGE 0x0204121#define REG_TDECTRL 0x0208122#define REG_TXDMA_OFFSET_CHK 0x020C123#define REG_TXDMA_STATUS 0x0210124#define REG_RQPN_NPQ 0x0214125 126#define REG_RXDMA_AGG_PG_TH 0x0280127/* FW shall update this register before128 * FW write RXPKT_RELEASE_POLL to 1129 */130#define REG_FW_UPD_RDPTR 0x0284131/* Control the RX DMA.*/132#define REG_RXDMA_CONTROL 0x0286133/* The number of packets in RXPKTBUF. */134#define REG_RXPKT_NUM 0x0287135 136#define REG_PCIE_CTRL_REG 0x0300137#define REG_INT_MIG 0x0304138#define REG_BCNQ_DESA 0x0308139#define REG_HQ_DESA 0x0310140#define REG_MGQ_DESA 0x0318141#define REG_VOQ_DESA 0x0320142#define REG_VIQ_DESA 0x0328143#define REG_BEQ_DESA 0x0330144#define REG_BKQ_DESA 0x0338145#define REG_RX_DESA 0x0340146 147#define REG_DBI 0x0348148#define REG_MDIO 0x0354149#define REG_DBG_SEL 0x0360150#define REG_PCIE_HRPWM 0x0361151#define REG_PCIE_HCPWM 0x0363152#define REG_UART_CTRL 0x0364153#define REG_WATCH_DOG 0x0368154#define REG_UART_TX_DESA 0x0370155#define REG_UART_RX_DESA 0x0378156 157#define REG_HDAQ_DESA_NODEF 0x0000158#define REG_CMDQ_DESA_NODEF 0x0000159 160#define REG_VOQ_INFORMATION 0x0400161#define REG_VIQ_INFORMATION 0x0404162#define REG_BEQ_INFORMATION 0x0408163#define REG_BKQ_INFORMATION 0x040C164#define REG_MGQ_INFORMATION 0x0410165#define REG_HGQ_INFORMATION 0x0414166#define REG_BCNQ_INFORMATION 0x0418167#define REG_TXPKT_EMPTY 0x041A168 169#define REG_CPU_MGQ_INFORMATION 0x041C170#define REG_FWHW_TXQ_CTRL 0x0420171#define REG_HWSEQ_CTRL 0x0423172#define REG_TXPKTBUF_BCNQ_BDNY 0x0424173#define REG_TXPKTBUF_MGQ_BDNY 0x0425174#define REG_MULTI_BCNQ_EN 0x0426175#define REG_MULTI_BCNQ_OFFSET 0x0427176#define REG_SPEC_SIFS 0x0428177#define REG_RL 0x042A178#define REG_DARFRC 0x0430179#define REG_RARFRC 0x0438180#define REG_RRSR 0x0440181#define REG_ARFR0 0x0444182#define REG_ARFR1 0x0448183#define REG_ARFR2 0x044C184#define REG_ARFR3 0x0450185#define REG_AGGLEN_LMT 0x0458186#define REG_AMPDU_MIN_SPACE 0x045C187#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D188#define REG_FAST_EDCA_CTRL 0x0460189#define REG_RD_RESP_PKT_TH 0x0463190#define REG_INIRTS_RATE_SEL 0x0480191#define REG_INIDATA_RATE_SEL 0x0484192#define REG_POWER_STATUS 0x04A4193#define REG_POWER_STAGE1 0x04B4194#define REG_POWER_STAGE2 0x04B8195#define REG_PKT_LIFE_TIME 0x04C0196#define REG_STBC_SETTING 0x04C4197#define REG_PROT_MODE_CTRL 0x04C8198#define REG_BAR_MODE_CTRL 0x04CC199#define REG_RA_TRY_RATE_AGG_LMT 0x04CF200#define REG_EARLY_MODE_CONTROL 0x04D0201#define REG_NQOS_SEQ 0x04DC202#define REG_QOS_SEQ 0x04DE203#define REG_NEED_CPU_HANDLE 0x04E0204#define REG_PKT_LOSE_RPT 0x04E1205#define REG_PTCL_ERR_STATUS 0x04E2206#define REG_TX_RPT_CTRL 0x04EC207#define REG_TX_RPT_TIME 0x04F0208#define REG_DUMMY 0x04FC209 210#define REG_EDCA_VO_PARAM 0x0500211#define REG_EDCA_VI_PARAM 0x0504212#define REG_EDCA_BE_PARAM 0x0508213#define REG_EDCA_BK_PARAM 0x050C214#define REG_BCNTCFG 0x0510215#define REG_PIFS 0x0512216#define REG_RDG_PIFS 0x0513217#define REG_SIFS_CTX 0x0514218#define REG_SIFS_TRX 0x0516219#define REG_AGGR_BREAK_TIME 0x051A220#define REG_SLOT 0x051B221#define REG_TX_PTCL_CTRL 0x0520222#define REG_TXPAUSE 0x0522223#define REG_DIS_TXREQ_CLR 0x0523224#define REG_RD_CTRL 0x0524225#define REG_TBTT_PROHIBIT 0x0540226#define REG_RD_NAV_NXT 0x0544227#define REG_NAV_PROT_LEN 0x0546228#define REG_BCN_CTRL 0x0550229#define REG_MBID_NUM 0x0552230#define REG_DUAL_TSF_RST 0x0553231#define REG_BCN_INTERVAL 0x0554232#define REG_MBSSID_BCN_SPACE 0x0554233#define REG_DRVERLYINT 0x0558234#define REG_BCNDMATIM 0x0559235#define REG_ATIMWND 0x055A236#define REG_USTIME_TSF 0x055C237#define REG_BCN_MAX_ERR 0x055D238#define REG_RXTSF_OFFSET_CCK 0x055E239#define REG_RXTSF_OFFSET_OFDM 0x055F240#define REG_TSFTR 0x0560241#define REG_INIT_TSFTR 0x0564242#define REG_PSTIMER 0x0580243#define REG_TIMER0 0x0584244#define REG_TIMER1 0x0588245#define REG_ACMHWCTRL 0x05C0246#define REG_ACMRSTCTRL 0x05C1247#define REG_ACMAVG 0x05C2248#define REG_VO_ADMTIME 0x05C4249#define REG_VI_ADMTIME 0x05C6250#define REG_BE_ADMTIME 0x05C8251#define REG_EDCA_RANDOM_GEN 0x05CC252#define REG_SCH_TXCMD 0x05D0253 254#define REG_APSD_CTRL 0x0600255#define REG_BWOPMODE 0x0603256#define REG_TCR 0x0604257#define REG_RCR 0x0608258#define REG_RX_PKT_LIMIT 0x060C259#define REG_RX_DLK_TIME 0x060D260#define REG_RX_DRVINFO_SZ 0x060F261 262#define REG_MACID 0x0610263#define REG_BSSID 0x0618264#define REG_MAR 0x0620265#define REG_MBIDCAMCFG 0x0628266 267#define REG_USTIME_EDCA 0x0638268#define REG_MAC_SPEC_SIFS 0x063A269#define REG_RESP_SIFS_CCK 0x063C270#define REG_RESP_SIFS_OFDM 0x063E271#define REG_ACKTO 0x0640272#define REG_CTS2TO 0x0641273#define REG_EIFS 0x0642274 275#define REG_NAV_CTRL 0x0650276#define REG_BACAMCMD 0x0654277#define REG_BACAMCONTENT 0x0658278#define REG_LBDLY 0x0660279#define REG_FWDLY 0x0661280#define REG_RXERR_RPT 0x0664281#define REG_TRXPTCL_CTL 0x0668282 283#define REG_CAMCMD 0x0670284#define REG_CAMWRITE 0x0674285#define REG_CAMREAD 0x0678286#define REG_CAMDBG 0x067C287#define REG_SECCFG 0x0680288 289#define REG_WOW_CTRL 0x0690290#define REG_PSSTATUS 0x0691291#define REG_PS_RX_INFO 0x0692292#define REG_UAPSD_TID 0x0693293#define REG_LPNAV_CTRL 0x0694294#define REG_WKFMCAM_NUM 0x0698295#define REG_WKFMCAM_RWD 0x069C296#define REG_RXFLTMAP0 0x06A0297#define REG_RXFLTMAP1 0x06A2298#define REG_RXFLTMAP2 0x06A4299#define REG_BCN_PSR_RPT 0x06A8300#define REG_CALB32K_CTRL 0x06AC301#define REG_PKT_MON_CTRL 0x06B4302#define REG_BT_COEX_TABLE 0x06C0303#define REG_WMAC_RESP_TXINFO 0x06D8304 305#define REG_USB_INFO 0xFE17306#define REG_USB_SPECIAL_OPTION 0xFE55307#define REG_USB_DMA_AGG_TO 0xFE5B308#define REG_USB_AGG_TO 0xFE5C309#define REG_USB_AGG_TH 0xFE5D310 311#define REG_TEST_USB_TXQS 0xFE48312#define REG_TEST_SIE_VID 0xFE60313#define REG_TEST_SIE_PID 0xFE62314#define REG_TEST_SIE_OPTIONAL 0xFE64315#define REG_TEST_SIE_CHIRP_K 0xFE65316#define REG_TEST_SIE_PHY 0xFE66317#define REG_TEST_SIE_MAC_ADDR 0xFE70318#define REG_TEST_SIE_STRING 0xFE80319 320#define REG_NORMAL_SIE_VID 0xFE60321#define REG_NORMAL_SIE_PID 0xFE62322#define REG_NORMAL_SIE_OPTIONAL 0xFE64323#define REG_NORMAL_SIE_EP 0xFE65324#define REG_NORMAL_SIE_PHY 0xFE68325#define REG_NORMAL_SIE_MAC_ADDR 0xFE70326#define REG_NORMAL_SIE_STRING 0xFE80327 328#define CR9346 REG_9346CR329#define MSR (REG_CR + 2)330#define ISR REG_HISR331#define TSFR REG_TSFTR332 333#define MACIDR0 REG_MACID334#define MACIDR4 (REG_MACID + 4)335 336#define PBP REG_PBP337 338#define IDR0 MACIDR0339#define IDR4 MACIDR4340 341#define UNUSED_REGISTER 0x1BF342#define DCAM UNUSED_REGISTER343#define PSR UNUSED_REGISTER344#define BBADDR UNUSED_REGISTER345#define PHYDATAR UNUSED_REGISTER346 347#define INVALID_BBRF_VALUE 0x12345678348 349#define MAX_MSS_DENSITY_2T 0x13350#define MAX_MSS_DENSITY_1T 0x0A351 352#define CMDEEPROM_EN BIT(5)353#define CMDEEPROM_SEL BIT(4)354#define CMD9346CR_9356SEL BIT(4)355#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)356#define AUTOLOAD_EFUSE CMDEEPROM_EN357 358#define GPIOSEL_GPIO 0359#define GPIOSEL_ENBT BIT(5)360 361#define GPIO_IN REG_GPIO_PIN_CTRL362#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)363#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)364#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)365 366/*8723/8188E Host System Interrupt367 *Mask Register (offset 0x58, 32 byte)368 */369#define HSIMR_GPIO12_0_INT_EN BIT(0)370#define HSIMR_SPS_OCP_INT_EN BIT(5)371#define HSIMR_RON_INT_EN BIT(6)372#define HSIMR_PDN_INT_EN BIT(7)373#define HSIMR_GPIO9_INT_EN BIT(25)374 375/* 8723/8188E Host System Interrupt376 * Status Register (offset 0x5C, 32 byte)377 */378#define HSISR_GPIO12_0_INT BIT(0)379#define HSISR_SPS_OCP_INT BIT(5)380#define HSISR_RON_INT_EN BIT(6)381#define HSISR_PDNINT BIT(7)382#define HSISR_GPIO9_INT BIT(25)383 384#define MSR_NOLINK 0x00385#define MSR_ADHOC 0x01386#define MSR_INFRA 0x02387#define MSR_AP 0x03388 389#define RRSR_RSC_OFFSET 21390#define RRSR_SHORT_OFFSET 23391#define RRSR_RSC_BW_40M 0x600000392#define RRSR_RSC_UPSUBCHNL 0x400000393#define RRSR_RSC_LOWSUBCHNL 0x200000394#define RRSR_SHORT 0x800000395#define RRSR_1M BIT(0)396#define RRSR_2M BIT(1)397#define RRSR_5_5M BIT(2)398#define RRSR_11M BIT(3)399#define RRSR_6M BIT(4)400#define RRSR_9M BIT(5)401#define RRSR_12M BIT(6)402#define RRSR_18M BIT(7)403#define RRSR_24M BIT(8)404#define RRSR_36M BIT(9)405#define RRSR_48M BIT(10)406#define RRSR_54M BIT(11)407#define RRSR_MCS0 BIT(12)408#define RRSR_MCS1 BIT(13)409#define RRSR_MCS2 BIT(14)410#define RRSR_MCS3 BIT(15)411#define RRSR_MCS4 BIT(16)412#define RRSR_MCS5 BIT(17)413#define RRSR_MCS6 BIT(18)414#define RRSR_MCS7 BIT(19)415#define BRSR_ACKSHORTPMB BIT(23)416 417#define RATR_1M 0x00000001418#define RATR_2M 0x00000002419#define RATR_55M 0x00000004420#define RATR_11M 0x00000008421#define RATR_6M 0x00000010422#define RATR_9M 0x00000020423#define RATR_12M 0x00000040424#define RATR_18M 0x00000080425#define RATR_24M 0x00000100426#define RATR_36M 0x00000200427#define RATR_48M 0x00000400428#define RATR_54M 0x00000800429#define RATR_MCS0 0x00001000430#define RATR_MCS1 0x00002000431#define RATR_MCS2 0x00004000432#define RATR_MCS3 0x00008000433#define RATR_MCS4 0x00010000434#define RATR_MCS5 0x00020000435#define RATR_MCS6 0x00040000436#define RATR_MCS7 0x00080000437#define RATR_MCS8 0x00100000438#define RATR_MCS9 0x00200000439#define RATR_MCS10 0x00400000440#define RATR_MCS11 0x00800000441#define RATR_MCS12 0x01000000442#define RATR_MCS13 0x02000000443#define RATR_MCS14 0x04000000444#define RATR_MCS15 0x08000000445 446#define RATE_1M BIT(0)447#define RATE_2M BIT(1)448#define RATE_5_5M BIT(2)449#define RATE_11M BIT(3)450#define RATE_6M BIT(4)451#define RATE_9M BIT(5)452#define RATE_12M BIT(6)453#define RATE_18M BIT(7)454#define RATE_24M BIT(8)455#define RATE_36M BIT(9)456#define RATE_48M BIT(10)457#define RATE_54M BIT(11)458#define RATE_MCS0 BIT(12)459#define RATE_MCS1 BIT(13)460#define RATE_MCS2 BIT(14)461#define RATE_MCS3 BIT(15)462#define RATE_MCS4 BIT(16)463#define RATE_MCS5 BIT(17)464#define RATE_MCS6 BIT(18)465#define RATE_MCS7 BIT(19)466#define RATE_MCS8 BIT(20)467#define RATE_MCS9 BIT(21)468#define RATE_MCS10 BIT(22)469#define RATE_MCS11 BIT(23)470#define RATE_MCS12 BIT(24)471#define RATE_MCS13 BIT(25)472#define RATE_MCS14 BIT(26)473#define RATE_MCS15 BIT(27)474 475#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)476#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\477 RATR_24M | RATR_36M | RATR_48M | RATR_54M)478#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\479 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\480 RATR_MCS6 | RATR_MCS7)481#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\482 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\483 RATR_MCS14 | RATR_MCS15)484 485#define BW_OPMODE_20MHZ BIT(2)486#define BW_OPMODE_5G BIT(1)487#define BW_OPMODE_11J BIT(0)488 489#define CAM_VALID BIT(15)490#define CAM_NOTVALID 0x0000491#define CAM_USEDK BIT(5)492 493#define CAM_NONE 0x0494#define CAM_WEP40 0x01495#define CAM_TKIP 0x02496#define CAM_AES 0x04497#define CAM_WEP104 0x05498 499#define TOTAL_CAM_ENTRY 32500#define HALF_CAM_ENTRY 16501 502#define CAM_WRITE BIT(16)503#define CAM_READ 0x00000000504#define CAM_POLLINIG BIT(31)505 506#define SCR_USEDK 0x01507#define SCR_TXSEC_ENABLE 0x02508#define SCR_RXSEC_ENABLE 0x04509 510#define WOW_PMEN BIT(0)511#define WOW_WOMEN BIT(1)512#define WOW_MAGIC BIT(2)513#define WOW_UWF BIT(3)514 515/*********************************************516* 8188 IMR/ISR bits517**********************************************/518#define IMR_DISABLED 0x0519/* IMR DW0(0x0060-0063) Bit 0-31 */520/* TXRPT interrupt when CCX bit of the packet is set */521#define IMR_TXCCK BIT(30)522/* Power Save Time Out Interrupt */523#define IMR_PSTIMEOUT BIT(29)524/* When GTIMER4 expires, this bit is set to 1 */525#define IMR_GTINT4 BIT(28)526/* When GTIMER3 expires, this bit is set to 1 */527#define IMR_GTINT3 BIT(27)528/* Transmit Beacon0 Error */529#define IMR_TBDER BIT(26)530/* Transmit Beacon0 OK */531#define IMR_TBDOK BIT(25)532/* TSF Timer BIT32 toggle indication interrupt */533#define IMR_TSF_BIT32_TOGGLE BIT(24)534/* Beacon DMA Interrupt 0 */535#define IMR_BCNDMAINT0 BIT(20)536/* Beacon Queue DMA OK0 */537#define IMR_BCNDOK0 BIT(16)538/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */539#define IMR_HSISR_IND_ON_INT BIT(15)540/* Beacon DMA Interrupt Extension for Win7 */541#define IMR_BCNDMAINT_E BIT(14)542/* CTWidnow End or ATIM Window End */543#define IMR_ATIMEND BIT(12)544/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/545#define IMR_HISR1_IND_INT BIT(11)546/* CPU to Host Command INT Status, Write 1 clear */547#define IMR_C2HCMD BIT(10)548/* CPU power Mode exchange INT Status, Write 1 clear */549#define IMR_CPWM2 BIT(9)550/* CPU power Mode exchange INT Status, Write 1 clear */551#define IMR_CPWM BIT(8)552/* High Queue DMA OK */553#define IMR_HIGHDOK BIT(7)554/* Management Queue DMA OK */555#define IMR_MGNTDOK BIT(6)556/* AC_BK DMA OK */557#define IMR_BKDOK BIT(5)558/* AC_BE DMA OK */559#define IMR_BEDOK BIT(4)560/* AC_VI DMA OK */561#define IMR_VIDOK BIT(3)562/* AC_VO DMA OK */563#define IMR_VODOK BIT(2)564/* Rx Descriptor Unavailable */565#define IMR_RDU BIT(1)566/* Receive DMA OK */567#define IMR_ROK BIT(0)568 569/* IMR DW1(0x00B4-00B7) Bit 0-31 */570/* Beacon DMA Interrupt 7 */571#define IMR_BCNDMAINT7 BIT(27)572/* Beacon DMA Interrupt 6 */573#define IMR_BCNDMAINT6 BIT(26)574/* Beacon DMA Interrupt 5 */575#define IMR_BCNDMAINT5 BIT(25)576/* Beacon DMA Interrupt 4 */577#define IMR_BCNDMAINT4 BIT(24)578/* Beacon DMA Interrupt 3 */579#define IMR_BCNDMAINT3 BIT(23)580/* Beacon DMA Interrupt 2 */581#define IMR_BCNDMAINT2 BIT(22)582/* Beacon DMA Interrupt 1 */583#define IMR_BCNDMAINT1 BIT(21)584/* Beacon Queue DMA OK Interrup 7 */585#define IMR_BCNDOK7 BIT(20)586/* Beacon Queue DMA OK Interrup 6 */587#define IMR_BCNDOK6 BIT(19)588/* Beacon Queue DMA OK Interrup 5 */589#define IMR_BCNDOK5 BIT(18)590/* Beacon Queue DMA OK Interrup 4 */591#define IMR_BCNDOK4 BIT(17)592/* Beacon Queue DMA OK Interrup 3 */593#define IMR_BCNDOK3 BIT(16)594/* Beacon Queue DMA OK Interrup 2 */595#define IMR_BCNDOK2 BIT(15)596/* Beacon Queue DMA OK Interrup 1 */597#define IMR_BCNDOK1 BIT(14)598/* ATIM Window End Extension for Win7 */599#define IMR_ATIMEND_E BIT(13)600/* Tx Error Flag Interrupt Status, write 1 clear. */601#define IMR_TXERR BIT(11)602/* Rx Error Flag INT Status, Write 1 clear */603#define IMR_RXERR BIT(10)604/* Transmit FIFO Overflow */605#define IMR_TXFOVW BIT(9)606/* Receive FIFO Overflow */607#define IMR_RXFOVW BIT(8)608 609#define HWSET_MAX_SIZE 512610#define EFUSE_MAX_SECTION 64611#define EFUSE_REAL_CONTENT_LEN 256612/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/613#define EFUSE_OOB_PROTECT_BYTES 18614 615#define EEPROM_DEFAULT_TSSI 0x0616#define EEPROM_DEFAULT_TXPOWERDIFF 0x0617#define EEPROM_DEFAULT_CRYSTALCAP 0x5618#define EEPROM_DEFAULT_BOARDTYPE 0x02619#define EEPROM_DEFAULT_TXPOWER 0x1010620#define EEPROM_DEFAULT_HT2T_TXPWR 0x10621 622#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3623#define EEPROM_DEFAULT_THERMALMETER 0x18624#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0625#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5626#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22627#define EEPROM_DEFAULT_HT40_2SDIFF 0x0628#define EEPROM_DEFAULT_HT20_DIFF 2629#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3630#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0631#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0632 633#define RF_OPTION1 0x79634#define RF_OPTION2 0x7A635#define RF_OPTION3 0x7B636#define RF_OPTION4 0x7C637 638#define EEPROM_DEFAULT_PID 0x1234639#define EEPROM_DEFAULT_VID 0x5678640#define EEPROM_DEFAULT_CUSTOMERID 0xAB641#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD642#define EEPROM_DEFAULT_VERSION 0643 644#define EEPROM_CHANNEL_PLAN_FCC 0x0645#define EEPROM_CHANNEL_PLAN_IC 0x1646#define EEPROM_CHANNEL_PLAN_ETSI 0x2647#define EEPROM_CHANNEL_PLAN_SPAIN 0x3648#define EEPROM_CHANNEL_PLAN_FRANCE 0x4649#define EEPROM_CHANNEL_PLAN_MKK 0x5650#define EEPROM_CHANNEL_PLAN_MKK1 0x6651#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7652#define EEPROM_CHANNEL_PLAN_TELEC 0x8653#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9654#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA655#define EEPROM_CHANNEL_PLAN_NCC 0xB656#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80657 658#define EEPROM_CID_DEFAULT 0x0659#define EEPROM_CID_TOSHIBA 0x4660#define EEPROM_CID_CCX 0x10661#define EEPROM_CID_QMI 0x0D662#define EEPROM_CID_WHQL 0xFE663 664#define RTL8188E_EEPROM_ID 0x8129665 666#define EEPROM_HPON 0x02667#define EEPROM_CLK 0x06668#define EEPROM_TESTR 0x08669 670#define EEPROM_TXPOWERCCK 0x10671#define EEPROM_TXPOWERHT40_1S 0x16672#define EEPROM_TXPOWERHT20DIFF 0x1B673#define EEPROM_TXPOWER_OFDMDIFF 0x1B674 675#define EEPROM_TX_PWR_INX 0x10676 677#define EEPROM_CHANNELPLAN 0xB8678#define EEPROM_XTAL_88E 0xB9679#define EEPROM_THERMAL_METER_88E 0xBA680#define EEPROM_IQK_LCK_88E 0xBB681 682#define EEPROM_RF_BOARD_OPTION_88E 0xC1683#define EEPROM_RF_FEATURE_OPTION_88E 0xC2684#define EEPROM_RF_BT_SETTING_88E 0xC3685#define EEPROM_VERSION 0xC4686#define EEPROM_CUSTOMER_ID 0xC5687#define EEPROM_RF_ANTENNA_OPT_88E 0xC9688 689#define EEPROM_MAC_ADDR 0xD0690#define EEPROM_VID 0xD6691#define EEPROM_DID 0xD8692#define EEPROM_SVID 0xDA693#define EEPROM_SMID 0xDC694 695#define STOPBECON BIT(6)696#define STOPHIGHT BIT(5)697#define STOPMGT BIT(4)698#define STOPVO BIT(3)699#define STOPVI BIT(2)700#define STOPBE BIT(1)701#define STOPBK BIT(0)702 703#define RCR_APPFCS BIT(31)704#define RCR_APP_MIC BIT(30)705#define RCR_APP_ICV BIT(29)706#define RCR_APP_PHYST_RXFF BIT(28)707#define RCR_APP_BA_SSN BIT(27)708#define RCR_ENMBID BIT(24)709#define RCR_LSIGEN BIT(23)710#define RCR_MFBEN BIT(22)711#define RCR_HTC_LOC_CTRL BIT(14)712#define RCR_AMF BIT(13)713#define RCR_ACF BIT(12)714#define RCR_ADF BIT(11)715#define RCR_AICV BIT(9)716#define RCR_ACRC32 BIT(8)717#define RCR_CBSSID_BCN BIT(7)718#define RCR_CBSSID_DATA BIT(6)719#define RCR_CBSSID RCR_CBSSID_DATA720#define RCR_APWRMGT BIT(5)721#define RCR_ADD3 BIT(4)722#define RCR_AB BIT(3)723#define RCR_AM BIT(2)724#define RCR_APM BIT(1)725#define RCR_AAP BIT(0)726#define RCR_MXDMA_OFFSET 8727#define RCR_FIFO_OFFSET 13728 729#define RSV_CTRL 0x001C730#define RD_CTRL 0x0524731 732#define REG_USB_INFO 0xFE17733#define REG_USB_SPECIAL_OPTION 0xFE55734#define REG_USB_DMA_AGG_TO 0xFE5B735#define REG_USB_AGG_TO 0xFE5C736#define REG_USB_AGG_TH 0xFE5D737 738#define REG_USB_VID 0xFE60739#define REG_USB_PID 0xFE62740#define REG_USB_OPTIONAL 0xFE64741#define REG_USB_CHIRP_K 0xFE65742#define REG_USB_PHY 0xFE66743#define REG_USB_MAC_ADDR 0xFE70744#define REG_USB_HRPWM 0xFE58745#define REG_USB_HCPWM 0xFE57746 747#define SW18_FPWM BIT(3)748 749#define ISO_MD2PP BIT(0)750#define ISO_UA2USB BIT(1)751#define ISO_UD2CORE BIT(2)752#define ISO_PA2PCIE BIT(3)753#define ISO_PD2CORE BIT(4)754#define ISO_IP2MAC BIT(5)755#define ISO_DIOP BIT(6)756#define ISO_DIOE BIT(7)757#define ISO_EB2CORE BIT(8)758#define ISO_DIOR BIT(9)759 760#define PWC_EV25V BIT(14)761#define PWC_EV12V BIT(15)762 763#define FEN_BBRSTB BIT(0)764#define FEN_BB_GLB_RSTN BIT(1)765#define FEN_USBA BIT(2)766#define FEN_UPLL BIT(3)767#define FEN_USBD BIT(4)768#define FEN_DIO_PCIE BIT(5)769#define FEN_PCIEA BIT(6)770#define FEN_PPLL BIT(7)771#define FEN_PCIED BIT(8)772#define FEN_DIOE BIT(9)773#define FEN_CPUEN BIT(10)774#define FEN_DCORE BIT(11)775#define FEN_ELDR BIT(12)776#define FEN_DIO_RF BIT(13)777#define FEN_HWPDN BIT(14)778#define FEN_MREGEN BIT(15)779 780#define PFM_LDALL BIT(0)781#define PFM_ALDN BIT(1)782#define PFM_LDKP BIT(2)783#define PFM_WOWL BIT(3)784#define ENPDN BIT(4)785#define PDN_PL BIT(5)786#define APFM_ONMAC BIT(8)787#define APFM_OFF BIT(9)788#define APFM_RSM BIT(10)789#define AFSM_HSUS BIT(11)790#define AFSM_PCIE BIT(12)791#define APDM_MAC BIT(13)792#define APDM_HOST BIT(14)793#define APDM_HPDN BIT(15)794#define RDY_MACON BIT(16)795#define SUS_HOST BIT(17)796#define ROP_ALD BIT(20)797#define ROP_PWR BIT(21)798#define ROP_SPS BIT(22)799#define SOP_MRST BIT(25)800#define SOP_FUSE BIT(26)801#define SOP_ABG BIT(27)802#define SOP_AMB BIT(28)803#define SOP_RCK BIT(29)804#define SOP_A8M BIT(30)805#define XOP_BTCK BIT(31)806 807#define ANAD16V_EN BIT(0)808#define ANA8M BIT(1)809#define MACSLP BIT(4)810#define LOADER_CLK_EN BIT(5)811#define _80M_SSC_DIS BIT(7)812#define _80M_SSC_EN_HO BIT(8)813#define PHY_SSC_RSTB BIT(9)814#define SEC_CLK_EN BIT(10)815#define MAC_CLK_EN BIT(11)816#define SYS_CLK_EN BIT(12)817#define RING_CLK_EN BIT(13)818 819#define BOOT_FROM_EEPROM BIT(4)820#define EEPROM_EN BIT(5)821 822#define AFE_BGEN BIT(0)823#define AFE_MBEN BIT(1)824#define MAC_ID_EN BIT(7)825 826#define WLOCK_ALL BIT(0)827#define WLOCK_00 BIT(1)828#define WLOCK_04 BIT(2)829#define WLOCK_08 BIT(3)830#define WLOCK_40 BIT(4)831#define R_DIS_PRST_0 BIT(5)832#define R_DIS_PRST_1 BIT(6)833#define LOCK_ALL_EN BIT(7)834 835#define RF_EN BIT(0)836#define RF_RSTB BIT(1)837#define RF_SDMRSTB BIT(2)838 839#define LDA15_EN BIT(0)840#define LDA15_STBY BIT(1)841#define LDA15_OBUF BIT(2)842#define LDA15_REG_VOS BIT(3)843#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)844 845#define LDV12_EN BIT(0)846#define LDV12_SDBY BIT(1)847#define LPLDO_HSM BIT(2)848#define LPLDO_LSM_DIS BIT(3)849#define _LDV12_VADJ(x) (((x) & 0xF) << 4)850 851#define XTAL_EN BIT(0)852#define XTAL_BSEL BIT(1)853#define _XTAL_BOSC(x) (((x) & 0x3) << 2)854#define _XTAL_CADJ(x) (((x) & 0xF) << 4)855#define XTAL_GATE_USB BIT(8)856#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)857#define XTAL_GATE_AFE BIT(11)858#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)859#define XTAL_RF_GATE BIT(14)860#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)861#define XTAL_GATE_DIG BIT(17)862#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)863#define XTAL_BT_GATE BIT(20)864#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)865#define _XTAL_GPIO(x) (((x) & 0x7) << 23)866 867#define CKDLY_AFE BIT(26)868#define CKDLY_USB BIT(27)869#define CKDLY_DIG BIT(28)870#define CKDLY_BT BIT(29)871 872#define APLL_EN BIT(0)873#define APLL_320_EN BIT(1)874#define APLL_FREF_SEL BIT(2)875#define APLL_EDGE_SEL BIT(3)876#define APLL_WDOGB BIT(4)877#define APLL_LPFEN BIT(5)878 879#define APLL_REF_CLK_13MHZ 0x1880#define APLL_REF_CLK_19_2MHZ 0x2881#define APLL_REF_CLK_20MHZ 0x3882#define APLL_REF_CLK_25MHZ 0x4883#define APLL_REF_CLK_26MHZ 0x5884#define APLL_REF_CLK_38_4MHZ 0x6885#define APLL_REF_CLK_40MHZ 0x7886 887#define APLL_320EN BIT(14)888#define APLL_80EN BIT(15)889#define APLL_1MEN BIT(24)890 891#define ALD_EN BIT(18)892#define EF_PD BIT(19)893#define EF_FLAG BIT(31)894 895#define EF_TRPT BIT(7)896#define LDOE25_EN BIT(31)897 898#define RSM_EN BIT(0)899#define TIMER_EN BIT(4)900 901#define TRSW0EN BIT(2)902#define TRSW1EN BIT(3)903#define EROM_EN BIT(4)904#define ENBT BIT(5)905#define ENUART BIT(8)906#define UART_910 BIT(9)907#define ENPMAC BIT(10)908#define SIC_SWRST BIT(11)909#define ENSIC BIT(12)910#define SIC_23 BIT(13)911#define ENHDP BIT(14)912#define SIC_LBK BIT(15)913 914#define LED0PL BIT(4)915#define LED1PL BIT(12)916#define LED0DIS BIT(7)917 918#define MCUFWDL_EN BIT(0)919#define MCUFWDL_RDY BIT(1)920#define FWDL_CHKSUM_RPT BIT(2)921#define MACINI_RDY BIT(3)922#define BBINI_RDY BIT(4)923#define RFINI_RDY BIT(5)924#define WINTINI_RDY BIT(6)925#define CPRST BIT(23)926 927#define XCLK_VLD BIT(0)928#define ACLK_VLD BIT(1)929#define UCLK_VLD BIT(2)930#define PCLK_VLD BIT(3)931#define PCIRSTB BIT(4)932#define V15_VLD BIT(5)933#define TRP_B15V_EN BIT(7)934#define SIC_IDLE BIT(8)935#define BD_MAC2 BIT(9)936#define BD_MAC1 BIT(10)937#define IC_MACPHY_MODE BIT(11)938#define VENDOR_ID BIT(19)939#define PAD_HWPD_IDN BIT(22)940#define TRP_VAUX_EN BIT(23)941#define TRP_BT_EN BIT(24)942#define BD_PKG_SEL BIT(25)943#define BD_HCI_SEL BIT(26)944#define TYPE_ID BIT(27)945 946#define CHIP_VER_RTL_MASK 0xF000947#define CHIP_VER_RTL_SHIFT 12948 949#define REG_LBMODE (REG_CR + 3)950 951#define HCI_TXDMA_EN BIT(0)952#define HCI_RXDMA_EN BIT(1)953#define TXDMA_EN BIT(2)954#define RXDMA_EN BIT(3)955#define PROTOCOL_EN BIT(4)956#define SCHEDULE_EN BIT(5)957#define MACTXEN BIT(6)958#define MACRXEN BIT(7)959#define ENSWBCN BIT(8)960#define ENSEC BIT(9)961 962#define _NETTYPE(x) (((x) & 0x3) << 16)963#define MASK_NETTYPE 0x30000964#define NT_NO_LINK 0x0965#define NT_LINK_AD_HOC 0x1966#define NT_LINK_AP 0x2967#define NT_AS_AP 0x3968 969#define _LBMODE(x) (((x) & 0xF) << 24)970#define MASK_LBMODE 0xF000000971#define LOOPBACK_NORMAL 0x0972#define LOOPBACK_IMMEDIATELY 0xB973#define LOOPBACK_MAC_DELAY 0x3974#define LOOPBACK_PHY 0x1975#define LOOPBACK_DMA 0x7976 977#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)978#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)979#define _PSRX_MASK 0xF980#define _PSTX_MASK 0xF0981#define _PSRX(x) (x)982#define _PSTX(x) ((x) << 4)983 984#define PBP_64 0x0985#define PBP_128 0x1986#define PBP_256 0x2987#define PBP_512 0x3988#define PBP_1024 0x4989 990#define RXDMA_ARBBW_EN BIT(0)991#define RXSHFT_EN BIT(1)992#define RXDMA_AGG_EN BIT(2)993#define QS_VO_QUEUE BIT(8)994#define QS_VI_QUEUE BIT(9)995#define QS_BE_QUEUE BIT(10)996#define QS_BK_QUEUE BIT(11)997#define QS_MANAGER_QUEUE BIT(12)998#define QS_HIGH_QUEUE BIT(13)999 1000#define HQSEL_VOQ BIT(0)1001#define HQSEL_VIQ BIT(1)1002#define HQSEL_BEQ BIT(2)1003#define HQSEL_BKQ BIT(3)1004#define HQSEL_MGTQ BIT(4)1005#define HQSEL_HIQ BIT(5)1006 1007#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)1008#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)1009#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)1010#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)1011#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)1012#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)1013 1014#define QUEUE_LOW 11015#define QUEUE_NORMAL 21016#define QUEUE_HIGH 31017 1018#define _LLT_NO_ACTIVE 0x01019#define _LLT_WRITE_ACCESS 0x11020#define _LLT_READ_ACCESS 0x21021 1022#define _LLT_INIT_DATA(x) ((x) & 0xFF)1023#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)1024#define _LLT_OP(x) (((x) & 0x3) << 30)1025#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)1026 1027#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))1028#define BB_WRITE_EN BIT(30)1029#define BB_READ_EN BIT(31)1030 1031#define _HPQ(x) ((x) & 0xFF)1032#define _LPQ(x) (((x) & 0xFF) << 8)1033#define _PUBQ(x) (((x) & 0xFF) << 16)1034#define _NPQ(x) ((x) & 0xFF)1035 1036#define HPQ_PUBLIC_DIS BIT(24)1037#define LPQ_PUBLIC_DIS BIT(25)1038#define LD_RQPN BIT(31)1039 1040#define BCN_VALID BIT(16)1041#define BCN_HEAD(x) (((x) & 0xFF) << 8)1042#define BCN_HEAD_MASK 0xFF001043 1044#define BLK_DESC_NUM_SHIFT 41045#define BLK_DESC_NUM_MASK 0xF1046 1047#define DROP_DATA_EN BIT(9)1048 1049#define EN_AMPDU_RTY_NEW BIT(7)1050 1051#define _INIRTSMCS_SEL(x) ((x) & 0x3F)1052 1053#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)1054#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)1055 1056#define RATE_REG_BITMAP_ALL 0xFFFFF1057 1058#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)1059 1060#define _RRSR_RSC(x) (((x) & 0x3) << 21)1061#define RRSR_RSC_RESERVED 0x01062#define RRSR_RSC_UPPER_SUBCHANNEL 0x11063#define RRSR_RSC_LOWER_SUBCHANNEL 0x21064#define RRSR_RSC_DUPLICATE_MODE 0x31065 1066#define USE_SHORT_G1 BIT(20)1067 1068#define _AGGLMT_MCS0(x) ((x) & 0xF)1069#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)1070#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)1071#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)1072#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)1073#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)1074#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)1075#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)1076 1077#define RETRY_LIMIT_SHORT_SHIFT 81078#define RETRY_LIMIT_LONG_SHIFT 01079 1080#define _DARF_RC1(x) ((x) & 0x1F)1081#define _DARF_RC2(x) (((x) & 0x1F) << 8)1082#define _DARF_RC3(x) (((x) & 0x1F) << 16)1083#define _DARF_RC4(x) (((x) & 0x1F) << 24)1084#define _DARF_RC5(x) ((x) & 0x1F)1085#define _DARF_RC6(x) (((x) & 0x1F) << 8)1086#define _DARF_RC7(x) (((x) & 0x1F) << 16)1087#define _DARF_RC8(x) (((x) & 0x1F) << 24)1088 1089#define _RARF_RC1(x) ((x) & 0x1F)1090#define _RARF_RC2(x) (((x) & 0x1F) << 8)1091#define _RARF_RC3(x) (((x) & 0x1F) << 16)1092#define _RARF_RC4(x) (((x) & 0x1F) << 24)1093#define _RARF_RC5(x) ((x) & 0x1F)1094#define _RARF_RC6(x) (((x) & 0x1F) << 8)1095#define _RARF_RC7(x) (((x) & 0x1F) << 16)1096#define _RARF_RC8(x) (((x) & 0x1F) << 24)1097 1098#define AC_PARAM_TXOP_LIMIT_OFFSET 161099#define AC_PARAM_ECW_MAX_OFFSET 121100#define AC_PARAM_ECW_MIN_OFFSET 81101#define AC_PARAM_AIFS_OFFSET 01102 1103#define _AIFS(x) (x)1104#define _ECW_MAX_MIN(x) ((x) << 8)1105#define _TXOP_LIMIT(x) ((x) << 16)1106 1107#define _BCNIFS(x) ((x) & 0xFF)1108#define _BCNECW(x) ((((x) & 0xF)) << 8)1109 1110#define _LRL(x) ((x) & 0x3F)1111#define _SRL(x) (((x) & 0x3F) << 8)1112 1113#define _SIFS_CCK_CTX(x) ((x) & 0xFF)1114#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8);1115 1116#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)1117#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8);1118 1119#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)1120 1121#define DIS_EDCA_CNT_DWN BIT(11)1122 1123#define EN_MBSSID BIT(1)1124#define EN_TXBCN_RPT BIT(2)1125#define EN_BCN_FUNCTION BIT(3)1126 1127#define TSFTR_RST BIT(0)1128#define TSFTR1_RST BIT(1)1129 1130#define STOP_BCNQ BIT(6)1131 1132#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)1133#define DIS_TSF_UDT0_TEST_CHIP BIT(5)1134 1135#define ACMHW_HWEN BIT(0)1136#define ACMHW_BEQEN BIT(1)1137#define ACMHW_VIQEN BIT(2)1138#define ACMHW_VOQEN BIT(3)1139#define ACMHW_BEQSTATUS BIT(4)1140#define ACMHW_VIQSTATUS BIT(5)1141#define ACMHW_VOQSTATUS BIT(6)1142 1143#define APSDOFF BIT(6)1144#define APSDOFF_STATUS BIT(7)1145 1146#define BW_20MHZ BIT(2)1147 1148#define RATE_BITMAP_ALL 0xFFFFF1149 1150#define RATE_RRSR_CCK_ONLY_1M 0xFFFF11151 1152#define TSFRST BIT(0)1153#define DIS_GCLK BIT(1)1154#define PAD_SEL BIT(2)1155#define PWR_ST BIT(6)1156#define PWRBIT_OW_EN BIT(7)1157#define ACRC BIT(8)1158#define CFENDFORM BIT(9)1159#define ICV BIT(10)1160 1161#define AAP BIT(0)1162#define APM BIT(1)1163#define AM BIT(2)1164#define AB BIT(3)1165#define ADD3 BIT(4)1166#define APWRMGT BIT(5)1167#define CBSSID BIT(6)1168#define CBSSID_DATA BIT(6)1169#define CBSSID_BCN BIT(7)1170#define ACRC32 BIT(8)1171#define AICV BIT(9)1172#define ADF BIT(11)1173#define ACF BIT(12)1174#define AMF BIT(13)1175#define HTC_LOC_CTRL BIT(14)1176#define UC_DATA_EN BIT(16)1177#define BM_DATA_EN BIT(17)1178#define MFBEN BIT(22)1179#define LSIGEN BIT(23)1180#define ENMBID BIT(24)1181#define APP_BASSN BIT(27)1182#define APP_PHYSTS BIT(28)1183#define APP_ICV BIT(29)1184#define APP_MIC BIT(30)1185#define APP_FCS BIT(31)1186 1187#define _MIN_SPACE(x) ((x) & 0x7)1188#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)1189 1190#define RXERR_TYPE_OFDM_PPDU 01191#define RXERR_TYPE_OFDM_FALSE_ALARM 11192#define RXERR_TYPE_OFDM_MPDU_OK 21193#define RXERR_TYPE_OFDM_MPDU_FAIL 31194#define RXERR_TYPE_CCK_PPDU 41195#define RXERR_TYPE_CCK_FALSE_ALARM 51196#define RXERR_TYPE_CCK_MPDU_OK 61197#define RXERR_TYPE_CCK_MPDU_FAIL 71198#define RXERR_TYPE_HT_PPDU 81199#define RXERR_TYPE_HT_FALSE_ALARM 91200#define RXERR_TYPE_HT_MPDU_TOTAL 101201#define RXERR_TYPE_HT_MPDU_OK 111202#define RXERR_TYPE_HT_MPDU_FAIL 121203#define RXERR_TYPE_RX_FULL_DROP 151204 1205#define RXERR_COUNTER_MASK 0xFFFFF1206#define RXERR_RPT_RST BIT(27)1207#define _RXERR_RPT_SEL(type) ((type) << 28)1208 1209#define SCR_TXUSEDK BIT(0)1210#define SCR_RXUSEDK BIT(1)1211#define SCR_TXENCENABLE BIT(2)1212#define SCR_RXDECENABLE BIT(3)1213#define SCR_SKBYA2 BIT(4)1214#define SCR_NOSKMC BIT(5)1215#define SCR_TXBCUSEDK BIT(6)1216#define SCR_RXBCUSEDK BIT(7)1217 1218#define USB_IS_HIGH_SPEED 01219#define USB_IS_FULL_SPEED 11220#define USB_SPEED_MASK BIT(5)1221 1222#define USB_NORMAL_SIE_EP_MASK 0xF1223#define USB_NORMAL_SIE_EP_SHIFT 41224 1225#define USB_TEST_EP_MASK 0x301226#define USB_TEST_EP_SHIFT 41227 1228#define USB_AGG_EN BIT(3)1229 1230#define MAC_ADDR_LEN 61231#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/1232 1233#define POLLING_LLT_THRESHOLD 201234#define POLLING_READY_TIMEOUT_COUNT 30001235 1236#define MAX_MSS_DENSITY_2T 0x131237#define MAX_MSS_DENSITY_1T 0x0A1238 1239#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))1240#define EPROM_CMD_CONFIG 0x31241#define EPROM_CMD_LOAD 11242 1243#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE1244 1245#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)1246 1247#define RPMAC_RESET 0x1001248#define RPMAC_TXSTART 0x1041249#define RPMAC_TXLEGACYSIG 0x1081250#define RPMAC_TXHTSIG1 0x10c1251#define RPMAC_TXHTSIG2 0x1101252#define RPMAC_PHYDEBUG 0x1141253#define RPMAC_TXPACKETNUM 0x1181254#define RPMAC_TXIDLE 0x11c1255#define RPMAC_TXMACHEADER0 0x1201256#define RPMAC_TXMACHEADER1 0x1241257#define RPMAC_TXMACHEADER2 0x1281258#define RPMAC_TXMACHEADER3 0x12c1259#define RPMAC_TXMACHEADER4 0x1301260#define RPMAC_TXMACHEADER5 0x1341261#define RPMAC_TXDADATYPE 0x1381262#define RPMAC_TXRANDOMSEED 0x13c1263#define RPMAC_CCKPLCPPREAMBLE 0x1401264#define RPMAC_CCKPLCPHEADER 0x1441265#define RPMAC_CCKCRC16 0x1481266#define RPMAC_OFDMRXCRC32OK 0x1701267#define RPMAC_OFDMRXCRC32ER 0x1741268#define RPMAC_OFDMRXPARITYER 0x1781269#define RPMAC_OFDMRXCRC8ER 0x17c1270#define RPMAC_CCKCRXRC16ER 0x1801271#define RPMAC_CCKCRXRC32ER 0x1841272#define RPMAC_CCKCRXRC32OK 0x1881273#define RPMAC_TXSTATUS 0x18c1274 1275#define RFPGA0_RFMOD 0x8001276 1277#define RFPGA0_TXINFO 0x8041278#define RFPGA0_PSDFUNCTION 0x8081279 1280#define RFPGA0_TXGAINSTAGE 0x80c1281 1282#define RFPGA0_RFTIMING1 0x8101283#define RFPGA0_RFTIMING2 0x8141284 1285#define RFPGA0_XA_HSSIPARAMETER1 0x8201286#define RFPGA0_XA_HSSIPARAMETER2 0x8241287#define RFPGA0_XB_HSSIPARAMETER1 0x8281288#define RFPGA0_XB_HSSIPARAMETER2 0x82c1289 1290#define RFPGA0_XA_LSSIPARAMETER 0x8401291#define RFPGA0_XB_LSSIPARAMETER 0x8441292 1293#define RFPGA0_RFWAKEUPPARAMETER 0x8501294#define RFPGA0_RFSLEEPUPPARAMETER 0x8541295 1296#define RFPGA0_XAB_SWITCHCONTROL 0x8581297#define RFPGA0_XCD_SWITCHCONTROL 0x85c1298 1299#define RFPGA0_XA_RFINTERFACEOE 0x8601300#define RFPGA0_XB_RFINTERFACEOE 0x8641301 1302#define RFPGA0_XAB_RFINTERFACESW 0x8701303#define RFPGA0_XCD_RFINTERFACESW 0x8741304 1305#define RFPGA0_XAB_RFPARAMETER 0x8781306#define RFPGA0_XCD_RFPARAMETER 0x87c1307 1308#define RFPGA0_ANALOGPARAMETER1 0x8801309#define RFPGA0_ANALOGPARAMETER2 0x8841310#define RFPGA0_ANALOGPARAMETER3 0x8881311#define RFPGA0_ANALOGPARAMETER4 0x88c1312 1313#define RFPGA0_XA_LSSIREADBACK 0x8a01314#define RFPGA0_XB_LSSIREADBACK 0x8a41315#define RFPGA0_XC_LSSIREADBACK 0x8a81316#define RFPGA0_XD_LSSIREADBACK 0x8ac1317 1318#define RFPGA0_PSDREPORT 0x8b41319#define TRANSCEIVEA_HSPI_READBACK 0x8b81320#define TRANSCEIVEB_HSPI_READBACK 0x8bc1321#define REG_SC_CNT 0x8c41322#define RFPGA0_XAB_RFINTERFACERB 0x8e01323#define RFPGA0_XCD_RFINTERFACERB 0x8e41324 1325#define RFPGA1_RFMOD 0x9001326 1327#define RFPGA1_TXBLOCK 0x9041328#define RFPGA1_DEBUGSELECT 0x9081329#define RFPGA1_TXINFO 0x90c1330 1331#define RCCK0_SYSTEM 0xa001332 1333#define RCCK0_AFESETTING 0xa041334#define RCCK0_CCA 0xa081335 1336#define RCCK0_RXAGC1 0xa0c1337#define RCCK0_RXAGC2 0xa101338 1339#define RCCK0_RXHP 0xa141340 1341#define RCCK0_DSPPARAMETER1 0xa181342#define RCCK0_DSPPARAMETER2 0xa1c1343 1344#define RCCK0_TXFILTER1 0xa201345#define RCCK0_TXFILTER2 0xa241346#define RCCK0_DEBUGPORT 0xa281347#define RCCK0_FALSEALARMREPORT 0xa2c1348#define RCCK0_TRSSIREPORT 0xa501349#define RCCK0_RXREPORT 0xa541350#define RCCK0_FACOUNTERLOWER 0xa5c1351#define RCCK0_FACOUNTERUPPER 0xa581352#define RCCK0_CCA_CNT 0xa601353 1354/* PageB(0xB00) */1355#define RPDP_ANTA 0xb001356#define RPDP_ANTA_4 0xb041357#define RPDP_ANTA_8 0xb081358#define RPDP_ANTA_C 0xb0c1359#define RPDP_ANTA_10 0xb101360#define RPDP_ANTA_14 0xb141361#define RPDP_ANTA_18 0xb181362#define RPDP_ANTA_1C 0xb1c1363#define RPDP_ANTA_20 0xb201364#define RPDP_ANTA_24 0xb241365 1366#define RCONFIG_PMPD_ANTA 0xb281367#define RCONFIG_RAM64x16 0xb2c1368 1369#define RBNDA 0xb301370#define RHSSIPAR 0xb341371 1372#define RCONFIG_ANTA 0xb681373#define RCONFIG_ANTB 0xb6c1374 1375#define RPDP_ANTB 0xb701376#define RPDP_ANTB_4 0xb741377#define RPDP_ANTB_8 0xb781378#define RPDP_ANTB_C 0xb7c1379#define RPDP_ANTB_10 0xb801380#define RPDP_ANTB_14 0xb841381#define RPDP_ANTB_18 0xb881382#define RPDP_ANTB_1C 0xb8c1383#define RPDP_ANTB_20 0xb901384#define RPDP_ANTB_24 0xb941385 1386#define RCONFIG_PMPD_ANTB 0xb981387 1388#define RBNDB 0xba01389 1390#define RAPK 0xbd81391#define RPM_RX0_ANTA 0xbdc1392#define RPM_RX1_ANTA 0xbe01393#define RPM_RX2_ANTA 0xbe41394#define RPM_RX3_ANTA 0xbe81395#define RPM_RX0_ANTB 0xbec1396#define RPM_RX1_ANTB 0xbf01397#define RPM_RX2_ANTB 0xbf41398#define RPM_RX3_ANTB 0xbf81399 1400/*Page C*/1401#define ROFDM0_LSTF 0xc001402 1403#define ROFDM0_TRXPATHENABLE 0xc041404#define ROFDM0_TRMUXPAR 0xc081405#define ROFDM0_TRSWISOLATION 0xc0c1406 1407#define ROFDM0_XARXAFE 0xc101408#define ROFDM0_XARXIQIMBALANCE 0xc141409#define ROFDM0_XBRXAFE 0xc181410#define ROFDM0_XBRXIQIMBALANCE 0xc1c1411#define ROFDM0_XCRXAFE 0xc201412#define ROFDM0_XCRXIQIMBANLANCE 0xc241413#define ROFDM0_XDRXAFE 0xc281414#define ROFDM0_XDRXIQIMBALANCE 0xc2c1415 1416#define ROFDM0_RXDETECTOR1 0xc301417#define ROFDM0_RXDETECTOR2 0xc341418#define ROFDM0_RXDETECTOR3 0xc381419#define ROFDM0_RXDETECTOR4 0xc3c1420 1421#define ROFDM0_RXDSP 0xc401422#define ROFDM0_CFOANDDAGC 0xc441423#define ROFDM0_CCADROPTHRESHOLD 0xc481424#define ROFDM0_ECCATHRESHOLD 0xc4c1425 1426#define ROFDM0_XAAGCCORE1 0xc501427#define ROFDM0_XAAGCCORE2 0xc541428#define ROFDM0_XBAGCCORE1 0xc581429#define ROFDM0_XBAGCCORE2 0xc5c1430#define ROFDM0_XCAGCCORE1 0xc601431#define ROFDM0_XCAGCCORE2 0xc641432#define ROFDM0_XDAGCCORE1 0xc681433#define ROFDM0_XDAGCCORE2 0xc6c1434 1435#define ROFDM0_AGCPARAMETER1 0xc701436#define ROFDM0_AGCPARAMETER2 0xc741437#define ROFDM0_AGCRSSITABLE 0xc781438#define ROFDM0_HTSTFAGC 0xc7c1439 1440#define ROFDM0_XATXIQIMBALANCE 0xc801441#define ROFDM0_XATXAFE 0xc841442#define ROFDM0_XBTXIQIMBALANCE 0xc881443#define ROFDM0_XBTXAFE 0xc8c1444#define ROFDM0_XCTXIQIMBALANCE 0xc901445#define ROFDM0_XCTXAFE 0xc941446#define ROFDM0_XDTXIQIMBALANCE 0xc981447#define ROFDM0_XDTXAFE 0xc9c1448 1449#define ROFDM0_RXIQEXTANTA 0xca01450#define ROFDM0_TXCOEFF1 0xca41451#define ROFDM0_TXCOEFF2 0xca81452#define ROFDM0_TXCOEFF3 0xcac1453#define ROFDM0_TXCOEFF4 0xcb01454#define ROFDM0_TXCOEFF5 0xcb41455#define ROFDM0_TXCOEFF6 0xcb81456 1457#define ROFDM0_RXHPPARAMETER 0xce01458#define ROFDM0_TXPSEUDONOISEWGT 0xce41459#define ROFDM0_FRAMESYNC 0xcf01460#define ROFDM0_DFSREPORT 0xcf41461 1462#define ROFDM1_LSTF 0xd001463#define ROFDM1_TRXPATHENABLE 0xd041464 1465#define ROFDM1_CF0 0xd081466#define ROFDM1_CSI1 0xd101467#define ROFDM1_SBD 0xd141468#define ROFDM1_CSI2 0xd181469#define ROFDM1_CFOTRACKING 0xd2c1470#define ROFDM1_TRXMESAURE1 0xd341471#define ROFDM1_INTFDET 0xd3c1472#define ROFDM1_PSEUDONOISESTATEAB 0xd501473#define ROFDM1_PSEUDONOISESTATECD 0xd541474#define ROFDM1_RXPSEUDONOISEWGT 0xd581475 1476#define ROFDM_PHYCOUNTER1 0xda01477#define ROFDM_PHYCOUNTER2 0xda41478#define ROFDM_PHYCOUNTER3 0xda81479 1480#define ROFDM_SHORTCFOAB 0xdac1481#define ROFDM_SHORTCFOCD 0xdb01482#define ROFDM_LONGCFOAB 0xdb41483#define ROFDM_LONGCFOCD 0xdb81484#define ROFDM_TAILCF0AB 0xdbc1485#define ROFDM_TAILCF0CD 0xdc01486#define ROFDM_PWMEASURE1 0xdc41487#define ROFDM_PWMEASURE2 0xdc81488#define ROFDM_BWREPORT 0xdcc1489#define ROFDM_AGCREPORT 0xdd01490#define ROFDM_RXSNR 0xdd41491#define ROFDM_RXEVMCSI 0xdd81492#define ROFDM_SIGREPORT 0xddc1493 1494#define RTXAGC_A_RATE18_06 0xe001495#define RTXAGC_A_RATE54_24 0xe041496#define RTXAGC_A_CCK1_MCS32 0xe081497#define RTXAGC_A_MCS03_MCS00 0xe101498#define RTXAGC_A_MCS07_MCS04 0xe141499#define RTXAGC_A_MCS11_MCS08 0xe181500#define RTXAGC_A_MCS15_MCS12 0xe1c1501 1502#define RTXAGC_B_RATE18_06 0x8301503#define RTXAGC_B_RATE54_24 0x8341504#define RTXAGC_B_CCK1_55_MCS32 0x8381505#define RTXAGC_B_MCS03_MCS00 0x83c1506#define RTXAGC_B_MCS07_MCS04 0x8481507#define RTXAGC_B_MCS11_MCS08 0x84c1508#define RTXAGC_B_MCS15_MCS12 0x8681509#define RTXAGC_B_CCK11_A_CCK2_11 0x86c1510 1511#define RFPGA0_IQK 0xe281512#define RTX_IQK_TONE_A 0xe301513#define RRX_IQK_TONE_A 0xe341514#define RTX_IQK_PI_A 0xe381515#define RRX_IQK_PI_A 0xe3c1516 1517#define RTX_IQK 0xe401518#define RRX_IQK 0xe441519#define RIQK_AGC_PTS 0xe481520#define RIQK_AGC_RSP 0xe4c1521#define RTX_IQK_TONE_B 0xe501522#define RRX_IQK_TONE_B 0xe541523#define RTX_IQK_PI_B 0xe581524#define RRX_IQK_PI_B 0xe5c1525#define RIQK_AGC_CONT 0xe601526 1527#define RBLUE_TOOTH 0xe6c1528#define RRX_WAIT_CCA 0xe701529#define RTX_CCK_RFON 0xe741530#define RTX_CCK_BBON 0xe781531#define RTX_OFDM_RFON 0xe7c1532#define RTX_OFDM_BBON 0xe801533#define RTX_TO_RX 0xe841534#define RTX_TO_TX 0xe881535#define RRX_CCK 0xe8c1536 1537#define RTX_POWER_BEFORE_IQK_A 0xe941538#define RTX_POWER_AFTER_IQK_A 0xe9c1539 1540#define RRX_POWER_BEFORE_IQK_A 0xea01541#define RRX_POWER_BEFORE_IQK_A_2 0xea41542#define RRX_POWER_AFTER_IQK_A 0xea81543#define RRX_POWER_AFTER_IQK_A_2 0xeac1544 1545#define RTX_POWER_BEFORE_IQK_B 0xeb41546#define RTX_POWER_AFTER_IQK_B 0xebc1547 1548#define RRX_POWER_BEFORE_IQK_B 0xec01549#define RRX_POWER_BEFORE_IQK_B_2 0xec41550#define RRX_POWER_AFTER_IQK_B 0xec81551#define RRX_POWER_AFTER_IQK_B_2 0xecc1552 1553#define RRX_OFDM 0xed01554#define RRX_WAIT_RIFS 0xed41555#define RRX_TO_RX 0xed81556#define RSTANDBY 0xedc1557#define RSLEEP 0xee01558#define RPMPD_ANAEN 0xeec1559 1560#define RZEBRA1_HSSIENABLE 0x01561#define RZEBRA1_TRXENABLE1 0x11562#define RZEBRA1_TRXENABLE2 0x21563#define RZEBRA1_AGC 0x41564#define RZEBRA1_CHARGEPUMP 0x51565#define RZEBRA1_CHANNEL 0x71566 1567#define RZEBRA1_TXGAIN 0x81568#define RZEBRA1_TXLPF 0x91569#define RZEBRA1_RXLPF 0xb1570#define RZEBRA1_RXHPFCORNER 0xc1571 1572#define RGLOBALCTRL 01573#define RRTL8256_TXLPF 191574#define RRTL8256_RXLPF 111575#define RRTL8258_TXLPF 0x111576#define RRTL8258_RXLPF 0x131577#define RRTL8258_RSSILPF 0xa1578 1579#define RF_AC 0x001580 1581#define RF_IQADJ_G1 0x011582#define RF_IQADJ_G2 0x021583#define RF_POW_TRSW 0x051584 1585#define RF_GAIN_RX 0x061586#define RF_GAIN_TX 0x071587 1588#define RF_TXM_IDAC 0x081589#define RF_BS_IQGEN 0x0F1590 1591#define RF_MODE1 0x101592#define RF_MODE2 0x111593 1594#define RF_RX_AGC_HP 0x121595#define RF_TX_AGC 0x131596#define RF_BIAS 0x141597#define RF_IPA 0x151598#define RF_POW_ABILITY 0x171599#define RF_MODE_AG 0x181600#define RRFCHANNEL 0x181601#define RF_CHNLBW 0x181602#define RF_TOP 0x191603 1604#define RF_RX_G1 0x1A1605#define RF_RX_G2 0x1B1606 1607#define RF_RX_BB2 0x1C1608#define RF_RX_BB1 0x1D1609 1610#define RF_RCK1 0x1E1611#define RF_RCK2 0x1F1612 1613#define RF_TX_G1 0x201614#define RF_TX_G2 0x211615#define RF_TX_G3 0x221616 1617#define RF_TX_BB1 0x231618#define RF_T_METER 0x421619 1620#define RF_SYN_G1 0x251621#define RF_SYN_G2 0x261622#define RF_SYN_G3 0x271623#define RF_SYN_G4 0x281624#define RF_SYN_G5 0x291625#define RF_SYN_G6 0x2A1626#define RF_SYN_G7 0x2B1627#define RF_SYN_G8 0x2C1628 1629#define RF_RCK_OS 0x301630#define RF_TXPA_G1 0x311631#define RF_TXPA_G2 0x321632#define RF_TXPA_G3 0x331633 1634#define RF_TX_BIAS_A 0x351635#define RF_TX_BIAS_D 0x361636#define RF_LOBF_9 0x381637#define RF_RXRF_A3 0x3C1638#define RF_TRSW 0x3F1639 1640#define RF_TXRF_A2 0x411641#define RF_TXPA_G4 0x461642#define RF_TXPA_A4 0x4B1643 1644#define RF_WE_LUT 0xEF1645 1646#define BBBRESETB 0x1001647#define BGLOBALRESETB 0x2001648#define BOFDMTXSTART 0x41649#define BCCKTXSTART 0x81650#define BCRC32DEBUG 0x1001651#define BPMACLOOPBACK 0x101652#define BTXLSIG 0xffffff1653#define BOFDMTXRATE 0xf1654#define BOFDMTXRESERVED 0x101655#define BOFDMTXLENGTH 0x1ffe01656#define BOFDMTXPARITY 0x200001657#define BTXHTSIG1 0xffffff1658#define BTXHTMCSRATE 0x7f1659#define BTXHTBW 0x801660#define BTXHTLENGTH 0xffff001661#define BTXHTSIG2 0xffffff1662#define BTXHTSMOOTHING 0x11663#define BTXHTSOUNDING 0x21664#define BTXHTRESERVED 0x41665#define BTXHTAGGREATION 0x81666#define BTXHTSTBC 0x301667#define BTXHTADVANCECODING 0x401668#define BTXHTSHORTGI 0x801669#define BTXHTNUMBERHT_LTF 0x3001670#define BTXHTCRC8 0x3fc001671#define BCOUNTERRESET 0x100001672#define BNUMOFOFDMTX 0xffff1673#define BNUMOFCCKTX 0xffff00001674#define BTXIDLEINTERVAL 0xffff1675#define BOFDMSERVICE 0xffff00001676#define BTXMACHEADER 0xffffffff1677#define BTXDATAINIT 0xff1678#define BTXHTMODE 0x1001679#define BTXDATATYPE 0x300001680#define BTXRANDOMSEED 0xffffffff1681#define BCCKTXPREAMBLE 0x11682#define BCCKTXSFD 0xffff00001683#define BCCKTXSIG 0xff1684#define BCCKTXSERVICE 0xff001685#define BCCKLENGTHEXT 0x80001686#define BCCKTXLENGHT 0xffff00001687#define BCCKTXCRC16 0xffff1688#define BCCKTXSTATUS 0x11689#define BOFDMTXSTATUS 0x21690#define IS_BB_REG_OFFSET_92S(_offset) \1691 ((_offset >= 0x800) && (_offset <= 0xfff))1692 1693#define BRFMOD 0x11694#define BJAPANMODE 0x21695#define BCCKTXSC 0x301696#define BCCKEN 0x10000001697#define BOFDMEN 0x20000001698 1699#define BOFDMRXADCPHASE 0x100001700#define BOFDMTXDACPHASE 0x400001701#define BXATXAGC 0x3f1702 1703#define BXBTXAGC 0xf001704#define BXCTXAGC 0xf0001705#define BXDTXAGC 0xf00001706 1707#define BPASTART 0xf00000001708#define BTRSTART 0x00f000001709#define BRFSTART 0x0000f0001710#define BBBSTART 0x000000f01711#define BBBCCKSTART 0x0000000f1712#define BPAEND 0xf1713#define BTREND 0x0f0000001714#define BRFEND 0x000f00001715#define BCCAMASK 0x000000f01716#define BR2RCCAMASK 0x00000f001717#define BHSSI_R2TDELAY 0xf80000001718#define BHSSI_T2RDELAY 0xf800001719#define BCONTXHSSI 0x4001720#define BIGFROMCCK 0x2001721#define BAGCADDRESS 0x3f1722#define BRXHPTX 0x70001723#define BRXHP2RX 0x380001724#define BRXHPCCKINI 0xc00001725#define BAGCTXCODE 0xc000001726#define BAGCRXCODE 0x3000001727 1728#define B3WIREDATALENGTH 0x8001729#define B3WIREADDREAALENGTH 0x4001730 1731#define B3WIRERFPOWERDOWN 0x11732#define B5GPAPEPOLARITY 0x400000001733#define B2GPAPEPOLARITY 0x800000001734#define BRFSW_TXDEFAULTANT 0x31735#define BRFSW_TXOPTIONANT 0x301736#define BRFSW_RXDEFAULTANT 0x3001737#define BRFSW_RXOPTIONANT 0x30001738#define BRFSI_3WIREDATA 0x11739#define BRFSI_3WIRECLOCK 0x21740#define BRFSI_3WIRELOAD 0x41741#define BRFSI_3WIRERW 0x81742#define BRFSI_3WIRE 0xf1743 1744#define BRFSI_RFENV 0x101745 1746#define BRFSI_TRSW 0x201747#define BRFSI_TRSWB 0x401748#define BRFSI_ANTSW 0x1001749#define BRFSI_ANTSWB 0x2001750#define BRFSI_PAPE 0x4001751#define BRFSI_PAPE5G 0x8001752#define BBANDSELECT 0x11753#define BHTSIG2_GI 0x801754#define BHTSIG2_SMOOTHING 0x011755#define BHTSIG2_SOUNDING 0x021756#define BHTSIG2_AGGREATON 0x081757#define BHTSIG2_STBC 0x301758#define BHTSIG2_ADVCODING 0x401759#define BHTSIG2_NUMOFHTLTF 0x3001760#define BHTSIG2_CRC8 0x3fc1761#define BHTSIG1_MCS 0x7f1762#define BHTSIG1_BANDWIDTH 0x801763#define BHTSIG1_HTLENGTH 0xffff1764#define BLSIG_RATE 0xf1765#define BLSIG_RESERVED 0x101766#define BLSIG_LENGTH 0x1fffe1767#define BLSIG_PARITY 0x201768#define BCCKRXPHASE 0x41769 1770#define BLSSIREADADDRESS 0x7f8000001771#define BLSSIREADEDGE 0x800000001772 1773#define BLSSIREADBACKDATA 0xfffff1774 1775#define BLSSIREADOKFLAG 0x10001776#define BCCKSAMPLERATE 0x81777#define BREGULATOR0STANDBY 0x11778#define BREGULATORPLLSTANDBY 0x21779#define BREGULATOR1STANDBY 0x41780#define BPLLPOWERUP 0x81781#define BDPLLPOWERUP 0x101782#define BDA10POWERUP 0x201783#define BAD7POWERUP 0x2001784#define BDA6POWERUP 0x20001785#define BXTALPOWERUP 0x40001786#define B40MDCLKPOWERUP 0x80001787#define BDA6DEBUGMODE 0x200001788#define BDA6SWING 0x3800001789 1790#define BADCLKPHASE 0x40000001791#define B80MCLKDELAY 0x180000001792#define BAFEWATCHDOGENABLE 0x200000001793 1794#define BXTALCAP01 0xc00000001795#define BXTALCAP23 0x31796#define BXTALCAP92X 0x0f0000001797#define BXTALCAP 0x0f0000001798 1799#define BINTDIFCLKENABLE 0x4001800#define BEXTSIGCLKENABLE 0x8001801#define BBANDGAP_MBIAS_POWERUP 0x100001802#define BAD11SH_GAIN 0xc00001803#define BAD11NPUT_RANGE 0x7000001804#define BAD110P_CURRENT 0x38000001805#define BLPATH_LOOPBACK 0x40000001806#define BQPATH_LOOPBACK 0x80000001807#define BAFE_LOOPBACK 0x100000001808#define BDA10_SWING 0x7e01809#define BDA10_REVERSE 0x8001810#define BDA_CLK_SOURCE 0x10001811#define BDA7INPUT_RANGE 0x60001812#define BDA7_GAIN 0x380001813#define BDA7OUTPUT_CM_MODE 0x400001814#define BDA7INPUT_CM_MODE 0x3800001815#define BDA7CURRENT 0xc000001816#define BREGULATOR_ADJUST 0x70000001817#define BAD11POWERUP_ATTX 0x11818#define BDA10PS_ATTX 0x101819#define BAD11POWERUP_ATRX 0x1001820#define BDA10PS_ATRX 0x10001821#define BCCKRX_AGC_FORMAT 0x2001822#define BPSDFFT_SAMPLE_POINT 0xc0001823#define BPSD_AVERAGE_NUM 0x30001824#define BIQPATH_CONTROL 0xc001825#define BPSD_FREQ 0x3ff1826#define BPSD_ANTENNA_PATH 0x301827#define BPSD_IQ_SWITCH 0x401828#define BPSD_RX_TRIGGER 0x4000001829#define BPSD_TX_TRIGGER 0x800000001830#define BPSD_SINE_TONE_SCALE 0x7f0000001831#define BPSD_REPORT 0xffff1832 1833#define BOFDM_TXSC 0x300000001834#define BCCK_TXON 0x11835#define BOFDM_TXON 0x21836#define BDEBUG_PAGE 0xfff1837#define BDEBUG_ITEM 0xff1838#define BANTL 0x101839#define BANT_NONHT 0x1001840#define BANT_HT1 0x10001841#define BANT_HT2 0x100001842#define BANT_HT1S1 0x1000001843#define BANT_NONHTS1 0x10000001844 1845#define BCCK_BBMODE 0x31846#define BCCK_TXPOWERSAVING 0x801847#define BCCK_RXPOWERSAVING 0x401848 1849#define BCCK_SIDEBAND 0x101850 1851#define BCCK_SCRAMBLE 0x81852#define BCCK_ANTDIVERSITY 0x80001853#define BCCK_CARRIER_RECOVERY 0x40001854#define BCCK_TXRATE 0x30001855#define BCCK_DCCANCEL 0x08001856#define BCCK_ISICANCEL 0x04001857#define BCCK_MATCH_FILTER 0x02001858#define BCCK_EQUALIZER 0x01001859#define BCCK_PREAMBLE_DETECT 0x8000001860#define BCCK_FAST_FALSECCA 0x4000001861#define BCCK_CH_ESTSTART 0x3000001862#define BCCK_CCA_COUNT 0x0800001863#define BCCK_CS_LIM 0x0700001864#define BCCK_BIST_MODE 0x800000001865#define BCCK_CCAMASK 0x400000001866#define BCCK_TX_DAC_PHASE 0x41867#define BCCK_RX_ADC_PHASE 0x200000001868#define BCCKR_CP_MODE 0x01001869#define BCCK_TXDC_OFFSET 0xf01870#define BCCK_RXDC_OFFSET 0xf1871#define BCCK_CCA_MODE 0xc0001872#define BCCK_FALSECS_LIM 0x3f001873#define BCCK_CS_RATIO 0xc000001874#define BCCK_CORGBIT_SEL 0x3000001875#define BCCK_PD_LIM 0x0f00001876#define BCCK_NEWCCA 0x800000001877#define BCCK_RXHP_OF_IG 0x80001878#define BCCK_RXIG 0x7f001879#define BCCK_LNA_POLARITY 0x8000001880#define BCCK_RX1ST_BAIN 0x7f00001881#define BCCK_RF_EXTEND 0x200000001882#define BCCK_RXAGC_SATLEVEL 0x1f0000001883#define BCCK_RXAGC_SATCOUNT 0xe01884#define BCCKRXRFSETTLE 0x1f1885#define BCCK_FIXED_RXAGC 0x80001886#define BCCK_ANTENNA_POLARITY 0x20001887#define BCCK_TXFILTER_TYPE 0x0c001888#define BCCK_RXAGC_REPORTTYPE 0x03001889#define BCCK_RXDAGC_EN 0x800000001890#define BCCK_RXDAGC_PERIOD 0x200000001891#define BCCK_RXDAGC_SATLEVEL 0x1f0000001892#define BCCK_TIMING_RECOVERY 0x8000001893#define BCCK_TXC0 0x3f00001894#define BCCK_TXC1 0x3f0000001895#define BCCK_TXC2 0x3f1896#define BCCK_TXC3 0x3f001897#define BCCK_TXC4 0x3f00001898#define BCCK_TXC5 0x3f0000001899#define BCCK_TXC6 0x3f1900#define BCCK_TXC7 0x3f001901#define BCCK_DEBUGPORT 0xff00001902#define BCCK_DAC_DEBUG 0x0f0000001903#define BCCK_FALSEALARM_ENABLE 0x80001904#define BCCK_FALSEALARM_READ 0x40001905#define BCCK_TRSSI 0x7f1906#define BCCK_RXAGC_REPORT 0xfe1907#define BCCK_RXREPORT_ANTSEL 0x800000001908#define BCCK_RXREPORT_MFOFF 0x400000001909#define BCCK_RXREPORT_SQLOSS 0x200000001910#define BCCK_RXREPORT_PKTLOSS 0x100000001911#define BCCK_RXREPORT_LOCKEDBIT 0x080000001912#define BCCK_RXREPORT_RATEERROR 0x040000001913#define BCCK_RXREPORT_RXRATE 0x030000001914#define BCCK_RXFA_COUNTER_LOWER 0xff1915#define BCCK_RXFA_COUNTER_UPPER 0xff0000001916#define BCCK_RXHPAGC_START 0xe0001917#define BCCK_RXHPAGC_FINAL 0x1c001918#define BCCK_RXFALSEALARM_ENABLE 0x80001919#define BCCK_FACOUNTER_FREEZE 0x40001920#define BCCK_TXPATH_SEL 0x100000001921#define BCCK_DEFAULT_RXPATH 0xc0000001922#define BCCK_OPTION_RXPATH 0x30000001923 1924#define BNUM_OFSTF 0x31925#define BSHIFT_L 0xc01926#define BGI_TH 0xc1927#define BRXPATH_A 0x11928#define BRXPATH_B 0x21929#define BRXPATH_C 0x41930#define BRXPATH_D 0x81931#define BTXPATH_A 0x11932#define BTXPATH_B 0x21933#define BTXPATH_C 0x41934#define BTXPATH_D 0x81935#define BTRSSI_FREQ 0x2001936#define BADC_BACKOFF 0x30001937#define BDFIR_BACKOFF 0xc0001938#define BTRSSI_LATCH_PHASE 0x100001939#define BRX_LDC_OFFSET 0xff1940#define BRX_QDC_OFFSET 0xff001941#define BRX_DFIR_MODE 0x18000001942#define BRX_DCNF_TYPE 0xe0000001943#define BRXIQIMB_A 0x3ff1944#define BRXIQIMB_B 0xfc001945#define BRXIQIMB_C 0x3f00001946#define BRXIQIMB_D 0xffc000001947#define BDC_DC_NOTCH 0x600001948#define BRXNB_NOTCH 0x1f0000001949#define BPD_TH 0xf1950#define BPD_TH_OPT2 0xc0001951#define BPWED_TH 0x7001952#define BIFMF_WIN_L 0x8001953#define BPD_OPTION 0x10001954#define BMF_WIN_L 0xe0001955#define BBW_SEARCH_L 0x300001956#define BWIN_ENH_L 0xc00001957#define BBW_TH 0x7000001958#define BED_TH2 0x38000001959#define BBW_OPTION 0x40000001960#define BRADIO_TH 0x180000001961#define BWINDOW_L 0xe00000001962#define BSBD_OPTION 0x11963#define BFRAME_TH 0x1c1964#define BFS_OPTION 0x601965#define BDC_SLOPE_CHECK 0x801966#define BFGUARD_COUNTER_DC_L 0xe001967#define BFRAME_WEIGHT_SHORT 0x70001968#define BSUB_TUNE 0xe000001969#define BFRAME_DC_LENGTH 0xe0000001970#define BSBD_START_OFFSET 0x300000001971#define BFRAME_TH_2 0x71972#define BFRAME_GI2_TH 0x381973#define BGI2_SYNC_EN 0x401974#define BSARCH_SHORT_EARLY 0x3001975#define BSARCH_SHORT_LATE 0xc001976#define BSARCH_GI2_LATE 0x700001977#define BCFOANTSUM 0x11978#define BCFOACC 0x21979#define BCFOSTARTOFFSET 0xc1980#define BCFOLOOPBACK 0x701981#define BCFOSUMWEIGHT 0x801982#define BDAGCENABLE 0x100001983#define BTXIQIMB_A 0x3ff1984#define BTXIQIMB_b 0xfc001985#define BTXIQIMB_C 0x3f00001986#define BTXIQIMB_D 0xffc000001987#define BTXIDCOFFSET 0xff1988#define BTXIQDCOFFSET 0xff001989#define BTXDFIRMODE 0x100001990#define BTXPESUDO_NOISEON 0x40000001991#define BTXPESUDO_NOISE_A 0xff1992#define BTXPESUDO_NOISE_B 0xff001993#define BTXPESUDO_NOISE_C 0xff00001994#define BTXPESUDO_NOISE_D 0xff0000001995#define BCCA_DROPOPTION 0x200001996#define BCCA_DROPTHRES 0xfff000001997#define BEDCCA_H 0xf1998#define BEDCCA_L 0xf01999#define BLAMBDA_ED 0x3002000#define BRX_INITIALGAIN 0x7f2001#define BRX_ANTDIV_EN 0x802002#define BRX_AGC_ADDRESS_FOR_LNA 0x7f002003#define BRX_HIGHPOWER_FLOW 0x80002004#define BRX_AGC_FREEZE_THRES 0xc00002005#define BRX_FREEZESTEP_AGC1 0x3000002006#define BRX_FREEZESTEP_AGC2 0xc000002007#define BRX_FREEZESTEP_AGC3 0x30000002008#define BRX_FREEZESTEP_AGC0 0xc0000002009#define BRXRSSI_CMP_EN 0x100000002010#define BRXQUICK_AGCEN 0x200000002011#define BRXAGC_FREEZE_THRES_MODE 0x400000002012#define BRX_OVERFLOW_CHECKTYPE 0x800000002013#define BRX_AGCSHIFT 0x7f2014#define BTRSW_TRI_ONLY 0x802015#define BPOWER_THRES 0x3002016#define BRXAGC_EN 0x12017#define BRXAGC_TOGETHER_EN 0x22018#define BRXAGC_MIN 0x42019#define BRXHP_INI 0x72020#define BRXHP_TRLNA 0x702021#define BRXHP_RSSI 0x7002022#define BRXHP_BBP1 0x70002023#define BRXHP_BBP2 0x700002024#define BRXHP_BBP3 0x7000002025#define BRSSI_H 0x7f00002026#define BRSSI_GEN 0x7f0000002027#define BRXSETTLE_TRSW 0x72028#define BRXSETTLE_LNA 0x382029#define BRXSETTLE_RSSI 0x1c02030#define BRXSETTLE_BBP 0xe002031#define BRXSETTLE_RXHP 0x70002032#define BRXSETTLE_ANTSW_RSSI 0x380002033#define BRXSETTLE_ANTSW 0xc00002034#define BRXPROCESS_TIME_DAGC 0x3000002035#define BRXSETTLE_HSSI 0x4000002036#define BRXPROCESS_TIME_BBPPW 0x8000002037#define BRXANTENNA_POWER_SHIFT 0x30000002038#define BRSSI_TABLE_SELECT 0xc0000002039#define BRXHP_FINAL 0x70000002040#define BRXHPSETTLE_BBP 0x72041#define BRXHTSETTLE_HSSI 0x82042#define BRXHTSETTLE_RXHP 0x702043#define BRXHTSETTLE_BBPPW 0x802044#define BRXHTSETTLE_IDLE 0x3002045#define BRXHTSETTLE_RESERVED 0x1c002046#define BRXHT_RXHP_EN 0x80002047#define BRXAGC_FREEZE_THRES 0x300002048#define BRXAGC_TOGETHEREN 0x400002049#define BRXHTAGC_MIN 0x800002050#define BRXHTAGC_EN 0x1000002051#define BRXHTDAGC_EN 0x2000002052#define BRXHT_RXHP_BBP 0x1c000002053#define BRXHT_RXHP_FINAL 0xe00000002054#define BRXPW_RADIO_TH 0x32055#define BRXPW_RADIO_EN 0x42056#define BRXMF_HOLD 0x38002057#define BRXPD_DELAY_TH1 0x382058#define BRXPD_DELAY_TH2 0x1c02059#define BRXPD_DC_COUNT_MAX 0x6002060#define BRXPD_DELAY_TH 0x80002061#define BRXPROCESS_DELAY 0xf00002062#define BRXSEARCHRANGE_GI2_EARLY 0x7000002063#define BRXFRAME_FUARD_COUNTER_L 0x38000002064#define BRXSGI_GUARD_L 0xc0000002065#define BRXSGI_SEARCH_L 0x300000002066#define BRXSGI_TH 0xc00000002067#define BDFSCNT0 0xff2068#define BDFSCNT1 0xff002069#define BDFSFLAG 0xf00002070#define BMF_WEIGHT_SUM 0x3000002071#define BMINIDX_TH 0x7f0000002072#define BDAFORMAT 0x400002073#define BTXCH_EMU_ENABLE 0x010000002074#define BTRSW_ISOLATION_A 0x7f2075#define BTRSW_ISOLATION_B 0x7f002076#define BTRSW_ISOLATION_C 0x7f00002077#define BTRSW_ISOLATION_D 0x7f0000002078#define BEXT_LNA_GAIN 0x7c002079 2080#define BSTBC_EN 0x42081#define BANTENNA_MAPPING 0x102082#define BNSS 0x202083#define BCFO_ANTSUM_ID 0x2002084#define BPHY_COUNTER_RESET 0x80000002085#define BCFO_REPORT_GET 0x40000002086#define BOFDM_CONTINUE_TX 0x100000002087#define BOFDM_SINGLE_CARRIER 0x200000002088#define BOFDM_SINGLE_TONE 0x400000002089#define BHT_DETECT 0x1002090#define BCFOEN 0x100002091#define BCFOVALUE 0xfff000002092#define BSIGTONE_RE 0x3f2093#define BSIGTONE_IM 0x7f002094#define BCOUNTER_CCA 0xffff2095#define BCOUNTER_PARITYFAIL 0xffff00002096#define BCOUNTER_RATEILLEGAL 0xffff2097#define BCOUNTER_CRC8FAIL 0xffff00002098#define BCOUNTER_MCSNOSUPPORT 0xffff2099#define BCOUNTER_FASTSYNC 0xffff2100#define BSHORTCFO 0xfff2101#define BSHORTCFOT_LENGTH 122102#define BSHORTCFOF_LENGTH 112103#define BLONGCFO 0x7ff2104#define BLONGCFOT_LENGTH 112105#define BLONGCFOF_LENGTH 112106#define BTAILCFO 0x1fff2107#define BTAILCFOT_LENGTH 132108#define BTAILCFOF_LENGTH 122109#define BNOISE_EN_PWDB 0xffff2110#define BCC_POWER_DB 0xffff00002111#define BMOISE_PWDB 0xffff2112#define BPOWERMEAST_LENGTH 102113#define BPOWERMEASF_LENGTH 32114#define BRX_HT_BW 0x12115#define BRXSC 0x62116#define BRX_HT 0x82117#define BNB_INTF_DET_ON 0x12118#define BINTF_WIN_LEN_CFG 0x302119#define BNB_INTF_TH_CFG 0x1c02120#define BRFGAIN 0x3f2121#define BTABLESEL 0x402122#define BTRSW 0x802123#define BRXSNR_A 0xff2124#define BRXSNR_B 0xff002125#define BRXSNR_C 0xff00002126#define BRXSNR_D 0xff0000002127#define BSNR_EVMT_LENGTH 82128#define BSNR_EVMF_LENGTH 12129#define BCSI1ST 0xff2130#define BCSI2ND 0xff002131#define BRXEVM1ST 0xff00002132#define BRXEVM2ND 0xff0000002133#define BSIGEVM 0xff2134#define BPWDB 0xff002135#define BSGIEN 0x100002136 2137#define BSFACTOR_QMA1 0xf2138#define BSFACTOR_QMA2 0xf02139#define BSFACTOR_QMA3 0xf002140#define BSFACTOR_QMA4 0xf0002141#define BSFACTOR_QMA5 0xf00002142#define BSFACTOR_QMA6 0xf00002143#define BSFACTOR_QMA7 0xf000002144#define BSFACTOR_QMA8 0xf0000002145#define BSFACTOR_QMA9 0xf00000002146#define BCSI_SCHEME 0x1000002147 2148#define BNOISE_LVL_TOP_SET 0x32149#define BCHSMOOTH 0x42150#define BCHSMOOTH_CFG1 0x382151#define BCHSMOOTH_CFG2 0x1c02152#define BCHSMOOTH_CFG3 0xe002153#define BCHSMOOTH_CFG4 0x70002154#define BMRCMODE 0x8000002155#define BTHEVMCFG 0x70000002156 2157#define BLOOP_FIT_TYPE 0x12158#define BUPD_CFO 0x402159#define BUPD_CFO_OFFDATA 0x802160#define BADV_UPD_CFO 0x1002161#define BADV_TIME_CTRL 0x8002162#define BUPD_CLKO 0x10002163#define BFC 0x60002164#define BTRACKING_MODE 0x80002165#define BPHCMP_ENABLE 0x100002166#define BUPD_CLKO_LTF 0x200002167#define BCOM_CH_CFO 0x400002168#define BCSI_ESTI_MODE 0x800002169#define BADV_UPD_EQZ 0x1000002170#define BUCHCFG 0x70000002171#define BUPDEQZ 0x80000002172 2173#define BRX_PESUDO_NOISE_ON 0x200000002174#define BRX_PESUDO_NOISE_A 0xff2175#define BRX_PESUDO_NOISE_B 0xff002176#define BRX_PESUDO_NOISE_C 0xff00002177#define BRX_PESUDO_NOISE_D 0xff0000002178#define BRX_PESUDO_NOISESTATE_A 0xffff2179#define BRX_PESUDO_NOISESTATE_B 0xffff00002180#define BRX_PESUDO_NOISESTATE_C 0xffff2181#define BRX_PESUDO_NOISESTATE_D 0xffff00002182 2183#define BZEBRA1_HSSIENABLE 0x82184#define BZEBRA1_TRXCONTROL 0xc002185#define BZEBRA1_TRXGAINSETTING 0x07f2186#define BZEBRA1_RXCOUNTER 0xc002187#define BZEBRA1_TXCHANGEPUMP 0x382188#define BZEBRA1_RXCHANGEPUMP 0x72189#define BZEBRA1_CHANNEL_NUM 0xf802190#define BZEBRA1_TXLPFBW 0x4002191#define BZEBRA1_RXLPFBW 0x6002192 2193#define BRTL8256REG_MODE_CTRL1 0x1002194#define BRTL8256REG_MODE_CTRL0 0x402195#define BRTL8256REG_TXLPFBW 0x182196#define BRTL8256REG_RXLPFBW 0x6002197 2198#define BRTL8258_TXLPFBW 0xc2199#define BRTL8258_RXLPFBW 0xc002200#define BRTL8258_RSSILPFBW 0xc02201 2202#define BBYTE0 0x12203#define BBYTE1 0x22204#define BBYTE2 0x42205#define BBYTE3 0x82206#define BWORD0 0x32207#define BWORD1 0xc2208#define BWORD 0xf2209 2210#define MASKBYTE0 0xff2211#define MASKBYTE1 0xff002212#define MASKBYTE2 0xff00002213#define MASKBYTE3 0xff0000002214#define MASKHWORD 0xffff00002215#define MASKLWORD 0x0000ffff2216#define MASKDWORD 0xffffffff2217#define MASK12BITS 0xfff2218#define MASKH4BITS 0xf00000002219#define MASKOFDM_D 0xffc000002220#define MASKCCK 0x3f3f3f3f2221 2222#define MASK4BITS 0x0f2223#define MASK20BITS 0xfffff2224#define RFREG_OFFSET_MASK 0xfffff2225 2226#define BENABLE 0x12227#define BDISABLE 0x02228 2229#define LEFT_ANTENNA 0x02230#define RIGHT_ANTENNA 0x12231 2232#define TCHECK_TXSTATUS 5002233#define TUPDATE_RXCOUNTER 1002234 2235#define REG_UN_used_register 0x01bf2236 2237/* WOL bit information */2238#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)2239#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)2240#define HAL92C_WOL_DISASSOC_EVENT BIT(2)2241#define HAL92C_WOL_DEAUTH_EVENT BIT(3)2242#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)2243 2244#define WOL_REASON_PTK_UPDATE BIT(0)2245#define WOL_REASON_GTK_UPDATE BIT(1)2246#define WOL_REASON_DISASSOC BIT(2)2247#define WOL_REASON_DEAUTH BIT(3)2248#define WOL_REASON_FW_DISCONNECT BIT(4)2249#endif2250