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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2013 Realtek Corporation.*/3 4#ifndef __RTL92CE_TRX_H__5#define __RTL92CE_TRX_H__6 7#define TX_DESC_SIZE 648#define TX_DESC_AGGR_SUBFRAME_SIZE 329 10#define RX_DESC_SIZE 3211#define RX_DRV_INFO_SIZE_UNIT 812 13#define TX_DESC_NEXT_DESC_OFFSET 4014#define USB_HWDESC_HEADER_LEN 3215#define CRCLENGTH 416 17static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val)18{19 le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));20}21 22static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val)23{24 le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));25}26 27static inline void set_tx_desc_bmc(__le32 *__pdesc, u32 __val)28{29 le32p_replace_bits(__pdesc, __val, BIT(24));30}31 32static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val)33{34 le32p_replace_bits(__pdesc, __val, BIT(25));35}36 37static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val)38{39 le32p_replace_bits(__pdesc, __val, BIT(26));40}41 42static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val)43{44 le32p_replace_bits(__pdesc, __val, BIT(27));45}46 47static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val)48{49 le32p_replace_bits(__pdesc, __val, BIT(28));50}51 52static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val)53{54 le32p_replace_bits(__pdesc, __val, BIT(31));55}56 57static inline int get_tx_desc_own(__le32 *__pdesc)58{59 return le32_get_bits(*(__pdesc), BIT(31));60}61 62static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val)63{64 le32p_replace_bits(__pdesc + 1, __val, GENMASK(5, 0));65}66 67static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val)68{69 le32p_replace_bits(__pdesc + 1, __val, GENMASK(12, 8));70}71 72static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val)73{74 le32p_replace_bits(__pdesc + 1, __val, GENMASK(19, 16));75}76 77static inline void set_tx_desc_nav_use_hdr(__le32 *__pdesc, u32 __val)78{79 le32p_replace_bits(__pdesc + 1, __val, BIT(20));80}81 82static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val)83{84 le32p_replace_bits(__pdesc + 1, __val, GENMASK(23, 22));85}86 87static inline void set_tx_desc_pkt_offset(__le32 *__pdesc, u32 __val)88{89 le32p_replace_bits(__pdesc + 1, __val, GENMASK(30, 26));90}91 92static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val)93{94 le32p_replace_bits(__pdesc + 2, __val, BIT(12));95}96 97static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val)98{99 le32p_replace_bits(__pdesc + 2, __val, BIT(13));100}101 102static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val)103{104 le32p_replace_bits(__pdesc + 2, __val, BIT(17));105}106 107static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val)108{109 le32p_replace_bits(__pdesc + 2, __val, GENMASK(22, 20));110}111 112static inline void set_tx_desc_antsel_a(__le32 *__pdesc, u32 __val)113{114 le32p_replace_bits(__pdesc + 2, __val, BIT(24));115}116 117static inline void set_tx_desc_antsel_b(__le32 *__pdesc, u32 __val)118{119 le32p_replace_bits(__pdesc + 2, __val, BIT(25));120}121 122static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val)123{124 le32p_replace_bits(__pdesc + 3, __val, GENMASK(27, 16));125}126 127static inline void set_tx_desc_hwseq_en(__le32 *__pdesc, u32 __val)128{129 le32p_replace_bits(__pdesc + 3, __val, BIT(31));130}131 132static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val)133{134 le32p_replace_bits(__pdesc + 4, __val, GENMASK(4, 0));135}136 137static inline void set_tx_desc_qos(__le32 *__pdesc, u32 __val)138{139 le32p_replace_bits(__pdesc + 4, __val, BIT(6));140}141 142static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val)143{144 le32p_replace_bits(__pdesc + 4, __val, BIT(8));145}146 147static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val)148{149 le32p_replace_bits(__pdesc + 4, __val, BIT(10));150}151 152static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val)153{154 le32p_replace_bits(__pdesc + 4, __val, BIT(11));155}156 157static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val)158{159 le32p_replace_bits(__pdesc + 4, __val, BIT(12));160}161 162static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val)163{164 le32p_replace_bits(__pdesc + 4, __val, BIT(13));165}166 167static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val)168{169 le32p_replace_bits(__pdesc + 4, __val, GENMASK(21, 20));170}171 172static inline void set_tx_desc_tx_stbc(__le32 *__pdesc, u32 __val)173{174 le32p_replace_bits(__pdesc + 4, __val, GENMASK(23, 22));175}176 177static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val)178{179 le32p_replace_bits(__pdesc + 4, __val, BIT(25));180}181 182static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val)183{184 le32p_replace_bits(__pdesc + 4, __val, BIT(26));185}186 187static inline void set_tx_desc_rts_bw(__le32 *__pdesc, u32 __val)188{189 le32p_replace_bits(__pdesc + 4, __val, BIT(27));190}191 192static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val)193{194 le32p_replace_bits(__pdesc + 4, __val, GENMASK(29, 28));195}196 197static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val)198{199 le32p_replace_bits(__pdesc + 4, __val, GENMASK(31, 30));200}201 202static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)203{204 le32p_replace_bits(__pdesc + 5, __val, GENMASK(5, 0));205}206 207static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val)208{209 le32p_replace_bits(__pdesc + 5, __val, BIT(6));210}211 212static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val)213{214 le32p_replace_bits(__pdesc + 5, __val, GENMASK(12, 8));215}216 217static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val)218{219 le32p_replace_bits(__pdesc + 5, __val, GENMASK(16, 13));220}221 222static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val)223{224 le32p_replace_bits(__pdesc + 6, __val, GENMASK(15, 11));225}226 227static inline void set_tx_desc_antsel_c(__le32 *__pdesc, u32 __val)228{229 le32p_replace_bits(__pdesc + 7, __val, BIT(29));230}231 232static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val)233{234 le32p_replace_bits(__pdesc + 7, __val, GENMASK(15, 0));235}236 237static inline int get_tx_desc_tx_buffer_size(__le32 *__pdesc)238{239 return le32_get_bits(*(__pdesc + 7), GENMASK(15, 0));240}241 242static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val)243{244 *(__pdesc + 8) = cpu_to_le32(__val);245}246 247static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc)248{249 return le32_to_cpu(*(__pdesc + 8));250}251 252static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val)253{254 *(__pdesc + 10) = cpu_to_le32(__val);255}256 257static inline int get_rx_desc_pkt_len(__le32 *__pdesc)258{259 return le32_get_bits(*(__pdesc), GENMASK(13, 0));260}261 262static inline int get_rx_desc_crc32(__le32 *__pdesc)263{264 return le32_get_bits(*(__pdesc), BIT(14));265}266 267static inline int get_rx_desc_icv(__le32 *__pdesc)268{269 return le32_get_bits(*(__pdesc), BIT(15));270}271 272static inline int get_rx_desc_drv_info_size(__le32 *__pdesc)273{274 return le32_get_bits(*(__pdesc), GENMASK(19, 16));275}276 277static inline int get_rx_desc_security(__le32 *__pdesc)278{279 return le32_get_bits(*(__pdesc), GENMASK(22, 20));280}281 282static inline int get_rx_desc_qos(__le32 *__pdesc)283{284 return le32_get_bits(*(__pdesc), BIT(23));285}286 287static inline int get_rx_desc_shift(__le32 *__pdesc)288{289 return le32_get_bits(*(__pdesc), GENMASK(25, 24));290}291 292static inline int get_rx_desc_physt(__le32 *__pdesc)293{294 return le32_get_bits(*(__pdesc), BIT(26));295}296 297static inline int get_rx_desc_swdec(__le32 *__pdesc)298{299 return le32_get_bits(*(__pdesc), BIT(27));300}301 302static inline int get_rx_desc_ls(__le32 *__pdesc)303{304 return le32_get_bits(*(__pdesc), BIT(28));305}306 307static inline int get_rx_desc_fs(__le32 *__pdesc)308{309 return le32_get_bits(*(__pdesc), BIT(29));310}311 312static inline int get_rx_desc_eor(__le32 *__pdesc)313{314 return le32_get_bits(*(__pdesc), BIT(30));315}316 317static inline int get_rx_desc_own(__le32 *__pdesc)318{319 return le32_get_bits(*(__pdesc), BIT(31));320}321 322static inline void set_rx_desc_pkt_len(__le32 *__pdesc, u32 __val)323{324 le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));325}326 327static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val)328{329 le32p_replace_bits(__pdesc, __val, BIT(30));330}331 332static inline void set_rx_desc_own(__le32 *__pdesc, u32 __val)333{334 le32p_replace_bits(__pdesc, __val, BIT(31));335}336 337static inline int get_rx_desc_macid(__le32 *__pdesc)338{339 return le32_get_bits(*(__pdesc + 1), GENMASK(5, 0));340}341 342static inline int get_rx_desc_paggr(__le32 *__pdesc)343{344 return le32_get_bits(*(__pdesc + 1), BIT(14));345}346 347static inline int get_rx_desc_faggr(__le32 *__pdesc)348{349 return le32_get_bits(*(__pdesc + 1), BIT(15));350}351 352static inline int get_rx_desc_a1_fit(__le32 *__pdesc)353{354 return le32_get_bits(*(__pdesc + 1), GENMASK(19, 16));355}356 357static inline int get_rx_desc_a2_fit(__le32 *__pdesc)358{359 return le32_get_bits(*(__pdesc + 1), GENMASK(23, 20));360}361 362static inline int get_rx_desc_pam(__le32 *__pdesc)363{364 return le32_get_bits(*(__pdesc + 1), BIT(24));365}366 367static inline int get_rx_desc_pwr(__le32 *__pdesc)368{369 return le32_get_bits(*(__pdesc + 1), BIT(25));370}371 372static inline int get_rx_desc_md(__le32 *__pdesc)373{374 return le32_get_bits(*(__pdesc + 1), BIT(26));375}376 377static inline int get_rx_desc_mf(__le32 *__pdesc)378{379 return le32_get_bits(*(__pdesc + 1), BIT(27));380}381 382static inline int get_rx_desc_type(__le32 *__pdesc)383{384 return le32_get_bits(*(__pdesc + 1), GENMASK(29, 28));385}386 387static inline int get_rx_desc_mc(__le32 *__pdesc)388{389 return le32_get_bits(*(__pdesc + 1), BIT(30));390}391 392static inline int get_rx_desc_bc(__le32 *__pdesc)393{394 return le32_get_bits(*(__pdesc + 1), BIT(31));395}396 397static inline int get_rx_desc_seq(__le32 *__pdesc)398{399 return le32_get_bits(*(__pdesc + 2), GENMASK(11, 0));400}401 402static inline int get_rx_desc_frag(__le32 *__pdesc)403{404 return le32_get_bits(*(__pdesc + 2), GENMASK(15, 12));405}406 407static inline int get_rx_desc_rxmcs(__le32 *__pdesc)408{409 return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));410}411 412static inline int get_rx_desc_rxht(__le32 *__pdesc)413{414 return le32_get_bits(*(__pdesc + 3), BIT(6));415}416 417static inline int get_rx_status_desc_rx_gf(__le32 *__pdesc)418{419 return le32_get_bits(*(__pdesc + 3), BIT(7));420}421 422static inline int get_rx_desc_splcp(__le32 *__pdesc)423{424 return le32_get_bits(*(__pdesc + 3), BIT(8));425}426 427static inline int get_rx_desc_bw(__le32 *__pdesc)428{429 return le32_get_bits(*(__pdesc + 3), BIT(9));430}431 432static inline int get_rx_desc_htc(__le32 *__pdesc)433{434 return le32_get_bits(*(__pdesc + 3), BIT(10));435}436 437static inline int get_rx_status_desc_eosp(__le32 *__pdesc)438{439 return le32_get_bits(*(__pdesc + 3), BIT(11));440}441 442static inline int get_rx_status_desc_bssid_fit(__le32 *__pdesc)443{444 return le32_get_bits(*(__pdesc + 3), GENMASK(13, 12));445}446 447static inline int get_rx_status_desc_rpt_sel(__le32 *__pdesc)448{449 return le32_get_bits(*(__pdesc + 3), GENMASK(15, 14));450}451 452static inline int get_rx_status_desc_pattern_match(__le32 *__pdesc)453{454 return le32_get_bits(*(__pdesc + 3), BIT(29));455}456 457static inline int get_rx_status_desc_unicast_match(__le32 *__pdesc)458{459 return le32_get_bits(*(__pdesc + 3), BIT(30));460}461 462static inline int get_rx_status_desc_magic_match(__le32 *__pdesc)463{464 return le32_get_bits(*(__pdesc + 3), BIT(31));465}466 467static inline u32 get_rx_desc_iv1(__le32 *__pdesc)468{469 return le32_to_cpu(*(__pdesc + 4));470}471 472static inline u32 get_rx_desc_tsfl(__le32 *__pdesc)473{474 return le32_to_cpu(*(__pdesc + 5));475}476 477static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc)478{479 return le32_to_cpu(*(__pdesc + 6));480}481 482static inline u32 get_rx_desc_buff_addr64(__le32 *__pdesc)483{484 return le32_to_cpu(*(__pdesc + 7));485}486 487static inline void set_rx_desc_buff_addr(__le32 *__pdesc, u32 __val)488{489 *(__pdesc + 6) = cpu_to_le32(__val);490}491 492static inline void set_rx_desc_buff_addr64(__le32 *__pdesc, u32 __val)493{494 *(__pdesc + 7) = cpu_to_le32(__val);495}496 497/* TX report 2 format in Rx desc*/498 499static inline int get_rx_rpt2_desc_pkt_len(__le32 *__status)500{501 return le32_get_bits(*(__status), GENMASK(8, 0));502}503 504static inline u32 get_rx_rpt2_desc_macid_valid_1(__le32 *__status)505{506 return le32_to_cpu(*(__status + 4));507}508 509static inline u32 get_rx_rpt2_desc_macid_valid_2(__le32 *__status)510{511 return le32_to_cpu(*(__status + 5));512}513 514static inline void set_earlymode_pktnum(__le32 *__paddr, u32 __value)515{516 le32p_replace_bits(__paddr, __value, GENMASK(3, 0));517}518 519static inline void set_earlymode_len0(__le32 *__paddr, u32 __value)520{521 le32p_replace_bits(__paddr, __value, GENMASK(15, 4));522}523 524static inline void set_earlymode_len1(__le32 *__paddr, u32 __value)525{526 le32p_replace_bits(__paddr, __value, GENMASK(27, 16));527}528 529static inline void set_earlymode_len2_1(__le32 *__paddr, u32 __value)530{531 le32p_replace_bits(__paddr, __value, GENMASK(31, 28));532}533 534static inline void set_earlymode_len2_2(__le32 *__paddr, u32 __value)535{536 le32p_replace_bits(__paddr + 1, __value, GENMASK(7, 0));537}538 539static inline void set_earlymode_len3(__le32 *__paddr, u32 __value)540{541 le32p_replace_bits(__paddr + 1, __value, GENMASK(19, 8));542}543 544static inline void set_earlymode_len4(__le32 *__paddr, u32 __value)545{546 le32p_replace_bits(__paddr + 1, __value, GENMASK(31, 20));547}548 549static inline void clear_pci_tx_desc_content(__le32 *__pdesc, int _size)550{551 if (_size > TX_DESC_NEXT_DESC_OFFSET)552 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);553 else554 memset(__pdesc, 0, _size);555}556 557#define RTL8188_RX_HAL_IS_CCK_RATE(rxmcs)\558 (rxmcs == DESC92C_RATE1M ||\559 rxmcs == DESC92C_RATE2M ||\560 rxmcs == DESC92C_RATE5_5M ||\561 rxmcs == DESC92C_RATE11M)562 563struct phy_status_rpt {564 u8 padding[2];565 u8 ch_corr[2];566 u8 cck_sig_qual_ofdm_pwdb_all;567 u8 cck_agc_rpt_ofdm_cfosho_a;568 u8 cck_rpt_b_ofdm_cfosho_b;569 u8 rsvd_1;/* ch_corr_msb; */570 u8 noise_power_db_msb;571 u8 path_cfotail[2];572 u8 pcts_mask[2];573 u8 stream_rxevm[2];574 u8 path_rxsnr[2];575 u8 noise_power_db_lsb;576 u8 rsvd_2[3];577 u8 stream_csi[2];578 u8 stream_target_csi[2];579 u8 sig_evm;580 u8 rsvd_3;581#if defined(__LITTLE_ENDIAN)582 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/583 u8 sgi_en:1;584 u8 rxsc:2;585 u8 idle_long:1;586 u8 r_ant_train_en:1;587 u8 ant_sel_b:1;588 u8 ant_sel:1;589#else /* __BIG_ENDIAN */590 u8 ant_sel:1;591 u8 ant_sel_b:1;592 u8 r_ant_train_en:1;593 u8 idle_long:1;594 u8 rxsc:2;595 u8 sgi_en:1;596 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/597#endif598} __packed;599 600struct rx_fwinfo_88e {601 u8 gain_trsw[4];602 u8 pwdb_all;603 u8 cfosho[4];604 u8 cfotail[4];605 s8 rxevm[2];606 s8 rxsnr[4];607 u8 pdsnr[2];608 u8 csi_current[2];609 u8 csi_target[2];610 u8 sigevm;611 u8 max_ex_pwr;612 u8 ex_intf_flag:1;613 u8 sgi_en:1;614 u8 rxsc:2;615 u8 reserve:4;616} __packed;617 618struct tx_desc_88e {619 u32 pktsize:16;620 u32 offset:8;621 u32 bmc:1;622 u32 htc:1;623 u32 lastseg:1;624 u32 firstseg:1;625 u32 linip:1;626 u32 noacm:1;627 u32 gf:1;628 u32 own:1;629 630 u32 macid:6;631 u32 rsvd0:2;632 u32 queuesel:5;633 u32 rd_nav_ext:1;634 u32 lsig_txop_en:1;635 u32 pifs:1;636 u32 rateid:4;637 u32 nav_usehdr:1;638 u32 en_descid:1;639 u32 sectype:2;640 u32 pktoffset:8;641 642 u32 rts_rc:6;643 u32 data_rc:6;644 u32 agg_en:1;645 u32 rdg_en:1;646 u32 bar_retryht:2;647 u32 agg_break:1;648 u32 morefrag:1;649 u32 raw:1;650 u32 ccx:1;651 u32 ampdudensity:3;652 u32 bt_int:1;653 u32 ant_sela:1;654 u32 ant_selb:1;655 u32 txant_cck:2;656 u32 txant_l:2;657 u32 txant_ht:2;658 659 u32 nextheadpage:8;660 u32 tailpage:8;661 u32 seq:12;662 u32 cpu_handle:1;663 u32 tag1:1;664 u32 trigger_int:1;665 u32 hwseq_en:1;666 667 u32 rtsrate:5;668 u32 apdcfe:1;669 u32 qos:1;670 u32 hwseq_ssn:1;671 u32 userrate:1;672 u32 dis_rtsfb:1;673 u32 dis_datafb:1;674 u32 cts2self:1;675 u32 rts_en:1;676 u32 hwrts_en:1;677 u32 portid:1;678 u32 pwr_status:3;679 u32 waitdcts:1;680 u32 cts2ap_en:1;681 u32 txsc:2;682 u32 stbc:2;683 u32 txshort:1;684 u32 txbw:1;685 u32 rtsshort:1;686 u32 rtsbw:1;687 u32 rtssc:2;688 u32 rtsstbc:2;689 690 u32 txrate:6;691 u32 shortgi:1;692 u32 ccxt:1;693 u32 txrate_fb_lmt:5;694 u32 rtsrate_fb_lmt:4;695 u32 retrylmt_en:1;696 u32 txretrylmt:6;697 u32 usb_txaggnum:8;698 699 u32 txagca:5;700 u32 txagcb:5;701 u32 usemaxlen:1;702 u32 maxaggnum:5;703 u32 mcsg1maxlen:4;704 u32 mcsg2maxlen:4;705 u32 mcsg3maxlen:4;706 u32 mcs7sgimaxlen:4;707 708 u32 txbuffersize:16;709 u32 sw_offset30:8;710 u32 sw_offset31:4;711 u32 rsvd1:1;712 u32 antsel_c:1;713 u32 null_0:1;714 u32 null_1:1;715 716 u32 txbuffaddr;717 u32 txbufferaddr64;718 u32 nextdescaddress;719 u32 nextdescaddress64;720 721 u32 reserve_pass_pcie_mm_limit[4];722} __packed;723 724struct rx_desc_88e {725 u32 length:14;726 u32 crc32:1;727 u32 icverror:1;728 u32 drv_infosize:4;729 u32 security:3;730 u32 qos:1;731 u32 shift:2;732 u32 phystatus:1;733 u32 swdec:1;734 u32 lastseg:1;735 u32 firstseg:1;736 u32 eor:1;737 u32 own:1;738 739 u32 macid:6;740 u32 tid:4;741 u32 hwrsvd:5;742 u32 paggr:1;743 u32 faggr:1;744 u32 a1_fit:4;745 u32 a2_fit:4;746 u32 pam:1;747 u32 pwr:1;748 u32 moredata:1;749 u32 morefrag:1;750 u32 type:2;751 u32 mc:1;752 u32 bc:1;753 754 u32 seq:12;755 u32 frag:4;756 u32 nextpktlen:14;757 u32 nextind:1;758 u32 rsvd:1;759 760 u32 rxmcs:6;761 u32 rxht:1;762 u32 amsdu:1;763 u32 splcp:1;764 u32 bandwidth:1;765 u32 htc:1;766 u32 tcpchk_rpt:1;767 u32 ipcchk_rpt:1;768 u32 tcpchk_valid:1;769 u32 hwpcerr:1;770 u32 hwpcind:1;771 u32 iv0:16;772 773 u32 iv1;774 775 u32 tsfl;776 777 u32 bufferaddress;778 u32 bufferaddress64;779 780} __packed;781 782void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,783 struct ieee80211_hdr *hdr, u8 *pdesc_tx,784 u8 *txbd, struct ieee80211_tx_info *info,785 struct ieee80211_sta *sta,786 struct sk_buff *skb,787 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);788bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,789 struct rtl_stats *status,790 struct ieee80211_rx_status *rx_status,791 u8 *pdesc, struct sk_buff *skb);792void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,793 bool istx, u8 desc_name, u8 *val);794u64 rtl88ee_get_desc(struct ieee80211_hw *hw,795 u8 *pdesc, bool istx, u8 desc_name);796bool rtl88ee_is_tx_desc_closed(struct ieee80211_hw *hw,797 u8 hw_queue, u16 index);798void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);799void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,800 struct sk_buff *skb);801#endif802