2031 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#ifndef __RTL92C_REG_H__5#define __RTL92C_REG_H__6 7#define REG_SYS_ISO_CTRL 0x00008#define REG_SYS_FUNC_EN 0x00029#define REG_APS_FSMCO 0x000410#define REG_SYS_CLKR 0x000811#define REG_9346CR 0x000A12#define REG_EE_VPD 0x000C13#define REG_AFE_MISC 0x001014#define REG_SPS0_CTRL 0x001115#define REG_SPS_OCP_CFG 0x001816#define REG_RSV_CTRL 0x001C17#define REG_RF_CTRL 0x001F18#define REG_LDOA15_CTRL 0x002019#define REG_LDOV12D_CTRL 0x002120#define REG_LDOHCI12_CTRL 0x002221#define REG_LPLDO_CTRL 0x002322#define REG_AFE_XTAL_CTRL 0x002423#define REG_AFE_PLL_CTRL 0x002824#define REG_EFUSE_CTRL 0x003025#define REG_EFUSE_TEST 0x003426#define REG_PWR_DATA 0x003827#define REG_CAL_TIMER 0x003C28#define REG_ACLK_MON 0x003E29#define REG_GPIO_MUXCFG 0x004030#define REG_GPIO_IO_SEL 0x004231#define REG_MAC_PINMUX_CFG 0x004332#define REG_GPIO_PIN_CTRL 0x004433#define REG_GPIO_INTM 0x004834#define REG_LEDCFG0 0x004C35#define REG_LEDCFG1 0x004D36#define REG_LEDCFG2 0x004E37#define REG_LEDCFG3 0x004F38#define REG_FSIMR 0x005039#define REG_FSISR 0x005440#define REG_HSIMR 0x005841#define REG_HSISR 0x005c42 43/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */44#define REG_GPIO_PIN_CTRL_2 0x006045/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */46#define REG_GPIO_IO_SEL_2 0x006247/* RTL8723 WIFI/BT/GPS Multi-Function control source. */48#define REG_MULTI_FUNC_CTRL 0x006849 50#define REG_MCUFWDL 0x008051 52#define REG_HMEBOX_EXT_0 0x008853#define REG_HMEBOX_EXT_1 0x008A54#define REG_HMEBOX_EXT_2 0x008C55#define REG_HMEBOX_EXT_3 0x008E56 57#define REG_BIST_SCAN 0x00D058#define REG_BIST_RPT 0x00D459#define REG_BIST_ROM_RPT 0x00D860#define REG_USB_SIE_INTF 0x00E061#define REG_PCIE_MIO_INTF 0x00E462#define REG_PCIE_MIO_INTD 0x00E863#define REG_HPON_FSM 0x00EC64#define REG_SYS_CFG 0x00F065#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/66 67#define REG_CR 0x010068#define REG_PBP 0x010469#define REG_TRXDMA_CTRL 0x010C70#define REG_TRXFF_BNDY 0x011471#define REG_TRXFF_STATUS 0x011872#define REG_RXFF_PTR 0x011C73#define REG_HIMR 0x012074#define REG_HISR 0x012475#define REG_HIMRE 0x012876#define REG_HISRE 0x012C77#define REG_CPWM 0x012F78#define REG_FWIMR 0x013079#define REG_FWISR 0x013480#define REG_PKTBUF_DBG_CTRL 0x014081#define REG_PKTBUF_DBG_DATA_L 0x014482#define REG_PKTBUF_DBG_DATA_H 0x014883 84#define REG_TC0_CTRL 0x015085#define REG_TC1_CTRL 0x015486#define REG_TC2_CTRL 0x015887#define REG_TC3_CTRL 0x015C88#define REG_TC4_CTRL 0x016089#define REG_TCUNIT_BASE 0x016490#define REG_MBIST_START 0x017491#define REG_MBIST_DONE 0x017892#define REG_MBIST_FAIL 0x017C93#define REG_C2HEVT_MSG_NORMAL 0x01A094#define REG_C2HEVT_MSG_TEST 0x01B895#define REG_C2HEVT_CLEAR 0x01BF96#define REG_MCUTST_1 0x01c097#define REG_FMETHR 0x01C898#define REG_HMETFR 0x01CC99#define REG_HMEBOX_0 0x01D0100#define REG_HMEBOX_1 0x01D4101#define REG_HMEBOX_2 0x01D8102#define REG_HMEBOX_3 0x01DC103 104#define REG_LLT_INIT 0x01E0105#define REG_BB_ACCEESS_CTRL 0x01E8106#define REG_BB_ACCESS_DATA 0x01EC107 108#define REG_RQPN 0x0200109#define REG_FIFOPAGE 0x0204110#define REG_TDECTRL 0x0208111#define REG_TXDMA_OFFSET_CHK 0x020C112#define REG_TXDMA_STATUS 0x0210113#define REG_RQPN_NPQ 0x0214114 115#define REG_RXDMA_AGG_PG_TH 0x0280116#define REG_RXPKT_NUM 0x0284117#define REG_RXDMA_STATUS 0x0288118 119#define REG_PCIE_CTRL_REG 0x0300120#define REG_INT_MIG 0x0304121#define REG_BCNQ_DESA 0x0308122#define REG_HQ_DESA 0x0310123#define REG_MGQ_DESA 0x0318124#define REG_VOQ_DESA 0x0320125#define REG_VIQ_DESA 0x0328126#define REG_BEQ_DESA 0x0330127#define REG_BKQ_DESA 0x0338128#define REG_RX_DESA 0x0340129#define REG_DBI 0x0348130#define REG_MDIO 0x0354131#define REG_DBG_SEL 0x0360132#define REG_PCIE_HRPWM 0x0361133#define REG_PCIE_HCPWM 0x0363134#define REG_UART_CTRL 0x0364135#define REG_UART_TX_DESA 0x0370136#define REG_UART_RX_DESA 0x0378137 138#define REG_HDAQ_DESA_NODEF 0x0000139#define REG_CMDQ_DESA_NODEF 0x0000140 141#define REG_VOQ_INFORMATION 0x0400142#define REG_VIQ_INFORMATION 0x0404143#define REG_BEQ_INFORMATION 0x0408144#define REG_BKQ_INFORMATION 0x040C145#define REG_MGQ_INFORMATION 0x0410146#define REG_HGQ_INFORMATION 0x0414147#define REG_BCNQ_INFORMATION 0x0418148 149#define REG_CPU_MGQ_INFORMATION 0x041C150#define REG_FWHW_TXQ_CTRL 0x0420151#define REG_HWSEQ_CTRL 0x0423152#define REG_TXPKTBUF_BCNQ_BDNY 0x0424153#define REG_TXPKTBUF_MGQ_BDNY 0x0425154#define REG_MULTI_BCNQ_EN 0x0426155#define REG_MULTI_BCNQ_OFFSET 0x0427156#define REG_SPEC_SIFS 0x0428157#define REG_RL 0x042A158#define REG_DARFRC 0x0430159#define REG_RARFRC 0x0438160#define REG_RRSR 0x0440161#define REG_ARFR0 0x0444162#define REG_ARFR1 0x0448163#define REG_ARFR2 0x044C164#define REG_ARFR3 0x0450165#define REG_AGGLEN_LMT 0x0458166#define REG_AMPDU_MIN_SPACE 0x045C167#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D168#define REG_FAST_EDCA_CTRL 0x0460169#define REG_RD_RESP_PKT_TH 0x0463170#define REG_INIRTS_RATE_SEL 0x0480171#define REG_INIDATA_RATE_SEL 0x0484172#define REG_POWER_STATUS 0x04A4173#define REG_POWER_STAGE1 0x04B4174#define REG_POWER_STAGE2 0x04B8175#define REG_PKT_LIFE_TIME 0x04C0176#define REG_STBC_SETTING 0x04C4177#define REG_PROT_MODE_CTRL 0x04C8178#define REG_BAR_MODE_CTRL 0x04CC179#define REG_RA_TRY_RATE_AGG_LMT 0x04CF180#define REG_NQOS_SEQ 0x04DC181#define REG_QOS_SEQ 0x04DE182#define REG_NEED_CPU_HANDLE 0x04E0183#define REG_PKT_LOSE_RPT 0x04E1184#define REG_PTCL_ERR_STATUS 0x04E2185#define REG_DUMMY 0x04FC186 187#define REG_EDCA_VO_PARAM 0x0500188#define REG_EDCA_VI_PARAM 0x0504189#define REG_EDCA_BE_PARAM 0x0508190#define REG_EDCA_BK_PARAM 0x050C191#define REG_BCNTCFG 0x0510192#define REG_PIFS 0x0512193#define REG_RDG_PIFS 0x0513194#define REG_SIFS_CTX 0x0514195#define REG_SIFS_TRX 0x0516196#define REG_SIFS_CCK 0x0514197#define REG_SIFS_OFDM 0x0516198#define REG_AGGR_BREAK_TIME 0x051A199#define REG_SLOT 0x051B200#define REG_TX_PTCL_CTRL 0x0520201#define REG_TXPAUSE 0x0522202#define REG_DIS_TXREQ_CLR 0x0523203#define REG_RD_CTRL 0x0524204#define REG_TBTT_PROHIBIT 0x0540205#define REG_RD_NAV_NXT 0x0544206#define REG_NAV_PROT_LEN 0x0546207#define REG_BCN_CTRL 0x0550208#define REG_MBID_NUM 0x0552209#define REG_DUAL_TSF_RST 0x0553210#define REG_BCN_INTERVAL 0x0554211#define REG_MBSSID_BCN_SPACE 0x0554212#define REG_DRVERLYINT 0x0558213#define REG_BCNDMATIM 0x0559214#define REG_ATIMWND 0x055A215#define REG_USTIME_TSF 0x055C216#define REG_BCN_MAX_ERR 0x055D217#define REG_RXTSF_OFFSET_CCK 0x055E218#define REG_RXTSF_OFFSET_OFDM 0x055F219#define REG_TSFTR 0x0560220#define REG_INIT_TSFTR 0x0564221#define REG_PSTIMER 0x0580222#define REG_TIMER0 0x0584223#define REG_TIMER1 0x0588224#define REG_ACMHWCTRL 0x05C0225#define REG_ACMRSTCTRL 0x05C1226#define REG_ACMAVG 0x05C2227#define REG_VO_ADMTIME 0x05C4228#define REG_VI_ADMTIME 0x05C6229#define REG_BE_ADMTIME 0x05C8230#define REG_EDCA_RANDOM_GEN 0x05CC231#define REG_SCH_TXCMD 0x05D0232 233#define REG_APSD_CTRL 0x0600234#define REG_BWOPMODE 0x0603235#define REG_TCR 0x0604236#define REG_RCR 0x0608237#define REG_RX_PKT_LIMIT 0x060C238#define REG_RX_DLK_TIME 0x060D239#define REG_RX_DRVINFO_SZ 0x060F240 241#define REG_MACID 0x0610242#define REG_BSSID 0x0618243#define REG_MAR 0x0620244#define REG_MBIDCAMCFG 0x0628245 246#define REG_USTIME_EDCA 0x0638247#define REG_MAC_SPEC_SIFS 0x063A248#define REG_RESP_SIFS_CCK 0x063C249#define REG_RESP_SIFS_OFDM 0x063E250/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */251#define REG_R2T_SIFS 0x063C252/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */253#define REG_T2T_SIFS 0x063E254#define REG_ACKTO 0x0640255#define REG_CTS2TO 0x0641256#define REG_EIFS 0x0642257 258#define REG_NAV_CTRL 0x0650259#define REG_BACAMCMD 0x0654260#define REG_BACAMCONTENT 0x0658261#define REG_LBDLY 0x0660262#define REG_FWDLY 0x0661263#define REG_RXERR_RPT 0x0664264#define REG_WMAC_TRXPTCL_CTL 0x0668265 266#define REG_CAMCMD 0x0670267#define REG_CAMWRITE 0x0674268#define REG_CAMREAD 0x0678269#define REG_CAMDBG 0x067C270#define REG_SECCFG 0x0680271 272#define REG_WOW_CTRL 0x0690273#define REG_PSSTATUS 0x0691274#define REG_PS_RX_INFO 0x0692275#define REG_LPNAV_CTRL 0x0694276#define REG_WKFMCAM_CMD 0x0698277#define REG_WKFMCAM_RWD 0x069C278#define REG_RXFLTMAP0 0x06A0279#define REG_RXFLTMAP1 0x06A2280#define REG_RXFLTMAP2 0x06A4281#define REG_BCN_PSR_RPT 0x06A8282#define REG_CALB32K_CTRL 0x06AC283#define REG_PKT_MON_CTRL 0x06B4284#define REG_BT_COEX_TABLE 0x06C0285#define REG_WMAC_RESP_TXINFO 0x06D8286 287#define REG_USB_INFO 0xFE17288#define REG_USB_SPECIAL_OPTION 0xFE55289#define REG_USB_DMA_AGG_TO 0xFE5B290#define REG_USB_AGG_TO 0xFE5C291#define REG_USB_AGG_TH 0xFE5D292 293#define REG_TEST_USB_TXQS 0xFE48294#define REG_TEST_SIE_VID 0xFE60295#define REG_TEST_SIE_PID 0xFE62296#define REG_TEST_SIE_OPTIONAL 0xFE64297#define REG_TEST_SIE_CHIRP_K 0xFE65298#define REG_TEST_SIE_PHY 0xFE66299#define REG_TEST_SIE_MAC_ADDR 0xFE70300#define REG_TEST_SIE_STRING 0xFE80301 302#define REG_NORMAL_SIE_VID 0xFE60303#define REG_NORMAL_SIE_PID 0xFE62304#define REG_NORMAL_SIE_OPTIONAL 0xFE64305#define REG_NORMAL_SIE_EP 0xFE65306#define REG_NORMAL_SIE_PHY 0xFE68307#define REG_NORMAL_SIE_MAC_ADDR 0xFE70308#define REG_NORMAL_SIE_STRING 0xFE80309 310#define CR9346 REG_9346CR311#define MSR (REG_CR + 2)312#define ISR REG_HISR313#define TSFR REG_TSFTR314 315#define MACIDR0 REG_MACID316#define MACIDR4 (REG_MACID + 4)317 318#define PBP REG_PBP319 320#define IDR0 MACIDR0321#define IDR4 MACIDR4322 323#define UNUSED_REGISTER 0x1BF324#define DCAM UNUSED_REGISTER325#define PSR UNUSED_REGISTER326#define BBADDR UNUSED_REGISTER327#define PHYDATAR UNUSED_REGISTER328 329#define INVALID_BBRF_VALUE 0x12345678330 331#define MAX_MSS_DENSITY_2T 0x13332#define MAX_MSS_DENSITY_1T 0x0A333 334#define CMDEEPROM_EN BIT(5)335#define CMDEEPROM_SEL BIT(4)336#define CMD9346CR_9356SEL BIT(4)337#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)338#define AUTOLOAD_EFUSE CMDEEPROM_EN339 340#define GPIOSEL_GPIO 0341#define GPIOSEL_ENBT BIT(5)342 343#define GPIO_IN REG_GPIO_PIN_CTRL344#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)345#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)346#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)347 348#define MSR_NOLINK 0x00349#define MSR_ADHOC 0x01350#define MSR_INFRA 0x02351#define MSR_AP 0x03352#define MSR_MASK 0x03353 354#define RRSR_RSC_OFFSET 21355#define RRSR_SHORT_OFFSET 23356#define RRSR_RSC_BW_40M 0x600000357#define RRSR_RSC_UPSUBCHNL 0x400000358#define RRSR_RSC_LOWSUBCHNL 0x200000359#define RRSR_SHORT 0x800000360#define RRSR_1M BIT(0)361#define RRSR_2M BIT(1)362#define RRSR_5_5M BIT(2)363#define RRSR_11M BIT(3)364#define RRSR_6M BIT(4)365#define RRSR_9M BIT(5)366#define RRSR_12M BIT(6)367#define RRSR_18M BIT(7)368#define RRSR_24M BIT(8)369#define RRSR_36M BIT(9)370#define RRSR_48M BIT(10)371#define RRSR_54M BIT(11)372#define RRSR_MCS0 BIT(12)373#define RRSR_MCS1 BIT(13)374#define RRSR_MCS2 BIT(14)375#define RRSR_MCS3 BIT(15)376#define RRSR_MCS4 BIT(16)377#define RRSR_MCS5 BIT(17)378#define RRSR_MCS6 BIT(18)379#define RRSR_MCS7 BIT(19)380#define BRSR_ACKSHORTPMB BIT(23)381 382#define RATR_1M 0x00000001383#define RATR_2M 0x00000002384#define RATR_55M 0x00000004385#define RATR_11M 0x00000008386#define RATR_6M 0x00000010387#define RATR_9M 0x00000020388#define RATR_12M 0x00000040389#define RATR_18M 0x00000080390#define RATR_24M 0x00000100391#define RATR_36M 0x00000200392#define RATR_48M 0x00000400393#define RATR_54M 0x00000800394#define RATR_MCS0 0x00001000395#define RATR_MCS1 0x00002000396#define RATR_MCS2 0x00004000397#define RATR_MCS3 0x00008000398#define RATR_MCS4 0x00010000399#define RATR_MCS5 0x00020000400#define RATR_MCS6 0x00040000401#define RATR_MCS7 0x00080000402#define RATR_MCS8 0x00100000403#define RATR_MCS9 0x00200000404#define RATR_MCS10 0x00400000405#define RATR_MCS11 0x00800000406#define RATR_MCS12 0x01000000407#define RATR_MCS13 0x02000000408#define RATR_MCS14 0x04000000409#define RATR_MCS15 0x08000000410 411#define RATE_1M BIT(0)412#define RATE_2M BIT(1)413#define RATE_5_5M BIT(2)414#define RATE_11M BIT(3)415#define RATE_6M BIT(4)416#define RATE_9M BIT(5)417#define RATE_12M BIT(6)418#define RATE_18M BIT(7)419#define RATE_24M BIT(8)420#define RATE_36M BIT(9)421#define RATE_48M BIT(10)422#define RATE_54M BIT(11)423#define RATE_MCS0 BIT(12)424#define RATE_MCS1 BIT(13)425#define RATE_MCS2 BIT(14)426#define RATE_MCS3 BIT(15)427#define RATE_MCS4 BIT(16)428#define RATE_MCS5 BIT(17)429#define RATE_MCS6 BIT(18)430#define RATE_MCS7 BIT(19)431#define RATE_MCS8 BIT(20)432#define RATE_MCS9 BIT(21)433#define RATE_MCS10 BIT(22)434#define RATE_MCS11 BIT(23)435#define RATE_MCS12 BIT(24)436#define RATE_MCS13 BIT(25)437#define RATE_MCS14 BIT(26)438#define RATE_MCS15 BIT(27)439 440#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)441#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M \442 | RATR_24M | RATR_36M | RATR_48M | RATR_54M)443#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \444 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \445 RATR_MCS6 | RATR_MCS7)446#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \447 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \448 RATR_MCS14 | RATR_MCS15)449 450#define BW_OPMODE_20MHZ BIT(2)451#define BW_OPMODE_5G BIT(1)452#define BW_OPMODE_11J BIT(0)453 454#define CAM_VALID BIT(15)455#define CAM_NOTVALID 0x0000456#define CAM_USEDK BIT(5)457 458#define CAM_NONE 0x0459#define CAM_WEP40 0x01460#define CAM_TKIP 0x02461#define CAM_AES 0x04462#define CAM_WEP104 0x05463 464#define TOTAL_CAM_ENTRY 32465#define HALF_CAM_ENTRY 16466 467#define CAM_WRITE BIT(16)468#define CAM_READ 0x00000000469#define CAM_POLLINIG BIT(31)470 471#define SCR_USEDK 0x01472#define SCR_TXSEC_ENABLE 0x02473#define SCR_RXSEC_ENABLE 0x04474 475#define WOW_PMEN BIT(0)476#define WOW_WOMEN BIT(1)477#define WOW_MAGIC BIT(2)478#define WOW_UWF BIT(3)479 480#define IMR8190_DISABLED 0x0481#define IMR_BCNDMAINT6 BIT(31)482#define IMR_BCNDMAINT5 BIT(30)483#define IMR_BCNDMAINT4 BIT(29)484#define IMR_BCNDMAINT3 BIT(28)485#define IMR_BCNDMAINT2 BIT(27)486#define IMR_BCNDMAINT1 BIT(26)487#define IMR_BCNDOK8 BIT(25)488#define IMR_BCNDOK7 BIT(24)489#define IMR_BCNDOK6 BIT(23)490#define IMR_BCNDOK5 BIT(22)491#define IMR_BCNDOK4 BIT(21)492#define IMR_BCNDOK3 BIT(20)493#define IMR_BCNDOK2 BIT(19)494#define IMR_BCNDOK1 BIT(18)495#define IMR_TIMEOUT2 BIT(17)496#define IMR_TIMEOUT1 BIT(16)497#define IMR_TXFOVW BIT(15)498#define IMR_PSTIMEOUT BIT(14)499#define IMR_BCNINT BIT(13)500#define IMR_RXFOVW BIT(12)501#define IMR_RDU BIT(11)502#define IMR_ATIMEND BIT(10)503#define IMR_BDOK BIT(9)504#define IMR_HIGHDOK BIT(8)505#define IMR_TBDOK BIT(7)506#define IMR_MGNTDOK BIT(6)507#define IMR_TBDER BIT(5)508#define IMR_BKDOK BIT(4)509#define IMR_BEDOK BIT(3)510#define IMR_VIDOK BIT(2)511#define IMR_VODOK BIT(1)512#define IMR_ROK BIT(0)513 514#define IMR_TXERR BIT(11)515#define IMR_RXERR BIT(10)516#define IMR_C2HCMD BIT(9)517#define IMR_CPWM BIT(8)518#define IMR_OCPINT BIT(1)519#define IMR_WLANOFF BIT(0)520 521#define EFUSE_REAL_CONTENT_LEN 512522#define EFUSE_OOB_PROTECT_BYTES 15523 524#define EEPROM_DEFAULT_TSSI 0x0525#define EEPROM_DEFAULT_TXPOWERDIFF 0x0526#define EEPROM_DEFAULT_CRYSTALCAP 0x5527#define EEPROM_DEFAULT_BOARDTYPE 0x02528#define EEPROM_DEFAULT_TXPOWER 0x1010529#define EEPROM_DEFAULT_HT2T_TXPWR 0x10530 531#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3532#define EEPROM_DEFAULT_THERMALMETER 0x12533#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0534#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5535#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22536#define EEPROM_DEFAULT_HT40_2SDIFF 0x0537#define EEPROM_DEFAULT_HT20_DIFF 2538#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0539#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0540 541#define RF_OPTION1 0x79542#define RF_OPTION2 0x7A543#define RF_OPTION3 0x7B544#define RF_OPTION4 0x7C545 546#define EEPROM_DEFAULT_PID 0x1234547#define EEPROM_DEFAULT_VID 0x5678548#define EEPROM_DEFAULT_CUSTOMERID 0xAB549#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD550#define EEPROM_DEFAULT_VERSION 0551 552#define EEPROM_CHANNEL_PLAN_FCC 0x0553#define EEPROM_CHANNEL_PLAN_IC 0x1554#define EEPROM_CHANNEL_PLAN_ETSI 0x2555#define EEPROM_CHANNEL_PLAN_SPAIN 0x3556#define EEPROM_CHANNEL_PLAN_FRANCE 0x4557#define EEPROM_CHANNEL_PLAN_MKK 0x5558#define EEPROM_CHANNEL_PLAN_MKK1 0x6559#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7560#define EEPROM_CHANNEL_PLAN_TELEC 0x8561#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9562#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA563#define EEPROM_CHANNEL_PLAN_NCC 0xB564#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80565 566#define EEPROM_CID_DEFAULT 0x0567#define EEPROM_CID_TOSHIBA 0x4568#define EEPROM_CID_CCX 0x10569#define EEPROM_CID_QMI 0x0D570#define EEPROM_CID_WHQL 0xFE571 572#define RTL8192_EEPROM_ID 0x8129573 574#define RTL8190_EEPROM_ID 0x8129575#define EEPROM_HPON 0x02576#define EEPROM_CLK 0x06577#define EEPROM_TESTR 0x08578 579#define EEPROM_VID 0x0A580#define EEPROM_DID 0x0C581#define EEPROM_SVID 0x0E582#define EEPROM_SMID 0x10583 584#define EEPROM_MAC_ADDR 0x16585 586#define EEPROM_CCK_TX_PWR_INX 0x5A587#define EEPROM_HT40_1S_TX_PWR_INX 0x60588#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66589#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69590#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C591#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F592#define EEPROM_HT20_MAX_PWR_OFFSET 0x72593 594#define EEPROM_TSSI_A 0x76595#define EEPROM_TSSI_B 0x77596#define EEPROM_THERMAL_METER 0x78597#define EEPROM_XTAL_K 0x78598#define EEPROM_RF_OPT1 0x79599#define EEPROM_RF_OPT2 0x7A600#define EEPROM_RF_OPT3 0x7B601#define EEPROM_RF_OPT4 0x7C602#define EEPROM_CHANNEL_PLAN 0x7D603#define EEPROM_VERSION 0x7E604#define EEPROM_CUSTOMER_ID 0x7F605 606#define EEPROM_PWRDIFF 0x54607 608#define EEPROM_TXPOWERCCK 0x5A609#define EEPROM_TXPOWERHT40_1S 0x60610#define EEPROM_TXPOWERHT40_2SDIFF 0x66611#define EEPROM_TXPOWERHT20DIFF 0x69612#define EEPROM_TXPOWER_OFDMDIFF 0x6C613 614#define EEPROM_TXPWR_GROUP 0x6F615 616#define EEPROM_CHANNELPLAN 0x75617 618#define STOPBECON BIT(6)619#define STOPHIGHT BIT(5)620#define STOPMGT BIT(4)621#define STOPVO BIT(3)622#define STOPVI BIT(2)623#define STOPBE BIT(1)624#define STOPBK BIT(0)625 626#define RCR_APPFCS BIT(31)627#define RCR_APP_FCS BIT(31)628#define RCR_APP_MIC BIT(30)629#define RCR_APP_ICV BIT(29)630#define RCR_APP_PHYSTS BIT(28)631#define RCR_APP_PHYST_RXFF BIT(28)632#define RCR_APP_BA_SSN BIT(27)633#define RCR_ENMBID BIT(24)634#define RCR_LSIGEN BIT(23)635#define RCR_MFBEN BIT(22)636#define RCR_HTC_LOC_CTRL BIT(14)637#define RCR_AMF BIT(13)638#define RCR_ACF BIT(12)639#define RCR_ADF BIT(11)640#define RCR_AICV BIT(9)641#define RCR_ACRC32 BIT(8)642#define RCR_CBSSID_BCN BIT(7)643#define RCR_CBSSID_DATA BIT(6)644#define RCR_CBSSID RCR_CBSSID_DATA645#define RCR_APWRMGT BIT(5)646#define RCR_ADD3 BIT(4)647#define RCR_AB BIT(3)648#define RCR_AM BIT(2)649#define RCR_APM BIT(1)650#define RCR_AAP BIT(0)651#define RCR_MXDMA_OFFSET 8652#define RCR_FIFO_OFFSET 13653 654#define RSV_CTRL 0x001C655#define RD_CTRL 0x0524656 657#define REG_USB_VID 0xFE60658#define REG_USB_PID 0xFE62659#define REG_USB_OPTIONAL 0xFE64660#define REG_USB_CHIRP_K 0xFE65661#define REG_USB_PHY 0xFE66662#define REG_USB_MAC_ADDR 0xFE70663#define REG_USB_HRPWM 0xFE58664#define REG_USB_HCPWM 0xFE57665 666#define SW18_FPWM BIT(3)667 668#define ISO_MD2PP BIT(0)669#define ISO_UA2USB BIT(1)670#define ISO_UD2CORE BIT(2)671#define ISO_PA2PCIE BIT(3)672#define ISO_PD2CORE BIT(4)673#define ISO_IP2MAC BIT(5)674#define ISO_DIOP BIT(6)675#define ISO_DIOE BIT(7)676#define ISO_EB2CORE BIT(8)677#define ISO_DIOR BIT(9)678 679#define PWC_EV25V BIT(14)680#define PWC_EV12V BIT(15)681 682#define FEN_BBRSTB BIT(0)683#define FEN_BB_GLB_RSTN BIT(1)684#define FEN_USBA BIT(2)685#define FEN_UPLL BIT(3)686#define FEN_USBD BIT(4)687#define FEN_DIO_PCIE BIT(5)688#define FEN_PCIEA BIT(6)689#define FEN_PPLL BIT(7)690#define FEN_PCIED BIT(8)691#define FEN_DIOE BIT(9)692#define FEN_CPUEN BIT(10)693#define FEN_DCORE BIT(11)694#define FEN_ELDR BIT(12)695#define FEN_DIO_RF BIT(13)696#define FEN_HWPDN BIT(14)697#define FEN_MREGEN BIT(15)698 699#define PFM_LDALL BIT(0)700#define PFM_ALDN BIT(1)701#define PFM_LDKP BIT(2)702#define PFM_WOWL BIT(3)703#define ENPDN BIT(4)704#define PDN_PL BIT(5)705#define APFM_ONMAC BIT(8)706#define APFM_OFF BIT(9)707#define APFM_RSM BIT(10)708#define AFSM_HSUS BIT(11)709#define AFSM_PCIE BIT(12)710#define APDM_MAC BIT(13)711#define APDM_HOST BIT(14)712#define APDM_HPDN BIT(15)713#define RDY_MACON BIT(16)714#define SUS_HOST BIT(17)715#define ROP_ALD BIT(20)716#define ROP_PWR BIT(21)717#define ROP_SPS BIT(22)718#define SOP_MRST BIT(25)719#define SOP_FUSE BIT(26)720#define SOP_ABG BIT(27)721#define SOP_AMB BIT(28)722#define SOP_RCK BIT(29)723#define SOP_A8M BIT(30)724#define XOP_BTCK BIT(31)725 726#define ANAD16V_EN BIT(0)727#define ANA8M BIT(1)728#define MACSLP BIT(4)729#define LOADER_CLK_EN BIT(5)730#define _80M_SSC_DIS BIT(7)731#define _80M_SSC_EN_HO BIT(8)732#define PHY_SSC_RSTB BIT(9)733#define SEC_CLK_EN BIT(10)734#define MAC_CLK_EN BIT(11)735#define SYS_CLK_EN BIT(12)736#define RING_CLK_EN BIT(13)737 738#define BOOT_FROM_EEPROM BIT(4)739#define EEPROM_EN BIT(5)740 741#define AFE_BGEN BIT(0)742#define AFE_MBEN BIT(1)743#define MAC_ID_EN BIT(7)744 745#define WLOCK_ALL BIT(0)746#define WLOCK_00 BIT(1)747#define WLOCK_04 BIT(2)748#define WLOCK_08 BIT(3)749#define WLOCK_40 BIT(4)750#define R_DIS_PRST_0 BIT(5)751#define R_DIS_PRST_1 BIT(6)752#define LOCK_ALL_EN BIT(7)753 754#define RF_EN BIT(0)755#define RF_RSTB BIT(1)756#define RF_SDMRSTB BIT(2)757 758#define LDA15_EN BIT(0)759#define LDA15_STBY BIT(1)760#define LDA15_OBUF BIT(2)761#define LDA15_REG_VOS BIT(3)762#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)763 764#define LDV12_EN BIT(0)765#define LDV12_SDBY BIT(1)766#define LPLDO_HSM BIT(2)767#define LPLDO_LSM_DIS BIT(3)768#define _LDV12_VADJ(x) (((x) & 0xF) << 4)769 770#define XTAL_EN BIT(0)771#define XTAL_BSEL BIT(1)772#define _XTAL_BOSC(x) (((x) & 0x3) << 2)773#define _XTAL_CADJ(x) (((x) & 0xF) << 4)774#define XTAL_GATE_USB BIT(8)775#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)776#define XTAL_GATE_AFE BIT(11)777#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)778#define XTAL_RF_GATE BIT(14)779#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)780#define XTAL_GATE_DIG BIT(17)781#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)782#define XTAL_BT_GATE BIT(20)783#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)784#define _XTAL_GPIO(x) (((x) & 0x7) << 23)785 786#define CKDLY_AFE BIT(26)787#define CKDLY_USB BIT(27)788#define CKDLY_DIG BIT(28)789#define CKDLY_BT BIT(29)790 791#define APLL_EN BIT(0)792#define APLL_320_EN BIT(1)793#define APLL_FREF_SEL BIT(2)794#define APLL_EDGE_SEL BIT(3)795#define APLL_WDOGB BIT(4)796#define APLL_LPFEN BIT(5)797 798#define APLL_REF_CLK_13MHZ 0x1799#define APLL_REF_CLK_19_2MHZ 0x2800#define APLL_REF_CLK_20MHZ 0x3801#define APLL_REF_CLK_25MHZ 0x4802#define APLL_REF_CLK_26MHZ 0x5803#define APLL_REF_CLK_38_4MHZ 0x6804#define APLL_REF_CLK_40MHZ 0x7805 806#define APLL_320EN BIT(14)807#define APLL_80EN BIT(15)808#define APLL_1MEN BIT(24)809 810#define ALD_EN BIT(18)811#define EF_PD BIT(19)812#define EF_FLAG BIT(31)813 814#define EF_TRPT BIT(7)815#define LDOE25_EN BIT(31)816 817#define RSM_EN BIT(0)818#define TIMER_EN BIT(4)819 820#define TRSW0EN BIT(2)821#define TRSW1EN BIT(3)822#define EROM_EN BIT(4)823#define ENBT BIT(5)824#define ENUART BIT(8)825#define UART_910 BIT(9)826#define ENPMAC BIT(10)827#define SIC_SWRST BIT(11)828#define ENSIC BIT(12)829#define SIC_23 BIT(13)830#define ENHDP BIT(14)831#define SIC_LBK BIT(15)832 833#define LED0PL BIT(4)834#define LED1PL BIT(12)835#define LED0DIS BIT(7)836 837#define MCUFWDL_EN BIT(0)838#define MCUFWDL_RDY BIT(1)839#define FWDL_CHKSUM_RPT BIT(2)840#define MACINI_RDY BIT(3)841#define BBINI_RDY BIT(4)842#define RFINI_RDY BIT(5)843#define WINTINI_RDY BIT(6)844#define CPRST BIT(23)845 846#define XCLK_VLD BIT(0)847#define ACLK_VLD BIT(1)848#define UCLK_VLD BIT(2)849#define PCLK_VLD BIT(3)850#define PCIRSTB BIT(4)851#define V15_VLD BIT(5)852#define TRP_B15V_EN BIT(7)853#define SIC_IDLE BIT(8)854#define BD_MAC2 BIT(9)855#define BD_MAC1 BIT(10)856#define IC_MACPHY_MODE BIT(11)857#define BT_FUNC BIT(16)858#define VENDOR_ID BIT(19)859#define PAD_HWPD_IDN BIT(22)860#define TRP_VAUX_EN BIT(23)861#define TRP_BT_EN BIT(24)862#define BD_PKG_SEL BIT(25)863#define BD_HCI_SEL BIT(26)864#define TYPE_ID BIT(27)865#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))866 867#define CHIP_VER_RTL_MASK 0xF000868#define CHIP_VER_RTL_SHIFT 12869 870#define REG_LBMODE (REG_CR + 3)871 872#define HCI_TXDMA_EN BIT(0)873#define HCI_RXDMA_EN BIT(1)874#define TXDMA_EN BIT(2)875#define RXDMA_EN BIT(3)876#define PROTOCOL_EN BIT(4)877#define SCHEDULE_EN BIT(5)878#define MACTXEN BIT(6)879#define MACRXEN BIT(7)880#define ENSWBCN BIT(8)881#define ENSEC BIT(9)882 883#define _NETTYPE(x) (((x) & 0x3) << 16)884#define MASK_NETTYPE 0x30000885#define NT_NO_LINK 0x0886#define NT_LINK_AD_HOC 0x1887#define NT_LINK_AP 0x2888#define NT_AS_AP 0x3889 890#define _LBMODE(x) (((x) & 0xF) << 24)891#define MASK_LBMODE 0xF000000892#define LOOPBACK_NORMAL 0x0893#define LOOPBACK_IMMEDIATELY 0xB894#define LOOPBACK_MAC_DELAY 0x3895#define LOOPBACK_PHY 0x1896#define LOOPBACK_DMA 0x7897 898#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)899#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)900#define _PSRX_MASK 0xF901#define _PSTX_MASK 0xF0902#define _PSRX(x) (x)903#define _PSTX(x) ((x) << 4)904 905#define PBP_64 0x0906#define PBP_128 0x1907#define PBP_256 0x2908#define PBP_512 0x3909#define PBP_1024 0x4910 911#define RXDMA_ARBBW_EN BIT(0)912#define RXSHFT_EN BIT(1)913#define RXDMA_AGG_EN BIT(2)914#define QS_VO_QUEUE BIT(8)915#define QS_VI_QUEUE BIT(9)916#define QS_BE_QUEUE BIT(10)917#define QS_BK_QUEUE BIT(11)918#define QS_MANAGER_QUEUE BIT(12)919#define QS_HIGH_QUEUE BIT(13)920 921#define HQSEL_VOQ BIT(0)922#define HQSEL_VIQ BIT(1)923#define HQSEL_BEQ BIT(2)924#define HQSEL_BKQ BIT(3)925#define HQSEL_MGTQ BIT(4)926#define HQSEL_HIQ BIT(5)927 928#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)929#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)930#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)931#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)932#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)933#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)934 935#define QUEUE_LOW 1936#define QUEUE_NORMAL 2937#define QUEUE_HIGH 3938 939#define _LLT_NO_ACTIVE 0x0940#define _LLT_WRITE_ACCESS 0x1941#define _LLT_READ_ACCESS 0x2942 943#define _LLT_INIT_DATA(x) ((x) & 0xFF)944#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)945#define _LLT_OP(x) (((x) & 0x3) << 30)946#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)947 948#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))949#define BB_WRITE_EN BIT(30)950#define BB_READ_EN BIT(31)951 952#define _HPQ(x) ((x) & 0xFF)953#define _LPQ(x) (((x) & 0xFF) << 8)954#define _PUBQ(x) (((x) & 0xFF) << 16)955#define _NPQ(x) ((x) & 0xFF)956 957#define HPQ_PUBLIC_DIS BIT(24)958#define LPQ_PUBLIC_DIS BIT(25)959#define LD_RQPN BIT(31)960 961#define BCN_VALID BIT(16)962#define BCN_HEAD(x) (((x) & 0xFF) << 8)963#define BCN_HEAD_MASK 0xFF00964 965#define BLK_DESC_NUM_SHIFT 4966#define BLK_DESC_NUM_MASK 0xF967 968#define DROP_DATA_EN BIT(9)969 970#define EN_AMPDU_RTY_NEW BIT(7)971 972#define _INIRTSMCS_SEL(x) ((x) & 0x3F)973 974#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)975#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)976 977#define RATE_REG_BITMAP_ALL 0xFFFFF978 979#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)980 981#define _RRSR_RSC(x) (((x) & 0x3) << 21)982#define RRSR_RSC_RESERVED 0x0983#define RRSR_RSC_UPPER_SUBCHANNEL 0x1984#define RRSR_RSC_LOWER_SUBCHANNEL 0x2985#define RRSR_RSC_DUPLICATE_MODE 0x3986 987#define USE_SHORT_G1 BIT(20)988 989#define _AGGLMT_MCS0(x) ((x) & 0xF)990#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)991#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)992#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)993#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)994#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)995#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)996#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)997 998#define RETRY_LIMIT_SHORT_SHIFT 8999#define RETRY_LIMIT_LONG_SHIFT 01000 1001#define _DARF_RC1(x) ((x) & 0x1F)1002#define _DARF_RC2(x) (((x) & 0x1F) << 8)1003#define _DARF_RC3(x) (((x) & 0x1F) << 16)1004#define _DARF_RC4(x) (((x) & 0x1F) << 24)1005#define _DARF_RC5(x) ((x) & 0x1F)1006#define _DARF_RC6(x) (((x) & 0x1F) << 8)1007#define _DARF_RC7(x) (((x) & 0x1F) << 16)1008#define _DARF_RC8(x) (((x) & 0x1F) << 24)1009 1010#define _RARF_RC1(x) ((x) & 0x1F)1011#define _RARF_RC2(x) (((x) & 0x1F) << 8)1012#define _RARF_RC3(x) (((x) & 0x1F) << 16)1013#define _RARF_RC4(x) (((x) & 0x1F) << 24)1014#define _RARF_RC5(x) ((x) & 0x1F)1015#define _RARF_RC6(x) (((x) & 0x1F) << 8)1016#define _RARF_RC7(x) (((x) & 0x1F) << 16)1017#define _RARF_RC8(x) (((x) & 0x1F) << 24)1018 1019#define AC_PARAM_TXOP_OFFSET 161020#define AC_PARAM_TXOP_LIMIT_OFFSET 161021#define AC_PARAM_ECW_MAX_OFFSET 121022#define AC_PARAM_ECW_MIN_OFFSET 81023#define AC_PARAM_AIFS_OFFSET 01024 1025#define _AIFS(x) (x)1026#define _ECW_MAX_MIN(x) ((x) << 8)1027#define _TXOP_LIMIT(x) ((x) << 16)1028 1029#define _BCNIFS(x) ((x) & 0xFF)1030#define _BCNECW(x) ((((x) & 0xF)) << 8)1031 1032#define _LRL(x) ((x) & 0x3F)1033#define _SRL(x) (((x) & 0x3F) << 8)1034 1035#define _SIFS_CCK_CTX(x) ((x) & 0xFF)1036#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)1037 1038#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)1039#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)1040 1041#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)1042 1043#define DIS_EDCA_CNT_DWN BIT(11)1044 1045#define EN_MBSSID BIT(1)1046#define EN_TXBCN_RPT BIT(2)1047#define EN_BCN_FUNCTION BIT(3)1048 1049#define TSFTR_RST BIT(0)1050#define TSFTR1_RST BIT(1)1051 1052#define STOP_BCNQ BIT(6)1053 1054#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)1055#define DIS_TSF_UDT0_TEST_CHIP BIT(5)1056 1057#define ACMHW_HWEN BIT(0)1058#define ACMHW_BEQEN BIT(1)1059#define ACMHW_VIQEN BIT(2)1060#define ACMHW_VOQEN BIT(3)1061#define ACMHW_BEQSTATUS BIT(4)1062#define ACMHW_VIQSTATUS BIT(5)1063#define ACMHW_VOQSTATUS BIT(6)1064 1065#define APSDOFF BIT(6)1066#define APSDOFF_STATUS BIT(7)1067 1068#define BW_20MHZ BIT(2)1069 1070#define RATE_BITMAP_ALL 0xFFFFF1071 1072#define RATE_RRSR_CCK_ONLY_1M 0xFFFF11073 1074#define TSFRST BIT(0)1075#define DIS_GCLK BIT(1)1076#define PAD_SEL BIT(2)1077#define PWR_ST BIT(6)1078#define PWRBIT_OW_EN BIT(7)1079#define ACRC BIT(8)1080#define CFENDFORM BIT(9)1081#define ICV BIT(10)1082 1083#define AAP BIT(0)1084#define APM BIT(1)1085#define AM BIT(2)1086#define AB BIT(3)1087#define ADD3 BIT(4)1088#define APWRMGT BIT(5)1089#define CBSSID BIT(6)1090#define CBSSID_DATA BIT(6)1091#define CBSSID_BCN BIT(7)1092#define ACRC32 BIT(8)1093#define AICV BIT(9)1094#define ADF BIT(11)1095#define ACF BIT(12)1096#define AMF BIT(13)1097#define HTC_LOC_CTRL BIT(14)1098#define UC_DATA_EN BIT(16)1099#define BM_DATA_EN BIT(17)1100#define MFBEN BIT(22)1101#define LSIGEN BIT(23)1102#define ENMBID BIT(24)1103#define APP_BASSN BIT(27)1104#define APP_PHYSTS BIT(28)1105#define APP_ICV BIT(29)1106#define APP_MIC BIT(30)1107#define APP_FCS BIT(31)1108 1109#define _MIN_SPACE(x) ((x) & 0x7)1110#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)1111 1112#define RXERR_TYPE_OFDM_PPDU 01113#define RXERR_TYPE_OFDM_FALSE_ALARM 11114#define RXERR_TYPE_OFDM_MPDU_OK 21115#define RXERR_TYPE_OFDM_MPDU_FAIL 31116#define RXERR_TYPE_CCK_PPDU 41117#define RXERR_TYPE_CCK_FALSE_ALARM 51118#define RXERR_TYPE_CCK_MPDU_OK 61119#define RXERR_TYPE_CCK_MPDU_FAIL 71120#define RXERR_TYPE_HT_PPDU 81121#define RXERR_TYPE_HT_FALSE_ALARM 91122#define RXERR_TYPE_HT_MPDU_TOTAL 101123#define RXERR_TYPE_HT_MPDU_OK 111124#define RXERR_TYPE_HT_MPDU_FAIL 121125#define RXERR_TYPE_RX_FULL_DROP 151126 1127#define RXERR_COUNTER_MASK 0xFFFFF1128#define RXERR_RPT_RST BIT(27)1129#define _RXERR_RPT_SEL(type) ((type) << 28)1130 1131#define SCR_TXUSEDK BIT(0)1132#define SCR_RXUSEDK BIT(1)1133#define SCR_TXENCENABLE BIT(2)1134#define SCR_RXDECENABLE BIT(3)1135#define SCR_SKBYA2 BIT(4)1136#define SCR_NOSKMC BIT(5)1137#define SCR_TXBCUSEDK BIT(6)1138#define SCR_RXBCUSEDK BIT(7)1139 1140#define USB_IS_HIGH_SPEED 01141#define USB_IS_FULL_SPEED 11142#define USB_SPEED_MASK BIT(5)1143 1144#define USB_NORMAL_SIE_EP_MASK 0xF1145#define USB_NORMAL_SIE_EP_SHIFT 41146 1147#define USB_TEST_EP_MASK 0x301148#define USB_TEST_EP_SHIFT 41149 1150#define USB_AGG_EN BIT(3)1151 1152#define LAST_ENTRY_OF_TX_PKT_BUFFER 2551153 1154#define POLLING_LLT_THRESHOLD 201155#define POLLING_READY_TIMEOUT_COUNT 10001156 1157#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))1158#define EPROM_CMD_CONFIG 0x31159#define EPROM_CMD_LOAD 11160 1161#define HWSET_MAX_SIZE 1281162#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE1163#define EFUSE_MAX_SECTION 161164 1165#define WL_HWPDN_EN BIT(0)1166 1167#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)1168 1169#define RPMAC_RESET 0x1001170#define RPMAC_TXSTART 0x1041171#define RPMAC_TXLEGACYSIG 0x1081172#define RPMAC_TXHTSIG1 0x10c1173#define RPMAC_TXHTSIG2 0x1101174#define RPMAC_PHYDEBUG 0x1141175#define RPMAC_TXPACKETNUM 0x1181176#define RPMAC_TXIDLE 0x11c1177#define RPMAC_TXMACHEADER0 0x1201178#define RPMAC_TXMACHEADER1 0x1241179#define RPMAC_TXMACHEADER2 0x1281180#define RPMAC_TXMACHEADER3 0x12c1181#define RPMAC_TXMACHEADER4 0x1301182#define RPMAC_TXMACHEADER5 0x1341183#define RPMAC_TXDADATYPE 0x1381184#define RPMAC_TXRANDOMSEED 0x13c1185#define RPMAC_CCKPLCPPREAMBLE 0x1401186#define RPMAC_CCKPLCPHEADER 0x1441187#define RPMAC_CCKCRC16 0x1481188#define RPMAC_OFDMRXCRC32OK 0x1701189#define RPMAC_OFDMRXCRC32ER 0x1741190#define RPMAC_OFDMRXPARITYER 0x1781191#define RPMAC_OFDMRXCRC8ER 0x17c1192#define RPMAC_CCKCRXRC16ER 0x1801193#define RPMAC_CCKCRXRC32ER 0x1841194#define RPMAC_CCKCRXRC32OK 0x1881195#define RPMAC_TXSTATUS 0x18c1196 1197#define RFPGA0_RFMOD 0x8001198 1199#define RFPGA0_TXINFO 0x8041200#define RFPGA0_PSDFUNCTION 0x8081201 1202#define RFPGA0_TXGAINSTAGE 0x80c1203 1204#define RFPGA0_RFTIMING1 0x8101205#define RFPGA0_RFTIMING2 0x8141206 1207#define RFPGA0_XA_HSSIPARAMETER1 0x8201208#define RFPGA0_XA_HSSIPARAMETER2 0x8241209#define RFPGA0_XB_HSSIPARAMETER1 0x8281210#define RFPGA0_XB_HSSIPARAMETER2 0x82c1211 1212#define RFPGA0_XA_LSSIPARAMETER 0x8401213#define RFPGA0_XB_LSSIPARAMETER 0x8441214 1215#define RFPGA0_RFWAKEUPPARAMETER 0x8501216#define RFPGA0_RFSLEEPUPPARAMETER 0x8541217 1218#define RFPGA0_XAB_SWITCHCONTROL 0x8581219#define RFPGA0_XCD_SWITCHCONTROL 0x85c1220 1221#define RFPGA0_XA_RFINTERFACEOE 0x8601222#define RFPGA0_XB_RFINTERFACEOE 0x8641223 1224#define RFPGA0_XAB_RFINTERFACESW 0x8701225#define RFPGA0_XCD_RFINTERFACESW 0x8741226 1227#define RFPGA0_XAB_RFPARAMETER 0x8781228#define RFPGA0_XCD_RFPARAMETER 0x87c1229 1230#define RFPGA0_ANALOGPARAMETER1 0x8801231#define RFPGA0_ANALOGPARAMETER2 0x8841232#define RFPGA0_ANALOGPARAMETER3 0x8881233#define RFPGA0_ANALOGPARAMETER4 0x88c1234 1235#define RFPGA0_XA_LSSIREADBACK 0x8a01236#define RFPGA0_XB_LSSIREADBACK 0x8a41237#define RFPGA0_XC_LSSIREADBACK 0x8a81238#define RFPGA0_XD_LSSIREADBACK 0x8ac1239 1240#define RFPGA0_PSDREPORT 0x8b41241#define TRANSCEIVEA_HSPI_READBACK 0x8b81242#define TRANSCEIVEB_HSPI_READBACK 0x8bc1243#define RFPGA0_XAB_RFINTERFACERB 0x8e01244#define RFPGA0_XCD_RFINTERFACERB 0x8e41245 1246#define RFPGA1_RFMOD 0x9001247 1248#define RFPGA1_TXBLOCK 0x9041249#define RFPGA1_DEBUGSELECT 0x9081250#define RFPGA1_TXINFO 0x90c1251 1252#define RCCK0_SYSTEM 0xa001253 1254#define RCCK0_AFESETTING 0xa041255#define RCCK0_CCA 0xa081256 1257#define RCCK0_RXAGC1 0xa0c1258#define RCCK0_RXAGC2 0xa101259 1260#define RCCK0_RXHP 0xa141261 1262#define RCCK0_DSPPARAMETER1 0xa181263#define RCCK0_DSPPARAMETER2 0xa1c1264 1265#define RCCK0_TXFILTER1 0xa201266#define RCCK0_TXFILTER2 0xa241267#define RCCK0_DEBUGPORT 0xa281268#define RCCK0_FALSEALARMREPORT 0xa2c1269#define RCCK0_TRSSIREPORT 0xa501270#define RCCK0_RXREPORT 0xa541271#define RCCK0_FACOUNTERLOWER 0xa5c1272#define RCCK0_FACOUNTERUPPER 0xa581273 1274#define ROFDM0_LSTF 0xc001275 1276#define ROFDM0_TRXPATHENABLE 0xc041277#define ROFDM0_TRMUXPAR 0xc081278#define ROFDM0_TRSWISOLATION 0xc0c1279 1280#define ROFDM0_XARXAFE 0xc101281#define ROFDM0_XARXIQIMBALANCE 0xc141282#define ROFDM0_XBRXAFE 0xc181283#define ROFDM0_XBRXIQIMBALANCE 0xc1c1284#define ROFDM0_XCRXAFE 0xc201285#define ROFDM0_XCRXIQIMBANLANCE 0xc241286#define ROFDM0_XDRXAFE 0xc281287#define ROFDM0_XDRXIQIMBALANCE 0xc2c1288 1289#define ROFDM0_RXDETECTOR1 0xc301290#define ROFDM0_RXDETECTOR2 0xc341291#define ROFDM0_RXDETECTOR3 0xc381292#define ROFDM0_RXDETECTOR4 0xc3c1293 1294#define ROFDM0_RXDSP 0xc401295#define ROFDM0_CFOANDDAGC 0xc441296#define ROFDM0_CCADROPTHRESHOLD 0xc481297#define ROFDM0_ECCATHRESHOLD 0xc4c1298 1299#define ROFDM0_XAAGCCORE1 0xc501300#define ROFDM0_XAAGCCORE2 0xc541301#define ROFDM0_XBAGCCORE1 0xc581302#define ROFDM0_XBAGCCORE2 0xc5c1303#define ROFDM0_XCAGCCORE1 0xc601304#define ROFDM0_XCAGCCORE2 0xc641305#define ROFDM0_XDAGCCORE1 0xc681306#define ROFDM0_XDAGCCORE2 0xc6c1307 1308#define ROFDM0_AGCPARAMETER1 0xc701309#define ROFDM0_AGCPARAMETER2 0xc741310#define ROFDM0_AGCRSSITABLE 0xc781311#define ROFDM0_HTSTFAGC 0xc7c1312 1313#define ROFDM0_XATXIQIMBALANCE 0xc801314#define ROFDM0_XATXAFE 0xc841315#define ROFDM0_XBTXIQIMBALANCE 0xc881316#define ROFDM0_XBTXAFE 0xc8c1317#define ROFDM0_XCTXIQIMBALANCE 0xc901318#define ROFDM0_XCTXAFE 0xc941319#define ROFDM0_XDTXIQIMBALANCE 0xc981320#define ROFDM0_XDTXAFE 0xc9c1321 1322#define ROFDM0_RXIQEXTANTA 0xca01323 1324#define ROFDM0_RXHPPARAMETER 0xce01325#define ROFDM0_TXPSEUDONOISEWGT 0xce41326#define ROFDM0_FRAMESYNC 0xcf01327#define ROFDM0_DFSREPORT 0xcf41328#define ROFDM0_TXCOEFF1 0xca41329#define ROFDM0_TXCOEFF2 0xca81330#define ROFDM0_TXCOEFF3 0xcac1331#define ROFDM0_TXCOEFF4 0xcb01332#define ROFDM0_TXCOEFF5 0xcb41333#define ROFDM0_TXCOEFF6 0xcb81334 1335#define ROFDM1_LSTF 0xd001336#define ROFDM1_TRXPATHENABLE 0xd041337 1338#define ROFDM1_CF0 0xd081339#define ROFDM1_CSI1 0xd101340#define ROFDM1_SBD 0xd141341#define ROFDM1_CSI2 0xd181342#define ROFDM1_CFOTRACKING 0xd2c1343#define ROFDM1_TRXMESAURE1 0xd341344#define ROFDM1_INTFDET 0xd3c1345#define ROFDM1_PSEUDONOISESTATEAB 0xd501346#define ROFDM1_PSEUDONOISESTATECD 0xd541347#define ROFDM1_RXPSEUDONOISEWGT 0xd581348 1349#define ROFDM_PHYCOUNTER1 0xda01350#define ROFDM_PHYCOUNTER2 0xda41351#define ROFDM_PHYCOUNTER3 0xda81352 1353#define ROFDM_SHORTCFOAB 0xdac1354#define ROFDM_SHORTCFOCD 0xdb01355#define ROFDM_LONGCFOAB 0xdb41356#define ROFDM_LONGCFOCD 0xdb81357#define ROFDM_TAILCF0AB 0xdbc1358#define ROFDM_TAILCF0CD 0xdc01359#define ROFDM_PWMEASURE1 0xdc41360#define ROFDM_PWMEASURE2 0xdc81361#define ROFDM_BWREPORT 0xdcc1362#define ROFDM_AGCREPORT 0xdd01363#define ROFDM_RXSNR 0xdd41364#define ROFDM_RXEVMCSI 0xdd81365#define ROFDM_SIGREPORT 0xddc1366 1367#define RTXAGC_A_RATE18_06 0xe001368#define RTXAGC_A_RATE54_24 0xe041369#define RTXAGC_A_CCK1_MCS32 0xe081370#define RTXAGC_A_MCS03_MCS00 0xe101371#define RTXAGC_A_MCS07_MCS04 0xe141372#define RTXAGC_A_MCS11_MCS08 0xe181373#define RTXAGC_A_MCS15_MCS12 0xe1c1374 1375#define RTXAGC_B_RATE18_06 0x8301376#define RTXAGC_B_RATE54_24 0x8341377#define RTXAGC_B_CCK1_55_MCS32 0x8381378#define RTXAGC_B_MCS03_MCS00 0x83c1379#define RTXAGC_B_MCS07_MCS04 0x8481380#define RTXAGC_B_MCS11_MCS08 0x84c1381#define RTXAGC_B_MCS15_MCS12 0x8681382#define RTXAGC_B_CCK11_A_CCK2_11 0x86c1383 1384#define RZEBRA1_HSSIENABLE 0x01385#define RZEBRA1_TRXENABLE1 0x11386#define RZEBRA1_TRXENABLE2 0x21387#define RZEBRA1_AGC 0x41388#define RZEBRA1_CHARGEPUMP 0x51389#define RZEBRA1_CHANNEL 0x71390 1391#define RZEBRA1_TXGAIN 0x81392#define RZEBRA1_TXLPF 0x91393#define RZEBRA1_RXLPF 0xb1394#define RZEBRA1_RXHPFCORNER 0xc1395 1396#define RGLOBALCTRL 01397#define RRTL8256_TXLPF 191398#define RRTL8256_RXLPF 111399#define RRTL8258_TXLPF 0x111400#define RRTL8258_RXLPF 0x131401#define RRTL8258_RSSILPF 0xa1402 1403#define RF_AC 0x001404 1405#define RF_IQADJ_G1 0x011406#define RF_IQADJ_G2 0x021407#define RF_POW_TRSW 0x051408 1409#define RF_GAIN_RX 0x061410#define RF_GAIN_TX 0x071411 1412#define RF_TXM_IDAC 0x081413#define RF_BS_IQGEN 0x0F1414 1415#define RF_MODE1 0x101416#define RF_MODE2 0x111417 1418#define RF_RX_AGC_HP 0x121419#define RF_TX_AGC 0x131420#define RF_BIAS 0x141421#define RF_IPA 0x151422#define RF_POW_ABILITY 0x171423#define RF_MODE_AG 0x181424#define RRFCHANNEL 0x181425#define RF_CHNLBW 0x181426#define RF_TOP 0x191427 1428#define RF_RX_G1 0x1A1429#define RF_RX_G2 0x1B1430 1431#define RF_RX_BB2 0x1C1432#define RF_RX_BB1 0x1D1433 1434#define RF_RCK1 0x1E1435#define RF_RCK2 0x1F1436 1437#define RF_TX_G1 0x201438#define RF_TX_G2 0x211439#define RF_TX_G3 0x221440 1441#define RF_TX_BB1 0x231442#define RF_T_METER 0x241443 1444#define RF_SYN_G1 0x251445#define RF_SYN_G2 0x261446#define RF_SYN_G3 0x271447#define RF_SYN_G4 0x281448#define RF_SYN_G5 0x291449#define RF_SYN_G6 0x2A1450#define RF_SYN_G7 0x2B1451#define RF_SYN_G8 0x2C1452 1453#define RF_RCK_OS 0x301454#define RF_TXPA_G1 0x311455#define RF_TXPA_G2 0x321456#define RF_TXPA_G3 0x331457 1458#define BBBRESETB 0x1001459#define BGLOBALRESETB 0x2001460#define BOFDMTXSTART 0x41461#define BCCKTXSTART 0x81462#define BCRC32DEBUG 0x1001463#define BPMACLOOPBACK 0x101464#define BTXLSIG 0xffffff1465#define BOFDMTXRATE 0xf1466#define BOFDMTXRESERVED 0x101467#define BOFDMTXLENGTH 0x1ffe01468#define BOFDMTXPARITY 0x200001469#define BTXHTSIG1 0xffffff1470#define BTXHTMCSRATE 0x7f1471#define BTXHTBW 0x801472#define BTXHTLENGTH 0xffff001473#define BTXHTSIG2 0xffffff1474#define BTXHTSMOOTHING 0x11475#define BTXHTSOUNDING 0x21476#define BTXHTRESERVED 0x41477#define BTXHTAGGREATION 0x81478#define BTXHTSTBC 0x301479#define BTXHTADVANCECODING 0x401480#define BTXHTSHORTGI 0x801481#define BTXHTNUMBERHT_LTF 0x3001482#define BTXHTCRC8 0x3fc001483#define BCOUNTERRESET 0x100001484#define BNUMOFOFDMTX 0xffff1485#define BNUMOFCCKTX 0xffff00001486#define BTXIDLEINTERVAL 0xffff1487#define BOFDMSERVICE 0xffff00001488#define BTXMACHEADER 0xffffffff1489#define BTXDATAINIT 0xff1490#define BTXHTMODE 0x1001491#define BTXDATATYPE 0x300001492#define BTXRANDOMSEED 0xffffffff1493#define BCCKTXPREAMBLE 0x11494#define BCCKTXSFD 0xffff00001495#define BCCKTXSIG 0xff1496#define BCCKTXSERVICE 0xff001497#define BCCKLENGTHEXT 0x80001498#define BCCKTXLENGHT 0xffff00001499#define BCCKTXCRC16 0xffff1500#define BCCKTXSTATUS 0x11501#define BOFDMTXSTATUS 0x21502#define IS_BB_REG_OFFSET_92S(_offset) \1503 (((_offset) >= 0x800) && ((_offset) <= 0xfff))1504 1505#define BRFMOD 0x11506#define BJAPANMODE 0x21507#define BCCKTXSC 0x301508#define BCCKEN 0x10000001509#define BOFDMEN 0x20000001510 1511#define BOFDMRXADCPHASE 0x100001512#define BOFDMTXDACPHASE 0x400001513#define BXATXAGC 0x3f1514 1515#define BXBTXAGC 0xf001516#define BXCTXAGC 0xf0001517#define BXDTXAGC 0xf00001518 1519#define BPASTART 0xf00000001520#define BTRSTART 0x00f000001521#define BRFSTART 0x0000f0001522#define BBBSTART 0x000000f01523#define BBBCCKSTART 0x0000000f1524#define BPAEND 0xf1525#define BTREND 0x0f0000001526#define BRFEND 0x000f00001527#define BCCAMASK 0x000000f01528#define BR2RCCAMASK 0x00000f001529#define BHSSI_R2TDELAY 0xf80000001530#define BHSSI_T2RDELAY 0xf800001531#define BCONTXHSSI 0x4001532#define BIGFROMCCK 0x2001533#define BAGCADDRESS 0x3f1534#define BRXHPTX 0x70001535#define BRXHP2RX 0x380001536#define BRXHPCCKINI 0xc00001537#define BAGCTXCODE 0xc000001538#define BAGCRXCODE 0x3000001539 1540#define B3WIREDATALENGTH 0x8001541#define B3WIREADDREAALENGTH 0x4001542 1543#define B3WIRERFPOWERDOWN 0x11544#define B5GPAPEPOLARITY 0x400000001545#define B2GPAPEPOLARITY 0x800000001546#define BRFSW_TXDEFAULTANT 0x31547#define BRFSW_TXOPTIONANT 0x301548#define BRFSW_RXDEFAULTANT 0x3001549#define BRFSW_RXOPTIONANT 0x30001550#define BRFSI_3WIREDATA 0x11551#define BRFSI_3WIRECLOCK 0x21552#define BRFSI_3WIRELOAD 0x41553#define BRFSI_3WIRERW 0x81554#define BRFSI_3WIRE 0xf1555 1556#define BRFSI_RFENV 0x101557 1558#define BRFSI_TRSW 0x201559#define BRFSI_TRSWB 0x401560#define BRFSI_ANTSW 0x1001561#define BRFSI_ANTSWB 0x2001562#define BRFSI_PAPE 0x4001563#define BRFSI_PAPE5G 0x8001564#define BBANDSELECT 0x11565#define BHTSIG2_GI 0x801566#define BHTSIG2_SMOOTHING 0x011567#define BHTSIG2_SOUNDING 0x021568#define BHTSIG2_AGGREATON 0x081569#define BHTSIG2_STBC 0x301570#define BHTSIG2_ADVCODING 0x401571#define BHTSIG2_NUMOFHTLTF 0x3001572#define BHTSIG2_CRC8 0x3fc1573#define BHTSIG1_MCS 0x7f1574#define BHTSIG1_BANDWIDTH 0x801575#define BHTSIG1_HTLENGTH 0xffff1576#define BLSIG_RATE 0xf1577#define BLSIG_RESERVED 0x101578#define BLSIG_LENGTH 0x1fffe1579#define BLSIG_PARITY 0x201580#define BCCKRXPHASE 0x41581 1582#define BLSSIREADADDRESS 0x7f8000001583#define BLSSIREADEDGE 0x800000001584 1585#define BLSSIREADBACKDATA 0xfffff1586 1587#define BLSSIREADOKFLAG 0x10001588#define BCCKSAMPLERATE 0x81589#define BREGULATOR0STANDBY 0x11590#define BREGULATORPLLSTANDBY 0x21591#define BREGULATOR1STANDBY 0x41592#define BPLLPOWERUP 0x81593#define BDPLLPOWERUP 0x101594#define BDA10POWERUP 0x201595#define BAD7POWERUP 0x2001596#define BDA6POWERUP 0x20001597#define BXTALPOWERUP 0x40001598#define B40MDCLKPOWERUP 0x80001599#define BDA6DEBUGMODE 0x200001600#define BDA6SWING 0x3800001601 1602#define BADCLKPHASE 0x40000001603#define B80MCLKDELAY 0x180000001604#define BAFEWATCHDOGENABLE 0x200000001605 1606#define BXTALCAP01 0xc00000001607#define BXTALCAP23 0x31608#define BXTALCAP92X 0x0f0000001609#define BXTALCAP 0x0f0000001610 1611#define BINTDIFCLKENABLE 0x4001612#define BEXTSIGCLKENABLE 0x8001613#define BBANDGAP_MBIAS_POWERUP 0x100001614#define BAD11SH_GAIN 0xc00001615#define BAD11NPUT_RANGE 0x7000001616#define BAD110P_CURRENT 0x38000001617#define BLPATH_LOOPBACK 0x40000001618#define BQPATH_LOOPBACK 0x80000001619#define BAFE_LOOPBACK 0x100000001620#define BDA10_SWING 0x7e01621#define BDA10_REVERSE 0x8001622#define BDA_CLK_SOURCE 0x10001623#define BDA7INPUT_RANGE 0x60001624#define BDA7_GAIN 0x380001625#define BDA7OUTPUT_CM_MODE 0x400001626#define BDA7INPUT_CM_MODE 0x3800001627#define BDA7CURRENT 0xc000001628#define BREGULATOR_ADJUST 0x70000001629#define BAD11POWERUP_ATTX 0x11630#define BDA10PS_ATTX 0x101631#define BAD11POWERUP_ATRX 0x1001632#define BDA10PS_ATRX 0x10001633#define BCCKRX_AGC_FORMAT 0x2001634#define BPSDFFT_SAMPLE_POINT 0xc0001635#define BPSD_AVERAGE_NUM 0x30001636#define BIQPATH_CONTROL 0xc001637#define BPSD_FREQ 0x3ff1638#define BPSD_ANTENNA_PATH 0x301639#define BPSD_IQ_SWITCH 0x401640#define BPSD_RX_TRIGGER 0x4000001641#define BPSD_TX_TRIGGER 0x800000001642#define BPSD_SINE_TONE_SCALE 0x7f0000001643#define BPSD_REPORT 0xffff1644 1645#define BOFDM_TXSC 0x300000001646#define BCCK_TXON 0x11647#define BOFDM_TXON 0x21648#define BDEBUG_PAGE 0xfff1649#define BDEBUG_ITEM 0xff1650#define BANTL 0x101651#define BANT_NONHT 0x1001652#define BANT_HT1 0x10001653#define BANT_HT2 0x100001654#define BANT_HT1S1 0x1000001655#define BANT_NONHTS1 0x10000001656 1657#define BCCK_BBMODE 0x31658#define BCCK_TXPOWERSAVING 0x801659#define BCCK_RXPOWERSAVING 0x401660 1661#define BCCK_SIDEBAND 0x101662 1663#define BCCK_SCRAMBLE 0x81664#define BCCK_ANTDIVERSITY 0x80001665#define BCCK_CARRIER_RECOVERY 0x40001666#define BCCK_TXRATE 0x30001667#define BCCK_DCCANCEL 0x08001668#define BCCK_ISICANCEL 0x04001669#define BCCK_MATCH_FILTER 0x02001670#define BCCK_EQUALIZER 0x01001671#define BCCK_PREAMBLE_DETECT 0x8000001672#define BCCK_FAST_FALSECCA 0x4000001673#define BCCK_CH_ESTSTART 0x3000001674#define BCCK_CCA_COUNT 0x0800001675#define BCCK_CS_LIM 0x0700001676#define BCCK_BIST_MODE 0x800000001677#define BCCK_CCAMASK 0x400000001678#define BCCK_TX_DAC_PHASE 0x41679#define BCCK_RX_ADC_PHASE 0x200000001680#define BCCKR_CP_MODE 0x01001681#define BCCK_TXDC_OFFSET 0xf01682#define BCCK_RXDC_OFFSET 0xf1683#define BCCK_CCA_MODE 0xc0001684#define BCCK_FALSECS_LIM 0x3f001685#define BCCK_CS_RATIO 0xc000001686#define BCCK_CORGBIT_SEL 0x3000001687#define BCCK_PD_LIM 0x0f00001688#define BCCK_NEWCCA 0x800000001689#define BCCK_RXHP_OF_IG 0x80001690#define BCCK_RXIG 0x7f001691#define BCCK_LNA_POLARITY 0x8000001692#define BCCK_RX1ST_BAIN 0x7f00001693#define BCCK_RF_EXTEND 0x200000001694#define BCCK_RXAGC_SATLEVEL 0x1f0000001695#define BCCK_RXAGC_SATCOUNT 0xe01696#define BCCK_FIXED_RXAGC 0x80001697#define BCCK_ANTENNA_POLARITY 0x20001698#define BCCK_TXFILTER_TYPE 0x0c001699#define BCCK_RXAGC_REPORTTYPE 0x03001700#define BCCK_RXDAGC_EN 0x800000001701#define BCCK_RXDAGC_PERIOD 0x200000001702#define BCCK_RXDAGC_SATLEVEL 0x1f0000001703#define BCCK_TIMING_RECOVERY 0x8000001704#define BCCK_TXC0 0x3f00001705#define BCCK_TXC1 0x3f0000001706#define BCCK_TXC2 0x3f1707#define BCCK_TXC3 0x3f001708#define BCCK_TXC4 0x3f00001709#define BCCK_TXC5 0x3f0000001710#define BCCK_TXC6 0x3f1711#define BCCK_TXC7 0x3f001712#define BCCK_DEBUGPORT 0xff00001713#define BCCK_DAC_DEBUG 0x0f0000001714#define BCCK_FALSEALARM_ENABLE 0x80001715#define BCCK_FALSEALARM_READ 0x40001716#define BCCK_TRSSI 0x7f1717#define BCCK_RXAGC_REPORT 0xfe1718#define BCCK_RXREPORT_ANTSEL 0x800000001719#define BCCK_RXREPORT_MFOFF 0x400000001720#define BCCK_RXREPORT_SQLOSS 0x200000001721#define BCCK_RXREPORT_PKTLOSS 0x100000001722#define BCCK_RXREPORT_LOCKEDBIT 0x080000001723#define BCCK_RXREPORT_RATEERROR 0x040000001724#define BCCK_RXREPORT_RXRATE 0x030000001725#define BCCK_RXFA_COUNTER_LOWER 0xff1726#define BCCK_RXFA_COUNTER_UPPER 0xff0000001727#define BCCK_RXHPAGC_START 0xe0001728#define BCCK_RXHPAGC_FINAL 0x1c001729#define BCCK_RXFALSEALARM_ENABLE 0x80001730#define BCCK_FACOUNTER_FREEZE 0x40001731#define BCCK_TXPATH_SEL 0x100000001732#define BCCK_DEFAULT_RXPATH 0xc0000001733#define BCCK_OPTION_RXPATH 0x30000001734 1735#define BNUM_OFSTF 0x31736#define BSHIFT_L 0xc01737#define BGI_TH 0xc1738#define BRXPATH_A 0x11739#define BRXPATH_B 0x21740#define BRXPATH_C 0x41741#define BRXPATH_D 0x81742#define BTXPATH_A 0x11743#define BTXPATH_B 0x21744#define BTXPATH_C 0x41745#define BTXPATH_D 0x81746#define BTRSSI_FREQ 0x2001747#define BADC_BACKOFF 0x30001748#define BDFIR_BACKOFF 0xc0001749#define BTRSSI_LATCH_PHASE 0x100001750#define BRX_LDC_OFFSET 0xff1751#define BRX_QDC_OFFSET 0xff001752#define BRX_DFIR_MODE 0x18000001753#define BRX_DCNF_TYPE 0xe0000001754#define BRXIQIMB_A 0x3ff1755#define BRXIQIMB_B 0xfc001756#define BRXIQIMB_C 0x3f00001757#define BRXIQIMB_D 0xffc000001758#define BDC_DC_NOTCH 0x600001759#define BRXNB_NOTCH 0x1f0000001760#define BPD_TH 0xf1761#define BPD_TH_OPT2 0xc0001762#define BPWED_TH 0x7001763#define BIFMF_WIN_L 0x8001764#define BPD_OPTION 0x10001765#define BMF_WIN_L 0xe0001766#define BBW_SEARCH_L 0x300001767#define BWIN_ENH_L 0xc00001768#define BBW_TH 0x7000001769#define BED_TH2 0x38000001770#define BBW_OPTION 0x40000001771#define BRADIO_TH 0x180000001772#define BWINDOW_L 0xe00000001773#define BSBD_OPTION 0x11774#define BFRAME_TH 0x1c1775#define BFS_OPTION 0x601776#define BDC_SLOPE_CHECK 0x801777#define BFGUARD_COUNTER_DC_L 0xe001778#define BFRAME_WEIGHT_SHORT 0x70001779#define BSUB_TUNE 0xe000001780#define BFRAME_DC_LENGTH 0xe0000001781#define BSBD_START_OFFSET 0x300000001782#define BFRAME_TH_2 0x71783#define BFRAME_GI2_TH 0x381784#define BGI2_SYNC_EN 0x401785#define BSARCH_SHORT_EARLY 0x3001786#define BSARCH_SHORT_LATE 0xc001787#define BSARCH_GI2_LATE 0x700001788#define BCFOANTSUM 0x11789#define BCFOACC 0x21790#define BCFOSTARTOFFSET 0xc1791#define BCFOLOOPBACK 0x701792#define BCFOSUMWEIGHT 0x801793#define BDAGCENABLE 0x100001794#define BTXIQIMB_A 0x3ff1795#define BTXIQIMB_b 0xfc001796#define BTXIQIMB_C 0x3f00001797#define BTXIQIMB_D 0xffc000001798#define BTXIDCOFFSET 0xff1799#define BTXIQDCOFFSET 0xff001800#define BTXDFIRMODE 0x100001801#define BTXPESUDO_NOISEON 0x40000001802#define BTXPESUDO_NOISE_A 0xff1803#define BTXPESUDO_NOISE_B 0xff001804#define BTXPESUDO_NOISE_C 0xff00001805#define BTXPESUDO_NOISE_D 0xff0000001806#define BCCA_DROPOPTION 0x200001807#define BCCA_DROPTHRES 0xfff000001808#define BEDCCA_H 0xf1809#define BEDCCA_L 0xf01810#define BLAMBDA_ED 0x3001811#define BRX_INITIALGAIN 0x7f1812#define BRX_ANTDIV_EN 0x801813#define BRX_AGC_ADDRESS_FOR_LNA 0x7f001814#define BRX_HIGHPOWER_FLOW 0x80001815#define BRX_AGC_FREEZE_THRES 0xc00001816#define BRX_FREEZESTEP_AGC1 0x3000001817#define BRX_FREEZESTEP_AGC2 0xc000001818#define BRX_FREEZESTEP_AGC3 0x30000001819#define BRX_FREEZESTEP_AGC0 0xc0000001820#define BRXRSSI_CMP_EN 0x100000001821#define BRXQUICK_AGCEN 0x200000001822#define BRXAGC_FREEZE_THRES_MODE 0x400000001823#define BRX_OVERFLOW_CHECKTYPE 0x800000001824#define BRX_AGCSHIFT 0x7f1825#define BTRSW_TRI_ONLY 0x801826#define BPOWER_THRES 0x3001827#define BRXAGC_EN 0x11828#define BRXAGC_TOGETHER_EN 0x21829#define BRXAGC_MIN 0x41830#define BRXHP_INI 0x71831#define BRXHP_TRLNA 0x701832#define BRXHP_RSSI 0x7001833#define BRXHP_BBP1 0x70001834#define BRXHP_BBP2 0x700001835#define BRXHP_BBP3 0x7000001836#define BRSSI_H 0x7f00001837#define BRSSI_GEN 0x7f0000001838#define BRXSETTLE_TRSW 0x71839#define BRXSETTLE_LNA 0x381840#define BRXSETTLE_RSSI 0x1c01841#define BRXSETTLE_BBP 0xe001842#define BRXSETTLE_RXHP 0x70001843#define BRXSETTLE_ANTSW_RSSI 0x380001844#define BRXSETTLE_ANTSW 0xc00001845#define BRXPROCESS_TIME_DAGC 0x3000001846#define BRXSETTLE_HSSI 0x4000001847#define BRXPROCESS_TIME_BBPPW 0x8000001848#define BRXANTENNA_POWER_SHIFT 0x30000001849#define BRSSI_TABLE_SELECT 0xc0000001850#define BRXHP_FINAL 0x70000001851#define BRXHPSETTLE_BBP 0x71852#define BRXHTSETTLE_HSSI 0x81853#define BRXHTSETTLE_RXHP 0x701854#define BRXHTSETTLE_BBPPW 0x801855#define BRXHTSETTLE_IDLE 0x3001856#define BRXHTSETTLE_RESERVED 0x1c001857#define BRXHT_RXHP_EN 0x80001858#define BRXAGC_FREEZE_THRES 0x300001859#define BRXAGC_TOGETHEREN 0x400001860#define BRXHTAGC_MIN 0x800001861#define BRXHTAGC_EN 0x1000001862#define BRXHTDAGC_EN 0x2000001863#define BRXHT_RXHP_BBP 0x1c000001864#define BRXHT_RXHP_FINAL 0xe00000001865#define BRXPW_RADIO_TH 0x31866#define BRXPW_RADIO_EN 0x41867#define BRXMF_HOLD 0x38001868#define BRXPD_DELAY_TH1 0x381869#define BRXPD_DELAY_TH2 0x1c01870#define BRXPD_DC_COUNT_MAX 0x6001871#define BRXPD_DELAY_TH 0x80001872#define BRXPROCESS_DELAY 0xf00001873#define BRXSEARCHRANGE_GI2_EARLY 0x7000001874#define BRXFRAME_FUARD_COUNTER_L 0x38000001875#define BRXSGI_GUARD_L 0xc0000001876#define BRXSGI_SEARCH_L 0x300000001877#define BRXSGI_TH 0xc00000001878#define BDFSCNT0 0xff1879#define BDFSCNT1 0xff001880#define BDFSFLAG 0xf00001881#define BMF_WEIGHT_SUM 0x3000001882#define BMINIDX_TH 0x7f0000001883#define BDAFORMAT 0x400001884#define BTXCH_EMU_ENABLE 0x010000001885#define BTRSW_ISOLATION_A 0x7f1886#define BTRSW_ISOLATION_B 0x7f001887#define BTRSW_ISOLATION_C 0x7f00001888#define BTRSW_ISOLATION_D 0x7f0000001889#define BEXT_LNA_GAIN 0x7c001890 1891#define BSTBC_EN 0x41892#define BANTENNA_MAPPING 0x101893#define BNSS 0x201894#define BCFO_ANTSUM_ID 0x2001895#define BPHY_COUNTER_RESET 0x80000001896#define BCFO_REPORT_GET 0x40000001897#define BOFDM_CONTINUE_TX 0x100000001898#define BOFDM_SINGLE_CARRIER 0x200000001899#define BOFDM_SINGLE_TONE 0x400000001900#define BHT_DETECT 0x1001901#define BCFOEN 0x100001902#define BCFOVALUE 0xfff000001903#define BSIGTONE_RE 0x3f1904#define BSIGTONE_IM 0x7f001905#define BCOUNTER_CCA 0xffff1906#define BCOUNTER_PARITYFAIL 0xffff00001907#define BCOUNTER_RATEILLEGAL 0xffff1908#define BCOUNTER_CRC8FAIL 0xffff00001909#define BCOUNTER_MCSNOSUPPORT 0xffff1910#define BCOUNTER_FASTSYNC 0xffff1911#define BSHORTCFO 0xfff1912#define BSHORTCFOT_LENGTH 121913#define BSHORTCFOF_LENGTH 111914#define BLONGCFO 0x7ff1915#define BLONGCFOT_LENGTH 111916#define BLONGCFOF_LENGTH 111917#define BTAILCFO 0x1fff1918#define BTAILCFOT_LENGTH 131919#define BTAILCFOF_LENGTH 121920#define BNOISE_EN_PWDB 0xffff1921#define BCC_POWER_DB 0xffff00001922#define BMOISE_PWDB 0xffff1923#define BPOWERMEAST_LENGTH 101924#define BPOWERMEASF_LENGTH 31925#define BRX_HT_BW 0x11926#define BRXSC 0x61927#define BRX_HT 0x81928#define BNB_INTF_DET_ON 0x11929#define BINTF_WIN_LEN_CFG 0x301930#define BNB_INTF_TH_CFG 0x1c01931#define BRFGAIN 0x3f1932#define BTABLESEL 0x401933#define BTRSW 0x801934#define BRXSNR_A 0xff1935#define BRXSNR_B 0xff001936#define BRXSNR_C 0xff00001937#define BRXSNR_D 0xff0000001938#define BSNR_EVMT_LENGTH 81939#define BSNR_EVMF_LENGTH 11940#define BCSI1ST 0xff1941#define BCSI2ND 0xff001942#define BRXEVM1ST 0xff00001943#define BRXEVM2ND 0xff0000001944#define BSIGEVM 0xff1945#define BPWDB 0xff001946#define BSGIEN 0x100001947 1948#define BSFACTOR_QMA1 0xf1949#define BSFACTOR_QMA2 0xf01950#define BSFACTOR_QMA3 0xf001951#define BSFACTOR_QMA4 0xf0001952#define BSFACTOR_QMA5 0xf00001953#define BSFACTOR_QMA6 0xf00001954#define BSFACTOR_QMA7 0xf000001955#define BSFACTOR_QMA8 0xf0000001956#define BSFACTOR_QMA9 0xf00000001957#define BCSI_SCHEME 0x1000001958 1959#define BNOISE_LVL_TOP_SET 0x31960#define BCHSMOOTH 0x41961#define BCHSMOOTH_CFG1 0x381962#define BCHSMOOTH_CFG2 0x1c01963#define BCHSMOOTH_CFG3 0xe001964#define BCHSMOOTH_CFG4 0x70001965#define BMRCMODE 0x8000001966#define BTHEVMCFG 0x70000001967 1968#define BLOOP_FIT_TYPE 0x11969#define BUPD_CFO 0x401970#define BUPD_CFO_OFFDATA 0x801971#define BADV_UPD_CFO 0x1001972#define BADV_TIME_CTRL 0x8001973#define BUPD_CLKO 0x10001974#define BFC 0x60001975#define BTRACKING_MODE 0x80001976#define BPHCMP_ENABLE 0x100001977#define BUPD_CLKO_LTF 0x200001978#define BCOM_CH_CFO 0x400001979#define BCSI_ESTI_MODE 0x800001980#define BADV_UPD_EQZ 0x1000001981#define BUCHCFG 0x70000001982#define BUPDEQZ 0x80000001983 1984#define BRX_PESUDO_NOISE_ON 0x200000001985#define BRX_PESUDO_NOISE_A 0xff1986#define BRX_PESUDO_NOISE_B 0xff001987#define BRX_PESUDO_NOISE_C 0xff00001988#define BRX_PESUDO_NOISE_D 0xff0000001989#define BRX_PESUDO_NOISESTATE_A 0xffff1990#define BRX_PESUDO_NOISESTATE_B 0xffff00001991#define BRX_PESUDO_NOISESTATE_C 0xffff1992#define BRX_PESUDO_NOISESTATE_D 0xffff00001993 1994#define BZEBRA1_HSSIENABLE 0x81995#define BZEBRA1_TRXCONTROL 0xc001996#define BZEBRA1_TRXGAINSETTING 0x07f1997#define BZEBRA1_RXCOUNTER 0xc001998#define BZEBRA1_TXCHANGEPUMP 0x381999#define BZEBRA1_RXCHANGEPUMP 0x72000#define BZEBRA1_CHANNEL_NUM 0xf802001#define BZEBRA1_TXLPFBW 0x4002002#define BZEBRA1_RXLPFBW 0x6002003 2004#define BRTL8256REG_MODE_CTRL1 0x1002005#define BRTL8256REG_MODE_CTRL0 0x402006#define BRTL8256REG_TXLPFBW 0x182007#define BRTL8256REG_RXLPFBW 0x6002008 2009#define BRTL8258_TXLPFBW 0xc2010#define BRTL8258_RXLPFBW 0xc002011#define BRTL8258_RSSILPFBW 0xc02012 2013#define BBYTE0 0x12014#define BBYTE1 0x22015#define BBYTE2 0x42016#define BBYTE3 0x82017#define BWORD0 0x32018#define BWORD1 0xc2019#define BWORD 0xf2020 2021#define BENABLE 0x12022#define BDISABLE 0x02023 2024#define LEFT_ANTENNA 0x02025#define RIGHT_ANTENNA 0x12026 2027#define TCHECK_TXSTATUS 5002028#define TUPDATE_RXCOUNTER 1002029 2030#endif2031