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1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../core.h"6#include "../pci.h"7#include "../base.h"8#include "reg.h"9#include "def.h"10#include "phy.h"11#include "dm.h"12#include "../rtl8192c/dm_common.h"13#include "../rtl8192c/fw_common.h"14#include "../rtl8192c/phy_common.h"15#include "hw.h"16#include "rf.h"17#include "trx.h"18#include "led.h"19 20#include <linux/module.h>21 22static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw)23{24 struct rtl_priv *rtlpriv = rtl_priv(hw);25 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));26 27 /*28 * ASPM PS mode.29 * 0 - Disable ASPM,30 * 1 - Enable ASPM without Clock Req,31 * 2 - Enable ASPM with Clock Req,32 * 3 - Alwyas Enable ASPM with Clock Req,33 * 4 - Always Enable ASPM without Clock Req.34 * set default to RTL8192CE:3 RTL8192E:235 * */36 rtlpci->const_pci_aspm = 3;37 38 /*Setting for PCI-E device */39 rtlpci->const_devicepci_aspm_setting = 0x03;40 41 /*Setting for PCI-E bridge */42 rtlpci->const_hostpci_aspm_setting = 0x02;43 44 /*45 * In Hw/Sw Radio Off situation.46 * 0 - Default,47 * 1 - From ASPM setting without low Mac Pwr,48 * 2 - From ASPM setting with low Mac Pwr,49 * 3 - Bus D350 * set default to RTL8192CE:0 RTL8192SE:251 */52 rtlpci->const_hwsw_rfoff_d3 = 0;53 54 /*55 * This setting works for those device with56 * backdoor ASPM setting such as EPHY setting.57 * 0 - Not support ASPM,58 * 1 - Support ASPM,59 * 2 - According to chipset.60 */61 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;62}63 64static int rtl92c_init_sw_vars(struct ieee80211_hw *hw)65{66 int err;67 struct rtl_priv *rtlpriv = rtl_priv(hw);68 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));69 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));70 char *fw_name;71 72 rtl8192ce_bt_reg_init(hw);73 74 rtlpriv->dm.dm_initialgain_enable = true;75 rtlpriv->dm.dm_flag = 0;76 rtlpriv->dm.disable_framebursting = false;77 rtlpriv->dm.thermalvalue = 0;78 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);79 80 /* compatible 5G band 88ce just 2.4G band & smsp */81 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;82 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;83 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;84 85 rtlpci->receive_config = (RCR_APPFCS |86 RCR_AMF |87 RCR_ADF |88 RCR_APP_MIC |89 RCR_APP_ICV |90 RCR_AICV |91 RCR_ACRC32 |92 RCR_AB |93 RCR_AM |94 RCR_APM |95 RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);96 97 rtlpci->irq_mask[0] =98 (u32) (IMR_ROK |99 IMR_VODOK |100 IMR_VIDOK |101 IMR_BEDOK |102 IMR_BKDOK |103 IMR_MGNTDOK |104 IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);105 106 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);107 108 /* for LPS & IPS */109 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;110 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;111 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;112 if (!rtlpriv->psc.inactiveps)113 pr_info("rtl8192ce: Power Save off (module option)\n");114 if (!rtlpriv->psc.fwctrl_lps)115 pr_info("rtl8192ce: FW Power Save off (module option)\n");116 rtlpriv->psc.reg_fwctrl_lps = 3;117 rtlpriv->psc.reg_max_lps_awakeintvl = 5;118 /* for ASPM, you can close aspm through119 * set const_support_pciaspm = 0 */120 rtl92c_init_aspm_vars(hw);121 122 if (rtlpriv->psc.reg_fwctrl_lps == 1)123 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;124 else if (rtlpriv->psc.reg_fwctrl_lps == 2)125 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;126 else if (rtlpriv->psc.reg_fwctrl_lps == 3)127 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;128 129 /* for firmware buf */130 rtlpriv->rtlhal.pfirmware = vzalloc(0x4000);131 if (!rtlpriv->rtlhal.pfirmware) {132 pr_err("Can't alloc buffer for fw\n");133 return 1;134 }135 136 /* request fw */137 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&138 !IS_92C_SERIAL(rtlhal->version))139 fw_name = "rtlwifi/rtl8192cfwU.bin";140 else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))141 fw_name = "rtlwifi/rtl8192cfwU_B.bin";142 else143 fw_name = "rtlwifi/rtl8192cfw.bin";144 145 rtlpriv->max_fw_size = 0x4000;146 pr_info("Using firmware %s\n", fw_name);147 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,148 rtlpriv->io.dev, GFP_KERNEL, hw,149 rtl_fw_cb);150 if (err) {151 pr_err("Failed to request firmware!\n");152 vfree(rtlpriv->rtlhal.pfirmware);153 rtlpriv->rtlhal.pfirmware = NULL;154 return 1;155 }156 157 return 0;158}159 160static void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)161{162 struct rtl_priv *rtlpriv = rtl_priv(hw);163 164 if (rtlpriv->rtlhal.pfirmware) {165 vfree(rtlpriv->rtlhal.pfirmware);166 rtlpriv->rtlhal.pfirmware = NULL;167 }168}169 170static struct rtl_hal_ops rtl8192ce_hal_ops = {171 .init_sw_vars = rtl92c_init_sw_vars,172 .deinit_sw_vars = rtl92c_deinit_sw_vars,173 .read_eeprom_info = rtl92ce_read_eeprom_info,174 .interrupt_recognized = rtl92ce_interrupt_recognized,175 .hw_init = rtl92ce_hw_init,176 .hw_disable = rtl92ce_card_disable,177 .hw_suspend = rtl92ce_suspend,178 .hw_resume = rtl92ce_resume,179 .enable_interrupt = rtl92ce_enable_interrupt,180 .disable_interrupt = rtl92ce_disable_interrupt,181 .set_network_type = rtl92ce_set_network_type,182 .set_chk_bssid = rtl92ce_set_check_bssid,183 .set_qos = rtl92ce_set_qos,184 .set_bcn_reg = rtl92ce_set_beacon_related_registers,185 .set_bcn_intv = rtl92ce_set_beacon_interval,186 .update_interrupt_mask = rtl92ce_update_interrupt_mask,187 .get_hw_reg = rtl92ce_get_hw_reg,188 .set_hw_reg = rtl92ce_set_hw_reg,189 .update_rate_tbl = rtl92ce_update_hal_rate_tbl,190 .fill_tx_desc = rtl92ce_tx_fill_desc,191 .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,192 .query_rx_desc = rtl92ce_rx_query_desc,193 .set_channel_access = rtl92ce_update_channel_access_setting,194 .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,195 .set_bw_mode = rtl92c_phy_set_bw_mode,196 .switch_channel = rtl92c_phy_sw_chnl,197 .dm_watchdog = rtl92c_dm_watchdog,198 .scan_operation_backup = rtl_phy_scan_operation_backup,199 .set_rf_power_state = rtl92c_phy_set_rf_power_state,200 .led_control = rtl92ce_led_control,201 .set_desc = rtl92ce_set_desc,202 .get_desc = rtl92ce_get_desc,203 .is_tx_desc_closed = rtl92ce_is_tx_desc_closed,204 .tx_polling = rtl92ce_tx_polling,205 .enable_hw_sec = rtl92ce_enable_hw_security_config,206 .set_key = rtl92ce_set_key,207 .get_bbreg = rtl92c_phy_query_bb_reg,208 .set_bbreg = rtl92c_phy_set_bb_reg,209 .set_rfreg = rtl92ce_phy_set_rf_reg,210 .get_rfreg = rtl92c_phy_query_rf_reg,211 .phy_rf6052_config = rtl92ce_phy_rf6052_config,212 .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,213 .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,214 .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,215 .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,216 .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,217 .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,218 .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,219 .get_btc_status = rtl_btc_status_false,220};221 222static struct rtl_mod_params rtl92ce_mod_params = {223 .sw_crypto = false,224 .inactiveps = true,225 .swctrl_lps = false,226 .fwctrl_lps = true,227 .aspm_support = 1,228 .debug_level = 0,229 .debug_mask = 0,230};231 232static const struct rtl_hal_cfg rtl92ce_hal_cfg = {233 .bar_id = 2,234 .write_readback = true,235 .name = "rtl92c_pci",236 .ops = &rtl8192ce_hal_ops,237 .mod_params = &rtl92ce_mod_params,238 239 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,240 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,241 .maps[SYS_CLK] = REG_SYS_CLKR,242 .maps[MAC_RCR_AM] = AM,243 .maps[MAC_RCR_AB] = AB,244 .maps[MAC_RCR_ACRC32] = ACRC32,245 .maps[MAC_RCR_ACF] = ACF,246 .maps[MAC_RCR_AAP] = AAP,247 .maps[MAC_HIMR] = REG_HIMR,248 .maps[MAC_HIMRE] = REG_HIMRE,249 250 .maps[EFUSE_TEST] = REG_EFUSE_TEST,251 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,252 .maps[EFUSE_CLK] = 0,253 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,254 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,255 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,256 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,257 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,258 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,259 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,260 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,261 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,262 263 .maps[RWCAM] = REG_CAMCMD,264 .maps[WCAMI] = REG_CAMWRITE,265 .maps[RCAMO] = REG_CAMREAD,266 .maps[CAMDBG] = REG_CAMDBG,267 .maps[SECR] = REG_SECCFG,268 .maps[SEC_CAM_NONE] = CAM_NONE,269 .maps[SEC_CAM_WEP40] = CAM_WEP40,270 .maps[SEC_CAM_TKIP] = CAM_TKIP,271 .maps[SEC_CAM_AES] = CAM_AES,272 .maps[SEC_CAM_WEP104] = CAM_WEP104,273 274 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,275 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,276 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,277 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,278 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,279 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,280 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,281 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,282 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,283 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,284 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,285 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,286 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,287 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,288 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,289 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,290 291 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,292 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,293 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,294 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,295 .maps[RTL_IMR_RDU] = IMR_RDU,296 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,297 .maps[RTL_IMR_BDOK] = IMR_BDOK,298 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,299 .maps[RTL_IMR_TBDER] = IMR_TBDER,300 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,301 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,302 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,303 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,304 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,305 .maps[RTL_IMR_VODOK] = IMR_VODOK,306 .maps[RTL_IMR_ROK] = IMR_ROK,307 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),308 309 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,310 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,311 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,312 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,313 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,314 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,315 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,316 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,317 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,318 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,319 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,320 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,321 322 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,323 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,324};325 326static const struct pci_device_id rtl92ce_pci_ids[] = {327 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},328 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},329 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},330 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},331 {},332};333 334MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);335 336MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");337MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");338MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");339MODULE_LICENSE("GPL");340MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");341MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");342MODULE_FIRMWARE("rtlwifi/rtl8192cfwU.bin");343MODULE_FIRMWARE("rtlwifi/rtl8192cfwU_B.bin");344 345module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);346module_param_named(debug_level, rtl92ce_mod_params.debug_level, int, 0644);347module_param_named(debug_mask, rtl92ce_mod_params.debug_mask, ullong, 0644);348module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444);349module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444);350module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444);351module_param_named(aspm, rtl92ce_mod_params.aspm_support, int, 0444);352MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");353MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");354MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");355MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");356MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");357MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");358MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");359 360static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);361 362static struct pci_driver rtl92ce_driver = {363 .name = KBUILD_MODNAME,364 .id_table = rtl92ce_pci_ids,365 .probe = rtl_pci_probe,366 .remove = rtl_pci_disconnect,367 .driver.pm = &rtlwifi_pm_ops,368};369 370module_pci_driver(rtl92ce_driver);371