2183 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../efuse.h"6#include "../base.h"7#include "../cam.h"8#include "../ps.h"9#include "../usb.h"10#include "reg.h"11#include "def.h"12#include "phy.h"13#include "../rtl8192c/phy_common.h"14#include "mac.h"15#include "dm.h"16#include "../rtl8192c/dm_common.h"17#include "../rtl8192c/fw_common.h"18#include "hw.h"19#include "../rtl8192ce/hw.h"20#include "trx.h"21#include "led.h"22#include "table.h"23 24static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)25{26 struct rtl_priv *rtlpriv = rtl_priv(hw);27 struct rtl_phy *rtlphy = &(rtlpriv->phy);28 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);29 30 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;31 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;32 if (IS_HIGHT_PA(rtlefuse->board_type)) {33 rtlphy->hwparam_tables[PHY_REG_PG].length =34 RTL8192CUPHY_REG_ARRAY_PG_HPLENGTH;35 rtlphy->hwparam_tables[PHY_REG_PG].pdata =36 RTL8192CUPHY_REG_ARRAY_PG_HP;37 } else {38 rtlphy->hwparam_tables[PHY_REG_PG].length =39 RTL8192CUPHY_REG_ARRAY_PGLENGTH;40 rtlphy->hwparam_tables[PHY_REG_PG].pdata =41 RTL8192CUPHY_REG_ARRAY_PG;42 }43 /* 2T */44 rtlphy->hwparam_tables[PHY_REG_2T].length =45 RTL8192CUPHY_REG_2TARRAY_LENGTH;46 rtlphy->hwparam_tables[PHY_REG_2T].pdata =47 RTL8192CUPHY_REG_2TARRAY;48 rtlphy->hwparam_tables[RADIOA_2T].length =49 RTL8192CURADIOA_2TARRAYLENGTH;50 rtlphy->hwparam_tables[RADIOA_2T].pdata =51 RTL8192CURADIOA_2TARRAY;52 rtlphy->hwparam_tables[RADIOB_2T].length =53 RTL8192CURADIOB_2TARRAYLENGTH;54 rtlphy->hwparam_tables[RADIOB_2T].pdata =55 RTL8192CU_RADIOB_2TARRAY;56 rtlphy->hwparam_tables[AGCTAB_2T].length =57 RTL8192CUAGCTAB_2TARRAYLENGTH;58 rtlphy->hwparam_tables[AGCTAB_2T].pdata =59 RTL8192CUAGCTAB_2TARRAY;60 /* 1T */61 if (IS_HIGHT_PA(rtlefuse->board_type)) {62 rtlphy->hwparam_tables[PHY_REG_1T].length =63 RTL8192CUPHY_REG_1T_HPARRAYLENGTH;64 rtlphy->hwparam_tables[PHY_REG_1T].pdata =65 RTL8192CUPHY_REG_1T_HPARRAY;66 rtlphy->hwparam_tables[RADIOA_1T].length =67 RTL8192CURADIOA_1T_HPARRAYLENGTH;68 rtlphy->hwparam_tables[RADIOA_1T].pdata =69 RTL8192CURADIOA_1T_HPARRAY;70 rtlphy->hwparam_tables[RADIOB_1T].length =71 RTL8192CURADIOB_1TARRAYLENGTH;72 rtlphy->hwparam_tables[RADIOB_1T].pdata =73 RTL8192CU_RADIOB_1TARRAY;74 rtlphy->hwparam_tables[AGCTAB_1T].length =75 RTL8192CUAGCTAB_1T_HPARRAYLENGTH;76 rtlphy->hwparam_tables[AGCTAB_1T].pdata =77 RTL8192CUAGCTAB_1T_HPARRAY;78 } else {79 rtlphy->hwparam_tables[PHY_REG_1T].length =80 RTL8192CUPHY_REG_1TARRAY_LENGTH;81 rtlphy->hwparam_tables[PHY_REG_1T].pdata =82 RTL8192CUPHY_REG_1TARRAY;83 rtlphy->hwparam_tables[RADIOA_1T].length =84 RTL8192CURADIOA_1TARRAYLENGTH;85 rtlphy->hwparam_tables[RADIOA_1T].pdata =86 RTL8192CU_RADIOA_1TARRAY;87 rtlphy->hwparam_tables[RADIOB_1T].length =88 RTL8192CURADIOB_1TARRAYLENGTH;89 rtlphy->hwparam_tables[RADIOB_1T].pdata =90 RTL8192CU_RADIOB_1TARRAY;91 rtlphy->hwparam_tables[AGCTAB_1T].length =92 RTL8192CUAGCTAB_1TARRAYLENGTH;93 rtlphy->hwparam_tables[AGCTAB_1T].pdata =94 RTL8192CUAGCTAB_1TARRAY;95 }96}97 98static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,99 bool autoload_fail,100 u8 *hwinfo)101{102 struct rtl_priv *rtlpriv = rtl_priv(hw);103 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));104 u8 rf_path, index, tempval;105 u16 i;106 107 for (rf_path = 0; rf_path < 2; rf_path++) {108 for (i = 0; i < 3; i++) {109 if (!autoload_fail) {110 rtlefuse->111 eeprom_chnlarea_txpwr_cck[rf_path][i] =112 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];113 rtlefuse->114 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =115 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +116 i];117 } else {118 rtlefuse->119 eeprom_chnlarea_txpwr_cck[rf_path][i] =120 EEPROM_DEFAULT_TXPOWERLEVEL;121 rtlefuse->122 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =123 EEPROM_DEFAULT_TXPOWERLEVEL;124 }125 }126 }127 for (i = 0; i < 3; i++) {128 if (!autoload_fail)129 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];130 else131 tempval = EEPROM_DEFAULT_HT40_2SDIFF;132 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =133 (tempval & 0xf);134 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =135 ((tempval & 0xf0) >> 4);136 }137 for (rf_path = 0; rf_path < 2; rf_path++)138 for (i = 0; i < 3; i++)139 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,140 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",141 rf_path, i,142 rtlefuse->143 eeprom_chnlarea_txpwr_cck[rf_path][i]);144 for (rf_path = 0; rf_path < 2; rf_path++)145 for (i = 0; i < 3; i++)146 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,147 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",148 rf_path, i,149 rtlefuse->150 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);151 for (rf_path = 0; rf_path < 2; rf_path++)152 for (i = 0; i < 3; i++)153 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,154 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",155 rf_path, i,156 rtlefuse->157 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);158 for (rf_path = 0; rf_path < 2; rf_path++) {159 for (i = 0; i < 14; i++) {160 index = rtl92c_get_chnl_group((u8)i);161 rtlefuse->txpwrlevel_cck[rf_path][i] =162 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];163 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =164 rtlefuse->165 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];166 if ((rtlefuse->167 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -168 rtlefuse->169 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])170 > 0) {171 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =172 rtlefuse->173 eeprom_chnlarea_txpwr_ht40_1s[rf_path]174 [index] - rtlefuse->175 eprom_chnl_txpwr_ht40_2sdf[rf_path]176 [index];177 } else {178 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;179 }180 }181 for (i = 0; i < 14; i++) {182 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,183 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,184 rtlefuse->txpwrlevel_cck[rf_path][i],185 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],186 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);187 }188 }189 for (i = 0; i < 3; i++) {190 if (!autoload_fail) {191 rtlefuse->eeprom_pwrlimit_ht40[i] =192 hwinfo[EEPROM_TXPWR_GROUP + i];193 rtlefuse->eeprom_pwrlimit_ht20[i] =194 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];195 } else {196 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;197 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;198 }199 }200 for (rf_path = 0; rf_path < 2; rf_path++) {201 for (i = 0; i < 14; i++) {202 index = rtl92c_get_chnl_group((u8)i);203 if (rf_path == RF90_PATH_A) {204 rtlefuse->pwrgroup_ht20[rf_path][i] =205 (rtlefuse->eeprom_pwrlimit_ht20[index]206 & 0xf);207 rtlefuse->pwrgroup_ht40[rf_path][i] =208 (rtlefuse->eeprom_pwrlimit_ht40[index]209 & 0xf);210 } else if (rf_path == RF90_PATH_B) {211 rtlefuse->pwrgroup_ht20[rf_path][i] =212 ((rtlefuse->eeprom_pwrlimit_ht20[index]213 & 0xf0) >> 4);214 rtlefuse->pwrgroup_ht40[rf_path][i] =215 ((rtlefuse->eeprom_pwrlimit_ht40[index]216 & 0xf0) >> 4);217 }218 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,219 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",220 rf_path, i,221 rtlefuse->pwrgroup_ht20[rf_path][i]);222 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,223 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",224 rf_path, i,225 rtlefuse->pwrgroup_ht40[rf_path][i]);226 }227 }228 for (i = 0; i < 14; i++) {229 index = rtl92c_get_chnl_group((u8)i);230 if (!autoload_fail)231 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];232 else233 tempval = EEPROM_DEFAULT_HT20_DIFF;234 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);235 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =236 ((tempval >> 4) & 0xF);237 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))238 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;239 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))240 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;241 index = rtl92c_get_chnl_group((u8)i);242 if (!autoload_fail)243 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];244 else245 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;246 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);247 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =248 ((tempval >> 4) & 0xF);249 }250 rtlefuse->legacy_ht_txpowerdiff =251 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];252 for (i = 0; i < 14; i++)253 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,254 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",255 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);256 for (i = 0; i < 14; i++)257 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,258 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",259 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);260 for (i = 0; i < 14; i++)261 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,262 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",263 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);264 for (i = 0; i < 14; i++)265 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,266 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",267 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);268 if (!autoload_fail)269 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);270 else271 rtlefuse->eeprom_regulatory = 0;272 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,273 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);274 if (!autoload_fail) {275 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];276 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];277 } else {278 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;279 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;280 }281 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,282 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",283 rtlefuse->eeprom_tssi[RF90_PATH_A],284 rtlefuse->eeprom_tssi[RF90_PATH_B]);285 if (!autoload_fail)286 tempval = hwinfo[EEPROM_THERMAL_METER];287 else288 tempval = EEPROM_DEFAULT_THERMALMETER;289 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);290 if (rtlefuse->eeprom_thermalmeter < 0x06 ||291 rtlefuse->eeprom_thermalmeter > 0x1c)292 rtlefuse->eeprom_thermalmeter = 0x12;293 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)294 rtlefuse->apk_thermalmeterignore = true;295 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;296 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,297 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);298}299 300static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)301{302 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));303 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));304 u8 boardtype;305 306 if (IS_NORMAL_CHIP(rtlhal->version)) {307 boardtype = ((contents[EEPROM_RF_OPT1]) &308 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/309 } else {310 boardtype = contents[EEPROM_RF_OPT4];311 boardtype &= BOARD_TYPE_TEST_MASK;312 }313 rtlefuse->board_type = boardtype;314 if (IS_HIGHT_PA(rtlefuse->board_type))315 rtlefuse->external_pa = 1;316 pr_info("Board Type %x\n", rtlefuse->board_type);317}318 319static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)320{321 struct rtl_priv *rtlpriv = rtl_priv(hw);322 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));323 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));324 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,325 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,326 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,327 0};328 u8 *hwinfo;329 330 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);331 if (!hwinfo)332 return;333 334 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))335 goto exit;336 337 _rtl92cu_read_txpower_info_from_hwpg(hw,338 rtlefuse->autoload_failflag, hwinfo);339 _rtl92cu_read_board_type(hw, hwinfo);340 341 rtlefuse->txpwr_fromeprom = true;342 if (rtlhal->oem_id == RT_CID_DEFAULT) {343 switch (rtlefuse->eeprom_oemid) {344 case EEPROM_CID_DEFAULT:345 if (rtlefuse->eeprom_did == 0x8176) {346 if ((rtlefuse->eeprom_svid == 0x103C &&347 rtlefuse->eeprom_smid == 0x1629))348 rtlhal->oem_id = RT_CID_819X_HP;349 else350 rtlhal->oem_id = RT_CID_DEFAULT;351 } else {352 rtlhal->oem_id = RT_CID_DEFAULT;353 }354 break;355 case EEPROM_CID_TOSHIBA:356 rtlhal->oem_id = RT_CID_TOSHIBA;357 break;358 case EEPROM_CID_QMI:359 rtlhal->oem_id = RT_CID_819X_QMI;360 break;361 case EEPROM_CID_WHQL:362 default:363 rtlhal->oem_id = RT_CID_DEFAULT;364 break;365 }366 }367exit:368 kfree(hwinfo);369}370 371static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)372{373 struct rtl_priv *rtlpriv = rtl_priv(hw);374 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));375 376 switch (rtlhal->oem_id) {377 case RT_CID_819X_HP:378 rtlpriv->ledctl.led_opendrain = true;379 break;380 case RT_CID_819X_LENOVO:381 case RT_CID_DEFAULT:382 case RT_CID_TOSHIBA:383 case RT_CID_CCX:384 case RT_CID_819X_ACER:385 case RT_CID_WHQL:386 default:387 break;388 }389 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",390 rtlhal->oem_id);391}392 393void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)394{395 396 struct rtl_priv *rtlpriv = rtl_priv(hw);397 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));398 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));399 u8 tmp_u1b;400 401 if (!IS_NORMAL_CHIP(rtlhal->version))402 return;403 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);404 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?405 EEPROM_93C46 : EEPROM_BOOT_EFUSE;406 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",407 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");408 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;409 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",410 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");411 _rtl92cu_read_adapter_info(hw);412 _rtl92cu_hal_customized_behavior(hw);413 return;414}415 416static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)417{418 struct rtl_priv *rtlpriv = rtl_priv(hw);419 int status = 0;420 u16 value16;421 u8 value8;422 /* polling autoload done. */423 u32 pollingcount = 0;424 425 do {426 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {427 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,428 "Autoload Done!\n");429 break;430 }431 if (pollingcount++ > 100) {432 pr_err("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");433 return -ENODEV;434 }435 } while (true);436 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */437 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);438 /* Power on when re-enter from IPS/Radio off/card disable */439 /* enable SPS into PWM mode */440 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);441 udelay(100);442 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);443 if (0 == (value8 & LDV12_EN)) {444 value8 |= LDV12_EN;445 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);446 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,447 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",448 value8);449 udelay(100);450 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);451 value8 &= ~ISO_MD2PP;452 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);453 }454 /* auto enable WLAN */455 pollingcount = 0;456 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);457 value16 |= APFM_ONMAC;458 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);459 do {460 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {461 pr_info("MAC auto ON okay!\n");462 break;463 }464 if (pollingcount++ > 1000) {465 pr_err("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");466 return -ENODEV;467 }468 } while (true);469 /* Enable Radio ,GPIO ,and LED function */470 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);471 /* release RF digital isolation */472 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);473 value16 &= ~ISO_DIOR;474 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);475 /* Reconsider when to do this operation after asking HWSD. */476 pollingcount = 0;477 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,478 REG_APSD_CTRL) & ~BIT(6)));479 do {480 pollingcount++;481 } while ((pollingcount < 200) &&482 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));483 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */484 value16 = rtl_read_word(rtlpriv, REG_CR);485 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |486 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);487 rtl_write_word(rtlpriv, REG_CR, value16);488 return status;489}490 491static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,492 u8 out_ep_num,493 u8 queue_sel)494{495 struct rtl_priv *rtlpriv = rtl_priv(hw);496 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));497 bool ischipn = IS_NORMAL_CHIP(rtlhal->version);498 u32 outepnum = (u32)out_ep_num;499 u32 numhq = 0;500 u32 numlq = 0;501 u32 numnq = 0;502 u32 numpubq;503 u32 value32;504 u8 value8;505 u32 txqpagenum, txqpageunit, txqremaininpage;506 507 numpubq = (ischipn) ? CHIP_B_PAGE_NUM_PUBQ :508 CHIP_A_PAGE_NUM_PUBQ;509 txqpagenum = TX_TOTAL_PAGE_NUMBER - numpubq;510 511 txqpageunit = txqpagenum / outepnum;512 txqremaininpage = txqpagenum % outepnum;513 if (queue_sel & TX_SELE_HQ)514 numhq = txqpageunit;515 if (queue_sel & TX_SELE_LQ)516 numlq = txqpageunit;517 /* HIGH priority queue always present in the configuration of518 * 2 out-ep. Remainder pages have assigned to High queue.519 */520 if (outepnum > 1 && txqremaininpage)521 numhq += txqremaininpage;522 /* NOTE: This step done before writing REG_RQPN. */523 if (ischipn) {524 if (queue_sel & TX_SELE_NQ)525 numnq = txqpageunit;526 value8 = (u8)_NPQ(numnq);527 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);528 }529 /* TX DMA */530 value32 = _HPQ(numhq) | _LPQ(numlq) | _PUBQ(numpubq) | LD_RQPN;531 rtl_write_dword(rtlpriv, REG_RQPN, value32);532}533 534static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw)535{536 struct rtl_priv *rtlpriv = rtl_priv(hw);537 u8 txpktbuf_bndy = TX_PAGE_BOUNDARY;538 u8 value8;539 540 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);541 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);542 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);543 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);544 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);545 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);546 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);547 rtl_write_byte(rtlpriv, REG_PBP, value8);548}549 550static void _rtl92c_init_chipn_reg_priority(struct ieee80211_hw *hw, u16 beq,551 u16 bkq, u16 viq, u16 voq,552 u16 mgtq, u16 hiq)553{554 struct rtl_priv *rtlpriv = rtl_priv(hw);555 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);556 557 value16 |= _TXDMA_BEQ_MAP(beq) | _TXDMA_BKQ_MAP(bkq) |558 _TXDMA_VIQ_MAP(viq) | _TXDMA_VOQ_MAP(voq) |559 _TXDMA_MGQ_MAP(mgtq) | _TXDMA_HIQ_MAP(hiq);560 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);561}562 563static void _rtl92cu_init_chipn_one_out_ep_priority(struct ieee80211_hw *hw,564 u8 queue_sel)565{566 u16 value;567 568 switch (queue_sel) {569 case TX_SELE_HQ:570 value = QUEUE_HIGH;571 break;572 case TX_SELE_LQ:573 value = QUEUE_LOW;574 break;575 case TX_SELE_NQ:576 value = QUEUE_NORMAL;577 break;578 default:579 WARN_ON(1); /* Shall not reach here! */580 return;581 }582 _rtl92c_init_chipn_reg_priority(hw, value, value, value, value,583 value, value);584 pr_info("Tx queue select: 0x%02x\n", queue_sel);585}586 587static void _rtl92cu_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw,588 u8 queue_sel)589{590 u16 beq, bkq, viq, voq, mgtq, hiq;591 u16 valuehi;592 u16 valuelow;593 594 switch (queue_sel) {595 default:596 WARN_ON(1);597 fallthrough;598 case (TX_SELE_HQ | TX_SELE_LQ):599 valuehi = QUEUE_HIGH;600 valuelow = QUEUE_LOW;601 break;602 case (TX_SELE_NQ | TX_SELE_LQ):603 valuehi = QUEUE_NORMAL;604 valuelow = QUEUE_LOW;605 break;606 case (TX_SELE_HQ | TX_SELE_NQ):607 valuehi = QUEUE_HIGH;608 valuelow = QUEUE_NORMAL;609 break;610 }611 612 beq = valuelow;613 bkq = valuelow;614 viq = valuehi;615 voq = valuehi;616 mgtq = valuehi;617 hiq = valuehi;618 619 _rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq);620 pr_info("Tx queue select: 0x%02x\n", queue_sel);621}622 623static void _rtl92cu_init_chipn_three_out_ep_priority(struct ieee80211_hw *hw,624 u8 queue_sel)625{626 u16 beq, bkq, viq, voq, mgtq, hiq;627 628 beq = QUEUE_LOW;629 bkq = QUEUE_LOW;630 viq = QUEUE_NORMAL;631 voq = QUEUE_HIGH;632 mgtq = QUEUE_HIGH;633 hiq = QUEUE_HIGH;634 635 _rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq);636 pr_info("Tx queue select :0x%02x..\n", queue_sel);637}638 639static void _rtl92cu_init_chipn_queue_priority(struct ieee80211_hw *hw,640 u8 out_ep_num,641 u8 queue_sel)642{643 switch (out_ep_num) {644 case 1:645 _rtl92cu_init_chipn_one_out_ep_priority(hw, queue_sel);646 break;647 case 2:648 _rtl92cu_init_chipn_two_out_ep_priority(hw, queue_sel);649 break;650 case 3:651 _rtl92cu_init_chipn_three_out_ep_priority(hw, queue_sel);652 break;653 default:654 WARN_ON(1); /* Shall not reach here! */655 break;656 }657}658 659static void _rtl92cu_init_chipt_queue_priority(struct ieee80211_hw *hw,660 u8 out_ep_num,661 u8 queue_sel)662{663 u8 hq_sele = 0;664 struct rtl_priv *rtlpriv = rtl_priv(hw);665 666 switch (out_ep_num) {667 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */668 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | HQSEL_HIQ;669 break;670 case 1:671 if (TX_SELE_LQ == queue_sel) {672 /* map all endpoint to Low queue */673 hq_sele = 0;674 } else if (TX_SELE_HQ == queue_sel) {675 /* map all endpoint to High queue */676 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |677 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;678 }679 break;680 default:681 WARN_ON(1); /* Shall not reach here! */682 break;683 }684 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);685 pr_info("Tx queue select :0x%02x..\n", hq_sele);686}687 688static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,689 u8 out_ep_num,690 u8 queue_sel)691{692 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));693 694 if (IS_NORMAL_CHIP(rtlhal->version))695 _rtl92cu_init_chipn_queue_priority(hw, out_ep_num, queue_sel);696 else697 _rtl92cu_init_chipt_queue_priority(hw, out_ep_num, queue_sel);698}699 700static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)701{702 u16 value16;703 u32 value32;704 struct rtl_priv *rtlpriv = rtl_priv(hw);705 706 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |707 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |708 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);709 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32));710 /* Accept all multicast address */711 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);712 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);713 /* Accept all management frames */714 value16 = 0xFFFF;715 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER,716 (u8 *)(&value16));717 /* Reject all control frame - default value is 0 */718 value16 = 0x0;719 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER,720 (u8 *)(&value16));721 /* Accept all data frames */722 value16 = 0xFFFF;723 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER,724 (u8 *)(&value16));725}726 727static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw)728{729 struct rtl_priv *rtlpriv = rtl_priv(hw);730 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);731 732 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);733 734 /* TODO: Remove these magic number */735 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);736 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);737 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);738 /* Change beacon AIFS to the largest number739 * beacause test chip does not contension before sending beacon.740 */741 if (IS_NORMAL_CHIP(rtlhal->version))742 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);743 else744 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);745}746 747static int _rtl92cu_init_mac(struct ieee80211_hw *hw)748{749 struct rtl_priv *rtlpriv = rtl_priv(hw);750 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));751 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);752 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);753 int err = 0;754 u32 boundary = TX_PAGE_BOUNDARY;755 u8 out_ep_nums = rtlusb->out_ep_nums;756 u8 queue_sel = rtlusb->out_queue_sel;757 758 err = _rtl92cu_init_power_on(hw);759 760 if (err) {761 pr_err("Failed to init power on!\n");762 return err;763 }764 if (!rtl92c_init_llt_table(hw, boundary)) {765 pr_err("Failed to init LLT Table!\n");766 return -EINVAL;767 }768 _rtl92cu_init_queue_reserved_page(hw, out_ep_nums, queue_sel);769 _rtl92c_init_trx_buffer(hw);770 _rtl92cu_init_queue_priority(hw, out_ep_nums, queue_sel);771 /* Get Rx PHY status in order to report RSSI and others. */772 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);773 rtl92c_init_interrupt(hw);774 rtl92c_init_network_type(hw);775 _rtl92cu_init_wmac_setting(hw);776 rtl92c_init_adaptive_ctrl(hw);777 rtl92c_init_edca(hw);778 rtl92c_init_rate_fallback(hw);779 rtl92c_init_retry_function(hw);780 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);781 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));782 _rtl92cu_init_beacon_parameters(hw);783 rtl92c_init_ampdu_aggregation(hw);784 rtl92c_init_beacon_max_error(hw);785 return err;786}787 788void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)789{790 struct rtl_priv *rtlpriv = rtl_priv(hw);791 u8 sec_reg_value = 0x0;792 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);793 794 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,795 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",796 rtlpriv->sec.pairwise_enc_algorithm,797 rtlpriv->sec.group_enc_algorithm);798 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {799 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,800 "not open sw encryption\n");801 return;802 }803 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;804 if (rtlpriv->sec.use_defaultkey) {805 sec_reg_value |= SCR_TXUSEDK;806 sec_reg_value |= SCR_RXUSEDK;807 }808 if (IS_NORMAL_CHIP(rtlhal->version))809 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);810 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);811 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",812 sec_reg_value);813 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);814}815 816static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)817{818 struct rtl_priv *rtlpriv = rtl_priv(hw);819 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));820 821 /* To Fix MAC loopback mode fail. */822 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);823 rtl_write_byte(rtlpriv, 0x15, 0xe9);824 /* HW SEQ CTRL */825 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */826 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);827 /* fixed USB interface interference issue */828 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);829 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);830 rtl_write_byte(rtlpriv, 0xfe42, 0x80);831 rtlusb->reg_bcn_ctrl_val = 0x18;832 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);833}834 835static void _initpabias(struct ieee80211_hw *hw)836{837 struct rtl_priv *rtlpriv = rtl_priv(hw);838 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));839 u8 pa_setting;840 841 /* FIXED PA current issue */842 pa_setting = efuse_read_1byte(hw, 0x1FA);843 if (!(pa_setting & BIT(0))) {844 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);845 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);846 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);847 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);848 }849 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&850 IS_92C_SERIAL(rtlhal->version)) {851 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);852 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);853 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);854 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);855 }856 if (!(pa_setting & BIT(4))) {857 pa_setting = rtl_read_byte(rtlpriv, 0x16);858 pa_setting &= 0x0F;859 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);860 }861}862 863int rtl92cu_hw_init(struct ieee80211_hw *hw)864{865 struct rtl_priv *rtlpriv = rtl_priv(hw);866 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));867 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));868 struct rtl_phy *rtlphy = &(rtlpriv->phy);869 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));870 int err = 0;871 unsigned long flags;872 873 /* As this function can take a very long time (up to 350 ms)874 * and can be called with irqs disabled, reenable the irqs875 * to let the other devices continue being serviced.876 *877 * It is safe doing so since our own interrupts will only be enabled878 * in a subsequent step.879 */880 local_save_flags(flags);881 local_irq_enable();882 883 rtlhal->fw_ready = false;884 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;885 err = _rtl92cu_init_mac(hw);886 if (err) {887 pr_err("init mac failed!\n");888 goto exit;889 }890 err = rtl92c_download_fw(hw);891 if (err) {892 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,893 "Failed to download FW. Init HW without FW now..\n");894 err = 1;895 goto exit;896 }897 898 rtlhal->fw_ready = true;899 rtlhal->last_hmeboxnum = 0; /* h2c */900 _rtl92cu_phy_param_tab_init(hw);901 rtl92cu_phy_mac_config(hw);902 rtl92cu_phy_bb_config(hw);903 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;904 rtl92c_phy_rf_config(hw);905 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&906 !IS_92C_SERIAL(rtlhal->version)) {907 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);908 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);909 }910 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,911 RF_CHNLBW, RFREG_OFFSET_MASK);912 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,913 RF_CHNLBW, RFREG_OFFSET_MASK);914 rtl92cu_bb_block_on(hw);915 rtl_cam_reset_all_entry(hw);916 rtl92cu_enable_hw_security_config(hw);917 ppsc->rfpwr_state = ERFON;918 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);919 if (ppsc->rfpwr_state == ERFON) {920 rtl92c_phy_set_rfpath_switch(hw, 1);921 if (rtlphy->iqk_initialized) {922 rtl92c_phy_iq_calibrate(hw, true);923 } else {924 rtl92c_phy_iq_calibrate(hw, false);925 rtlphy->iqk_initialized = true;926 }927 rtl92c_dm_check_txpower_tracking(hw);928 rtl92c_phy_lc_calibrate(hw);929 }930 _rtl92cu_hw_configure(hw);931 _initpabias(hw);932 rtl92c_dm_init(hw);933exit:934 local_irq_disable();935 local_irq_restore(flags);936 return err;937}938 939static void disable_rfafeandresetbb(struct ieee80211_hw *hw)940{941 struct rtl_priv *rtlpriv = rtl_priv(hw);942/**************************************943a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue944b. RF path 0 offset 0x00 = 0x00 disable RF945c. APSD_CTRL 0x600[7:0] = 0x40946d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine947e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine948***************************************/949 u8 erfpath = 0, value8 = 0;950 951 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);952 rtl_set_rfreg(hw, (enum radio_path)erfpath, 0x0, MASKBYTE0, 0x0);953 954 value8 |= APSDOFF;955 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/956 value8 = 0;957 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTN);958 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/959 value8 &= (~FEN_BB_GLB_RSTN);960 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/961}962 963static void _resetdigitalprocedure1(struct ieee80211_hw *hw, bool withouthwsm)964{965 struct rtl_priv *rtlpriv = rtl_priv(hw);966 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));967 968 if (rtlhal->fw_version <= 0x20) {969 /*****************************970 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status971 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)972 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE973 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)974 ******************************/975 u16 valu16 = 0;976 977 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);978 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);979 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &980 (~FEN_CPUEN))); /* reset MCU ,8051 */981 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;982 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |983 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */984 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);985 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |986 FEN_CPUEN)); /* enable MCU ,8051 */987 } else {988 u8 retry_cnts = 0;989 990 /* IF fw in RAM code, do reset */991 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {992 /* reset MCU ready status */993 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);994 /* 8051 reset by self */995 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);996 while ((retry_cnts++ < 100) &&997 (FEN_CPUEN & rtl_read_word(rtlpriv,998 REG_SYS_FUNC_EN))) {999 udelay(50);1000 }1001 if (retry_cnts >= 100) {1002 pr_err("8051 reset failed!.........................\n");1003 /* if 8051 reset fail, reset MAC. */1004 rtl_write_byte(rtlpriv,1005 REG_SYS_FUNC_EN + 1,1006 0x50);1007 udelay(100);1008 }1009 }1010 /* Reset MAC and Enable 8051 */1011 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);1012 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);1013 }1014 if (withouthwsm) {1015 /*****************************1016 Without HW auto state machine1017 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock1018 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL1019 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK1020 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON1021 ******************************/1022 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);1023 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);1024 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);1025 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);1026 }1027}1028 1029static void _resetdigitalprocedure2(struct ieee80211_hw *hw)1030{1031 struct rtl_priv *rtlpriv = rtl_priv(hw);1032/*****************************1033k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction1034l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock1035m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON1036******************************/1037 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);1038 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);1039}1040 1041static void _disablegpio(struct ieee80211_hw *hw)1042{1043 struct rtl_priv *rtlpriv = rtl_priv(hw);1044/***************************************1045j. GPIO_PIN_CTRL 0x44[31:0]=0x0001046k. Value = GPIO_PIN_CTRL[7:0]1047l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level1048m. GPIO_MUXCFG 0x42 [15:0] = 0x07801049n. LEDCFG 0x4C[15:0] = 0x80801050***************************************/1051 u8 value8;1052 u16 value16;1053 u32 value32;1054 1055 /* 1. Disable GPIO[7:0] */1056 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);1057 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;1058 value8 = (u8)(value32&0x000000FF);1059 value32 |= ((value8<<8) | 0x00FF0000);1060 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);1061 /* 2. Disable GPIO[10:8] */1062 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);1063 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;1064 value8 = (u8)(value16&0x000F);1065 value16 |= ((value8<<4) | 0x0780);1066 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);1067 /* 3. Disable LED0 & 1 */1068 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);1069}1070 1071static void disable_analog(struct ieee80211_hw *hw, bool withouthwsm)1072{1073 struct rtl_priv *rtlpriv = rtl_priv(hw);1074 u16 value16 = 0;1075 u8 value8 = 0;1076 1077 if (withouthwsm) {1078 /*****************************1079 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power1080 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power1081 r. When driver call disable, the ASIC will turn off remaining1082 clock automatically1083 ******************************/1084 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);1085 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);1086 value8 &= (~LDV12_EN);1087 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);1088 }1089 1090/*****************************1091h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode1092i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend1093******************************/1094 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);1095 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);1096 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);1097 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);1098}1099 1100static void carddisable_hwsm(struct ieee80211_hw *hw)1101{1102 /* ==== RF Off Sequence ==== */1103 disable_rfafeandresetbb(hw);1104 /* ==== Reset digital sequence ====== */1105 _resetdigitalprocedure1(hw, false);1106 /* ==== Pull GPIO PIN to balance level and LED control ====== */1107 _disablegpio(hw);1108 /* ==== Disable analog sequence === */1109 disable_analog(hw, false);1110}1111 1112static void carddisablewithout_hwsm(struct ieee80211_hw *hw)1113{1114 /*==== RF Off Sequence ==== */1115 disable_rfafeandresetbb(hw);1116 /* ==== Reset digital sequence ====== */1117 _resetdigitalprocedure1(hw, true);1118 /* ==== Pull GPIO PIN to balance level and LED control ====== */1119 _disablegpio(hw);1120 /* ==== Reset digital sequence ====== */1121 _resetdigitalprocedure2(hw);1122 /* ==== Disable analog sequence === */1123 disable_analog(hw, true);1124}1125 1126static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,1127 u8 set_bits, u8 clear_bits)1128{1129 struct rtl_priv *rtlpriv = rtl_priv(hw);1130 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));1131 1132 rtlusb->reg_bcn_ctrl_val |= set_bits;1133 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;1134 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);1135}1136 1137static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)1138{1139 struct rtl_priv *rtlpriv = rtl_priv(hw);1140 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);1141 u8 tmp1byte = 0;1142 1143 if (IS_NORMAL_CHIP(rtlhal->version)) {1144 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);1145 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,1146 tmp1byte & (~BIT(6)));1147 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);1148 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);1149 tmp1byte &= ~(BIT(0));1150 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);1151 } else {1152 rtl_write_byte(rtlpriv, REG_TXPAUSE,1153 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));1154 }1155}1156 1157static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)1158{1159 struct rtl_priv *rtlpriv = rtl_priv(hw);1160 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);1161 u8 tmp1byte = 0;1162 1163 if (IS_NORMAL_CHIP(rtlhal->version)) {1164 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);1165 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,1166 tmp1byte | BIT(6));1167 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);1168 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);1169 tmp1byte |= BIT(0);1170 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);1171 } else {1172 rtl_write_byte(rtlpriv, REG_TXPAUSE,1173 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));1174 }1175}1176 1177static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)1178{1179 struct rtl_priv *rtlpriv = rtl_priv(hw);1180 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);1181 1182 if (IS_NORMAL_CHIP(rtlhal->version))1183 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));1184 else1185 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));1186}1187 1188static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)1189{1190 struct rtl_priv *rtlpriv = rtl_priv(hw);1191 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);1192 1193 if (IS_NORMAL_CHIP(rtlhal->version))1194 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);1195 else1196 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);1197}1198 1199static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,1200 enum nl80211_iftype type)1201{1202 struct rtl_priv *rtlpriv = rtl_priv(hw);1203 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);1204 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;1205 1206 bt_msr &= 0xfc;1207 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==1208 NL80211_IFTYPE_STATION) {1209 _rtl92cu_stop_tx_beacon(hw);1210 _rtl92cu_enable_bcn_sub_func(hw);1211 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {1212 _rtl92cu_resume_tx_beacon(hw);1213 _rtl92cu_disable_bcn_sub_func(hw);1214 } else {1215 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,1216 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",1217 type);1218 }1219 switch (type) {1220 case NL80211_IFTYPE_UNSPECIFIED:1221 bt_msr |= MSR_NOLINK;1222 ledaction = LED_CTL_LINK;1223 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1224 "Set Network type to NO LINK!\n");1225 break;1226 case NL80211_IFTYPE_ADHOC:1227 bt_msr |= MSR_ADHOC;1228 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1229 "Set Network type to Ad Hoc!\n");1230 break;1231 case NL80211_IFTYPE_STATION:1232 bt_msr |= MSR_INFRA;1233 ledaction = LED_CTL_LINK;1234 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1235 "Set Network type to STA!\n");1236 break;1237 case NL80211_IFTYPE_AP:1238 bt_msr |= MSR_AP;1239 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1240 "Set Network type to AP!\n");1241 break;1242 default:1243 pr_err("Network type %d not supported!\n", type);1244 goto error_out;1245 }1246 rtl_write_byte(rtlpriv, MSR, bt_msr);1247 rtlpriv->cfg->ops->led_control(hw, ledaction);1248 if ((bt_msr & MSR_MASK) == MSR_AP)1249 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);1250 else1251 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);1252 return 0;1253error_out:1254 return 1;1255}1256 1257void rtl92cu_card_disable(struct ieee80211_hw *hw)1258{1259 struct rtl_priv *rtlpriv = rtl_priv(hw);1260 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1261 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));1262 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1263 enum nl80211_iftype opmode;1264 1265 mac->link_state = MAC80211_NOLINK;1266 opmode = NL80211_IFTYPE_UNSPECIFIED;1267 _rtl92cu_set_media_status(hw, opmode);1268 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);1269 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);1270 if (rtlusb->disablehwsm)1271 carddisable_hwsm(hw);1272 else1273 carddisablewithout_hwsm(hw);1274 1275 /* after power off we should do iqk again */1276 rtlpriv->phy.iqk_initialized = false;1277}1278 1279void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)1280{1281 struct rtl_priv *rtlpriv = rtl_priv(hw);1282 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);1283 u32 reg_rcr;1284 1285 if (rtlpriv->psc.rfpwr_state != ERFON)1286 return;1287 1288 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));1289 1290 if (check_bssid) {1291 u8 tmp;1292 1293 if (IS_NORMAL_CHIP(rtlhal->version)) {1294 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);1295 tmp = BIT(4);1296 } else {1297 reg_rcr |= RCR_CBSSID;1298 tmp = BIT(4) | BIT(5);1299 }1300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,1301 (u8 *) (®_rcr));1302 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);1303 } else {1304 u8 tmp;1305 1306 if (IS_NORMAL_CHIP(rtlhal->version)) {1307 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);1308 tmp = BIT(4);1309 } else {1310 reg_rcr &= ~RCR_CBSSID;1311 tmp = BIT(4) | BIT(5);1312 }1313 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));1314 rtlpriv->cfg->ops->set_hw_reg(hw,1315 HW_VAR_RCR, (u8 *) (®_rcr));1316 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);1317 }1318}1319 1320/*========================================================================== */1321 1322int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)1323{1324 struct rtl_priv *rtlpriv = rtl_priv(hw);1325 1326 if (_rtl92cu_set_media_status(hw, type))1327 return -EOPNOTSUPP;1328 1329 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {1330 if (type != NL80211_IFTYPE_AP)1331 rtl92cu_set_check_bssid(hw, true);1332 } else {1333 rtl92cu_set_check_bssid(hw, false);1334 }1335 1336 return 0;1337}1338 1339static void _beacon_function_enable(struct ieee80211_hw *hw)1340{1341 struct rtl_priv *rtlpriv = rtl_priv(hw);1342 1343 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);1344 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);1345}1346 1347void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)1348{1349 1350 struct rtl_priv *rtlpriv = rtl_priv(hw);1351 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1352 u16 bcn_interval, atim_window;1353 u32 value32;1354 1355 bcn_interval = mac->beacon_interval;1356 atim_window = 2; /*FIX MERGE */1357 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);1358 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1359 _rtl92cu_init_beacon_parameters(hw);1360 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);1361 /*1362 * Force beacon frame transmission even after receiving beacon frame1363 * from other ad hoc STA1364 *1365 *1366 * Reset TSF Timer to zero, added by Roger. 2008.06.241367 */1368 value32 = rtl_read_dword(rtlpriv, REG_TCR);1369 value32 &= ~TSFRST;1370 rtl_write_dword(rtlpriv, REG_TCR, value32);1371 value32 |= TSFRST;1372 rtl_write_dword(rtlpriv, REG_TCR, value32);1373 rtl_dbg(rtlpriv, COMP_INIT | COMP_BEACON, DBG_LOUD,1374 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",1375 value32);1376 /* TODO: Modify later (Find the right parameters)1377 * NOTE: Fix test chip's bug (about contention windows's randomness) */1378 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||1379 (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||1380 (mac->opmode == NL80211_IFTYPE_AP)) {1381 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);1382 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);1383 }1384 _beacon_function_enable(hw);1385}1386 1387void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)1388{1389 struct rtl_priv *rtlpriv = rtl_priv(hw);1390 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1391 u16 bcn_interval = mac->beacon_interval;1392 1393 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",1394 bcn_interval);1395 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1396}1397 1398void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,1399 u32 add_msr, u32 rm_msr)1400{1401}1402 1403void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)1404{1405 struct rtl_priv *rtlpriv = rtl_priv(hw);1406 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1407 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1408 1409 switch (variable) {1410 case HW_VAR_RCR:1411 *((u32 *)(val)) = mac->rx_conf;1412 break;1413 case HW_VAR_RF_STATE:1414 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;1415 break;1416 case HW_VAR_FWLPS_RF_ON:{1417 enum rf_pwrstate rfstate;1418 u32 val_rcr;1419 1420 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,1421 (u8 *)(&rfstate));1422 if (rfstate == ERFOFF) {1423 *((bool *) (val)) = true;1424 } else {1425 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);1426 val_rcr &= 0x00070000;1427 if (val_rcr)1428 *((bool *) (val)) = false;1429 else1430 *((bool *) (val)) = true;1431 }1432 break;1433 }1434 case HW_VAR_FW_PSMODE_STATUS:1435 *((bool *) (val)) = ppsc->fw_current_inpsmode;1436 break;1437 case HW_VAR_CORRECT_TSF:{1438 u64 tsf;1439 u32 *ptsf_low = (u32 *)&tsf;1440 u32 *ptsf_high = ((u32 *)&tsf) + 1;1441 1442 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));1443 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);1444 *((u64 *)(val)) = tsf;1445 break;1446 }1447 case HW_VAR_MGT_FILTER:1448 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);1449 break;1450 case HW_VAR_CTRL_FILTER:1451 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);1452 break;1453 case HW_VAR_DATA_FILTER:1454 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);1455 break;1456 case HAL_DEF_WOWLAN:1457 break;1458 default:1459 pr_err("switch case %#x not processed\n", variable);1460 break;1461 }1462}1463 1464static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)1465{1466 /* Currently nothing happens here.1467 * Traffic stops after some seconds in WPA2 802.11n mode.1468 * Maybe because rtl8192cu chip should be set from here?1469 * If I understand correctly, the realtek vendor driver sends some urbs1470 * if its "here".1471 *1472 * This is maybe necessary:1473 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, skb);1474 */1475 dev_kfree_skb(skb);1476 1477 return true;1478}1479 1480void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)1481{1482 struct rtl_priv *rtlpriv = rtl_priv(hw);1483 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1484 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1485 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));1486 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1487 u8 idx = 0;1488 1489 switch (variable) {1490 case HW_VAR_ETHER_ADDR:{1491 for (idx = 0; idx < ETH_ALEN; idx++) {1492 rtl_write_byte(rtlpriv, (REG_MACID + idx),1493 val[idx]);1494 }1495 break;1496 }1497 case HW_VAR_BASIC_RATE:{1498 u16 rate_cfg = ((u16 *) val)[0];1499 u8 rate_index = 0;1500 1501 rate_cfg &= 0x15f;1502 /* TODO */1503 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO1504 * && ((rate_cfg & 0x150) == 0)) {1505 * rate_cfg |= 0x010;1506 * } */1507 rate_cfg |= 0x01;1508 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);1509 rtl_write_byte(rtlpriv, REG_RRSR + 1,1510 (rate_cfg >> 8) & 0xff);1511 while (rate_cfg > 0x1) {1512 rate_cfg >>= 1;1513 rate_index++;1514 }1515 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,1516 rate_index);1517 break;1518 }1519 case HW_VAR_BSSID:{1520 for (idx = 0; idx < ETH_ALEN; idx++) {1521 rtl_write_byte(rtlpriv, (REG_BSSID + idx),1522 val[idx]);1523 }1524 break;1525 }1526 case HW_VAR_SIFS:{1527 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);1528 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);1529 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);1530 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);1531 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);1532 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);1533 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");1534 break;1535 }1536 case HW_VAR_SLOT_TIME:{1537 u8 e_aci;1538 1539 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);1540 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,1541 "HW_VAR_SLOT_TIME %x\n", val[0]);1542 1543 for (e_aci = 0; e_aci < AC_MAX; e_aci++)1544 rtlpriv->cfg->ops->set_hw_reg(hw,1545 HW_VAR_AC_PARAM,1546 &e_aci);1547 break;1548 }1549 case HW_VAR_ACK_PREAMBLE:{1550 u8 reg_tmp;1551 u8 short_preamble = (bool)*val;1552 1553 reg_tmp = 0;1554 if (short_preamble)1555 reg_tmp |= 0x80;1556 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);1557 break;1558 }1559 case HW_VAR_AMPDU_MIN_SPACE:{1560 u8 min_spacing_to_set;1561 u8 sec_min_space;1562 1563 min_spacing_to_set = *val;1564 if (min_spacing_to_set <= 7) {1565 switch (rtlpriv->sec.pairwise_enc_algorithm) {1566 case NO_ENCRYPTION:1567 case AESCCMP_ENCRYPTION:1568 sec_min_space = 0;1569 break;1570 case WEP40_ENCRYPTION:1571 case WEP104_ENCRYPTION:1572 case TKIP_ENCRYPTION:1573 sec_min_space = 6;1574 break;1575 default:1576 sec_min_space = 7;1577 break;1578 }1579 if (min_spacing_to_set < sec_min_space)1580 min_spacing_to_set = sec_min_space;1581 mac->min_space_cfg = ((mac->min_space_cfg &1582 0xf8) |1583 min_spacing_to_set);1584 *val = min_spacing_to_set;1585 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,1586 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",1587 mac->min_space_cfg);1588 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,1589 mac->min_space_cfg);1590 }1591 break;1592 }1593 case HW_VAR_SHORTGI_DENSITY:{1594 u8 density_to_set;1595 1596 density_to_set = *val;1597 density_to_set &= 0x1f;1598 mac->min_space_cfg &= 0x07;1599 mac->min_space_cfg |= (density_to_set << 3);1600 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,1601 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",1602 mac->min_space_cfg);1603 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,1604 mac->min_space_cfg);1605 break;1606 }1607 case HW_VAR_AMPDU_FACTOR:{1608 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};1609 u8 factor_toset;1610 u8 *p_regtoset = NULL;1611 u8 index = 0;1612 1613 p_regtoset = regtoset_normal;1614 factor_toset = *val;1615 if (factor_toset <= 3) {1616 factor_toset = (1 << (factor_toset + 2));1617 if (factor_toset > 0xf)1618 factor_toset = 0xf;1619 for (index = 0; index < 4; index++) {1620 if ((p_regtoset[index] & 0xf0) >1621 (factor_toset << 4))1622 p_regtoset[index] =1623 (p_regtoset[index] & 0x0f)1624 | (factor_toset << 4);1625 if ((p_regtoset[index] & 0x0f) >1626 factor_toset)1627 p_regtoset[index] =1628 (p_regtoset[index] & 0xf0)1629 | (factor_toset);1630 rtl_write_byte(rtlpriv,1631 (REG_AGGLEN_LMT + index),1632 p_regtoset[index]);1633 }1634 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,1635 "Set HW_VAR_AMPDU_FACTOR: %#x\n",1636 factor_toset);1637 }1638 break;1639 }1640 case HW_VAR_AC_PARAM:{1641 u8 e_aci = *val;1642 u32 u4b_ac_param;1643 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);1644 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);1645 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);1646 1647 u4b_ac_param = (u32) mac->ac[e_aci].aifs;1648 u4b_ac_param |= (u32) ((cw_min & 0xF) <<1649 AC_PARAM_ECW_MIN_OFFSET);1650 u4b_ac_param |= (u32) ((cw_max & 0xF) <<1651 AC_PARAM_ECW_MAX_OFFSET);1652 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;1653 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,1654 "queue:%x, ac_param:%x\n",1655 e_aci, u4b_ac_param);1656 switch (e_aci) {1657 case AC1_BK:1658 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,1659 u4b_ac_param);1660 break;1661 case AC0_BE:1662 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,1663 u4b_ac_param);1664 break;1665 case AC2_VI:1666 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,1667 u4b_ac_param);1668 break;1669 case AC3_VO:1670 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,1671 u4b_ac_param);1672 break;1673 default:1674 WARN_ONCE(true, "rtl8192cu: invalid aci: %d !\n",1675 e_aci);1676 break;1677 }1678 break;1679 }1680 case HW_VAR_RCR:{1681 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);1682 mac->rx_conf = ((u32 *) (val))[0];1683 rtl_dbg(rtlpriv, COMP_RECV, DBG_DMESG,1684 "### Set RCR(0x%08x) ###\n", mac->rx_conf);1685 break;1686 }1687 case HW_VAR_RETRY_LIMIT:{1688 u8 retry_limit = val[0];1689 1690 rtl_write_word(rtlpriv, REG_RL,1691 retry_limit << RETRY_LIMIT_SHORT_SHIFT |1692 retry_limit << RETRY_LIMIT_LONG_SHIFT);1693 rtl_dbg(rtlpriv, COMP_MLME, DBG_DMESG,1694 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",1695 retry_limit);1696 break;1697 }1698 case HW_VAR_DUAL_TSF_RST:1699 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));1700 break;1701 case HW_VAR_EFUSE_BYTES:1702 rtlefuse->efuse_usedbytes = *((u16 *) val);1703 break;1704 case HW_VAR_EFUSE_USAGE:1705 rtlefuse->efuse_usedpercentage = *val;1706 break;1707 case HW_VAR_IO_CMD:1708 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));1709 break;1710 case HW_VAR_WPA_CONFIG:1711 rtl_write_byte(rtlpriv, REG_SECCFG, *val);1712 break;1713 case HW_VAR_SET_RPWM:{1714 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);1715 1716 if (rpwm_val & BIT(7))1717 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);1718 else1719 rtl_write_byte(rtlpriv, REG_USB_HRPWM,1720 *val | BIT(7));1721 break;1722 }1723 case HW_VAR_H2C_FW_PWRMODE:{1724 u8 psmode = *val;1725 1726 if ((psmode != FW_PS_ACTIVE_MODE) &&1727 (!IS_92C_SERIAL(rtlhal->version)))1728 rtl92c_dm_rf_saving(hw, true);1729 rtl92c_set_fw_pwrmode_cmd(hw, (*val));1730 break;1731 }1732 case HW_VAR_FW_PSMODE_STATUS:1733 ppsc->fw_current_inpsmode = *((bool *) val);1734 break;1735 case HW_VAR_H2C_FW_JOINBSSRPT:{1736 u8 mstatus = *val;1737 u8 tmp_reg422;1738 bool recover = false;1739 1740 if (mstatus == RT_MEDIA_CONNECT) {1741 rtlpriv->cfg->ops->set_hw_reg(hw,1742 HW_VAR_AID, NULL);1743 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);1744 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));1745 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);1746 tmp_reg422 = rtl_read_byte(rtlpriv,1747 REG_FWHW_TXQ_CTRL + 2);1748 if (tmp_reg422 & BIT(6))1749 recover = true;1750 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,1751 tmp_reg422 & (~BIT(6)));1752 rtl92c_set_fw_rsvdpagepkt(hw,1753 &usb_cmd_send_packet);1754 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);1755 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));1756 if (recover)1757 rtl_write_byte(rtlpriv,1758 REG_FWHW_TXQ_CTRL + 2,1759 tmp_reg422 | BIT(6));1760 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);1761 }1762 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));1763 break;1764 }1765 case HW_VAR_AID:{1766 u16 u2btmp;1767 1768 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);1769 u2btmp &= 0xC000;1770 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,1771 (u2btmp | mac->assoc_id));1772 break;1773 }1774 case HW_VAR_CORRECT_TSF:{1775 u8 btype_ibss = val[0];1776 1777 if (btype_ibss)1778 _rtl92cu_stop_tx_beacon(hw);1779 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));1780 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &1781 0xffffffff));1782 rtl_write_dword(rtlpriv, REG_TSFTR + 4,1783 (u32)((mac->tsf >> 32) & 0xffffffff));1784 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);1785 if (btype_ibss)1786 _rtl92cu_resume_tx_beacon(hw);1787 break;1788 }1789 case HW_VAR_MGT_FILTER:1790 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);1791 mac->rx_mgt_filter = *(u16 *)val;1792 break;1793 case HW_VAR_CTRL_FILTER:1794 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);1795 mac->rx_ctrl_filter = *(u16 *)val;1796 break;1797 case HW_VAR_DATA_FILTER:1798 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);1799 mac->rx_data_filter = *(u16 *)val;1800 break;1801 case HW_VAR_KEEP_ALIVE:{1802 u8 array[2];1803 1804 array[0] = 0xff;1805 array[1] = *((u8 *)val);1806 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2,1807 array);1808 break;1809 }1810 default:1811 pr_err("switch case %#x not processed\n", variable);1812 break;1813 }1814}1815 1816static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,1817 struct ieee80211_sta *sta)1818{1819 struct rtl_priv *rtlpriv = rtl_priv(hw);1820 struct rtl_phy *rtlphy = &(rtlpriv->phy);1821 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1822 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1823 u32 ratr_value;1824 u8 ratr_index = 0;1825 u8 nmode = mac->ht_enable;1826 u8 mimo_ps = IEEE80211_SMPS_OFF;1827 u16 shortgi_rate;1828 u32 tmp_ratr_value;1829 u8 curtxbw_40mhz = mac->bw_40;1830 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?1831 1 : 0;1832 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?1833 1 : 0;1834 enum wireless_mode wirelessmode = mac->mode;1835 1836 if (rtlhal->current_bandtype == BAND_ON_5G)1837 ratr_value = sta->deflink.supp_rates[1] << 4;1838 else1839 ratr_value = sta->deflink.supp_rates[0];1840 if (mac->opmode == NL80211_IFTYPE_ADHOC)1841 ratr_value = 0xfff;1842 1843 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |1844 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);1845 switch (wirelessmode) {1846 case WIRELESS_MODE_B:1847 if (ratr_value & 0x0000000c)1848 ratr_value &= 0x0000000d;1849 else1850 ratr_value &= 0x0000000f;1851 break;1852 case WIRELESS_MODE_G:1853 ratr_value &= 0x00000FF5;1854 break;1855 case WIRELESS_MODE_N_24G:1856 case WIRELESS_MODE_N_5G:1857 nmode = 1;1858 if (mimo_ps == IEEE80211_SMPS_STATIC) {1859 ratr_value &= 0x0007F005;1860 } else {1861 u32 ratr_mask;1862 1863 if (get_rf_type(rtlphy) == RF_1T2R ||1864 get_rf_type(rtlphy) == RF_1T1R)1865 ratr_mask = 0x000ff005;1866 else1867 ratr_mask = 0x0f0ff005;1868 1869 ratr_value &= ratr_mask;1870 }1871 break;1872 default:1873 if (rtlphy->rf_type == RF_1T2R)1874 ratr_value &= 0x000ff0ff;1875 else1876 ratr_value &= 0x0f0ff0ff;1877 1878 break;1879 }1880 1881 ratr_value &= 0x0FFFFFFF;1882 1883 if (nmode && ((curtxbw_40mhz &&1884 curshortgi_40mhz) || (!curtxbw_40mhz &&1885 curshortgi_20mhz))) {1886 ratr_value |= 0x10000000;1887 tmp_ratr_value = (ratr_value >> 12);1888 1889 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {1890 if ((1 << shortgi_rate) & tmp_ratr_value)1891 break;1892 }1893 1894 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |1895 (shortgi_rate << 4) | (shortgi_rate);1896 }1897 1898 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);1899 1900 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",1901 rtl_read_dword(rtlpriv, REG_ARFR0));1902}1903 1904static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,1905 struct ieee80211_sta *sta,1906 u8 rssi_level, bool update_bw)1907{1908 struct rtl_priv *rtlpriv = rtl_priv(hw);1909 struct rtl_phy *rtlphy = &(rtlpriv->phy);1910 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1911 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1912 struct rtl_sta_info *sta_entry = NULL;1913 u32 ratr_bitmap;1914 u8 ratr_index;1915 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;1916 u8 curshortgi_40mhz = curtxbw_40mhz &&1917 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?1918 1 : 0;1919 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?1920 1 : 0;1921 enum wireless_mode wirelessmode = 0;1922 bool shortgi = false;1923 u8 rate_mask[5];1924 u8 macid = 0;1925 u8 mimo_ps = IEEE80211_SMPS_OFF;1926 1927 sta_entry = (struct rtl_sta_info *) sta->drv_priv;1928 wirelessmode = sta_entry->wireless_mode;1929 if (mac->opmode == NL80211_IFTYPE_STATION ||1930 mac->opmode == NL80211_IFTYPE_MESH_POINT)1931 curtxbw_40mhz = mac->bw_40;1932 else if (mac->opmode == NL80211_IFTYPE_AP ||1933 mac->opmode == NL80211_IFTYPE_ADHOC)1934 macid = sta->aid + 1;1935 1936 if (rtlhal->current_bandtype == BAND_ON_5G)1937 ratr_bitmap = sta->deflink.supp_rates[1] << 4;1938 else1939 ratr_bitmap = sta->deflink.supp_rates[0];1940 if (mac->opmode == NL80211_IFTYPE_ADHOC)1941 ratr_bitmap = 0xfff;1942 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |1943 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);1944 switch (wirelessmode) {1945 case WIRELESS_MODE_B:1946 ratr_index = RATR_INX_WIRELESS_B;1947 if (ratr_bitmap & 0x0000000c)1948 ratr_bitmap &= 0x0000000d;1949 else1950 ratr_bitmap &= 0x0000000f;1951 break;1952 case WIRELESS_MODE_G:1953 ratr_index = RATR_INX_WIRELESS_GB;1954 1955 if (rssi_level == 1)1956 ratr_bitmap &= 0x00000f00;1957 else if (rssi_level == 2)1958 ratr_bitmap &= 0x00000ff0;1959 else1960 ratr_bitmap &= 0x00000ff5;1961 break;1962 case WIRELESS_MODE_A:1963 ratr_index = RATR_INX_WIRELESS_A;1964 ratr_bitmap &= 0x00000ff0;1965 break;1966 case WIRELESS_MODE_N_24G:1967 case WIRELESS_MODE_N_5G:1968 ratr_index = RATR_INX_WIRELESS_NGB;1969 1970 if (mimo_ps == IEEE80211_SMPS_STATIC) {1971 if (rssi_level == 1)1972 ratr_bitmap &= 0x00070000;1973 else if (rssi_level == 2)1974 ratr_bitmap &= 0x0007f000;1975 else1976 ratr_bitmap &= 0x0007f005;1977 } else {1978 if (rtlphy->rf_type == RF_1T2R ||1979 rtlphy->rf_type == RF_1T1R) {1980 if (curtxbw_40mhz) {1981 if (rssi_level == 1)1982 ratr_bitmap &= 0x000f0000;1983 else if (rssi_level == 2)1984 ratr_bitmap &= 0x000ff000;1985 else1986 ratr_bitmap &= 0x000ff015;1987 } else {1988 if (rssi_level == 1)1989 ratr_bitmap &= 0x000f0000;1990 else if (rssi_level == 2)1991 ratr_bitmap &= 0x000ff000;1992 else1993 ratr_bitmap &= 0x000ff005;1994 }1995 } else {1996 if (curtxbw_40mhz) {1997 if (rssi_level == 1)1998 ratr_bitmap &= 0x0f0f0000;1999 else if (rssi_level == 2)2000 ratr_bitmap &= 0x0f0ff000;2001 else2002 ratr_bitmap &= 0x0f0ff015;2003 } else {2004 if (rssi_level == 1)2005 ratr_bitmap &= 0x0f0f0000;2006 else if (rssi_level == 2)2007 ratr_bitmap &= 0x0f0ff000;2008 else2009 ratr_bitmap &= 0x0f0ff005;2010 }2011 }2012 }2013 2014 if ((curtxbw_40mhz && curshortgi_40mhz) ||2015 (!curtxbw_40mhz && curshortgi_20mhz)) {2016 2017 if (macid == 0)2018 shortgi = true;2019 else if (macid == 1)2020 shortgi = false;2021 }2022 break;2023 default:2024 ratr_index = RATR_INX_WIRELESS_NGB;2025 2026 if (rtlphy->rf_type == RF_1T2R)2027 ratr_bitmap &= 0x000ff0ff;2028 else2029 ratr_bitmap &= 0x0f0ff0ff;2030 break;2031 }2032 sta_entry->ratr_index = ratr_index;2033 2034 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,2035 "ratr_bitmap :%x\n", ratr_bitmap);2036 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |2037 (ratr_index << 28);2038 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;2039 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,2040 "Rate_index:%x, ratr_val:%x, %5phC\n",2041 ratr_index, ratr_bitmap, rate_mask);2042 memcpy(rtlpriv->rate_mask, rate_mask, 5);2043 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a2044 * "scheduled while atomic" if called directly */2045 schedule_work(&rtlpriv->works.fill_h2c_cmd);2046 2047 if (macid != 0)2048 sta_entry->ratr_index = ratr_index;2049}2050 2051void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,2052 struct ieee80211_sta *sta,2053 u8 rssi_level, bool update_bw)2054{2055 struct rtl_priv *rtlpriv = rtl_priv(hw);2056 2057 if (rtlpriv->dm.useramask)2058 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level, update_bw);2059 else2060 rtl92cu_update_hal_rate_table(hw, sta);2061}2062 2063void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)2064{2065 struct rtl_priv *rtlpriv = rtl_priv(hw);2066 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));2067 u16 sifs_timer;2068 2069 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,2070 &mac->slot_time);2071 if (!mac->ht_enable)2072 sifs_timer = 0x0a0a;2073 else2074 sifs_timer = 0x0e0e;2075 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);2076}2077 2078bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)2079{2080 struct rtl_priv *rtlpriv = rtl_priv(hw);2081 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));2082 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;2083 u8 u1tmp = 0;2084 bool actuallyset = false;2085 unsigned long flag = 0;2086 /* to do - usb autosuspend */2087 u8 usb_autosuspend = 0;2088 2089 if (ppsc->swrf_processing)2090 return false;2091 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);2092 if (ppsc->rfchange_inprogress) {2093 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);2094 return false;2095 } else {2096 ppsc->rfchange_inprogress = true;2097 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);2098 }2099 cur_rfstate = ppsc->rfpwr_state;2100 if (usb_autosuspend) {2101 /* to do................... */2102 } else {2103 if (ppsc->pwrdown_mode) {2104 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);2105 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?2106 ERFOFF : ERFON;2107 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,2108 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);2109 } else {2110 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,2111 rtl_read_byte(rtlpriv,2112 REG_MAC_PINMUX_CFG) & ~(BIT(3)));2113 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);2114 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?2115 ERFON : ERFOFF;2116 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,2117 "GPIO_IN=%02x\n", u1tmp);2118 }2119 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",2120 e_rfpowerstate_toset);2121 }2122 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {2123 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,2124 "GPIOChangeRF - HW Radio ON, RF ON\n");2125 ppsc->hwradiooff = false;2126 actuallyset = true;2127 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==2128 ERFOFF)) {2129 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,2130 "GPIOChangeRF - HW Radio OFF\n");2131 ppsc->hwradiooff = true;2132 actuallyset = true;2133 } else {2134 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,2135 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",2136 ppsc->hwradiooff, e_rfpowerstate_toset);2137 }2138 if (actuallyset) {2139 ppsc->hwradiooff = true;2140 if (e_rfpowerstate_toset == ERFON) {2141 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&2142 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))2143 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);2144 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)2145 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))2146 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);2147 }2148 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);2149 ppsc->rfchange_inprogress = false;2150 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);2151 /* For power down module, we need to enable register block2152 * contrl reg at 0x1c. Then enable power down control bit2153 * of register 0x04 BIT4 and BIT15 as 1.2154 */2155 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {2156 /* Enable register area 0x0-0xc. */2157 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);2158 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);2159 }2160 if (e_rfpowerstate_toset == ERFOFF) {2161 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)2162 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);2163 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)2164 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);2165 }2166 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {2167 /* Enter D3 or ASPM after GPIO had been done. */2168 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)2169 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);2170 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)2171 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);2172 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);2173 ppsc->rfchange_inprogress = false;2174 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);2175 } else {2176 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);2177 ppsc->rfchange_inprogress = false;2178 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);2179 }2180 *valid = 1;2181 return !ppsc->hwradiooff;2182}2183