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1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../core.h"6#include "def.h"7#include "reg.h"8#include "dm_common.h"9#include "phy_common.h"10#include "rf_common.h"11 12static const u8 channel_all[59] = {13 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,14 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,15 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,16 114, 116, 118, 120, 122, 124, 126, 128, 130,17 132, 134, 136, 138, 140, 149, 151, 153, 155,18 157, 159, 161, 163, 16519};20 21static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,22 enum radio_path rfpath, u32 offset)23{24 struct rtl_priv *rtlpriv = rtl_priv(hw);25 struct rtl_phy *rtlphy = &rtlpriv->phy;26 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];27 u32 newoffset;28 u32 tmplong, tmplong2;29 u8 rfpi_enable = 0;30 u32 retvalue;31 32 newoffset = offset;33 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);34 if (rfpath == RF90_PATH_A)35 tmplong2 = tmplong;36 else37 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);38 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |39 (newoffset << 23) | BLSSIREADEDGE;40 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,41 tmplong & (~BLSSIREADEDGE));42 udelay(10);43 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);44 udelay(100);45 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,46 tmplong | BLSSIREADEDGE);47 udelay(10);48 if (rfpath == RF90_PATH_A)49 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,50 BIT(8));51 else if (rfpath == RF90_PATH_B)52 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,53 BIT(8));54 if (rfpi_enable)55 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,56 BLSSIREADBACKDATA);57 else58 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,59 BLSSIREADBACKDATA);60 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",61 rfpath, pphyreg->rf_rb, retvalue);62 return retvalue;63}64 65static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,66 enum radio_path rfpath,67 u32 offset, u32 data)68{69 struct rtl_priv *rtlpriv = rtl_priv(hw);70 struct rtl_phy *rtlphy = &rtlpriv->phy;71 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];72 u32 data_and_addr;73 u32 newoffset;74 75 newoffset = offset;76 /* T65 RF */77 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;78 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);79 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",80 rfpath, pphyreg->rf3wire_offset, data_and_addr);81}82 83u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,84 u32 regaddr, u32 bitmask)85{86 struct rtl_priv *rtlpriv = rtl_priv(hw);87 u32 original_value, readback_value, bitshift;88 89 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,90 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",91 regaddr, rfpath, bitmask);92 rtl92d_pci_lock(rtlpriv);93 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);94 bitshift = calculate_bit_shift(bitmask);95 readback_value = (original_value & bitmask) >> bitshift;96 rtl92d_pci_unlock(rtlpriv);97 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,98 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",99 regaddr, rfpath, bitmask, original_value);100 return readback_value;101}102EXPORT_SYMBOL_GPL(rtl92d_phy_query_rf_reg);103 104void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,105 u32 regaddr, u32 bitmask, u32 data)106{107 struct rtl_priv *rtlpriv = rtl_priv(hw);108 struct rtl_phy *rtlphy = &rtlpriv->phy;109 u32 original_value, bitshift;110 111 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,112 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",113 regaddr, bitmask, data, rfpath);114 if (bitmask == 0)115 return;116 rtl92d_pci_lock(rtlpriv);117 if (rtlphy->rf_mode != RF_OP_BY_FW) {118 if (bitmask != RFREG_OFFSET_MASK) {119 original_value = _rtl92d_phy_rf_serial_read(hw,120 rfpath,121 regaddr);122 bitshift = calculate_bit_shift(bitmask);123 data = ((original_value & (~bitmask)) |124 (data << bitshift));125 }126 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);127 }128 rtl92d_pci_unlock(rtlpriv);129 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,130 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",131 regaddr, bitmask, data, rfpath);132}133EXPORT_SYMBOL_GPL(rtl92d_phy_set_rf_reg);134 135void rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)136{137 struct rtl_priv *rtlpriv = rtl_priv(hw);138 struct rtl_phy *rtlphy = &rtlpriv->phy;139 140 /* RF Interface Sowrtware Control */141 /* 16 LSBs if read 32-bit from 0x870 */142 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;143 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */144 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;145 /* 16 LSBs if read 32-bit from 0x874 */146 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;147 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */148 149 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;150 /* RF Interface Readback Value */151 /* 16 LSBs if read 32-bit from 0x8E0 */152 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;153 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */154 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;155 /* 16 LSBs if read 32-bit from 0x8E4 */156 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;157 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */158 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;159 160 /* RF Interface Output (and Enable) */161 /* 16 LSBs if read 32-bit from 0x860 */162 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;163 /* 16 LSBs if read 32-bit from 0x864 */164 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;165 166 /* RF Interface (Output and) Enable */167 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */168 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;169 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */170 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;171 172 /* Addr of LSSI. Write RF register by driver */173 /* LSSI Parameter */174 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =175 RFPGA0_XA_LSSIPARAMETER;176 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =177 RFPGA0_XB_LSSIPARAMETER;178 179 /* RF parameter */180 /* BB Band Select */181 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;182 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;183 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;184 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;185 186 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */187 /* Tx gain stage */188 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;189 /* Tx gain stage */190 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;191 /* Tx gain stage */192 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;193 /* Tx gain stage */194 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;195 196 /* Transceiver A~D HSSI Parameter-1 */197 /* wire control parameter1 */198 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;199 /* wire control parameter1 */200 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;201 202 /* Transceiver A~D HSSI Parameter-2 */203 /* wire control parameter2 */204 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;205 /* wire control parameter2 */206 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;207 208 /* RF switch Control */209 /* TR/Ant switch control */210 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;211 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;212 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;213 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;214 215 /* AGC control 1 */216 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;217 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;218 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;219 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;220 221 /* AGC control 2 */222 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;223 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;224 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;225 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;226 227 /* RX AFE control 1 */228 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;229 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;230 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;231 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;232 233 /*RX AFE control 1 */234 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;235 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;236 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;237 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;238 239 /* Tx AFE control 1 */240 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;241 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;242 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;243 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;244 245 /* Tx AFE control 2 */246 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;247 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;248 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;249 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;250 251 /* Transceiver LSSI Readback SI mode */252 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;253 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;254 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;255 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;256 257 /* Transceiver LSSI Readback PI mode */258 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;259 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;260}261EXPORT_SYMBOL_GPL(rtl92d_phy_init_bb_rf_register_definition);262 263void rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,264 u32 regaddr, u32 bitmask, u32 data)265{266 struct rtl_priv *rtlpriv = rtl_priv(hw);267 struct rtl_phy *rtlphy = &rtlpriv->phy;268 int index;269 270 if (regaddr == RTXAGC_A_RATE18_06)271 index = 0;272 else if (regaddr == RTXAGC_A_RATE54_24)273 index = 1;274 else if (regaddr == RTXAGC_A_CCK1_MCS32)275 index = 6;276 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)277 index = 7;278 else if (regaddr == RTXAGC_A_MCS03_MCS00)279 index = 2;280 else if (regaddr == RTXAGC_A_MCS07_MCS04)281 index = 3;282 else if (regaddr == RTXAGC_A_MCS11_MCS08)283 index = 4;284 else if (regaddr == RTXAGC_A_MCS15_MCS12)285 index = 5;286 else if (regaddr == RTXAGC_B_RATE18_06)287 index = 8;288 else if (regaddr == RTXAGC_B_RATE54_24)289 index = 9;290 else if (regaddr == RTXAGC_B_CCK1_55_MCS32)291 index = 14;292 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)293 index = 15;294 else if (regaddr == RTXAGC_B_MCS03_MCS00)295 index = 10;296 else if (regaddr == RTXAGC_B_MCS07_MCS04)297 index = 11;298 else if (regaddr == RTXAGC_B_MCS11_MCS08)299 index = 12;300 else if (regaddr == RTXAGC_B_MCS15_MCS12)301 index = 13;302 else303 return;304 305 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;306 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,307 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",308 rtlphy->pwrgroup_cnt, index,309 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);310 if (index == 13)311 rtlphy->pwrgroup_cnt++;312}313EXPORT_SYMBOL_GPL(rtl92d_store_pwrindex_diffrate_offset);314 315void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)316{317 struct rtl_priv *rtlpriv = rtl_priv(hw);318 struct rtl_phy *rtlphy = &rtlpriv->phy;319 320 rtlphy->default_initialgain[0] =321 rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);322 rtlphy->default_initialgain[1] =323 rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);324 rtlphy->default_initialgain[2] =325 rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);326 rtlphy->default_initialgain[3] =327 rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);328 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,329 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",330 rtlphy->default_initialgain[0],331 rtlphy->default_initialgain[1],332 rtlphy->default_initialgain[2],333 rtlphy->default_initialgain[3]);334 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);335 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, MASKDWORD);336 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,337 "Default framesync (0x%x) = 0x%x\n",338 ROFDM0_RXDETECTOR3, rtlphy->framesync);339}340EXPORT_SYMBOL_GPL(rtl92d_phy_get_hw_reg_originalvalue);341 342static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,343 u8 *cckpowerlevel, u8 *ofdmpowerlevel)344{345 struct rtl_priv *rtlpriv = rtl_priv(hw);346 struct rtl_phy *rtlphy = &rtlpriv->phy;347 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;348 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));349 u8 index = channel - 1;350 351 /* 1. CCK */352 if (rtlhal->current_bandtype == BAND_ON_2_4G) {353 /* RF-A */354 cckpowerlevel[RF90_PATH_A] =355 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];356 /* RF-B */357 cckpowerlevel[RF90_PATH_B] =358 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];359 } else {360 cckpowerlevel[RF90_PATH_A] = 0;361 cckpowerlevel[RF90_PATH_B] = 0;362 }363 /* 2. OFDM for 1S or 2S */364 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {365 /* Read HT 40 OFDM TX power */366 ofdmpowerlevel[RF90_PATH_A] =367 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];368 ofdmpowerlevel[RF90_PATH_B] =369 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];370 } else if (rtlphy->rf_type == RF_2T2R) {371 /* Read HT 40 OFDM TX power */372 ofdmpowerlevel[RF90_PATH_A] =373 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];374 ofdmpowerlevel[RF90_PATH_B] =375 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];376 }377}378 379static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,380 u8 channel, u8 *cckpowerlevel,381 u8 *ofdmpowerlevel)382{383 struct rtl_priv *rtlpriv = rtl_priv(hw);384 struct rtl_phy *rtlphy = &rtlpriv->phy;385 386 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];387 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];388}389 390static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)391{392 u8 place = chnl;393 394 if (chnl > 14) {395 for (place = 14; place < ARRAY_SIZE(channel_all); place++) {396 if (channel_all[place] == chnl) {397 place++;398 break;399 }400 }401 }402 return place;403}404 405void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)406{407 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));408 struct rtl_priv *rtlpriv = rtl_priv(hw);409 u8 cckpowerlevel[2], ofdmpowerlevel[2];410 411 if (!rtlefuse->txpwr_fromeprom)412 return;413 channel = _rtl92c_phy_get_rightchnlplace(channel);414 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],415 &ofdmpowerlevel[0]);416 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)417 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],418 &ofdmpowerlevel[0]);419 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)420 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);421 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);422}423EXPORT_SYMBOL_GPL(rtl92d_phy_set_txpower_level);424 425void rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, u8 rfpath,426 u32 *pu4_regval)427{428 struct rtl_priv *rtlpriv = rtl_priv(hw);429 struct rtl_phy *rtlphy = &rtlpriv->phy;430 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];431 432 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");433 /*----Store original RFENV control type----*/434 switch (rfpath) {435 case RF90_PATH_A:436 case RF90_PATH_C:437 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);438 break;439 case RF90_PATH_B:440 case RF90_PATH_D:441 *pu4_regval =442 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);443 break;444 }445 /*----Set RF_ENV enable----*/446 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);447 udelay(1);448 /*----Set RF_ENV output high----*/449 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);450 udelay(1);451 /* Set bit number of Address and Data for RF register */452 /* Set 1 to 4 bits for 8255 */453 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);454 udelay(1);455 /*Set 0 to 12 bits for 8255 */456 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);457 udelay(1);458 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");459}460EXPORT_SYMBOL_GPL(rtl92d_phy_enable_rf_env);461 462void rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,463 u32 *pu4_regval)464{465 struct rtl_priv *rtlpriv = rtl_priv(hw);466 struct rtl_phy *rtlphy = &rtlpriv->phy;467 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];468 469 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");470 /*----Restore RFENV control type----*/471 switch (rfpath) {472 case RF90_PATH_A:473 case RF90_PATH_C:474 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);475 break;476 case RF90_PATH_B:477 case RF90_PATH_D:478 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,479 *pu4_regval);480 break;481 }482 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");483}484EXPORT_SYMBOL_GPL(rtl92d_phy_restore_rf_env);485 486u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)487{488 u8 place;489 490 if (chnl > 14) {491 for (place = 14; place < ARRAY_SIZE(channel_all); place++) {492 if (channel_all[place] == chnl)493 return place - 13;494 }495 }496 497 return 0;498}499EXPORT_SYMBOL_GPL(rtl92d_get_rightchnlplace_for_iqk);500 501void rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, const u32 *adda_reg,502 u32 *adda_backup, u32 regnum)503{504 struct rtl_priv *rtlpriv = rtl_priv(hw);505 u32 i;506 507 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");508 for (i = 0; i < regnum; i++)509 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);510}511EXPORT_SYMBOL_GPL(rtl92d_phy_save_adda_registers);512 513void rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,514 const u32 *macreg, u32 *macbackup)515{516 struct rtl_priv *rtlpriv = rtl_priv(hw);517 u32 i;518 519 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n");520 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)521 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);522 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);523}524EXPORT_SYMBOL_GPL(rtl92d_phy_save_mac_registers);525 526void rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,527 const u32 *adda_reg, bool patha_on, bool is2t)528{529 struct rtl_priv *rtlpriv = rtl_priv(hw);530 u32 pathon;531 u32 i;532 533 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n");534 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;535 if (patha_on)536 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?537 0x04db25a4 : 0x0b1b25a4;538 for (i = 0; i < IQK_ADDA_REG_NUM; i++)539 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);540}541EXPORT_SYMBOL_GPL(rtl92d_phy_path_adda_on);542 543void rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,544 const u32 *macreg, u32 *macbackup)545{546 struct rtl_priv *rtlpriv = rtl_priv(hw);547 u32 i;548 549 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n");550 rtl_write_byte(rtlpriv, macreg[0], 0x3F);551 552 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)553 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &554 (~BIT(3))));555 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5))));556}557EXPORT_SYMBOL_GPL(rtl92d_phy_mac_setting_calibration);558 559static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)560{561 u32 ret;562 563 if (val1 >= val2)564 ret = val1 - val2;565 else566 ret = val2 - val1;567 return ret;568}569 570static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)571{572 int i;573 574 for (i = 0; i < ARRAY_SIZE(channel5g); i++)575 if (channel == channel5g[i])576 return true;577 return false;578}579 580void rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,581 const u32 *targetchnl, u32 *curvecount_val,582 bool is5g, u32 *curveindex)583{584 struct rtl_priv *rtlpriv = rtl_priv(hw);585 u32 smallest_abs_val = 0xffffffff, u4tmp;586 u8 i, j;587 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;588 589 for (i = 0; i < chnl_num; i++) {590 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))591 continue;592 curveindex[i] = 0;593 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {594 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],595 curvecount_val[j]);596 597 if (u4tmp < smallest_abs_val) {598 curveindex[i] = j;599 smallest_abs_val = u4tmp;600 }601 }602 smallest_abs_val = 0xffffffff;603 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",604 i, curveindex[i]);605 }606}607EXPORT_SYMBOL_GPL(rtl92d_phy_calc_curvindex);608 609void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)610{611 struct rtl_priv *rtlpriv = rtl_priv(hw);612 struct rtl_phy *rtlphy = &rtlpriv->phy;613 u8 i;614 615 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,616 "settings regs %zu default regs %d\n",617 ARRAY_SIZE(rtlphy->iqk_matrix),618 IQK_MATRIX_REG_NUM);619 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */620 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {621 rtlphy->iqk_matrix[i].value[0][0] = 0x100;622 rtlphy->iqk_matrix[i].value[0][2] = 0x100;623 rtlphy->iqk_matrix[i].value[0][4] = 0x100;624 rtlphy->iqk_matrix[i].value[0][6] = 0x100;625 rtlphy->iqk_matrix[i].value[0][1] = 0x0;626 rtlphy->iqk_matrix[i].value[0][3] = 0x0;627 rtlphy->iqk_matrix[i].value[0][5] = 0x0;628 rtlphy->iqk_matrix[i].value[0][7] = 0x0;629 rtlphy->iqk_matrix[i].iqk_done = false;630 }631}632EXPORT_SYMBOL_GPL(rtl92d_phy_reset_iqk_result);633 634static void rtl92d_phy_set_io(struct ieee80211_hw *hw)635{636 struct rtl_priv *rtlpriv = rtl_priv(hw);637 struct dig_t *de_digtable = &rtlpriv->dm_digtable;638 struct rtl_phy *rtlphy = &rtlpriv->phy;639 640 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,641 "--->Cmd(%#x), set_io_inprogress(%d)\n",642 rtlphy->current_io_type, rtlphy->set_io_inprogress);643 644 switch (rtlphy->current_io_type) {645 case IO_CMD_RESUME_DM_BY_SCAN:646 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;647 rtl92d_dm_write_dig(hw);648 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);649 break;650 case IO_CMD_PAUSE_DM_BY_SCAN:651 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;652 de_digtable->cur_igvalue = 0x37;653 if (rtlpriv->rtlhal.interface == INTF_USB)654 de_digtable->cur_igvalue = 0x17;655 rtl92d_dm_write_dig(hw);656 break;657 default:658 pr_err("switch case %#x not processed\n",659 rtlphy->current_io_type);660 break;661 }662 663 rtlphy->set_io_inprogress = false;664 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",665 rtlphy->current_io_type);666}667 668bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)669{670 struct rtl_priv *rtlpriv = rtl_priv(hw);671 struct rtl_phy *rtlphy = &rtlpriv->phy;672 bool postprocessing = false;673 674 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,675 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",676 iotype, rtlphy->set_io_inprogress);677 678 do {679 switch (iotype) {680 case IO_CMD_RESUME_DM_BY_SCAN:681 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,682 "[IO CMD] Resume DM after scan\n");683 postprocessing = true;684 break;685 case IO_CMD_PAUSE_DM_BY_SCAN:686 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,687 "[IO CMD] Pause DM before scan\n");688 postprocessing = true;689 break;690 default:691 pr_err("switch case %#x not processed\n",692 iotype);693 break;694 }695 } while (false);696 697 if (postprocessing && !rtlphy->set_io_inprogress) {698 rtlphy->set_io_inprogress = true;699 rtlphy->current_io_type = iotype;700 } else {701 return false;702 }703 704 rtl92d_phy_set_io(hw);705 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);706 return true;707}708EXPORT_SYMBOL_GPL(rtl92d_phy_set_io_cmd);709 710void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)711{712 struct rtl_priv *rtlpriv = rtl_priv(hw);713 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));714 u8 offset = REG_MAC_PHY_CTRL_NORMAL;715 u8 phy_ctrl = 0xf0;716 717 if (rtlhal->interface == INTF_USB) {718 phy_ctrl = rtl_read_byte(rtlpriv, offset);719 phy_ctrl &= ~(BIT(0) | BIT(1) | BIT(2));720 }721 722 switch (rtlhal->macphymode) {723 case DUALMAC_DUALPHY:724 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,725 "MacPhyMode: DUALMAC_DUALPHY\n");726 rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0) | BIT(1));727 break;728 case SINGLEMAC_SINGLEPHY:729 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,730 "MacPhyMode: SINGLEMAC_SINGLEPHY\n");731 rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(2));732 break;733 case DUALMAC_SINGLEPHY:734 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,735 "MacPhyMode: DUALMAC_SINGLEPHY\n");736 rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0));737 break;738 }739}740EXPORT_SYMBOL_GPL(rtl92d_phy_config_macphymode);741 742void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)743{744 struct rtl_priv *rtlpriv = rtl_priv(hw);745 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));746 struct rtl_phy *rtlphy = &rtlpriv->phy;747 748 switch (rtlhal->macphymode) {749 case DUALMAC_SINGLEPHY:750 rtlphy->rf_type = RF_2T2R;751 rtlhal->version |= RF_TYPE_2T2R;752 rtlhal->bandset = BAND_ON_BOTH;753 rtlhal->current_bandtype = BAND_ON_2_4G;754 break;755 756 case SINGLEMAC_SINGLEPHY:757 rtlphy->rf_type = RF_2T2R;758 rtlhal->version |= RF_TYPE_2T2R;759 rtlhal->bandset = BAND_ON_BOTH;760 rtlhal->current_bandtype = BAND_ON_2_4G;761 break;762 763 case DUALMAC_DUALPHY:764 rtlphy->rf_type = RF_1T1R;765 rtlhal->version &= RF_TYPE_1T1R;766 /* Now we let MAC0 run on 5G band. */767 if (rtlhal->interfaceindex == 0) {768 rtlhal->bandset = BAND_ON_5G;769 rtlhal->current_bandtype = BAND_ON_5G;770 } else {771 rtlhal->bandset = BAND_ON_2_4G;772 rtlhal->current_bandtype = BAND_ON_2_4G;773 }774 break;775 default:776 break;777 }778}779EXPORT_SYMBOL_GPL(rtl92d_phy_config_macphymode_info);780 781u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)782{783 u8 group;784 785 if (channel_all[chnl] <= 3)786 group = 0;787 else if (channel_all[chnl] <= 9)788 group = 1;789 else if (channel_all[chnl] <= 14)790 group = 2;791 else if (channel_all[chnl] <= 44)792 group = 3;793 else if (channel_all[chnl] <= 54)794 group = 4;795 else if (channel_all[chnl] <= 64)796 group = 5;797 else if (channel_all[chnl] <= 112)798 group = 6;799 else if (channel_all[chnl] <= 126)800 group = 7;801 else if (channel_all[chnl] <= 140)802 group = 8;803 else if (channel_all[chnl] <= 153)804 group = 9;805 else if (channel_all[chnl] <= 159)806 group = 10;807 else808 group = 11;809 return group;810}811EXPORT_SYMBOL_GPL(rtl92d_get_chnlgroup_fromarray);812 813u8 rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex)814{815 u8 group;816 817 if (channel_all[chnlindex] <= 3) /* Chanel 1-3 */818 group = 0;819 else if (channel_all[chnlindex] <= 9) /* Channel 4-9 */820 group = 1;821 else if (channel_all[chnlindex] <= 14) /* Channel 10-14 */822 group = 2;823 else if (channel_all[chnlindex] <= 64)824 group = 6;825 else if (channel_all[chnlindex] <= 140)826 group = 7;827 else828 group = 8;829 return group;830}831 832void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)833{834 struct rtl_priv *rtlpriv = rtl_priv(hw);835 836 switch (rtlpriv->rtlhal.macphymode) {837 case DUALMAC_DUALPHY:838 rtl_write_byte(rtlpriv, REG_DMC, 0x0);839 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);840 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);841 break;842 case DUALMAC_SINGLEPHY:843 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);844 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);845 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);846 break;847 case SINGLEMAC_SINGLEPHY:848 rtl_write_byte(rtlpriv, REG_DMC, 0x0);849 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);850 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);851 break;852 default:853 break;854 }855}856EXPORT_SYMBOL_GPL(rtl92d_phy_config_maccoexist_rfpage);857